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Hardware-in-the-Loop (HIL) Testing for Power

Electronics Systems Modeled in Simulink

Joel Van Sickel - MathWorks Application Engineer


Patrie Schenk - Speed goat Technical Sales
MathWorks speedgoat

Overview

1. Hardware-in-the-Ioop (HIL) overview


2. Review of a system level model of a motor and inverter in Simulin k
3. Use of HDL Coder to generate floating-po int HDL from the Simulink model to achieve 1 MHz
simulation (1 IJs time-step)
4. HIL simulation using Simulink Real-Time and Speedgoat target hardware

2
MathWorks°speedguat

What is HIL

Algorithm Model

Motor and
Controller Inverter Models

J
MathWorks ..peedgoat I

What is HIL

Algorithm Model

Motor and
Controller Inverter Models

---

J
MathWorks°speedguat

Demo

4
MathWorks' speedgaat

Demo

1 111i
-

5
MathWorks°speedguat

Demo

5
MathWorks speedgo8t

Why HIL?

6
MathWorks speedgo8t

Why HIL?

7
MathWorks speedgo8t

Why HIL?

B
MathWorks ..peedgoat

Power Electronics and Motor Control - Switching

2 Ways to simulate power electronics

• Average
- Easy to implement in real time
- Ignores dynamics of switching devices
- Good enough for some types of analysis

9
MathWorks ..peedgoat

Power Electronics and Motor Control - Switching

2 Ways to simulate power electronics

• Switching
- Captures switching events
- Requires simulation 100 times faster
than switching frequency

9
MathWorks ..peedgoat

CPU vs FPGA Simulations

2 Ways to simulate power electronics

• CPU
- Cheaper hardware
- Can run continuous domain simulation
- Run any code gen compatible block


.'"~''''''' ...............
"_ ..•

10
MathWorks ..peedgoat

CPU vs FPGA Simulations

2 Ways to simulate power electronics

• FPGA
- Multiple orders of magnitude faster
- Requires discrete domain simulation
- Uses single precision floating point values

10
MathWorks speedgoat

Review of a System Level Model of a Motor and Inverter in


Simulink
Field-Oriented Velocity Control
Test Bench

System
Inputs

Verify
Outputs

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•••1110_

O/C 1"0
_ 1110_

".'-".
-"k> ..

Controller_Algorithm

11
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curren I

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4 oc=====~=======±======~======±=======~====~=======±======~======±=====~
2 J .. 5 6 1 8 9 10

Runnin!l _Sample based j()lfS~"o T.. 9.93-t I


. . PllintAndControlier_HOLConversion2' - Simulinlc x
-Tools -Help

Field-Oriented Velocity Control


Test Bench
Copyright 2014 The MathWorks, Inc.

System
InpulS

Verify
Outputs
focVelocityEncoderProduction
!I;(';
"_'110..

c/o t-~ ~ o,c

~, 1 0' G ...

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. . PllIntAndController_HDlConversion2lMotor_And_lolldlMotor_And_lolld_Simulinlc_HDl - Simulinlc x
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MotorJ.nd_load_SimuJink_HDl. X PWM_PerIpOeraCAnlU nvener PIantAOOControI_HOt..C:onver5Io2

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Motor And Load

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PMSM )( PW"U'eriphenll_.AAcUI'M!Iter

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MathWorks speedguat

High Level Process for Deploying Model to FPGA

1. Create high level subsystem for defining 1/0


2. Convert model to discrete time
3. Convert all double precision signals to single precision signals
4. Use HDL workflow advisor to setup model settings
5. Use HDL workflow advisor to use all HDL compatible blocks
6. Use HDL workflow advisor to create Xilinx Viva do project and perform synthesis
7. Deploy model to the Speedgoat real-time machine .

12
. . HDl_Wrapptr2: - Simuhnk x
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Diagnostics
o Use noaUng-poln1 multl pllcalion to handle net slope corrections

I!OI Hardware Implementation Application lifespan (days): ~IO


Model Re ferencing ~ 1
0 r SImulatIOn Target
Code generation
I> COde GeneratIOn Integer and fllCed-point we
i~ ,. coverage
~ HDl COde GeneralJon o Remove code trom floatlng-poInllO Integer conversions thaI wraps out-of-range values ~ 2
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• • • •

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HDL PMSM Inverter Model
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treat the coostant value as a 1-0 array. Ot:hefWise, output a matrix with the

- t-
same dimensfons as the constant value.

---- M~n

10
Signal Attributes
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• File Edit Aun ~p

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L4. SII't Targtlll't Frequency
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• File Edit Aun ~p

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1.3. Set Target Interl'iKe
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1.3. Set Target Interl'iKe
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I
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v kt9~. ~ SVRem ~tIon
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ft~ Edit VIfNi DISplay OtllQ!arT\ ~.Iysi:s Help

• • • •

HDl.]MSI·Unverter_ModeI

~ My_HDl_UbraIY .. ~HDl_PMSM_IJ1Yefter_Modd .. •
.~ r----=--------------------------------~~-------------

~ Block Parameters: x
Constant
Output the constant specffied by the 'Constant value' parameter_ If
'Con5tant value' Is a vector and 'Interpret vector parameters as 1-0' Is on,
treat the constant value as a 1-0 array_ Otherwise, output a matrix with the

f~ i((!
same dimensions as the constant value.

Main Signal Attributes


output minimum: output maximum: ... 1010...
10 IJ 10 lill
~----~~~~~
~~~-~
--'~I~=~;'~====~========v~I==>=>~
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• • • • • • 10.0 ,, • •

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1.3. Chedt Block Com~tlbUity


v HOt. Wukftow AdvIsor
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" 1.3. Set Targer IllttIfatr


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v 3. HDl C.ocII! Geleatioi r
v ] . 1 Set Code GeebM Opooll5 InllJlln k Hl ock
1_I.L Set Basic 0ptj0rt5
] . 1.2. Set Ad'v;)nced ()pW b
l . Ll. Set OptII,,,",OOIi OptIons
" ].2. Generate RTLCode and IP~

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• • • • • • 10.0 •

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2.3. Chedt Block Com~t1blllty


v HOt. Woiktlow AdYl50r
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v 1 Set Target
& "' 1..1.. ~ Taroet DeYw;e and Svntt'l$S Tool Q1edt model fOf ~ed blocks
o "' 1..2. Set TorgetRet'cmlCe ~ Input: Parameters

& " 1,3. Set Tolfget Intelfacr o IQOOre warnings


& VI. Set Target mquency
.., ijj 2. ~ Medel FOf HOl Code Q:neriiltlol1
o 2. 1. 0Iedc QoOOI SettinQs
R~"1lI6 Task

o " 2..2. 01edt AIgebr.M: Loops

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v ~ 3. HOt. Cooe Gelid ittioo I
v ~ ]. 1. Set CDae GeneratiofI 0pI:i0ns
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o ] , t.2. SctAdYarlD!dOlA:b"
1, t.l. Set OpamuatDl Ootlans
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o " 1.3 ~ Target Inteffaa!
Reset i(lput port:
f) L't SetTarget iffQuencv
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0M!dr;:5<I~ThJes
v ~ 3. HDl God!! Gel'letdtcli'

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1. L Set Code GeneBtJon Options
o 1.1.L
--
Set Ba5iC 0jAIi1$
o l. L2. Set AlmrI:II!d 0ptknJ;
G 3.1.3. Set: 0pbmaatia1 0pt.I0ns
o " 3.2. Ger.eiate RTL~and IPCcII'e
v k$ " ~S~ ~tIon 0""""

...
" . L CTe.!te PIO)t'ct
".2. IItJiId R>GA B6tream
v q, 5. Download to Target
5.1. GI!nI!rlIll'. snuttk Real- Tin!: ~

FixedSte DrKf et
.. uo" HDl.W"","'1JS,,,.d';"'-J03l: .'MSMJ<IUN",,",,-ti! x
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• • • • • • 10.0 •

o x

3.1.2. AdVanced Options


v HOt. Woiktlow AdYl50r
Clock setdl ""~
v 1 Set Target
& " 1..1.. ~ Taroet DeYw;e and Svntt'l$S Tool
o " L2.SetT.getRefcmlCe~
t) " 1,3. ~ Tolfget Intelfacr
--
Clock Input port:
SyndJiOiiOUS

~[""=====~[ Clod< """" _ _ _ "'


[dko,,_""""=
"---_ _ _--'

& VI. Set Target mquency [..... [ Clod<....", """ •


liZ! 2. ~ Medel FOf HOl Code Q:neriiltlol1 ~==~
' -,11--------'[ Clod< ~
v
-"
",,
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' ' -_

& 2. 1. 0Iedc QoOOI SettinQs
" " " " " " ' " ,.""" "'
[ fEl
",

& " 2..2. OleO. Algebrarc Loops Additional settings


o. L). Ch«I< __ CDmpo"""",

o ,. Vt own Sample T\mI:s.


Al:l<JIing Point U' litJrary;
v ~ 3. HOt. COOe Gelid aboi i
v 1.1. Set Coae Generation Optjons LJbfafy; NatM FIoi!tJng Point •
o 3. J. L S«: Ba5ic Optili '"
. , 1. I~SdMvanced~6
o t.l.
1, Set OpamuatOl OptIDr"6 MAX •
o " 3.2. Ge:nerate RTL Code and IPCcn
v ~ '4 Embtt.W S'f$lCITIlIilI:\I.lItlon
" L ~iJte Pfo)CCt
<4.2. &A:I FPGA Bitstream
v fa 5. Download 10 T-oe.:
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..,..,
» D
85..
. . HOl_Wrapper2· · Si mu link C/C. .... Code •
file Edn VIeW Olsplay OtagfllM SimulatIOn Analysis Ch«k Model CompahblblY I-""H""
OLC",,,,,,,,,-__ •
II> ~. 1"'10"'.0_---' Open In Ch«k Subsystem Companbihty PlCCode •
o".,.'n Block Parameters ~SubsyslefnJ
Geoenle HOl for Subsyst~
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HOl C~ PropM1e'5 "-""'-
~~~-----------------------------------~
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HO'- 610<, ""'...,.
[ HDl Workflow AdvIs«

NMvIgale to Code

Find RcfeferKed VariablH


Test Harness •
Format •
Rotate & Rip •
Arrange •


SigJYIs & Ports •
ReqUirements •
t.near AnalysIS •
DH.g" IJeonfier •

-
C-.".


+
» -'"' •
... HOl_Wrappu2· Simulm)- x
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• • • • • • • 10.0

"®~I~~~~X~~'~~~~~~~::::::::~~~~~~~~~~J ~ HDl Properties: SpeedGoaU0311_PMSM_H ll _Wrapper


x
~ General Target: Specification
Implementation

Architecture Module •

lmplementatlon Parameters
AdaptivePipeUnlng Inherit •
Balanc:eOeIays Inhe", •

OockRatePipellnlng Inherit •

~I
CoostrainedOutputPlpeline O,::-_ _ ====_~I
lli.trtbutodPlpelJnlng ::[O=ff:;;:=======~
'l
OSPStyle none •

f1attenHlerarchy on
. ...... .
(!f -.c- _
InputPipe!lne 0
I::l
outputffpellne 0
.......- - -,
~ -, ,-"

SharlngFactof 0

streamlngFactor 0

cancel Help

.
..
..,.., ---:
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Ready ftudStepDfKr~u
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• • • • • • • 11.0
- • •


~ Block Pol"meters: SpeedGoaU0333_PMSM_H!l_Wrapper
X ~'_.~Il ....2It11''-!illl.oI5
Speedgoat 10333 Interface Block. (mask.)
Slmullnk Real-Time Interface Block for Speedgoat 103J3-325K.

Parameters

Device Index:

....I ~___________-----'I','
PCI slot (-1: autosearch):
1~
-I ____________________~1J
5<1mple time:

1-1 L!J
port: 1 pull resistor pull·up 3.3V •
port: 2 pull resistor pull-up 3.3V •
port: 3 pull resistor pull-up 3.3V •
port 4 pull resistor pull·up 3.3V •
port: 5 puU resistor ~up 3.3V •
port: 6 pull resistor pull·up 3.3V • -. . . ,
v a ~-

!iii OK cancel Help App!y

»
FludStt'pDfKrt'U
. . gm_HOL_Wrolpper2_ilrt· Simul'"k x
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~ Configuration Parameters: gm_HDl _WrappH;U Jrt/ElaboratedModeIConfiguration (Active) o x

Sotver
Data Import/Export Target options

" OptimiZatJon
~ Diagnostics
o Build for default target computer

Hardware Implementatlon
o Automallcally download appliCafion aner bUIlding
Model Referencing Name of SlmuUnk Real-Tlme object created by build process: 1
.1mi=I _ .---____________---'
Simulation Target D Use default communication timeout
" Code Generation
Spedty the communicatlon Umeout In secondS: ),,30
-'---_
Report
comments
Execution optlons
Symbols
Custom Code ExectJUon mode. Real-Time
Verification
Real-time Interrupt source: TImer
Stmullnk Real-Time OptIOns
110 board generating the Interrupt. NoneJOther
" Coverage
~ HOL Code Generatlon
,
PCI sJol(-l autosearch) or ISA base address: -1
Slmscape
Slmscape Multlbody lG Data logging optkms
" Slmscape Multlbody
o Monitor Task Executlon TIme

SIgnal logging data buffer size to doUbles- cl''''ooooo


='''-___________________-'
l ........................................ ............. .................
~ ~
y

OK cancel Help

»
MathWorks speedguat

Simulink Programmable FPGA 110 modules


Optimized for Power Electronics HIL and Rep
The 10334 1/0 module is optimized for HIL simulation of real power stages. The card combines
fast, low-latency analog and digital 1/0 capabilities , and is optimized for use with HDL Coder
Workflow Advisor from MathWorks.

Analog connectivity:
16 x 5 MHz ADC . +/-10V. ENOB > 13-bit at 5 MHz
16 x 2 MHz DAC. +/-10V. settling time <1 us

Multi-Gigabit Transceivers:
4 x MGT for inter-board commun ication
Enables scalability - I/O and computational resources

Selectable rear plug-ins add:


Digital TTLlRS422 I/O support for PWM / Encoder
Front SFP cages to access MGT at the out side of the enclosure

15
o
..
. . Simulation Data In~pector - untitlt-d· X
Q ~ •• ••
<±) Inspect Compare _ commandYalue _ rotorVelocity
••
f1~
,oo~-~-------;;:::=========::::---~

lOill
...... -'"
TET BaseRale.1Tl!lxTET
80

B TET BaseRate TET


TETSubRatel minTEr
"
•- TETSubRatel.maxTET
TETSubRate1 TEl

..- dCurrenl

QCurren t
qCurrenlCommand
"
,
II
.,
phaseCumm(1)
·20
enwderOlfset

...... 0
" " " " " ' .0 ,~
' .0
" '-'
" " ' .0 ,.,
"
.., "
,. 10_0 ",
(I ..........v>'I~

Name phaseCurrent1J • phaseCurrenl(l) _ phaseCurren1l21

uno •
(1) Units
Data Type single
,
Sample TIme 0.0001

Model OpenloopHwrestBe
Btodt Name ADC_TransduCl!CVOL ,
Block Path OpenloopHWTeslBe

Pon ,
Dimensions 121
.,
Channel 111
R""
QYemde GlObal Toler
Run 1 OpenloopHW
n.
4
, ,. ., .. ., ., 10_ ~
PROJECT S*iORTC\JT5 SeiJf~h Docurnef\t~tlon

OJ

OJ
OJ
OJ
OJ

OJ
(IJ

·1
x
PROJECT S*iORTC\JT5 SeiJf~h Docurnef\t~tlon

Clean Up Project
5e't Up PrDjetlt

•-
¢ • 'W fj • C: • "'projects • HOL_PMSM_2017b • HOL_PMSM • work • • p
CUrROt Folder ® Ed' rtlH1e:_~t!S.-tX ® x
D Name · All Fil6 View p )T • I .. @ . Name · Y"lue
gm_HDl..Wrapper2.s/rUll\..rtw ....
gm _HOl_Wripperl_slrt_wel!lfl'lr_sln...
D Name ... Stalus Classification paramEncoderCali ... Ixl PQfO~r ...
~~ paramEncoderRot ... Ixl POfDflYC
gm_HDl_Wrapp6_s1rU ltu tw Depe:ndency Analysis -tasks None
Cont,oI5_0p~loop ~ i'5' None p"ramEncoderRot. .. /ltl Poramer
hdlJlI} paramloadTorque... 0
HOl_Wrilpper_grutw OpenloopHWTestBed.six
pa",mMotorBr"ke... 0
OpenloopHWTestBed2_sht_rtw paramMoto rOn 0
OpenloopHWTestBed2_weblnilt_slrt •.
p""mOpenloopY... Ixl Poramrl
pmsm _,cpO~_actlJiltors_slrt_rtw
OpenLoopHWT~tBli!d2.s1x paroJmOpenloo plJ ... Ixl Paro~'
PWM_Test2_slrt_rtw
v OpenloopHWTe5t8edl.51x paramOpenloopV... lxl Parnmet
PWM_TesUlrt rhol paramOverBusVol... 8.0000e-OS
PlotOpenloopControls,m •
slpl] ~ Classification paramOverBusVol... 0
(j] tert_slrtJtw pwmJowspeed.milt
paramOverBusVol ... 24.3000
co ntroller.mldatx paramOverCurren ... bJ Poro~t
co ntroller.xml Opml oopHWTertBedZ_webinilr.sb: (Simulink Mod el) Not in proj ect A
paramOverCurren ... Ilrl Paramer
controllerbio.m paramOverCurren ... Ixl PomfMt
Command Window R\
controllerpt.m paramPwmComp ... 111'1 Pon:ltT~r
controUerref.m New to MAMB? See resources for Getting St art¢d. x
paramPwmComp... 111'1 Pommer
conuoUerri.m
» c qp .v~ewTaz g et Scre e n paramPwmCo mp ... !.xl Poro~t
eontfollerView. png \
Co py _oCPlantAndContfoUer_HOLe... fo. » 1 param Test TypeSel ...

foeVelodty£ncoderlo3!lSlrtRealTlm...
I paramVelocityCo... 100
paramVelocity(o ... bl Poromn
l~ foeVelocity£ncoderlo3! lS1rtRealTlm... paramVelocityCo... Ixl PQramet
~ focVeJoc ityfncoderlo331 SlrtRealTlm ... param VelocityCo ... Ixl Poro~r
D focVeiocityfncoderto331 SlrtRealTlm... pmsm Ix? stnJct
focVelocity£ncoderto331 SlrtRealTlm..•
pwm Ix7 strvd
E) foeVel ocityEncoderlo331 SlrtRnlTlm .. . samplelime Ixl stnJd
E) focVtl oeityEncoderlo331SlrtRealTlm ... v Ixl rtrod ¥

I Ort,,;ls < >

·1
MathWorks speedguat

Current Waveforms
oso-x 4104A . H'f5333OtI27: TUQ Har 13 17:05:35 2018

16
MathWorks speedguat

High Level Process for Deploying Model to FPGA

1. Create high level subsystem for defining 1/0


2. Convert model to discrete time
3. Convert all double precision signals to single precision signals
4. Use HDL workflow advisor to setup model settings
5. Use HDL workflow advisor to use all HDL compatible blocks
6. Use HDL workflow advisor to create Xilinx Viva do project and perform synthesis
7. Deploy model to the Speedgoat rea l-time machine .

12
MathWorks speedguat

Conclusion

1. Integrate desktop simulation with HIL simulation


2. Native Floating Point support for FPGA
3. Workflow advisor creates a seamless transition from desktop simulation to FPGA implementation

For more Information:

www.MathWorks.com

www.Speedgoat.com
17