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A 5.2 μA Quiescent Current LDO Regulator with High
Stability and Wide Load Range for CZT Detectors
Shiquan Fan, Member, IEEE, Haiqi Li, Zhuoqi Guo, Li Geng, Member, IEEE

Abstract—Cadmium Zinc Telluride (CZT) detectors are the
highly considered for room-temperature hard X-ray and
Gamma-ray detection. The readout systems are needed in the
detectors to output the detecting data. The features of power
supplies are very important for the readout circuits. In this paper,
a low-dropout (LDO) regulator with very low power consumption
and wide load variation is presented. A combining compensation
method which includes partially controlled load-tracking
technique and equivalent series resistance (ESR) compensation
technique are proposed to enhance the loop stability of the LDO
regulator. Meanwhile, high DC gain is obtained to improve the
power ripple rejection (PSRR), which can decrease the noise from
the power supply. The prototype LDO chip has been fabricated
and tested with a standard 0.18 μm CMOS technology. The
measured results show that the LDO regulator can provide up to
150 mA load current with a stable output voltage of 2.8 V under
an input voltage scope from 2.9 V to 3.6 V. The measured PSRR is
up to -60 dB. The output noise spectral densities are 1.16
μVRMS/ and 211 nVRMS/ at 1 kHz and 100 kHz,
respectively, at load current of 150 mA. Especially, the ultra-low
quiescent currents of 5.2 μA at no load and 18.2 μA at full load
bring great benefit to the ultra-low power integrated readout
systems.
Index Terms— CZT detector, readout circuit, power
management, low-dropout (LDO) regulator, ultra-low quiescent
current, high stability.
I. INTRODUCTION
C OMPARED with the scintillator based detectors,
semiconductor detectors have a higher charge yield of
converting rays into electric signals, which have wide
applications in medical imaging, space, and security systems
[1]-[2]. Among them, with the rapid development of material
science and fabrication process, Cadmium Zinc Telluride (CZT)
detector has become the competitive choice for
room-temperature hard X-ray and Gamma-ray detection
because of its good sensitivity and miniaturization prospect.
The radiation detector converts the energy into the pulse
Manuscript received November 2, 2016, revised January 23, 2017, February
18, 2017. This work was supported in part by the National Natural Science
Foundation of China (Grant No. 61504105, 61271089), the China Postdoctoral
Science Foundation (Grant No. 2015M582658), the National Key R&D
Program of China (Grant No. 2016YFB0400200) and the China Scholarship
Council (CSC No. 201506285143).
S. Fan, Z. Guo, and L. Geng are with the School of Microelectronics, Xi’an
Jiaotong University, Xi’an, Shaanxi, 710049, P.R. China (e-mail:
junjunfan@mail.xjtu.edu.cn; gengli@mail.xjtu.edu.cn).
H. Li was with the School of Microelectronics, Xi’an Jiaotong University，
now is with GalaxyCore Inc., Shanghai, 201203, China.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
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signals whose amplitudes are proportional to the radiation
energy. Then the signals are amplified, de-noised, shaped, peak
detected, and converted from the analog signals to the digital
signals, which are finally processed. To accomplish the whole
detecting sensor, the readout system is necessary. However, the
traditional discrete readout circuits occupy big area and are
complicatedly implemented. Moreover, with the developing
demands of the detection, more and more readout channels are
needed, which determines that the discrete readout component
is not a feasible solution. With the rapid development of
integrated circuit technology, readout circuits for radiation
detectors could be implemented in sub-micron CMOS
processes, which results in the ability to integrate analog and
digital function on the same chip, as shown in Fig.1. Power
management unit could also be integrated together with other
circuits, thus minimizing the cost, size and weight of the overall
system. Normally, a switched DC-DC converter is used to give
a primary voltage conversion and several LDOs are cascade
connected as the second conversion components to provide
clean supply voltage with low ripples and noise for the blocks
of the readout channel [3]-[6].
Fig. 1 Architecture of readout system with power management.
As the clean supply provider, features of the LDO regulator
such as load range, quiescent current, transient response, high
power supply rejection ratio (PSRR) and noise are concerned.
Typical power consumptions of readout circuits for CZT
detectors are 0.1 mW-10 mW/ch and the detector array size can
vary from 2×2 to 32×32. For arrays with various sizes, different
power loads are required. In addition, power consumption of
one readout channel is not always the same at different work
conditions. As a result, wide load range of the power
management unit is required.
The quiescent current of LDO regulator has an effect on
energy efficiency of the entire system. However, if the
quiescent current decreases, the stability of the LDO with wide
load is threatened. In addition, ultra low quiescent current
power management unit with high preference applied for
portable detectors is also very important to extend the life time
and reduce the maintain-fee [4]-[8].
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Furthermore, to save the power consumption of the chip, 1

standby mode and different load situations are set in the readout PEA  (1)
REA CEA
circuit. Therefore, the transient performance of the LDO
g mB
regulator is important. PB  (2)
Additional, readout circuit is sensitive to the ripples and CP
noise of the supply. Large ripples and noise may bring read 1
errors. Thus the LDO regulator should provide clean power PL  (3)
supply with high PSRR and low noise to the readout arrays. ( RL / / RP / /( RF1  RF2 ))CO
Therefore, LDOs applied for the readout array should have the 1
features such as wide load range, low quiescent current, fast ZESR  (4)
RESR CO
transient response, high PSRR and low noise.
For LDO regulator, if the load changes extensively, the ωPL is the dominant pole. The second pole ωPEA is cancelled
output pole will change significantly. The conventional by ωZESR. The stability is achieved by locating a pole at ωPB
pole-zero cancelling technique is difficult to guarantee the beyond the unity-gain frequency of the loop.
stability of loop because the normal compensation strategy can
only provide a fixed left-half-plane (LHP) zero [9]. It leads to
the insufficient phase margin (PM) when the output pole is far
from the fixed zero [7], [10]-[12]. Furthermore, the power loss
of LDO regulator should be restricted carefully. Also, the
stability meets greater challenges if ultra-low quiescent current
is focused on, which leads to the internal high-impedance nodes,
and thus generates the lower frequency of poles to decrease
loop PM significantly [3], [13]-[17].
In this paper, a partially controlled load-tracking method is
combined to an equivalent series resistance (ESR)
compensation technique to extend the load range and achieve Fig. 2 Traditional LDO regulator with ESR compensation method.
ultra-low quiescent current, which satisfies the need of a
readout array with 20×20 channels with up to 150 mA load The challenges of LDO regulator when it operates in wide
current (the maximum load current is 0.375 mA/ch). Besides, in load with restrict quiescent power are illustrated in Fig. 3. In
order to eliminate the radiation effects on LDO regulator, Fig.3 (a), the LDO regulator is well compensated at light load
redundancy design for transistors reduces the drift of threshold condition. But with the increase of the load current, the
voltage. In the meanwhile, techniques of gate-all-around and dominant pole, ωPL, moves to high frequency with a decrease of
guard-ring are adopted in the back-end layout to cut off the path gain because the operation of Mp changes from sub-threshold
of radiation induced leakage current and eliminate the leakage region to saturation region, which leads to the increase of the
caused by field oxygen reverse. unity gain bandwidth (UGBW). As a result, ωPB moves from
The rest of this paper is organized as follows. In Section II, outside the UGBW to within the UGBW in heavy load
stability problems of traditional LDO regulators with low condition. This process makes the LDO regulator unstable.
quiescent current are discussed. Then, the combining technique Similar, in Fig. 3(b), for the LDO regulator with ultra-low
including partially controlled load-tracking technique and ESR quiescent current, because of the internal high-impedances of
compensation are proposed. The circuit implementation is the output of EA and buffer, ωPEA and ωPB change to lower
presented in Section III. Detailed measurement results are
frequency. Especially for ωPB, it might move in the UGBW,
illustrated in Section IV. Finally, the conclusion is given in
which leads to the instability.
Section V.
The structure of the proposed combining compensation
II. STABILITY CHALLENGES AND PROPOSED COMBINING method is shown in Fig. 4. A LHP zero, ωZZ, which could track
COMPENSATION METHOD the load, is generated by employing an adaptive RC network to
compensate the non-dominant pole, ωPEA. Also, an equivalent
The structure of a traditional LDO regulator with ESR ESR compensation is designed to compensate ωPB.
compensation is shown in Fig. 2. It consists of an error
amplifier (EA), a buffer, and a regulation PMOS, M p. The
transconductance of the EA, the buffer and the regulation
PMOS are signed as gm, gmB and gmp, respectively. CO and RESR
are the output capacitor and its equivalent series resistor,
respectively. CEA and CP are the parasitic capacitors of the
output node of the EA and buffer, respectively. The output
resistance of the regulation PMOS is RP. REA are the output
impendence of the EA. RESR is used to compensate the stability
of the loop. This loop has three poles, ωPEA, ωPB and ωPL, and a Fig. 3 Loop gain response of the LDO regulator: (a) Difference between light
zero, ωZESR, which are illustrated in Fig. 2. The poles and zero load and heavy load of a traditional LDO regulator, (b) Difference between the
are written as: traditional LDO regulator and LDO regulator with low quiescent current.

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A. Partially controlled load-tracking technique 1

As shown in the middle part of Fig. 4, MZ is connected in ZF  (7)
RF1CF
diode mode to guarantee the saturation operation of MOS
transistor. Thus the small signal of output resistance of M Z is 1
PF  (8)
approximately equal to reciprocal value of transconductance ( RF1 / / RF2 )CF
gmZ [18], which is much smaller than that of M S1. Thus, the
ωPF and ωZF are designed very closely and cancelled by each
load-tracking zero, ωZZ, can be written as:
other. In addition, according to (7) and (8), the frequency of ωZF
1
ZZ  is always lower than that of ωPF. The UGBW of LDO regulator
1 (5) increases if ωPF and ωZF are all located within the UGBW.
( RZ  )CZ
g mZ Meanwhile, if the UGBW of the LDO regulator is near ωZF, the
Vin PM of the LDO regulator can be increased significantly.
Power Stage with MS2 and MP have a W/L ratio of 1:K, and they are driven by
Buffer 1/N :1/K :1 Pseudo-ESR the same gate-source voltage. Thus current passing through MS2
gmS1 gmS2 gmp
ωPB is proportional to the load current with coefficient of 1/K. If
VREF gmB
ωPEA proper RS and K are selected to ensure that RS<<KRL and
gm MS1 MS2 MP
VFB
CgsP CgdP ωPL Vout CORS<<CFRF1, ωZS is expressed as:
RZ CZ
REA CEA RS 1
ωZZ CF RF1
RESR ZS 
g mS2 (9)
 RESR )CO
MZ
gmZ ωZS RL
( RS
RF2
g mP
CO
Partially Controlled
Since RESR is quite small in this design, which is much less
EA Load Tracking than RSgmS2/gmP, ωZS is simplified as:
Fig. 4 The structure of the proposed LDO regulator.
1 K
The current passing through MZ includes two branches. One
ZS  =
g mS2 RSCO (10)
comes from the output node of EA, which is almost ( RS )CO
g mP
independent of the load condition. Another comes from M S1.
Because MS1 and MP have a W/L ratio of 1:N and they are According to (10), ωZS is generated by RS/K and CO.
driven by the same gate-source voltage, the current through this Therefore, it is essentially an ESR compensation method with a
branch is proportional to the load current with a coefficient of controlled ESR resistor which equals to RS/K. By carefully
1/N. If load current varies, 1/gmZ varies to the opposite direction. designing the value of RS and K, a low-cost ceramic capacitor
Therefore, according to (5), ωZZ changes with the load current, with low-ESR could be used in the proposed LDO regulator.
which can be used to cancel the non-dominant pole, ωPEA. This The current passing through MS2 will flow to the load, thus the
method can slow down the moving speed of zero and reduce the ESR sensing circuit does not introduce extra power
moving range. Meanwhile, it also extends the UGBW of the
consumption.
loop and improves PM in the middle frequency band of the
LDO regulator. There exists another pole ωPB between buffer and regulation
As shown in Fig. 4, gmS1 and gmS2 are the transconductance of PMOS. According to (2) and Fig. 4, ωPB can be written as
MS1 and MS2, respectively. CEA is the parasitic capacitor of the g gmB
output node of EA. Compared with the Miller Compensation PB  mB = (11)
CP CgsP +CgdP gmP RO
capacitor CZ, CEA is very small and can be ignored. Therefore,
the pole at the output node of EA, ωPEA, can be expressed as: Where, RO and IL are the output resistance and load current of
the LDO regulator, respectively. RO = RL // RP // ( RF1 + RF2).
1
PEA  With the increase of the load current from light loads to
g (6)
REA ( 1  mS1 )CZ heavy loads, MP firstly operates in the sub-threshold region,
g mZ and then converts to the saturation region. It means that gmP is
The equivalent capacitance at the output node of EA is proportional to IL at first, then changes to be proportional to
enlarged by (1+gmS1/gmZ) due to the Miller effect. Thus, ωPEA sqrt(IL) in the saturation region. Normally, RF1 + RF2>>RL, RL =
decreases dramatically due to the large value of CZ and Vout / IL, and RP = 1/ (λIL), where λ is the channel length
(1+gmS1/gmZ). Because gmS1 and gmZ synchronously vary with modulation parameter [19]. Thus, RO is proportional to 1/IL.
the load current, ωPEA is not influenced by the load condition.
Therefore, when MP operates in the sub-threshold region, ωPB is
B. Power stage with pseudo-ESR technique a constant. When MP operates in the saturation region, with the
Power stage with equivalent ESR technique is shown in the increase of the load current, ωPB moves to high frequency with
right part of Fig. 4. RS, feedback capacitor CF and MOS low speed, which means ωPB could varies partially with the
transistor MS2 are introduced in the LDO regulator. The drain variation of load current.
current of Mp is sensed by RS, while the feedback capacitor CF
does not only generate a sensing zero, ωZS, but also forms a C. Stability analysis of LDO regulator
pole-zero pair, ωPF and ωZF [10]. Therefore, ωPF and ωZF are Based on the previous discussion, the loop gain transfer
expressed as: function of the designed LDO regulator can be obtained by

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s s represented by (12), G(s) is the feedback coefficient and equal

(1 )( 1  )
ZZ ZS to 1 (note that β is already included in H(s)).
H( s )   ADC (12)
s s s
(1 )( 1  )( 1  )
PEA PB PL
ADC and β are the DC gain and the feedback coefficient,
respectively. Assume the output resistance of the buffer and
regulation PMOS Mp are RB and RP, respectively, as shown in
Fig. 4, ADC and β satisfy
 g mB Fig. 6 Typical feedback loop of LDO regulator.
 ADC  g m REA g R  1 RB g mP RO  g m REA g mP RO
 mB B Therefore, the PSRR in low frequency can be written as:
  R (13) Vout 1
PSRR  
F2
 RF1  RF2 Vin 1  H( s )
(14)

 where RO =( RL / / RP / /( RF1 +RF2 )) In low frequency, the absolute value of H(s) is much larger
The compensation principle can be illustrated by comparing than 1, thus (14) can be simplified as:
the loop gain responses at light load and heavy load conditions, 1
PSRR  (15)
respectively, as shown in Fig. 5. H( s )
According to (15), high DC gain should be designed to
enhance the PSRR performance. Meanwhile, the dominant zero
of PSRR is the dominant pole of the feedback loop, which
means that the frequency of dominant pole of the feedback loop
should be designed as high as possible to extend the PSRR
range, but it may decrease the stability of the feedback loop
because of the increased UGBW. Therefore, a trade-off design
is needed.

III. TRANSISTOR CIRCUIT IMPLEMENTATION

Fig. 5 Loop response of the proposed frequency compensation. The transistor circuit implementation and quiescent current
distribution of the LDO regulator are illustrated in Fig. 7.
1). At light load condition, ωPL is the dominant pole while
ωPEA is the first non-dominant pole, the third pole ωPB locates
near the UGBW with constant frequency. The stability can be
enhanced by locating ωZZ near ωPEA and cancelling ωPB by ωZS.
With the increase of output current, ωPEA is a constant pole, ωPL
moves to the high frequency, ωZZ moves along the same
direction as that of ωPL. Therefore, ωZZ can partially track the
movement of ωPL within a wide load current range. At the same
time, when UGBW increases, the position of ωZS enters into the
UGBW. ωPB moves to high frequency with low speed because
the operation region of the regulation PMOS converts from the
sub-threshold region to the saturation region. This process
makes ωPB be much closer to ωZS. Fig. 7 Transistor implementation of the presented LDO regulator.
2). At heavy load condition, the pole frequency of ωPL may The LDO regulator includes five parts: current bias, EA,
be higher than that of the fixed pole ωPEA. ωPL becomes the first buffer, load tracking zero generator and power stage with
non-dominant pole while ωPEA is the dominant pole due to large pseudo-ESR. The output of EA should have wide voltage range
capacitor CZ and the high output impedance of the EA. In this to ensure that the LDO regulator operates within extremely
process, enough phase margin could be provided by ωZZ and wide load region. Thus an operational trans-conductance
ωZS to compensate the phase loss caused by the poles ωPL and amplifier (OTA) is employed. M1 and M2 are the input
ωPEA.
differential pairs gain stage of EA. M3 and M4 are used as the
D. Analysis of PSRR load of M1 and M2. M5-M8 translate differential signal into one
The output signals of CZT detectors are very weak. They output. In order to achieve low quiescent current and high slew
must be processed by the low noise readout systems. Power rate, the current flows through M5 and differential pairs are
supply may bring noise to the readout circuit, thus the PSRR of scaled down comparing with the current of output stage. VREF is
LDO regulator should be discussed. According to Fig. 4, the the reference voltage, which is produced by bandgap. MB2 and
main path of noise from power supply to output is MP. The MB build up the voltage buffer, which drives the gate of M P.
feedback loop of LDO regulator can be shown in Fig.6, where Since the buffer is simply implemented by a source follower
H(s) is the open loop transfer function of the LDO regulator with current-source load, the ripples of the power supply

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present at the gate of the regulation PMOS MP. Therefore, the 39.0dB. In addition, PMs under different load currents are
ripples between gate and source of MP are cancelled. shown in Fig. 9(b). The worst-case PM is bigger than 60°. The
The total quiescent current of the presented LDO regulator designed LDO regulator has good stability under wide load
includes the current passing through the MOSFETs of M 5, M6, range.
MB1, MB2, MS1, MS2 and RF1, as shown in Fig. 7. Because the The post-simulation of the current flowing through M S1 and
W/L ratio ofMS1, MS2and MP is 1/N :1/K :1, where N and K are MS2 are 382 pA and 4.43 nA at no load condition, respectively
much larger than 1, the current which passing through the M S1 and 13 μA and 191 μA in full load condition, respectively. The
and MS2 is much smaller than the current passing through M P. feedback network consumes only 1 μA. Based on Fig. 7 and
In no load condition, the current flowing through M P is nearly relevant discussed above, the quiescent current of the proposed
equal to the current flowing through the resistor RF1. Therefore, LDO regulator is only 5.2 μA at no load condition and 18.2 μA
the quiescent currents of MS1 and MS2 are equal to 1/N and 1/K at full load of 150 mA.
times of the current flowing through RF1, respectively. The
currents are very small and could be ignored. The drain current
of MS2 flowing through Rs brings extra quiescent current.
However, this current flows into the feedback network and the
load and does not introduce extra power consumption to the
LDO regulator.
Fig. 8 shows the small-signal model of the transistor circuit,
where gm2, gmB, gmP/N, gmP/K and gmP are the trans-conductance
of M2, MB, MS1, MS2 and MP in Fig. 7, respectively. IL and Vout
are the load current and output voltage, respectively. Thus,
parameters in (12) satisfy

 1
PB  ( r / / r )( C  C g R ) (a)
 B B2 gsP gdP mP O

 1 K
PL  , ZS =
 ROCO RSCO
 1
PEA 
 g
 ( rO6 / / rO8 )( 1  mP )CZ (16)
 Ng mZ
 1 RF2
ZZ  , 
 1 R F1 +RF2
( RZ  )CZ
 g mZ

 ADC  g m2 ( rO6 / / rO8 )g mP RO
 where, RO  RL / / RP / /( RF1 +RF2 )

(b)
Fig. 9 Simulation results of (a) open loop response at different load conditions,
and (b) Relationship between phase margin and load current.

IV. EXPERIMENTAL RESULTS AND DISCUSSION

The LDO regulator has been implemented with a standard
0.18μm CMOS process. The micro-photo of the LDO regulator
with an active core area of 540 × 400 μm2 is shown in Fig. 10.

Fig. 8 Small-signal model of the LDO regulator.

Post-simulation results of the loop behavior are obtained by

using cadence ADE tool, as shown in Fig. 9. The loop gains and
phase margin in different load conditions are shown in Fig. 9(a).
When load current changes from heavy condition to light
condition, ɷPL shifts from high frequency to low frequency.
Phase margin changes with the load current. If the load current
is 150 mA, the open loop gain is 75.9dB, PM is 62.1°and the
gain margin (GM) is 16.2dB. When load current decreases to
1mA, the open loop gain is 89.2dB, PM is 69.2°and GM is Fig. 10 Micro-photo of the LDO regulator.

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The output voltage of the LDO regulator is 2.8 V with an
input voltage range from 2.9V to 3.3 V to guarantee the high
power conversion efficiency. The output capacitor with
capacitance of 1 μF is a low-cost ceramic capacitor. The low
dropout voltage of 100 mV is obtained when the load current is
150 mA.
The measurement results of line regulation, load regulation
and PSRR are shown in Fig. 11, Fig. 12 and Fig. 13,
respectively.Fig.11 shows that the variations of Vout are 0.5 mV,
0.5 mV, 1.2 mV, 1.9 mV and 2.7 mV when Vin changes from
2.9 V to 3.3 V under the current conditions of 1 μA, 1 mA, 50
mA, 100 mA and150 mA, respectively. The calculated line
regulations are 1.25 mV/V, 1.25 mV/V, 3.0 mV/V, 4.75 mV/V
and 6.75 mV/V, respectively. Fig.12 shows that when Vin is 3.3
V, the variations of Vout is 38 mV when load current changes
from 1 mA to 150 mA. The calculated load regulation is 0.25
mV/mA. Fig. 13 shows the measurement results of PSRR,
where the input and output voltage are 3.3 V and 2.8 V,
respectively. PSRR is up to -60 dB when the frequency is less
than 300 Hz with the load current from 1 μA to 100 mA. For the
higher frequency, PSRR for large load will decrease.
Fig. 11 Measured line regulation
Fig. 12 Measured load regulation
Fig. 13 Measured PSRR
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6
The noise spectral densities of noise floor and output of the
LDO regulator in different load conditions are measured, as
shown in Fig. 14. The measurement results show that the output
noise spectral densities are 1.25 μVRMS/ and 5.10
nVRMS/ at 1 kHz and 100 kHz under 0 mA load condition,
respectively, and 1.16 μVRMS/ and 211 nVRMS/ at 1
kHz and 100 kHz under 150 mA load condition. The noise
performance for the 0 mA load condition continues to improve
with frequency, and becomes un-measurable (below the
measurement noise floor) beyond ~50 kHz.
From the results in Fig. 14, we conclude that the noise
performance of the proposed LDO regulator is general but
sufficient for the demand of the designed readout circuit. We
also note that the noise spectral density of this LDO, especially
at heavy load, needs to be further improved if the LDO is used
for ultra-sensitive applications.
Fig. 14 Measured output noise spectral density in extremely load conditions
Fig.15 shows the experiment results of line transient
response. When the input voltage changes from 2.9 V to 3.3 V
and then returns to 2.9 V with transient time of 2μs,the settling
time are 5 μs with 30mV output spike and 6 μs with 20 mV
output spike, respectively
Fig. 15 Measured line transient response waveform
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TABLE I Performance Comparisons

Parameter [3] [6] [8] [12] [13] [14] This work
Technology 0.35 μm 0.18 μm 0.35 μm 0.35 μm 0.35 μm 0.35 μm 0.18 μm
Area 0.044 mm2 0.039 mm2 0.040 mm2 0.226 mm2 0.412 mm2 0.264 mm2 0.216 mm2
Supply voltage 3.3 ~ 3.7 V 1.4 ~ 1.8 V 1.2 V 2V 3.0 ~ 6.0 V 2.0 ~ 5.5 V 2.9 ~ 3.3 V
Output voltage 3.0 V 1.2 V 1.0 V 1.8 V 2.8 V > 1.8 V 2.8 V
1 ~ 10 μF 1 μF
Output capacitor 0.2 ~ 35 μF 0.47 μF 100 pF 0.47 ~ 22 μF 1 μF
ESR: 0.1~0.4Ω (cera. cap.)
Dropout voltage 300 mV 200 mV 200 mV 200 mV 200 mV 200 mV 100 mV
34 mV/V 7.25 mV/V 17 mV/V 4.09 mV/V 1.25 mV/V(no load)
Line regulation N/A 2 mV/V
(full load) (full load) (full load) (full load) 6.75 mV/V(full load)
Load regulation 0.45 mV/mA 0.14 mV/mA N/A 0.1 mV/mA 0.085 mV/mA 0.17 mV/mA 0.25 mV/mA
Max. load 200 mA 50 mA 100 mA 100 mA 100 mA 200 mA 150 mA
3mV/40μs(1mA) 30mV/5μs(100mA)
Line transient N/A N/A N/A N/A N/A
1V step (40μs) 2.9V→3.3V(2μs)
210 mV/ 3 μs 25 mV/ 2 μs 300 mV/ 2.5 μs 55 mV 200 mV/ 40 μs 65 mV/ 60 μs 40 mV/ 20 μs
Load transient
0→110mA 10μA→50mA 0.1mA→100mA(2μs) 0→100mA(50ns) 0→100mA 0→200mA(0.1μs) 0→150mA(0.1μs)
Quiescent 147 (no load) 0.9 (no load) 1.2 (no load) 72 (no load) 20 (no load) 5.2 (no load)
4
current (μA) 314 (full load ) 83 (full load ) 14 (full load) 120 (full load) 340 (full load ) 18.2 (full load )
80 (no load) 2.1 (no load) 159 (light load) 0.04 (no load) 4 (no load) 2 (no load) 2 (no load)
UGBW (kHz)
2000 (full load) 6100 (full load) 186 (heavy load) 250 (full load) 300 (full load) 30 (full load) 450 (full load)
Minimum PM 40° 50° 60° 50° 60° 69° 62.1°
<-20 dB -42 dB -32 dB <-45dB <-50 dB
PSRR N/A N/A
@ 10 kHz @ 1 MHz @ 1 MHz @ 20kHz @ 1kHz
334@ 1 kHz 1250@ 1 kHz(no load)
Output noise 5@ 100 kHz(no load)
65@ 100 kHz N/A N/A N/A N/A N/A 1160@ 1 kHz(full load)
(nVRMS/ ) (no load) 211@ 100 kHz(full load)

Fig. 16(a)-(b) show the measurement waveforms of load

transient response. Fig. 16(a) shows the load current changes
from 10 mA to 75 mA, then to 150 mA, and finally returns to 10
mA with a step-change time of 100 ns. The output spikes are
within 100 mV. Fig. 16(b) shows that when the load current
changes between 0 mA and 150 mA with a step-change time of
1 μs, the output spikes are 75 mV and 40 mV, respectively. The
load transient response of step-down process is longer than that
of step-up process. This is because the regulation transistor
temporarily loses the regulating capability when its current
decreases to 0 mA. The output capacitor releases charges only
through the feedback resistor. Therefore, it requires long
discharge time.
The tested waveforms confirm the good static, dynamic and
(a) loop stability performance of the proposed LDO regulator.
Finally, the performance comparison of this work with previous
published works is summarized in Table I. The merits of
ultra-low quiescent current, wide load range, high loop stability
and low die active area with the high performance of the LDO
regulator are well matched the requirement of very low power
applications for the CZT detectors.

(b)
Fig. 16 Measured load transient response waveforms when (a) load current
changes from 10 mA to 75 mA, then to 150mA, and finally returns to 10 mA,
and (b) load current changes between 0 mA and 150 mA.
V. CONCLUSIONS
In this paper, an extremely low quiescent current, wide load
current range and low chip-area LDO regulator has been
implemented by combining partially controlled load-tracking
and pseudo-ESR compensation techniques. The minimum
quiescent current is only 5.2 μA. The measured waveforms
show that the designed LDO regulator can provide up to 150
mA load current with a stable output voltage of 2.8 V. This
work has seemliest phase margin in full load range with small
quiescent current, which has the benefit to be applied in low
power integrated systems.

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REFERENCE management system design and development. His research interests

[1] A. Brambilla, P. O. Buffet, G. Gonon, J. Rinkel, V. Moulin, C. Boudon,
include analog and mixed-signal integrated circuit design and power
and L. Verger, “Fast CdTe and CdZnTe semiconductor detector arrays for management circuit and system design.
spectroscopic X-ray imaging,” IEEE Transactions on Nuclear Science, Dr. Fan was the recipient of the Science and Technology
vol. 60, no. 1, pp.408-415, Feb. 2013. Improvement Award, by Shaanxi municipal government in 2015, and
[2] J. Luo, Z. Deng, G. Wang, C. Cheng, and Y. Liu, “Design of a low noise the twice recipients of the Lam Research Thesis Award, by Lam
readout CdZnTe detector,” in Proc. IEEE Nuclear Science Symposium Research Corporation in 2015.
and Medical Imaging Conference, Nov. 2012, pp.4098-4101.
[3] J. Wang, D. Y. Gao, C. H. Guo, K. Jaaskelainen, and Y. Hu, “A High
Load Current, Low-Noise, Area-Efficient, Full On-Chip Regulator for
CMOS Pixel Sensors,” IEEE Transactions on Nuclear Science, vol. 59,
no. 3, pp.582-588, Jun. 2012.
[4] G. A. Rincon-Mora, and P. E. Allen, “A low-voltage, low quiescent
Haiqi Li received the B.Sc. degree in
current, low drop-out regulator,” IEEE J. Solid-State Circuits, vol. 33, no. integrated circuit design and integrated system
1, pp.36–44, Jan. 1998. from Shandong University, Jinan, China, in
[5] C. H. Huang, Y. T. Ma, and W. C. Liao, “Design of a low-voltage 2010, and received the M. Sc. Degree in
low-dropout regulator,” IEEE Trans. Very Large Scale Integr. (VLSI) microelectronics from Xi'an Jiaotong
Syst., vol. 22, no. 6, pp.1308–1313, June 2014. University, Xi'an, China, in 2014.
[6] A. Maity, and A. Patra, “Design and analysis of an adaptively biased Since 2014, he has been with GalaxyCore
low-dropout regulator using enhanced current mirror buffer,” IEEE Trans. Inc., Shanghai, China, as an R&D Engineer,
Power Electron., vol. 31, no. 3, pp.2324–2336, Mar. 2016.
[7] K. C. Kwok, and P. K. T. Mok, “Pole-zero tracking frequency
where he has been involved in the development
compensation for low dropout regulator,” in Proc. IEEE International of power management ICs. His current research interests include high
Symposium on Circuits and Systems, May. 2002, pp.735-738. accuracy bandgap reference, LDO regulator and chip ESD design.
[8] X. Qu, Z. K. Zhou, B. Zhang, and Z. J. Li, “An ultralow-power
fast-transient capacitor-free low-dropout regulator with assistant
push-pull output stage,” IEEE Trans. Circuits Syst. –II: Exp. Briefs, vol.
60, no. 2, pp.96–100, Feb. 2013.
[9] M. Ho, J. Guo, K. H. Mak, W. L. Goh, S. Bu, Y. Zheng, X. Tang, and K.
N. Leung, “A CMOS low-dropout regulator with dominant-pole Zhuoqi Guo received the B.Sc. degree in
substitution,” IEEE Trans. Power Electron., vol. 31, no. 9, pp.6362–6371, microelectronics from Xi’an Jiaotong University,
Sep. 2016. Xi’an, China, in 2011, where he is currently
[10] K. N. Leung, and P. K. T. Mok, “A capacitor-free CMOS low-dropout working toward the Ph.D. degree in the
regulator with Damping-Factor-Control Frequency Compensation,” IEEE Department of Microelectronics.
J. Solid-State Circuits, vol. 38, no. 10, pp.1691–1702, Oct. 2003.
[11] S. Q. Fan, Z. M. Xue, H. Lo, Y. Song, and L. Geng, “Area-efficient
From 2011 to 2013, he was with Realsil
on-chip DC-DC converter with multiple-output for bio-medical Microelectronics Co., Ltd., Suzhou, China, as a
applications,” IEEE Trans. Circuits Syst. –I: Reg. Papers, vol. 61, no. 11, layout engineer. His research interests include
pp.3298–3308, Nov. 2014. power management circuits and systems.
[12] K. N. Leung, and Y. S. Ng, “A CMOS low-dropout regulator with a
momentarily current-boosting voltage buffer,” IEEE Trans. Circuits Syst.
–I: Reg. Papers, vol. 57, no. 9, pp.2312–2319, Sep. 2010.
[13] T. F. Kwok, and W. H. Ki, “A stable compensation scheme for low
dropout regulator in the absence of ESR,” in Proc. IEEE European
Solid-State Circuits Conference, Sep. 2007, pp.416-419.
[14] M. Al-Shyoukh, H. Lee, and R. Perez, “A transient-enhanced low Li Geng (M’06) received the B.Sc. degree in
quiescent current low-dropout regulator with buffer impedance physics and M.Sc. and Ph.D. degrees in electrical
attenuation,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp.1732–1742,
Aug. 2007.
engineering from Xi’an University of technology,
[15] C. C. Zhan, and W. H. Ki, “Output-capacitor-free adaptively biased Xi’an, China, in 1990, 1998 and 2001,
low-dropout regulator for system-on-chips,” IEEE Trans. Circuits Syst. –I: respectively.
Reg. Papers, vol. 57, no. 5, pp.1017–1028, May. 2010. From November 1999 to June 2000, she was a
[16] T. Y. Man, P. K. T. Mok, and M. Chan, “A high slew-rate push-pull Visiting Scholar with the Department of
output amplifier for low-quiescent current low-dropout regulators with Electrical Engineering, Ilmenau University of
transient-response improvement,” IEEE Trans. Circuits Syst. –II: Exp. Technology, Germany. From August 2007 to
Briefs, vol. 54, no. 9, pp.755–759, Sep. 2007. August 2008, she was a Visiting Professor with the Department of
[17] P. Y. Or, and K. N. Leung, “An output-capacitorless low-dropout
regulator with direct voltage-spike detection,” IEEE J. Solid-State
Electrical Engineering, Stanford University, CA, USA. She is
Circuits, vol. 45, no. 2, pp.458–466, Feb. 2010. currently a Professor in the Department of Microelectronics, Xi’an
[18] P. E. Allen, and D. R. Holberg, “CMOS analog circuit design,” published Jiaotong University. She also serves as the director of the Department
by Oxford University Press Inc., Second Edition, pp.101-102, 2002. of Microelectronics, Xi’an Jiaotong University. Her current research
[19] R. J. Baker, “CMOS circuit design, layout, and simulation,” published by interests include power management integrated circuits, low-voltage
A John Wiley & Sons, Inc., Third Edition, pp.131-160, 2010. low-power analog and mixed-signal integrated circuits, RF integrated
circuit, and bio-implant systems.
Dr. Geng was a Technical Program Committee Member of ASSCC
Shiquan Fan (S’13) received the B.Sc. degree, from 2010 to 2016. She was the recipient of the Science and
the M.Sc. degree and the Ph.D. degree in Technology Improvement Award, by Ministry of National Mechanical
microelectronics from Xi’an Jiaotong University, Industry, China, in 1999, and the recipient of the Science and
Xi’an, China, in 2003, 2009 and 2014, Technology Improvement Award, by Shaanxi municipal government
respectively, where he is currently an assistant in 2000, 2001, 2010 and 2015, respectively.
professor in the School of Microelectronics.
From spring 2003 to winter 2006, he was
working as an R&D Engineer for power

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