Mat. Res. Soc. Symp. Proc. Vol.

710 © 2002 Materials Research Society

Wafer Bonding using Dielectric Polymer Thin Films in 3D Integration

Y. Kwon, J.-Q. Lu, R. P. Kraft, J. F. McDonald, R. J. Gutmann and T. S. Cale

Focus Center - New York, Rensselaer: Interconnections for Gigascale Integration
Rensselaer Polytechnic Institute, Troy, New York 12180

ABSTRACT

A key process in our approach to monolithic three-dimensional (3D) integration is the

bonding of 200-mm wafers using dielectric polymer thin films as bonding glues. After
discussing the desired properties of polymer thin films, we describe how bonding
protocols are evaluated using silicon and glass wafers. After bonding, the fraction of
bonded area was inspected optically and a razor blade method was used to indicate
bonding strength. Thermal stability and bonding integrity were evaluated using thermal
cycling and backside grinding and polishing. To date, we have studied benzocyclobutene
(BCB), FlareTM, and methylsilsesquioxane (MSSQ) and Parylene-N as bonding glues.
Wafer pairs bonded using BCB showed a larger fraction of bonded area, and those using
Flare indicated higher thermal stability. Both BCB and Flare glues provided good
bonding integrity after backside grinding tests. Changes in the chemical structures of
BCB and Flare glue during bonding were analyzed using FTIR in order to understand the
bonding mechanism and to improve the bonding process.

INTRODUCTION

Wafer bonding using dielectric polymer thin films as bonding glues is an important
step in the process flow we use to fabricate three-dimensional (3D) ICs with active
devices stacked in multiple layers. A schematic of 3D chip stacking using wafer bonding,
thinning and inter-wafer interconnection is presented in Figure 1. Wafers stacked in this
way can be fabricated with different unit processes and different wafer materials; hence,
heterogeneous integration can be realized. This 3D technology may alleviate Cu/low-k
interconnect bottlenecks and performance limitations of planar ICs caused by long wires
[1]; i.e., interconnect delay can be reduced, and chip performance and functionality can
be increased [1-4]. In addition, highly integrated systems may be realized using this 3D
IC technology, e.g., hard intellectual property core-based implementations, and high-
speed digital systems like application specific ICs or systems-on-a-chip [1,4]. For
example, memory devices or image processing devices can be stacked with logic devices.
In this paper we report on the silicon-to-glass wafer bonding using polymer thin
films. Bonding studies on silicon and glass wafers are being used to evaluate proposed
bonding protocols. The process technology developed in this work can be transferred to
bonding of wafers made of other materials (e.g., silicon-to-silicon, SiO2-to-SiO2, silicon-
to-compound semiconductor).

3D IC STRUCTURE AND BONDING GLUE PROPERTIES

Figure 2 shows an illustration of our 3D approach, which uses wafer bonding and
copper damascene patterning for inter-wafer interconnection. Here, three wafers with ICs

DD12.18.1
 Via Bridge Via Plug
Wafers 3-D Chip Dielectric
Sequentially Substrate
align, bond, Stack 3rd Level
Device
Surface
I/Os, A/Ds, sensors (Thinned
and glue logic thin and Substrate) Multi-Level
Interconnects
interconnect Bond
Dielectric (Face-to-back)
Memory Substrate
Dice 2nd Level
Device
Surface
(Thinned
Substrate) Multi-Level
Interconnects
I/Os, A/Ds, sensors
Processor/Logic and glue logic Bond
(Face-to-face)
Multi-Level
1st Level Interconnects
Device
Surface
Figure 1. 3D integration can be used to Substrate

combine wafers which are processed at Figure 2. 3D integration concept using

different conditions, and which have wafer-bonding, showing glue layers,
different functionalities. This allows vertical vias (plug- and bridge-type), and
heterogeneous systems to be fabricated, and bonding approaches of "face-to-face" and
hard IP core based implementations. "face-to-back".

are bonded/stacked together, either face-to-face (second level to first level) or face-to-
back (third level to second level). Multilevel interconnects and bonding/thinning are also
depicted in this illustration. Glue layers are used in every wafer-to-wafer bond to enhance
adhesion. Short, vertical, high aspect ratio (HAR) vias (plug- and bridge-type) replace the
long distance interconnects. After aligning and bonding the initial two wafers, the top
wafer should be thinned and planarized. This is followed by inter-wafer interconnection
using copper damascene patterning including HAR via etching and filling, and the
damascene patterning process is finalized by chemical-mechanical planarization (CMP).
To maximize potential circuit performance using the 3D approach, the wafer
alignment accuracy must be in the range of microns, i.e., close to typical feature sizes in
the back-end-of-the-line (BEOL) process. An EVGroup (EVG) EV640 SmartViewTM
Aligner is used to provide 1 to 2 µm alignment accuracy with 200-mm wafers, as we
have shown previously [5]. Inter-wafer vias with small diameters and short lengths are
also required. Thus, the backside of the top wafer must be thinned to about 10 µm and
leveled after wafer bonding. We have thinned the top wafers to 50 µm with good bonding
integrity results, but bonding defects and inter-wafer edge effects presently prevent
thinning to the desired 10 µm range. Several options for wafer thinning are being
explored.
The four major process steps in our 3D integration, i.e., wafer alignment, bonding,
thinning and inter-wafer vias should be compatible with conventional BEOL processes
and final packaging process. We focus on wafer bonding in this paper.
The polymer thin films used in 200 mm wafer bonding should have a uniform
thickness over the entire area, and properties compatible with subsequent processes such
as thinning and via interconnection as well as conventional BEOL processes. The desired
properties of polymer glues include: (1) good adhesion to prevent interface delamination
and void/defect propagation; (2) capability of thin film deposition to minimize inter-
wafer via aspect ratio; (3) modest processing temperatures and bonding pressures to
avoid degrading performance and reliability of the device wafer; and (4) thermal and
mechanical stability to survive against the impact of subsequent processes [6]. The
candidates currently under evaluation for bonding glue are spin-on amorphous polymers,

DD12.18.2
such as benzocyclobutene (BCB), FlareTM, and methylsilsesquioxane (MSSQ) and semi-
crystalline polymer as Parylene-N. These materials have good cleanroom process
capability with relatively good chemical and physical properties for wafer bonding.
Unlike other wafer bonding technologies, our bonding process using polymer thin films
does not involve high temperature, high pressure and/or electrical bias. Therefore, it is
compatible with conventional IC fabrication processes.

EXPERIMENT AND RESULTS

Wafer bonding is conducted in an EV501 wafer bonder manufactured by EVG. Prior

to the bonding process, top and bottom wafers are pre-cleaned, spin-coated with polymer
glue materials (except Parylene-N) by a FlaxiFabTM spin coater and baked on a hot plate
with nitrogen flow. Parylene-N is vapor-deposited on the wafer in a SCS multi-wafer
deposition system (PDS 1050). The wafers are placed face-to-face on a bond chuck,
separated by three spacers, clamped by two clamps and loaded into the wafer bonder. The
bonding process starts with a pump-down to 10-4 mbar, and heating the bonder chuck to a
given temperature with the wafers separated by the spacers. The bond is started by
pressing in the middle of the top wafer to create an initial contact, while allowing the
spacers to be removed. Upon removal of the spacers, a uniform bonding down pressure is
applied over the wafer pair. The wafer pair is then further heated to complete the bonding
process. Finally, the wafers are slowly cooled and unloaded.
In the 3D integration process, processed wafers are first aligned in the EV640 aligner
prior to loading in the bonder chamber. During the alignment, spacers are used to
separate the two wafers. The pump-down minimizes oxidization of the polymer glue and
decreases the possibility of capturing air between glue-to-glue gaps, which can be a
reason for void generation. The down pressure is applied to minimize any gaps between
the glue layers on the top and bottom wafers, and to facilitate the cross-linking and
intermixing reactions of glues. Curing (the cross-linking network formation or the
intermixing of polymer chains) is the defining step of the wafer bonding, i.e., it provides
the bond between the two wafers. A holding time is needed during the bonding process to
form a completely cured structure. A slow cool-down process is important to minimize
debonding due to stresses generated by CTE differences between the polymer glue and
wafers.
After bonding, optical inspection is used to evaluate alternative glues and process
conditions through the glass wafer of the bonded silicon-to-glass wafer pair. The bond
strength is evaluated qualitatively using a razor blade to attempt to separate the wafers.
Our experiments show that the fraction of bonded area and the bond strength mainly
depend on the pre-clean method, the applied bonding pressure and the pressure vs. time
protocol. Particles and defects also influence the bonding results.
Good bonding results have been obtained with BCB or Flare glue. Other glues studied
so far have problems, such as a small fraction of bonded area (MSSQ) or weak bonding
strength (Parylene-N) [7]. Figures 3 and 4 show photos of bonded wafers (200-mm p-
type (100) prime silicon wafer to Corning 7740 glass wafer) using Flare and BCB,
respectively. While the quality is good, some issues related to the bonding are: (1) void
generation due to outgassing of the remaining solvent and/or by-product created during
the curing process; (2) void or bonding defect generation due to particles or polymer

DD12.18.3
Figure 3. Wafer bonding result using Figure 4. Wafer bonding result using
Flare (silicon-to-glass). BCB (silicon-to-glass).

structural defects; and (3) wafer bow caused by residual stress.

As can be seen from Figures 3 and 4, BCB is the better bonding glue (to date). After
baking, the thickness of BCB per wafer is 1.43 µm, and that of Flare per wafer is 0.33
µm. Small particles on the wafer surface are more likely to be buried by the thick BCB
film than the thinner Flare film. In addition, the BCB can reflow more than Flare since
BCB has higher cross-linking density; the active reflow property of BCB can fill the
empty spaces around particles. The reflow property of BCB can be observed by the
change of edge bead area during bonding. In the spin-on process, the glue on the wafer
edge bead is removed to avoid cross-contamination. This edge bead using BCB almost
disappeared during bonding, i.e., BCB reflows out to fill the edge-bead (see Figure 4).
These effects may explain why using BCB leads
to a larger fraction of bonding area than when
Flare is used.
The introduction of an adhesion promoter in
the spin-on process may influence the bonding
result using Flare. An adhesion promoter was not
used in our previous bonding experiments with
Flare, but was used with BCB. Both BCB and
Flare are hydrophobic, while the glass wafer and
native oxide of the silicon wafer are hydrophilic.
Since the adhesion promoter has both hydrophobic
and hydrophilic properties, adhesion at the
interface between the wafer and glue is increased.
The increased adhesion reduces the non-bonded
area at the interface. Figure 5 shows the result of Figure 5. Result of wafer bonding
enhanced Flare bonding with an adhesion when using an adhesion promoter
promoter (compare to Figure 3). Therefore, the used in addition to Flare. The
introduction of adhesion promoter may be an fraction of bonded area is better than
effective way to improve the fraction of bonded that of Figure 3 except for the edge
area in Flare bonding. bead area.
DD12.18.4
 Another major discrepancy between bonding glues of BCB and Flare is the range of
thermal stability temperature: 350 oC for BCB and greater than 400 oC for Flare. Flare
has better thermal stability than BCB because of its higher glass transition temperature.
Some of the pairs bonded with BCB or Flare underwent a mechanical stress test
(mechanical grinding and CMP) in order to evaluate the bonding integrity. After grinding
and CMP of the top-wafer to ~50 µm, the wafer pair bonded using BCB shows no change
in defect structure, while that using Flare has a little change in defect structure. Further
study of the effect with alternative thinning processes is in progress.
BCB has a very rigid structure due to extensive cross-linkable groups. The cross-
linking reaction starts from opening of side rings of arylcyclobutenes, the end groups of
the BCB monomer. Opened side rings produce orthoxylylenes as reactive intermediates
and the intermediates react with vinyl groups through Diels-Alder reactions in the range
of 150-300 oC. The high density of cross-linking groups accounts for the desired active
reflow described previously [8].
Flare is non-fluorinated poly aryl ether. The cross-linking reaction during the curing
process and the inclusion of many aromatic groups increase the film rigidity and thermal
stability [9]. Thus, active reflow during bonding is not significant.
Fourier Transform Infrared Spectroscopy (FTIR) was used to help understand the
bonding mechanism in terms of surface chemical structure. Figures 6 and 7 show FTIR
spectra for BCB and Flare, respectively. The BCB FTIR spectra indicate that BCB
monomers are fully cross-linked; the absence of benzene side ring peak and the
production of an aliphatic C-H peak during the wafer bonding process [6]. Flare FTIR
spectra show the complete removal of solvent as the cyclohexanone peak disappeared
after the bake process [10].

CONCLUSIONS

Wafer bonding using dielectric polymer glues is one of the key processes for
achieving our monolithic 3D chip integration. We demonstrated 200-mm wafer bonding
using polymer glues with processes compatible with conventional BEOL processes and
subsequent inter-wafer interconnection and packaging processes. Compared with other
glues, the wafer pairs bonded using BCB or Flare showed better bonding results. The

Top : As-spun
Top : Before bond Middle : After baking
Transmittance (A.U.)

Bottom : After bond Bottom : After curing

Transmittance (A.U.)

3000 2500 2000 1500 1000 500 3000 2500 2000 1500 1000 500
-1 -1
Wavenumbers (cm ) Wavenumbers (cm )

Figure 6. FTIR spectra of BCB before and Figure 7. FTIR spectra of Flare as spun,
after curing/bonding. after baking and after curing/bonding.
DD12.18.5
optical inspection of bonded wafers indicated the bonding using BCB had the larger
fraction of bonded area, while thermal cycle tests showed bonding using Flare had higher
thermal stability. Both BCB and Flare glues provided good bonding integrity after
backside grinding and CMP. FTIR analysis of BCB and Flare was used to evaluate
changes in chemical structure during the bonding process. As a result, solvent
evaporation during the baking process (Flare) and hard cross-linking during the bonding
process (BCB) were detected. More detailed thermal, mechanical and spectroscopic
analyses of the bonding glue are needed to understand the wafer bonding mechanism
using polymeric glues.

ACKNOWLEDGMENTS

This work is sponsored by DARPA, MARCO and NYSTAR through the Interconnect
Focus Center. We acknowledge the contributions of other 3D program participants at
Rensselaer and the University at Albany.

REFERENCES

1. J.-Q. Lu, A. Kumar, Y. Kwon, E.T. Eisenbraun, R.P. Kraft, J.F. McDonald, R.J.
Gutmann, T.S. Cale, P. Belemjain, O. Erdogan, J. Castracane, A.E. Kaloyeros, in
Advanced Metallization Conference in 2000 (AMC 2000), p. 515, Vol. V16 from the
MRS Conference Proceedings Series (Conf. at San Diego, CA, October 3-5, 2000),
Eds. D. Edelstein, G. Dixit, Y. Yasuda and T. Ohba, Spring 2001.
2. A. Rahman, A. Fan, J. Chung, and R. Reif, in Proceedings of 1999 International
Interconnect Technology Conf. (IITC), p. 233, May 1999, San Francisco, CA.
3. K.W. Lee, T. Nakamura, T. One, Y. Yamada, T. Mizukusa, H. Hasimoto, K.T. Park,
H. Kurino and M. Koyanagi, in International Electron Devices Meeting (IEDM), p.
165, CA, Dec. 2000.
4. R.J. Gutmann, J.-Q. Lu, R.P. Kraft, P.M. Belemjian, O. Erdogan, J. Barrett, and J.F.
McDonald, in DesignCon 2001: Wireless and Optical Broadband Design
Conference, CA, February 2001.
5. J.-Q. Lu, Y. Kwon, R.P. Kraft, R.J. Gutmann, J.F. McDonald, and T.S. Cale, in IEEE
International Interconnect Technology Conference (IITC), p. 219, CA, June 2001.
6. Y. Kwon, J.-Q. Lu, R.J. Gutmann, R.P. Kraft, J.F. McDonald and T.S. Cale, in Sixth
International Symposium on Semiconductor Wafer Bonding: Science, Technology,
and Applications, at 2001 ECS/ISC, San Francisco, CA, 2001.
7. J.-Q. Lu, Y. Kwon, R.P. Kraft, R.J. Gutmann, J.F. McDonald, and T.S. Cale, in
International Conference on Dielectrics and Conductors for ULSI Multilevel
Interconnection (DCMIC), CA, March 2001.
8. R.W. Johnson, T.L. Phillips, W.K. Weidner, S.F. Hahn, D.C. Burdeaux, and P.H.
Townsend, IEEE Trans. Comp., Hybrids, Manuf. Technol., 13, 347 (1990).
9. N.H. Hendricks, K.S.Y. Lau, A.R. Smith, and W.B. Wan, Mater. Res. Soc. Symp.
Proc., Vol. 381, p. 59, 1995.
10. R.J. Gutmann, J.-Q. Lu, Y. Kwon, J.F. McDonald and T.S. Cale, in 1st International
IEEE Conference on Polymers and Adhesives in Microelectronics and Photonics,
Potsdam, Germany, October 2001.

DD12.18.6