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A phase difference between the two input signals results in a dc voltage Vd,
which is proportional to the phase difference, θ e = θ i-θ o .
If the input signals are both square-waves, the phase detector characteristic
will be linear, as illustrated in Figure 10-7. The gain of this circuit is constant over the
range of input θ e = +π /2 and is given by kφ = Vd/θ e = A/(π /2). That is,
2 A volts
kφ = (10-4)
π radian
Figure 10-7. Phase comparator characteristic for square-wave
inputs.
As illustrated for the circuit of Figure 10-10, the RS-FF phase detector can
produce a linear PLL over a full θ e range of 2π rad, which is twice that for the other
phase detectors. The problem with using digital phase detectors in sensitive
communication receiver applications is in the difficulty of filtering the sharp impulses
and their harmonics to prevent radio-frequency interference (RFI).
In Figure 10-14, with the VCO input grounded and Vo = 0, measurements will
show that fi = fFR. However, if f i ≠ f FR , then the beat is observed at Vo. When the
switch is closed, the beat-frequency signal at Vo will cause the VCO frequency fo to
change. If the voltage is large enough (high loop gain) and the filter bandwidth wide
enough, then the VCO will be deviated from fFR and lock at the instant that fo = fi .
The amount by which the VCO frequency must be changed is ∆ f = fi - fFR. The time
required for the loop to lock depends on the type of loop and loop dynamics. For the
simplest PLL with no loop filter, this acquisition time is on the order of 1/kv seconds.
Also, the range of fi over which the loop will lock, the lock range, is equal to the
hold-in range for the simple PLL.
When the loop is locked we know that fo = fi. Only a phase difference
between the signal and the VCO can exist. This phase difference θ e = θi-θ o is
called the static (dc) phase error. θ e is the input to the phase detector when the loop
is locked and is required in order for the phase detector to produce a dc output
voltage Vd which, when amplified by the dc amplifier, will produce exactly enough Vo
to keep the VCO frequency deviated by ∆ f. If fi increases, then ∆ f increases and θ e
must increase in order to provide for more Vo to keep the VCO tracking fi. The
definition of locked is that fi = fo and the loop will track any change in fi. Any
subsequent shift of θ i or θ o will be tracked-out so that only θ e remains.
Hold-In Range
The range of frequencies for fi over which the loop can maintain lock is
called hold-in range. Assuming that the amplifier does not saturate and the VCO has a
wide frequency range, the phase detector characteristic limits the hold-in range. It
should be clear from the phase detector characteristics (Figures 10-6 and 10-7) that,
as the static phase error increases due to increasing fi, a limit for Vd is reached beyond
which the phase detector cannot supply more voltage for VCO correction. The phase
detector simply cannot produce more than A volts. The total range of Vd is ±A = 2A,
so that the total range of θ e is π radians. From Equation 10-7, the minimum to
maximum input frequency range, fi(max) - fi(min) = ∆ fH, will be
∆ fH = π kL
or
∆ fH = kv / 2 (10-9)
The edge-triggered R-S flipflop phase comparator of Figure 10-9 can provide twice
this, ∆ fH = kv.
Loop Gain and Static Phase Error
The locked PLL is seen in Figure 10-16. The phase comparator develops an
output voltage Vd in response to a phase difference between the reference input and
the VCO. The transfer gain kφ has units of volts/radian of phase difference. The
amplifier shown is wideband with a voltage gain of kA volts/volt (dimensionless).
Thus, Vo = kAVd.
The VCO free-running frequency is fFR. The VCO frequency fo will change in
response to an input voltage change. The transfer gain ko has units of kHz/V. The loop
gain for this system is simply the gain of each block multiplied around the loop, thus
kL = kφ .kA.ko (10-6)
The units of kL are (V/rad).(V/V).(kHz/V) = kHz/rad.
Assume that a signal with frequency fi is an input to the phase detector, and
the loop is locked. If the frequency difference before lock was ∆ f = fi - fER, then a
voltage Vo = ∆ f / ko is required to keep the VCO frequency equal to fi. So the phase
comparator must produce Vd = Vo/kA = ∆ f / kokA, and the static phase error θ e = θ i
Solution:
1. k A = ( R f / R1 ) + 1 = 4 k/1k + 1 = 5.
2. k L = k φ k A k 0 = 0.1 V/rad x 5 x (-30 kHz/V) = -15x103(Hz/rad). Then, kv = 15x103
cycles/s-rad x (2π rad/cycle) = 94.3 k sec-1, and kv(dB) = 20 log kv =
20log(94.3x103) = 99.5dB at 1 rad/s.
3. Vo will be a sinusoidally varying voltage with a frequency of |fi – fFR| = 10 kHz.
This assumes that a very small capacitor internal to the phase comparator filters
out fo, fi and fo + fi.
4. (a). When the loop is locked, fo = fi = 100 kHz by definition of locked, and only a
phase difference can exist between the input signal and VCO. This phase
difference θ e is the loop-error signal (static phase error) which results in Vd at the
detector output and, when amplified by kA, provides enough voltage Vo to make the
VCO frequency be exactly equal to fi.
(b). The free-running frequency of the VCO is 110 kHz. In order for the VCO to
equal 100 kHz, the VCO input voltage must be Vo = (100 kHz -110 kHz)/ko = 10
kHz/(-30 kHz/V) = 0.33Vdc. Then, because kA = 5, Vd must be Vd = 0.33V/5 =
0.0667V. Finally θ e = Vd/kφ = 0.0667V/0.1V/rad = 0.667 rad. Once again, we
have derived the basic relationship, θ e = ∆ f/kL = (fi - fER)/kL = -10 kHz/(-15x103
Hz/rad) = 0.667 rad.
(c). The input to the phase detector (loop-locked) was determined from θ e =
∆ f/kL = 0.667 rad. Since Vd = kφ θ e, we have Vd = 0.1 V/rad x 0.667 rad =
0.0667Vdc. Now, we are assuming Zin of the op-amp is much larger than R of the
loop filter, so there is no voltage drop across R. The input to the op-amp is
0.0667Vdc, so that Vo = kAVd = 5 ×0.0667Vdc = 0.33Vdc. This is enough to keep the
VCO at 100 kHz when in fact its rest frequency is 110 kHz.
5. The question is, when the loop is locked, how much can fi change in frequency
before the loop just cannot provide enough Vo to keep the VCO at fo = fi? Assuming
that the VCO and dc amplifier don't saturate, we look at the phase detector
characteristic. Clearly Vd can increase with θ e until Vd ---> Vmax = A, at which point
θ e = π /2. Beyond this, Vd decreases for increasing static phase error, and the
phase detector simply cannot provide more output voltage to continue increasing fo,
and the loop breaks lock. The total hold-in range is +2π , or π rad. The frequency
difference between these break-lock points will be ∆ fH = θ e(max) x kL = π x 15
kHz/rad = 47.1 kHz.
6. At the frequency where θ e = π /2, we have Vd(max) = A. Therefore Vd = kφ θ e =
0.1 V/rad × π/2 rad = 0. 157Vdc.
FM and FSK APPLICATIONS of PLLs
When a PLL has locked to an input signal, the VCO will follow slow changes
in the input signal frequency fi. Suppose fi increases by an amount ∆ fi. In order for
the loop to remain locked (fo - fi), the VCO voltage must increase by ∆ Vo = ∆ fi/ko.
This voltage change is produced by the amplified change in Vd, which is produced by
an increased phase difference, ∆ θ e = 2π ∆ fi/kv.
As a specific example, suppose that an FM signal with carrier frequency fi is
modulated to an index of mf = 4 by a 1-kHz sinusoid. The carrier frequency will be
deviated above and below fi by an amount ∆ fi = mffm = 4 ×1 kHz = 4 kHz pk. If this
FM signal is the input to a PLL with a VCO gain of ko = 10 kHz/V and loop
bandwidth 1 kHz, then the VCO input voltage Vo will be a 1-kHz sinusoid with a
peak amplitude of ∆ Vo = ∆ fi/ko = (4 kHz pk)/(10 kHz/V) = 400 mV pk.
NOISE MARGIN
To get a quantitative idea of the loop noise margin, consider the results of
Example 10-3 as seen in Figure 10-23b. The output voltage Vo is 2V for a transmitted
MARK. How high can Vo rise on a noise transient caused by a deviation of the
MARK frequency or circuit variations of Vo before the loop breaks lock? The static
phase error when fi = fM = 2 kHz is θ e = ∆ f/kL = (2 kHz - 3.5 kHz)/(1.19 kHz/rad) =
1.26 rad. However, for typical phase detector's, the loop will break lock if θ e exceeds
π /2 = 1.57 rad. Consequently loop transients that would cause θ e to increase by
0.31 rad will result in a loss of lock. In terms of voltages, Vd(max) = kφ θ e(max) =
(0.3184 V/rad) × (1.57 rad) = 0.5V and Vo(max) = 5 ×0.5 = 2.5V. Since Vo(MARK) =
2V and we-have calculated Vo(max) = 2.5V, we see that the noise margin for Vo will
be Vo(NM) = 0.5 Vpk. This can result from noise in the PLL itself, from the noise
input signal-amplitude if no limiter precedes the PLL or from an input signal
frequency deviation (due to noise) of ∆ fi(NM) = ko x Vo(NM) = (0.75 kHz/v) x
(0.5Vpk) = 375 Hz peak noise.
EXAMPLE:
A PLL with ko = -0.75 kHz/V, fFR = 3.5 kHz, kφ = 0.3184 V/rad, and kA = 5 is
used as an FSK demodulator. The input signal has fS = 4 kHz, fM =2 kHz, and the
modulation is shown in Figure 10-23a. As seen, the baud rate is 1333 bits/s and the
data is …1 0 0… Sketch accurately the PLL output Vo(t).
Solution:
For fi = fM = 2 kHz, Vo = ∆ fo/ko = (fi–fFR)/ko = (2 kHz – 3.5 kHz)/(-0.75 kHz/V)
= +2V. For fi = fS = 4 kHz, Vo = (4 kHz – 3.5 kHz)/(-0.75 kHz/V) = -0.67V. The loop
time constant is τ =1/kv = 1/(0.75 kHz/V)(0.3184 V/rad)(5)(2π rad/cycle) = 1/7502
= 0. 133 ms. It takes 0.133 ms for Vo to rise from -0.67V to 63% of the total voltage
range 2V - (-0.67V) = 2.67V. 63% of 2.67V is 1.69V, so at time τ , Vo = 1.69V -
0.67V = 1.02V (see the plot of Vo in Figure 10-23b).
Figure 10-23. FSK input (a) and demodulated output (b) of PLL.
Figure 8.3-6. PLL frequency multiplier.
∆ f = 0. Suppose further that the PLL has sufficient loop gain to track the
input phase φ (t) within a small error ε(t ) , so sin ε (t ) ≈ ε (t ) = φ(t ) −φv (t ) . These
suppositions constitute the basis for the linearized PLL model in Fig. 8.3-8a,
where the LPF has been represented by its impulse response h(t).
Since we’ll now focus on the phase variations, we view φ (t) as the
input “signal” which is compared with the feedback “signal”
t
φv (t ) = 2πK v ∫ y (λ)dλ
to produce the output y(t). We emphasize that viewpoint by redrawing the linearized
model as a negative feedback system, Fig. 8.3-8b. Note that the VCO becomes an
integrator with gain 2π Kv while phase comparison becomes subtraction.
The most frequency used technique for frequency synthesis is the indirect
method utilizing a voltage-controlled oscillator in a programmable PLL. The simplest
system is the one-loop synthesizer of Figure 10-39, consisting of a digitally
programmable divide-by-N circuit used to divide the VCO Output frequency for
comparison with a stable reference source.
The divider can be a simple integer divider such as the 74192 programmable
up-down counter, or noninteger divider systems such as the fractional-N method
(producing fo = (N+1/M)fref) and the two-modulus prescaler circuit of Figure 10-44,
the MC12012, for example, using a technique called pulse swallowing. For our
purposes, only integer dividers are considered.
The loop gain for the simple PLL synthesizer of Figure 10-39 is
kφ k o
kL = (10-27)
N
it is important to realize that the frequency-divider circuit reduces the loop gain so
that the other loop components need to have relatively higher gain than the
conventional PLL. A more troublesome design problem, however, is that, as N
changes, so does the loop gain. There are linearizer circuit to ameliorate this problem.
Figure 10-40 shows the use of a very high frequency prescaler in a one-loop
synthesizer used for push-button TV channel selection. The VHF local oscillator
(LO) frequency is greater than 100 MHz, so high frequency emitter-coupled logic
(ECL) dividers are used to prescale the VHF signal below 1 MHz, where low-cost
TTL or CMOS technology can be used. The prescaler will reduce the resolution by an
amount equal to the prescale division ration P. Hence,
Resolution = Pfref (10-28)
with a prescaler.
EXAMPLE:
The microprocessor-controlled VHF LO synthesizer of Figure 10-40 has a
phase comparator with kφ = 1 V/rad and an output impedance of 3.5 kΩ. Determine
the following:
1. fref.
2. N for the TV to receive channel 5 (fLO = 123.000 MHz).
3. The synthesizer frequency resolution.
4. Loop gain and value of capacitor to compensate the loop to δ = 0.5 and have
the VCO frequency within ± 10 % of its specified value in less than 10 ms
after selection of channel 5. (Assume that the maximum frequency step at the
phase detector is within the loop bandwidth.)
5. What value must the VCO sensitivity be?
Solution:
1. fref = fXO/3580=3583.5 kHz/3580 = 1.00098 kHz.
2. f 0 = 256 N ref , therefore N = 123.000 MHz/[(256)(1.00098 kHz)] = 480.
3. With the prescaler, the resolution will be Pfref = 256fref = 256.25 kHz. To prove
this, change the programmable divider to N+1 = 481, and compare the new fo to
the old.
fo(N + 1) =1.00098 kHz × 256 × 481 =123,256.67 kHz
fo(N) = 1.00098 kHz × 256 × 480 = 123,000.42 kHz
Resolution: fo(N + 1) – Nfo = 256.25 kHz.
4. With the assumption stated, the loop will lock up unaided (without frequency
sweep circuitry); hence, we use the universal overshoot and ringing curves of
Figure 10-27. Vo must stay within relative values 0.90 and 1.1 (+10 %) on the δ
= 0.5 curve. This is satisfied by ω nt = 4.6. With t = ts = 10 ms, we need the loop
to have ω n = 4.6/10 ms = 460 rad/s. Since δ = 0.5 ωc / k v , then ω c = kv for δ =
0.5. Also ωn = ωc k v , so that ω n = ω c = kv = 460 rad/s.
A capacitor is placed across the phase detector output (Ro = 3.5 kΩ) to form
the lag-compensation network. C = 1/ω cRo = 1/(460 × 3500) = 0.62 μF.
5. kv = 2π kφ ko/N = 460 rad/s. Therefore, ko is required to be ko = Nkv/2π kφ = (256 x
480) x (460) / 2π(1V/rad) = 9 MHz/V. This figure is not unrealistic for 123 MHz
VCO.
Translation Loops and Multiple-Loop Synthesizers
and
f ref
Resolution = (M 2 M 3 M n )
(10-30)