PLY

Manual for EC 307 Basic Electronics Laboratory

E,K
Hari V S
t.,C
Dep
EC
Contents

1 V I Characteristics of Diodes 4

PLY
1.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Tasks to be performed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 Diode under forward bias . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Diode under reverse bias . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.3 V I Characteristics of zener diode . . . . . . . . . . . . . . . . . . . . 5

2 Rectifiers 6
E,K
2.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Design & Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Half wave rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Centre Tapped Full Wave Rectifier . . . . . . . . . . . . . . . . . . . 7
2.2.3 Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
t.,C

3 Regulated Dual Power Supply 9

3.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Design & Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dep

4 Common Emitter Transistor Characteristics 10

4.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.1 Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.2 Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Common Base Transistor Characteristics 12

5.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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5.2 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1
 5.2.1 Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2.2 Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 Common Source FET Characteristics 14

6.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Circuit Diagram & Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2.1 Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2.2 Transfer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Biasing Circuits for BJT and FET 16

7.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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7.2 Circuit Diagram & Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2.1 Collector to Base Bias of BJT . . . . . . . . . . . . . . . . . . . . . . 16
7.2.2 Voltade Divider Biasing of BJT . . . . . . . . . . . . . . . . . . . . . 16
7.3 Biasing of FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8 Series Voltage Regulator 19

8.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.2 Design and Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
E,K
8.2.1 Without Short Circuit Protection . . . . . . . . . . . . . . . . . . . . 19
8.2.2 With Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . 20
t.,C
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2
List of Figures

1.1 Diode under forward bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Diode under reverse bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

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1.3 V I characteristics of zener diode . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Halfwave rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Centre tapped full wave rectifier . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Dual power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

E,K
4.1 Experimental setup for Plotting Common Emitter Characteristics . . . . . . 10

5.1 Experimental setup for Plotting Common Base Characteristics . . . . . . . . 12

6.1 Experimental setup for Plotting the Characteristics of FET . . . . . . . . . . 14

7.1 Collector to Base Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

t.,C

7.2 Voltage Divider Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.3 Biasing Circuit for FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.1 Series Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.2 Series Voltage Regulator with Short Circuit Protection . . . . . . . . . . . . 19
Dep
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3
Chapter 1

V I Characteristics of Diodes

PLY
1.1 Aim 0-10V
+V -
The task is to plot the V I characteristics of
D
+
1. Si & Ge diodes under forward bias 10V A 0-50 µA
-

2. Ge diode under reverse bias

E,K
3. Zener diode under reverse bias
Figure 1.2: Diode under reverse bias

1.2 Tasks to be performed • Check its functional correctness of com-

ponents.
1.2.1 Diode under forward bias
t.,C

• Wire up the circuit as shown in

Fig.(1.1).Use a Si diode.
0-1V

+V - • Vary the rheostat/potentiometer from

minimum to maximum in small steps.
Dep

D
0-100mA

+ • Observe voltmeter & ammeter read-

5V A ings.Plot the V I characteristics.Mark
-
the cut in voltage.

• Graphically obtain the forward resis-

tance
Figure 1.1: Diode under forward bias ∆V
EC

rf = lim
∆I→0 ∆I

4
 • Repeat the whole procedure for a Ge 0-10V
diode.Please take care to plot both char- +V -
acteristics on the same X-Y axes.
D

0-100mA
+
1.2.2 Diode under reverse bias 10V A
-
• Check its functional correctness of com-
ponents.

• Wire up the circuit as shown in

Figure 1.3: V I characteristics of zener diode
Fig.(1.2).Use a Ge diode.

• Vary the rheostat/potentiometer from
minimum to maximum in small steps.
• Observe voltmeter & ammeter read-
ings.Plot the reverse V I characteristics.
• Graphically obtain the reverse resistance
E,K
∆V
rr = lim
∆I→0 ∆I
PLY
1. Write the diode current equation.
2. What is contact potential?Is it measur-
able?If not,why?
3. Why does a diode not conduct until the
cut in voltage is reached ?
4. Give the range of reverse saturation cur-
rents in Si & Ge diodes.

5. Why are zener diodes not damaged at

1.2.3 V I Characteristics of
break down?
zener diode
t.,C

6. Give one application of zener diode.

• Check its functional correctness of zener
diode.

• Wire up the circuit as shown in Fig.(1.3).

Dep

• Vary the rheostat/potentiometer from

minimum to maximum in small steps.

• Observe voltmeter & ammeter read-

ings.Plot the reverse V I characteris-
tics.Observe the break down voltage.

Answer the the following questions in your

EC

rough report & fair report.

5
Chapter 2

Rectifiers

PLY
2.1 Aim 6-0-6 D1

The task is to build rectifier circuits with & 230V/ +

50Hz
without filter.
RL
C Vo
D2
2.2 Design & Procedure
-
E,K
2.2.1 Half wave rectifier
Figure 2.2: Centre tapped full wave rectifier
Let Vo = 6V .Use a 6-0-6 transformer.Let
RL = 10KΩ Use a Si diode.
• Wire up the circuit as shown in Fig. 2.1.

Without Filter • Connect the input to the ac mains and

t.,C

observe the half wave rectified output

D waveform across RL .Measure the output
6-0-6
+ DC voltage & observe that
Vm
230V/ RL C Vo Vdc = (2.1)
50Hz π
Dep

- With Filter
Let the ripple voltage(Vγ ) be 10% of peak am-
Figure 2.1: Halfwave rectifier plitude (Vm )
Vm
Vγ ≈ √ (2.2)
2 3f RL C
• Check its functional correctness of com-
EC

Vγ
ponents. Design C for Vm
= 0.1 & f = 50Hz

6
 +
• Connect C across RL in Fig. 2.1). D1 D2

• Plot the output waveform.

RL C Vo
• Replace C with 10 × C & observe the D3 230 V
50Hz D4
change in output waveform.
-

2.2.2 Centre Tapped Full Wave

Figure 2.3: Bridge Rectifier
Rectifier
Without Filter 2.2.3 Bridge Rectifier

PLY
• Check the functional correctness of com- Without Filter
ponents.
• Check the functional correctness of com-
• Wire up the circuit as shown in Fig. ponents.
(2.2).Use Si diodes.
• Wire up the circuit as shown in Fig.
• Observe full wave rectified out- (2.3).Use Si diodes.
put.Measure the DC output voltage
E,K
and verify that • Observe full wave rectified out-
put.Measure the DC output voltage
2Vm and verify that Vdc = 2Vπm
Vdc = (2.3)
π

With Filter With Filter

t.,C

Let the ripple voltage(Vγ ) be 10% of peak am- Let the ripple voltage(Vγ ) be 10% of peak am-
plitude (Vm ) plitude (Vm )

Vm Vm
Vγ ≈ (2.4) Vγ ≈ (2.5)
2f RL C 2f RL C
Dep

Vγ Vγ
Design C for Vm
= 0.1 & f = 50Hz Design C for Vm
= 0.1 & f = 50Hz
• Connect C across RL in Fig. (2.2). • Connect C across RL in Fig.(2.3).
• Plot the output waveform. • Plot the output waveform.
• Replace C with 10 × C & observe the • Replace C with 10 × C & observe the
EC

change in output waveform. change in output waveform.

7
 Answer the the following questions in your
rough report & fair report.

1. Redraw Figs.(2.2)& (2.3) as negative

rectifiers.

2. What is the disadvantage of capacitor fil-

ter?

3. Prove Eqns.(2.1) to (2.5).

PLY
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8
Chapter 3

Regulated Dual Power Supply

PLY
3.1 Aim • Wire up the circuit as shown in Fig.(3.1).

The task is to build 5V-0- -5V dual power • Connect the input to the ac mains and
supply. observe the +5V & -5V at the output
terminals..

3.2 Design & Circuit Dia- • Answer the the following questions in
your rough report & fair report.
E,K
gram
1. What is PIV of diode?
As the required output is below 6V, use a 6-0-
2. What do you mean by thermal run-
6 transformer.Let RL = 10KΩ & C = 470µF
away?
Use Si diodes.
3. What do you mean by thermal shut
+
t.,C

7805
230 V + down in 78/79xx chips ?
D1 50Hz D2 RL C Vo 1
4. How do you modify the circuit to
- -
+ + obtain -12V-0-+12V DC supply?
Vo 2
D3 D4 RL C 5. What is the maximum current rat-
- 7905 - ing of 7805?
Dep

Figure 3.1: Dual power supply

3.3 Procedure
• Check the functional correctness of com-
EC

ponents.

9
Chapter 4

Common Emitter Transistor

Characteristics

PLY
4.1 Aim • Wire up the circuit as shown in
Fig.(4.1).Use a Si transistor.
The task is to plot the input & output char-
acteristics of common emitter BJT . • Keep VCE = 0 by adjusting the poten-
tiometer at the output side.
E,K
4.2 Procedure • Vary the rheostat/potentiometer at the
input side & Observe voltmeter & amme-
4.2.1 Input Characteristics ter readings at the input side .Plot the
input characteristics.
Input characteristics are plots of IB against
VBE for different VCE values.They look like • Graphically obtain the input resistance
t.,C

diode characteristics.
0−100mA
∆VBE
ri = lim (4.1)
- A + ∆IB →0 ∆IB

10V 0-50 10V

µΑ +
• Plot input characteristics for different
0−10V

+ A - Q V
+
Dep

- VCE values.
0−1V

V
-

4.2.2 Output Characteristics

Figure 4.1: Experimental setup for Plotting
In output characteristics the variation of IC
Common Emitter Characteristics
is plotted against VCE for different IB values.

• Check its functional correctness of com- • Set IB =0 by varying the rheo-

EC

ponents & instruments. stat/potentiometer at the input side.

10
• Observe voltmeter & ammeter readings
at the output.Plot IC against VCE .

• Graphically obtain the output resistance

∆VCE
ro = lim (4.2)
∆IC →0 ∆IC

• Repeat the procedure for different IB

values.

• Compute CE short circuit current gain

PLY
∆IC
β= (4.3)
∆IB
for a constant VCB

• Answer the the following questions in

your rough report & fair report.
E,K
1. Write the collector current equation
in terms of IB ,β & ICO .
2. What is the use of a transistor in
CE configuration?
3. Comment on the input & output
t.,C

impedances of CE amplifier.
4. Why are minority currents promi-
nent in BJTs?
5. Mark the three regions of operation
Dep

in the BJT output characteristics.

EC

11
Chapter 5

Common Base Transistor

Characteristics

PLY
5.1 Aim • Wire up the circuit as shown in
Fig.(5.1).Use a Si transistor.
The task is to plot the input & output char-
acteristics of common base BJT . • Keep VCB = 0 by adjusting the poten-
tiometer at the output side.
E,K
5.2 Procedure • Vary the rheostat/potentiometer at the
input side & Observe voltmeter & am-
5.2.1 Input Characteristics meter readings at the input side . Plot
the input characteristics.
Input characteristics are plots of IE against
VEB for different VCB values.They look like • Graphically obtain the input resistance
t.,C

diode characteristics.
∆VEB
0-50mA 0-50mA ri = lim (5.1)
- A + Q - A + ∆IE →0 ∆IE

- + 10V
0-10V

• Plot input characteristics for different

0-1V

V V
10V + -
Dep

VCB values.

Figure 5.1: Experimental setup for Plotting 5.2.2 Output Characteristics

Common Base Characteristics In output characteristics the variation of IC
is plotted against VCB for different IE values.

• Check its functional correctness of com- • Set IE = 10mA by varying the rheo-
EC

ponents & instruments. stat/potentiometer at the input side.

12
• Observe voltmeter & ammeter readings
at the output.Plot IC against VCB .

• Graphically obtain the output resistance

∆VCB
ro = lim (5.2)
∆IC →0 ∆IC

• Repeat the procedure for different IE

values.

• Compute CB short circuit current gain

PLY
∆IC
α= (5.3)
∆IE
for a constant VCB

• Answer the the following questions in

your rough report & fair report.
E,K
1. Write the collector current equation
in terms of IE ,α & ICO .
2. What is the use of a transistor in
CB configuration?
3. Comment on the input & output
t.,C

impedances of CB amplifier.
Dep
EC

13
Chapter 6

Common Source FET Characteristics

PLY
6.1 Aim • Check its functional correctness of com-
ponents & instruments.
The task is to plot the output & transfer char-
acteristics of common source n-channel FET • Wire up the circuit as shown in Fig.(6.1).
. • Keep VGS = 0 by adjusting the poten-
tiometer at the input side.
6.2 Circuit Diagram &
E,K
• Vary the rheostat/potentiometer at the
output side & Observe voltmeter & am-
Procedure meter readings at the output side .Plot
the output characteristics.
6.2.1 Output Characteristics
• Graphically compute the drain resis-
Output characteristics are plots of drain cur- tance in the linear region
t.,C

rent ID against drain-source voltage VDS for

different gate-source voltage VGS values. ∆VDS
rd = lim (6.1)
∆ID →0 ∆ID
0-50mA
- A + • Plot output characteristics for different
VGS values.
Dep

+
5V - Q V 0-10V 10V
0-5V V
- 6.2.2 Transfer Characteristics
+
In transfer characteristics the variation of ID
is plotted against VGS for different VDS val-
Figure 6.1: Experimental setup for Plotting ues.
the Characteristics of FET • Set VDS =0 by varying the rheo-
EC

stat/potentiometer at the input side.

14
• Observe voltmeter & ammeter readings
at the output.Plot ID against VGS .

• Graphically compute the

transconductance(gm ) in the linear
region
∆ID
gm = lim (6.2)
∆VGS →0 ∆VGS

• Compute the amplification factor

PLY
µ = g m × rd

• Repeat the procedure for different VDS

values.

• Answer the the following questions in

your rough report & fair report.
E,K
1. What is pinch off voltage?
2. Why is FET unipolar despite the
presence of both electrons & holes
in the channel?
3. Which is the charge transport
t.,C

mechanism in FET?
4. Why is the input impedance of FET
high?
5. Give the equation for drain current
Dep

in terms of VGS ,VP & IDSS .

EC

15
Chapter 7

Biasing Circuits for BJT and FET

PLY
7.1 Aim In the input loop

The task is to design and implement biasing VCC = IC RC +IB RB +VBEactive +IE RE (7.5)
circuits for BJT and FET .
IB RB = VCBactive
7.2 Circuit Diagram & = VCEactive − VBEactive
VCC
E,K
Procedure =
2
− 0.8
= 6.7V (7.6)
7.2.1 Collector to Base Bias of
IC
BJT IB ≈ (7.7)
β
The circuit is shown in Fig.(7.1) Let VCC = So
t.,C

15V ,β = 200 and IC = 5mA. For active 6.7

RB ≈ (7.8)
region of operation, VCEactive = VCC
2 IB
VCC = IC RC + VCEactive + IE RE (7.1) • Check the functional correctness of com-
ponents.
Let the voltage across RE be 10% of VCC
Dep

• Wire up the circuit as in Fig.(7.1).

IC ≈ IE (7.2) VCC
• Observe that VCE = 2
So
0.1VCC
RE = (7.3) 7.2.2 Voltade Divider Biasing
IE
and of BJT
VCC − VCE − IE RE The circuit is shown in Fig.(7.2). Let VCC =
EC

RC = (7.4) 15V ,β = 200 and IC = 5mA. For active

IC

16
 VCC VCC

RC R1 RC
RB

Q
Q
R2 RE
RE

PLY
Figure 7.2: Voltage Divider Bias
Figure 7.1: Collector to Base Bias

VCC
region of operation, VCEactive = 2 VCC − VBEactive − IE RE
R1 = (7.15)
10IB
VCC = IC RC + VCEactive + IE RE (7.9)
E,K
• Check the functional correctness of com-
For active region of operation, VCEactive = ponents.
VCC
2
.Let the voltage across RE be 10% of VCC .
So • Wire up the circuit as in Fig. (7.2).
1.5
RE = (7.10)
IE • Power up the circuit and observe that
t.,C

VCC − VCE − IE RE VCE = VCC

RC = (7.11) 2
IC
IC
IB ≈ (7.12) 7.3 Biasing of FET
β
Assume that 10IB flows through R1 and 9IB The circuit is shown in Fig. (7.3). Let VDD =
Dep

flows through R2 . 15V & ID = 5mA.For linear operation VDS =

VDD
R2 2
VCC = VBEactive + IE RE
R1 + R2
VDD = ID RD + VDSactive + ID RD (7.16)
= 0.8 + 1.5
= 2.3V (7.13) VGS = −ID RS (7.17)
2.3
(7.14) Let VGS = 1V and RG = 1M Ω.Compute RS
EC

R2 =
9IB and RD .

17
 VCC

RD

RG RS

PLY
Figure 7.3: Biasing Circuit for FET

• Check the functional correctness of com-

ponents.
E,K
• Wire up the circuit as in Fig.(7.3).

• Power up the circuit and observe that

VDS = VDD
2

• Answer the the following questions in

your rough report and fair report.
t.,C

1. What is Q point? Why should be

at the centre of the load line?
2. What is the use of RE in Figs. (7.1)
and (7.2)?
Dep

3. For the circuit in Fig. (7.2) write

the equations for the stabilty fac-
tors for variation in VBE , β and ICO .
EC

18
Chapter 8

Series Voltage Regulator

PLY
8.1 Aim Q1
+ +

0-0.5A
R3
The task is to build series voltage regulator R4 A
for output voltage VO = 10V and output cur- R1
RL
rent IO = 100mA with and without short cir-
Vunregulated Vo
cuit protection. Q2
E,K
R2
8.2 Design and Procedure -
VZ
-

8.2.1 Without Short Circuit

Protection Figure 8.1: Series Voltage Regulator
The circuit is as in Fig.(8.1).
t.,C

Q1 RSC
R1 +
VO = VZ [1 + ] (8.1) + 0-0.5A
R2 R3
A
Q3 R4
R1
Let VZ = 4.7V and R1 = 10KΩ. Compute RL
R2 . Let the collector current IC2 of Q2 be
Dep

Vunregulated Vo
5mA Q2

Vunregulatedmax − VCEsat − VZ R2
R3 = (8.2) VZ
IC 2 - -

VO − VZ
R4 = (8.3)
IZ
Figure 8.2: Series Voltage Regulator with
Use SL100 as Q1 and BC107 as Q2 . Use
EC

Short Circuit Protection

10KΩ variable load.

19
 • Check the functional correctness of com- resistance from maximum to near mini-
ponents. mum. Observe the load current and out-
put voltages. Plot the load regulation
• Wire up the circuit as in Fig.(8.1). curve.

• Connect the input to the unregulated Dc
supply. Vary the input voltage from 8V
to 15 V in steps of 1V and observe the
change in output voltage.
• Plot the line regulation curve.
• Answer the following questions in your
rough report and fair report.
1. Define line regulaton and load reg-
ulation.
2. Redraw the circuit in Fig.(8.2) to

PLY
incorporate current boosting also.
• Keep the input voltage at 15V.Observe
the output voltage as 10V. Vary the load
resistance from maximum to near mini-
mum. Observe the load current and out-
put voltages. Plot the load regulation
curve.
E,K
8.2.2 With Short Circuit Pro-
tection
The circuit is as shown in Fig.(8.2). Let the
short circuit current ISC be 100mA. The
t.,C

0.7
RSC = (8.4)
ISC

• Rewire the circuit as in Fig.(8.2). Use

BC107 as Q3 .
Dep

• Connect the input to unregulated sup-

ply. Vary the input voltage from 8V
to 15 V in steps of 1V and observe the
change in output voltage. Plot the line
regulation curve.

• Keep the input voltage at 15V.Observe

EC

the output voltage as 10V. Vary the load

20
Bibliography

[1] Donald L Schilling & Charles Belove:

Electronic Circuits - Discrete & Inte-
grated, Tata McGraw Hill

PLY
[2] J Millman : Microelectronics, McGraw
Hill

[3] J Millman & C Halkias: Integrated Elec-

tronics, McGraw Hill
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