3
December 1417, 2004
Atlantis, Paradise Island, Bahamas
Abstract— In this paper, an efﬁcient design scheme for consumption. These are attractive features from the embed
implementation of the ProportionalIntegralDerivative (PID) ded systems design point of view [4].
controller using Field Programmable Gate Array (FPGA) Conventional implementation of FPGA based controllers
technology is presented. The algorithm is implemented using
a Distributed Arithmetic (DA)based scheme where a Look have not focused on optimal use of hardware resources.
UpTable (LUT) mechanism inside the FPGA is utilized. Two These designs usually require a large number of multipliers
novel DAbased PID controllers have been proposed for FPGA and adders and do not efﬁciently utilize the memoryrich
implementation. The implementation results show that, the two characteristics of FPGAs [5]. An FPGA chip consists of
DA methods require 13% and 4% of logic devices, respectively, a lot of memory blocks, referred to as LookUp Tables
compared to the design using multipliers. Furthermore, the
power consumption is reduced by about 40%. A design which (LUT), which can be utilized to implement efﬁcient designs.
is efﬁcient in terms of power consumption and chip area In this work, we utilize the Distributed Arithmetic (DA)
while having adequate speed means that the FPGA chip can scheme [6], which is an efﬁcient LUT design method, and
be used to accommodate more controllers with low power is very promising in the FPGA implementation of PID
consumption, resulting in a cost reduction of the controller controller. The organization of this paper is as follows. In
hardware.
Keyowrds: FPGA design, embedded controllers, distributed section 2, an improved PID controller is considered and
arithmetic, power optimization, PID controller. its implementation using the DA scheme is discussed. In
Section 3, the implementation results on a Xilinx FPGA
I. I NTRODUCTION chip are discussed. Comparisons are made between the
proposed scheme and the design based on conventional
Proportional Integral Derivative (PID) controller is the methods.
most common type of controller used in dynamic systems
[1]. An important feature of this controller is that it does II. PID C ONTROLLER I MPLEMENTATION
not need a precise analytical model of the system that is
being controlled. For this reason, PID controllers have been The application of a PID controller in a feedback control
widely used in process control, manufacturing, robotics, system is shown in Fig. 1., where uc is the command signal,
automation, transportation, and interestingly in realtime y is the feedback signal, e is the error signal, and u is
scheduling of concurrent tasks in multitasking applications the control input. The simplest form of the PID control
[1]. algorithm is given by
PID controllers are often combined with logic, sequential t
functions, and other blocks to implement complicated sys u(t) = Kp e + KI e(τ )dτ + KD ė (1)
tems. Implementation of PID controllers has gone through 0
several stages of evolution, from the early mechanical and From a practical point of view, implementation of the above
pneumatic designs to the microprocessorbased systems. algorithm has certain limitations [4]. Firstly, actuator satu
Recently, Field Programmable Gate Arrays (FPGA) have ration can cause integrator windup, leading to a sluggish
become an alternative solution for the realization of digi transient response. Secondly, the pure differentiation term
tal control systems, previously dominated by the general ampliﬁes noise, leading to a deterioration of the control
purpose microprocessor and application speciﬁc integrated command. Finally, the differentiation term acts on the error
circuits (ASIC) [1][3]. The FPGAbased controllers offer signal, taking the derivative of the command signal as
advantages such as highspeed computation, complex func well. This procedure can lead to spikes in the command
tionality, realtime processing capabilities, and low power signal when, for example, a user changes the setpoint
abruptly. Following [4], a modiﬁed PID control algorithm
This research was supported in part by grants RGPIN227612 and RG
PIN261527 from the Natural Sciences and Engineering Research Council that overcomes the above problems is given in the Laplace
of Canada (NSERC). domain by
0780386825/04/$20.00 ©2004 IEEE 4885
TABLE I
C ONTENTS OF THE LU TP .
1
U (s) = K(bUc (s) − Y (s) + (Uc (s) − Y (s))
sTi u(kT )[j] y(kT )[j] LU TP
sTd 0 0 0
− Y (s)) (2) 0 1 −K
1 + sTd /N 1 0 Kb
1 1 Kb − K
where K, b, Ti , Td , and N are controller parameters, and
U (s), Uc (s), and Y (s) denote the Laplace transforms of u, TABLE II
uc , and y, respectively. In order to implement the control C ONTENTS OF THE LU TI .
algorithm using digital technology, equation (2) has to be
discretized. Denoting the sampling period by T , and using I((k − 1)T )[j] u((k − 1)T )[j] y((k − 1)T )[j] LU TI
backward differences to discretize the derivative term and 0 0 0 0
0 0 1 − KT
T
forward differences for the integral term, one has KT
i
0 1 0 Ti
0 1 1 0
u(kT ) = P (kT ) + I(kT ) + D(kT ) (3) 1 0 0 1
1 0 1 1 − KT
T i
where k denotes the kth sampling instant and 1 1 0 1 + KT
Ti
1 1 1 1
P (kT ) = K(bu(kT ) − y(kT ))
KT
I(kT ) = I((k − 1)T ) + (u((k − 1)T )
Ti
−y((k − 1)T ))
m−1
Td KTd N P (kT ) = (Kb × u(kT )[j] −
D(kT ) = D((k − 1)T ) −
Td + N T Td + N T j=0
(y(kT ) − y((k − 1)T )) . (4) K × y(kT )[j]) × 2j (5)
where y(kT ) is the output of the system at the current
m−1
KT
instant, y((k − 1)T ) is the output of the system at the I(kT ) = (I((k − 1)T )[j] + (u((k −
Ti
previous instant, uc (kT ) is the desired output of the system, j=0
I((k − 1)T ) is the integral term at the previous instant, 1)T )[j] − y((k − 1)T )[j])) × 2j (6)
D((k − 1)T ) is the derivative term at the previous instant,
m−1
Td
K, b, Ti , Td , N are controller parameters, and T is the D(kT ) = ( D((k − 1)T )[j] −
T d + NT
sampling period. j=0
Having obtained the discretized control algorithm, the KTd N
((y(kT )[j] − y((k −
focus is now on its efﬁcient implementation. The direct Td + N T
implementation of the above algorithms using FPGA re 1)T )[j]) × 2j )) (7)
quires a total of 5 multipliers, 5 adders/subtractors, and 4
delay blocks. The P (kT ) term requires 2 multipliers and
1 adder/subtractor, the I(kT ) term requires 1 multiplier The results of (Kb × u(kT )[j] − K × y(kT )[j]),
and 2 adders/subtractors, and the D(kT ) term requires (I((k − 1)T )[j] + KT Ti (u((k − 1)T )[j] − y((k − 1)T )[j]))
2 multipliers and 2 adders/subtractors. The u((k − 1)T ), and ( Td +N
Td
T D((k − 1)T )[j] − TKT dN
d +N T
(y(kT )[j] − y((k −
y((k − 1)T ), I((k − 1)T ) and D((k − 1)T ) terms each 1)T )[j])) can be precomputed and stored in three LUTs,
requires a delay block. Thus, a total of 4 delay blocks are namely, LU TP , LU TI and LU TD . The contents of the
required. three LUTs are shown in Tables I, II and III, respectively.
The multiplierbased design uses many multipliers and Using the three LUTs and the corresponding shiftadd
adders. Since FPGA has a limited number of conﬁgurable accumulators (ACCs), the P (kT ), I(kT ), and D(kT ) terms
logic blocks for the above calculations, the multiplierbased can be obtained in m clock cycles. The main advantage
design is not efﬁcient for FPGA. In order to reduce the of the DA expression given by (5), (6) and (7) lies in its
required multipliers and adders, we apply the DA method capability to compute the PID function utilizing the LUT
[5] in order to replace the multiplication operation by simple rich FPGA.
shifting and addition operation. This is discussed as follows. Based on the above equations, the direct DA implementa
tion of the PID controller, namely, DAI, is shown in Figure
A. Direct DA Implementation (DAI) 2. It consists of four delay blocks, three LUTs, three ACCs,
Let us consider the controller terms given in (4). Assum and two adders. The delay blocks 1 and 2 are used to obtain
ing that u(kT ), u((k − 1)T ), y(kT ), and y((k − 1)T ) are u((k−1)T ) and y((k−1)T ), respectively. The delay blocks
mbit numbers and [j] represents the jth bit of the numbers, 3 and 4 are used to generate the terms I((k − 1)T ) and
we have D((k − 1)T ), respectively. Three LUTs and three ACCs
4886
uC + e u
PID Controller Dynamic System
SetPoint

y
Sensor
D((k − y(k)T )[j] y((k−1)T )[j] LU TD u((k − 1)T )[j] y((k − 1)T )[j] LU TI
1)T )[j] 0 0 0
0 0 0 0 0 1 − KT
KTd N T i
0 0 1 Td +N T 1 0 KT
KTd N Ti
0 1 0 − T +N T 1 1 0
d
0 1 1 0
Td
1 0 0 Td +N T TABLE V
(KN +1)Td C ONTENTS OF THE LU TD .
1 0 1 Td +N T
(1−KN )Td
1 1 0 Td +N T
Td
y(k)T )[j] y((k − 1)T )[j] LU TD
1 1 1 Td +N T 0 0 0
KTd N
0 1 Td +N T
KTd N
1 0 − T +N T
d
U(kT) D1
I
y(kT) D2 LUPI ACC P+I+D
D3
D4
LUT and the corresponding ACC will generate the PID amongst the three designs.
output in m clock cycles, in the second pipeline stage. This
twostage implementation of the DAbased PID controller, III. FPGA I MPLEMENTATION R ESULTS
namely, DAII, is shown in Figure 3. It requires three LUTs,
three ACCs and two delay blocks , while DAI requires two The proposed DAbased PID controller DAII is im
more adders and two more delay blocks. Thus, the hardware plemented using the Xilinx Inc. FPGA technology and
resources required by DAII are less than those of DAI. can be used as a general purpose controller for different
DAII needs two stages to accomplish one PID calcula applicaitons. The FPGA design ﬂow is as follows. First,
tion in a pipeline. The ﬁrst stage consists of two LUTs and the controller was implemented by using the Xilinx ISE
two ACCs to calculate I(kT ) and D (kT ), respectively. foundation tools [9] and simulated at the Register Transfer
The second stage consists of one LUT and one ACC to Level (RTL) to verify the correctness of the design. By us
calculate the summation of the PID function using the ing the Xilinx ISE Foundation tools, the logic synthesis was
results of I(kT ) and D (kT ) available in the ﬁrst stage. carried out to optimize the design, and the placement and
These stages are pipelined so that when the second stage is routing were carried out automatically to generate the FPGA
performing the ﬁrst calculation, the ﬁrst stage is performing implementation ﬁle. Finally, the generated implementation
the next calculation. Thus, the throughput (speed) is only ﬁle was downloaded to the FPGA development board for
m clock cycles. The two stages, each requiring m clock testing.
cycles, introduce a latency of 2m clock cycles. For the PID case, all the parameters were taken from [8]
The performance, in terms of complexity and speed, of and the input is a 13bit number. All the numbers in the
the proposed designs, and the multiplierbased design are PID expressions can be either negative or positive and are
listed in Table 7. Compared to the multiplierbased PID con represented by ﬁxedpoint 2’s complement numbers.
troller, the two DAbased designs, DAI and DAII, utilize This PID controller is targeted to a Xilinx SpartanIIE
the memory rich characteristics of the FPGA. The proposed FPGA xc2s200eFT256 6. The simulation and testing are
design (DAII) requires less adders/subtractors and less conducted on the FPGA board to validate the functions of
delay blocks as compared to the direct DA implementation, the PID controller as shown in Fig. 4.
i.e., DAI. The speed (throughput) of DAII design is a little The implementation results of the DAII PID controller
bit higher than that of DAI, but the latency is more. Since are shown in Table 8. Using the proposed method, the DAII
the latency only occurs once during the power up, it is not PID controller uses 13 slices, 13 slice ﬂipﬂops and 3 block
of much concern in our control system consideration. Thus, RAMs. For the purpose of comparison, the corresponding
the DAII design has improved characteristics compared to DAI and multiplierbased designs are also implemented for
DAI and is the most preferred design in the control system the 13bit input case. The implementation results of the two
4888
u(kT) D
I LUTI ACC
y(kT) D
u(kT)
P LUTPID ACC P+I+D
y(kT)
D y(kT)
LUTD' ACC
TABLE VI
C ONTENTS OF THE LU TP ID .
TABLE VII
C OMPLEXITY AND S PEED OF PID C ONTROLLERS
3 LUTs, 3 ACCs,
DA I 4 delay blocks,2 adders m + 1 clock cycles m + 1 clock cycles
5 multipliers
Multiplierbased I 4 delay blocks,5 adders 1 clock cycle 1 clock cycle
designs are also shown in Table 7. The clock frequency of clock are fast enough, the tradeoff of speed to hardware
all three designs is 50 M Hz. resource and power saving is useful for the PID controller
It is seen from Table 7 that the DAI design uses about design.
13% of the logic resources required by the design using The DAII offers more improvement over DAI. In par
multipliers. On the other hand, the power consumption of ticular, the DAII design uses only about 4% of the logic
DAI is reduced by 40%. Due to the serial nature of the resources required by the design using multipliers. The
DA method, the DAI PID controller needs 14 clock cycles power consumption of DAII is reduced by 38%. The DAII
while the design using multipliers needs 1 clock cycle. Since PID controller needs 13 clock cycles to generate one result.
in the control system considered, the 14 cycles of 50 MHz The latency of DAII is more than DAI since DAII needs
4889
TABLE VIII
FPGA I MPLEMENTATION R ESULTS OF PID C ONTROLLERS (C LOCK FREQUENCY = 50 M Hz)
42 Slices,
DA I 52 Slice FlipFlops, 14 cycles 14 cycles 9.29 mW
3 Block RAMs
321 Slices,
multiplierbased 104 Slice FlipFlops 1 cycle 1 cycle 15 mW
two stages of pipeline. The latency only occurs once during [5] W. Wolf, Computers as Components: Principles of Embedded Com
the power up. Afterwards, the outputs of the PID algorithm puting System Design, San Francisco, Morgan Kaufman, 2001.
[6] A. White, “Application of Distributed Arithmetic to Digital Signal
are generated every 13 clock cycles in the pipeline. Thus, Processing: A Tutorial Review,” IEEE Accoustic, Speech, and Signal
the throughput of DAII is 13 clock cycles which is faster Processing Magzine, vol. 6, pp. 419, 1989.
than that of the DAI scheme. [7] C. Lu, J.A. Stankovic, G. Tao, and S.H. Son, “Design and Evaluation
of a Feedback Control EDF Scheduling Algorithm”, 20th IEEE Real
A design which is efﬁcient in terms of power consump Time Systems Symposium (RTSS 1999), Phoenix, AZ, December 1999
tion and chip area means that the FPGA chip can be used [8] M. Moallem, ”A Laboratory Testbed for Embedded Computer Con
to accommodate more controllers with adequate speed and trol,” in press, IEEE Trans. on Education.
[9] Xilinx ISE 6 Software Manuals, Xilinx Inc. , California,
low power consumption, resulting in a cost reduction of USA,(www.xilinx.com), 2003.
the controller hardware. For the implementation example
considered here, one Xilinx FPGA chip, namely, Spartan
IIE FPGA xc2s200eFT256 6, can accommodate only
7 multiplierbased designs. However, the same chip can
implement about 56 DAI designs or 180 DAII designs.
IV. C ONCLUSION
In this paper, two novel DAbased PID controllers have
been proposed for FPGA implementation. By using the DA
based LUT scheme, the memory inside FPGA has been
utilized to provide efﬁcient design for PID controllers.
The FPGA implementation results show that, the two DA
designs requires only 13% and 4% of logic devices, re
spectively, compared to the design using multipliers. Fur
thermore, the power consumption is reduced by about 40%.
Future work will involve the implementation and integration
of a DAbased PID controller into a complete control
system consisting of analog and digital I/O.
V. ACKNOWLEDGMENT
The authors would like to thank Rumi Zhang for his great
help in editing the paper and preparing the ﬁgures.
R EFERENCES
[1] K.J. Astrom and B. Wittenmark, Computer Controlled Systems, Pren
tice Hall, New Jersery, USA, 1997
[2] R. Chen, L. Chen and L. Chen, “System Design Consideration for
Digital Wheelchair Controller,” IEEE Trans. On Industrial Electronics,
vol. 47, pp. 898907, Aug. 2000.
[3] L. Samet, N. Masmoudi, M. W. Kharrat, and L. Kamoun, “A digital
PID Controller for Realtime and Multiloop Control: A Comparative
Study,” IEEE Int. Conf. on Electronics, Circuits and Systems, vol. 1,
pp. 291296, Sept. 1998.
[4] B. Wittenmark, K. J. Astrom, and KE., Arzen, Computer Control: An
Overview, Technical Report, Department of Automatic Control, Lund
Institute of Technology, Sweden (www.control.lth.se/ kursdr/ifac.pdf),
April 2003. Fig. 4. Setup of the FPGAbased PID controller
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