5 4 3 2 1

D
DECA D

Section Title Page Section Title Page

01.0 Design Introduction 07.0 Video & Audio

1.01 Cover Page 1 07.01 MIPI Interface 15

1.02 Block Diagram 2 07.02 HDMI TX 16

02.0 MAX 10 10M50DAF484 07.03 Audio CODEC 17

02.01 MAX 10 BANK1 & BANK2 3 08.0 Ethernet

C C

02.02 MAX 10 BANK3 & BANK4 4 08.01 Ethernet 18

02.03 MAX 10 BANK5 & BANK6 5 09.0 USB PHY

02.04 MAX 10 BANK7 & BANK8 6 09.01 USB PHY 19

02.05 MAX 10 Clocks & Configuration 7 10.0 Analog Interface

02.06 MAX10 Power & GND 8 09.02 10.01 SMA Connectors & Differential Amplifier 20

02.07 MAX10 Decoupling 9 11.0 Sensors

03.0 Clock 11.01 Accelerometer 21

03.01 Clock 10 11.02 Gesture, Humidity, Temperature Sensors 22

B B

04.0 JTAG 12.0 User Interface

04.01 USB Blaster II 11 12.01 LED & BUTTON & SWITCH 23

05.0 Expansion Port 13.0 System Power

05.01 Expansion Headers - BBB Headers 12 13.01 1.2V & 1.5V & 1.8V & 5V 24

06.0 Memory 13.02 2.5V & 2.8V & 3.3V 25

06.01 DDR3 SDRAM & QSPI Flash 13

06.02 SD Card 14

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B Cover Page C

Date: Wednesday, March 11, 2015 Sheet 1 of 25

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B Block Diagram C

Date: Friday, May 22, 2015 Sheet 2 of 25

5 4 3 2 1
 5 4 3 2 1

CAD Notes:
1. Put all the 1pF caps close to each MAX10 analog pin.
2. Route the analog input signal adjacent to the REFGND.

U1A

MIPI Interface MAX 10 LEFT BANKS

D MIPI_MD_p[3..0] BANK-1A BANK-2 D
15
VCCIO = 2.5V VCCIO = 2.5V
MIPI_MD_n[3..0] ADC1IN1 F5 P4 NET_RX_DV
15 DIFFIO_RX_L1N/ADC1IN1 DIFFIO_RX_L29N
ADC1IN2 F4 P5 NET_CRS
7,15 MIPI_MC_p E4 DIFFIO_RX_L1P/ADC1IN2 DIFFIO_RX_L29P N3 MIPI_MD_n3
E3 DIFFIO_RX_L2N/ADC2IN1 DIFFIO_RX_L37N N2 MIPI_MD_p3
7,15 MIPI_MC_n ADC1IN3 J8 DIFFIO_RX_L2P/ADC2IN8 DIFFIO_RX_L37P R4 NET_COL
ADC1IN4 J9 DIFFIO_RX_L3N/ADC1IN3 DIFFIO_RX_L39N R5 NET_MDC
G4 DIFFIO_RX_L3P/ADC1IN4 DIFFIO_RX_L39P T1 MIPI_MD_n2
F3 DIFFIO_RX_L4N/ADC2IN3 DIFFIO_RX_L40N T2 MIPI_MD_p2
MIPI Control Interface ADC1IN6 H3 DIFFIO_RX_L4P/ADC2IN4 DIFFIO_RX_L40P N8 NET_MDIO
MIPI_RESET_n ADC1IN5 J4 DIFFIO_RX_L5P/ADC1IN6 DIFFIO_RX_L41N N9 NET_TXD2
15 DIFFIO_RX_L5N/ADC1IN5 DIFFIO_RX_L41P
LINE_IN_L_ADC H4 P1 MIPI_MD_n1
MIPI_MCLK G3 DIFFIO_RX_L6N/ADC2IN5 DIFFIO_RX_L42N N1 MIPI_MD_p1
15 DIFFIO_RX_L6P/ADC2IN6 DIFFIO_RX_L42P
ADC1IN7 K5 T3 MIPI_RESET_n
MIPI_WP K6 DIFFIO_RX_L7N/ADC1IN7 DIFFIO_RX_L43N U2 NET_TXD0
15 DIFFIO_RX_L7P/ADC1IN8 DIFFIO_RX_L43P
J3 U1 MIPI_WP
MIPI_CORE_EN K4 DIFFIO_RX_L8P/ADC2IN2 DIFFIO_RX_L44N V1 NET_RX_ER
15 DIFFIO_RX_L8N/ADC2IN7 DIFFIO_RX_L44P U4 NET_RXD1
DIFFIO_RX_L45N U5 NET_RXD0
BANK-1B DIFFIO_RX_L45P
MIPI I2C Interface VCCIO = 2.5V U3 MIPI_MCLK
K8 DIFFIO_RX_L46N V3 MIPI_CORE_EN
MIPI_I2C_SDA D3 DIFFIO_RX_L15N DIFFIO_RX_L46P P8 NET_RXD3
15 DIFFIO_RX_L16N DIFFIO_RX_L47N
D2 R7 NET_RXD2
C DIFFIO_RX_L16P DIFFIO_RX_L47P C
MIPI_I2C_SCL K2 W1 NET_TXD1
R181 15 DIFFIO_RX_L19N DIFFIO_RX_L48N
L2 W2 NET_TXD3
AIN0 12 10 ADC1IN1 L8 DIFFIO_RX_L19P DIFFIO_RX_L48P R1 MIPI_MD_n0
L9 DIFFIO_RX_L20N DIFFIO_RX_L60N R2 MIPI_MD_p0
E1 DIFFIO_RX_L20P DIFFIO_RX_L60P M2 MIPI_I2C_SDA
C126 F2 DIFFIO_RX_L21N VREFB2N0 M1 MIPI_I2C_SCL
H1 DIFFIO_RX_L21P IO_BANK2
1p J1 DIFFIO_RX_L22N
Audio LINE-IN to MAX10 ADC G1 DIFFIO_RX_L22P
R49 DIFFIO_RX_L23N
F1
AIN1 12 10 ADC1IN2 17 LINE_IN_L_ADC M4 DIFFIO_RX_L23P
M3 DIFFIO_RX_L24N
K1 DIFFIO_RX_L24P
C24 L1 DIFFIO_RX_L25N
C1 DIFFIO_RX_L25P
1p D1 VREFB1N0
Ethernet IO_BANK1
R180
AIN2 12 10 ADC1IN3
NET_TXD[3..0] 18 10M50DAF484C6GES

C125 NET_RXD[3..0] 18
18
B 1p NET_MDIO B
R50
AIN3 12 10 ADC1IN4 NET_RX_ER 18
NET_RX_DV 18
NET_COL 18
C25 NET_CRS 18
NET_MDC 18
1p
R179
AIN4 12 10 ADC1IN5
Header Analog Input MIPI_MD_p0 MIPI_MD_p1 MIPI_MD_p2 MIPI_MD_p3
AIN[6..0] 12
R220 R221 R230 R219
C124

1p
100 100 100 100
R51 MIPI_MD_n0 MIPI_MD_n1 MIPI_MD_n2 MIPI_MD_n3
AIN5 12 10 ADC1IN6

C26

A 1p A
REFGND1
R178
DNI
AIN6 12 10 ADC1IN7
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
All rights reserved.
REFGND No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
C123
DECA
1p Size Document Number Rev
B MAX 10 Bank 1, Bank 2 C

Date: Wednesday, March 11, 2015 Sheet 3 of 25

5 4 3 2 1
 5 4 3 2 1

QSPI Flash
FLASH_NCSO 13
FLASH_DCLK 13

FLASH_DATA[3..0] 13
D FLASH_RESET_n D
13
U1B

Header GPIO MAX 10 BOTTOM BANKS

7,12 GPIO1_D[22..0] BANK-3 BANK-4
VCCIO = 3.3V VCCIO = 3.3V
7,12 GPIO0_D[43..0] GPIO1_D13 Y7 W11 GPIO0_D35
LIGHT_I2C_SCL Y8 DIFFIO_RX_B10N DIFFIO_RX_B25N Y11 GPIO0_D32
12 PWR_BUT CAP_SENSE_I2C_SCL AB2 DIFFIO_RX_B10P DIFFIO_RX_B25P AB10 GPIO0_D30
CAP_SENSE_I2C_SDA AB3 DIFFIO_RX_B12N DIFFIO_RX_B27N AB11 GPIO0_D28
SYS_RESET_n PMONITOR_I2C_SCL Y3 DIFFIO_RX_B12P DIFFIO_RX_B27P AB12 GPIO0_D26
12 DIFFIO_RX_B14N DIFFIO_RX_B29N
PMONITOR_ALERT Y4 AB13 GPIO0_D24
AA5 DIFFIO_RX_B14P DIFFIO_RX_B29P W12 GPIO0_D34
Temperature Sensor AB5 DIFFIO_RX_B17N DIFFIO_RX_B35N W13 GPIO0_D33
22 TEMP_SIO GPIO1_D10 AB6 DIFFIO_RX_B17P DIFFIO_RX_B35P AA14 GPIO0_D23
22 TEMP_SC GPIO1_D9 AB7 DIFFIO_RX_B19N DIFFIO_RX_B38N AB15 GPIO0_D18
22 TEMP_CS_n LIGHT_I2C_SDA AA8 DIFFIO_RX_B19P DIFFIO_RX_B38P AA15 GPIO0_D21
GPIO1_D6 AB8 DIFFIO_RX_B21N DIFFIO_RX_B40N Y16 GPIO0_D9
LIGHT_INT AA9 DIFFIO_RX_B21P DIFFIO_RX_B40P AB16 GPIO0_D16
RH_TEMP_DRDY_n AB9 DIFFIO_RX_B23N DIFFIO_RX_B42N AA16 GPIO0_D15
Humidity and Temperature Sensor FLASH_DATA1 V4 DIFFIO_RX_B23P DIFFIO_RX_B42P AB19 GPIO0_D8
22 RH_TEMP_I2C_SCL FLASH_DATA2 V5 DIFFIO_RX_B2N DIFFIO_RX_B44N AB20 GPIO0_D7
22 RH_TEMP_I2C_SDA PMONITOR_I2C_SDA Y1 DIFFIO_RX_B2P DIFFIO_RX_B44P AA19 GPIO0_D5
C 22 DIFFIO_RX_B4N DIFFIO_RX_B46N C
RH_TEMP_DRDY_n TEMP_SIO Y2 Y18 GPIO0_D1
TEMP_SC AA1 DIFFIO_RX_B4P DIFFIO_RX_B46P AB21 GPIO0_D6
SYS_RESET_n AA2 DIFFIO_RX_B6N DIFFIO_RX_B50N AA20 GPIO0_D4
GPIO1_D0 Y5 DIFFIO_RX_B6P DIFFIO_RX_B50P AB17 GPIO0_D14
Gesture Sensor GPIO1_D1 Y6 DIFFIO_RX_B8N DIFFIO_RX_B58N AB18 GPIO0_D11
GPIO1_D16 W9 DIFFIO_RX_B8P DIFFIO_RX_B58P V11 GPIO0_D37
22 LIGHT_I2C_SCL FLASH_RESET_n W10 DIFFIO_TX_RX_B11N DIFFIO_TX_RX_B24N V12 GPIO0_D36
22 LIGHT_I2C_SDA GPIO1_D3 W7 DIFFIO_TX_RX_B11P DIFFIO_TX_RX_B24P R12 FLASH_DCLK
22 LIGHT_INT GPIO1_D4 W8 DIFFIO_TX_RX_B13N DIFFIO_TX_RX_B26N P12 FLASH_DATA0
FLASH_NCSO R10 DIFFIO_TX_RX_B13P DIFFIO_TX_RX_B26P AA11 GPIO0_D29
FLASH_DATA3 P10 DIFFIO_TX_RX_B15N DIFFIO_TX_RX_B28N AA12 GPIO0_D27
GPIO1_D12 AA6 DIFFIO_TX_RX_B15P DIFFIO_TX_RX_B28P V13 GPIO0_D38
Power Monitor GPIO1_D11 AA7 DIFFIO_TX_RX_B16N DIFFIO_TX_RX_B34N W14 GPIO0_D41
PMONITOR_I2C_SCL 24 GPIO1_D17 W5 DIFFIO_TX_RX_B16P DIFFIO_TX_RX_B34P R13 GPIO0_D43
PMONITOR_I2C_SDA 24 GPIO1_D2 W6 DIFFIO_TX_RX_B1N DIFFIO_TX_RX_B36N P13 SD_SEL
PMONITOR_ALERT 24 RH_TEMP_I2C_SCL Y10 DIFFIO_TX_RX_B1P DIFFIO_TX_RX_B36P Y13 GPIO0_D31
RH_TEMP_I2C_SDA AA10 DIFFIO_TX_RX_B22N DIFFIO_TX_RX_B37N Y14 GPIO0_D20
PWR_BUT U6 DIFFIO_TX_RX_B22P DIFFIO_TX_RX_B37P V14 GPIO0_D39
GPIO1_D15 U7 DIFFIO_TX_RX_B3N DIFFIO_TX_RX_B39N W15 GPIO0_D19
GPIO1_D19 W4 DIFFIO_TX_RX_B3P DIFFIO_TX_RX_B39P U15 GPIO0_D42
CapSense Buttons GPIO1_D22 W3 DIFFIO_TX_RX_B5N DIFFIO_TX_RX_B41N V16 GPIO0_D10
CAP_SENSE_I2C_SCL 23 GPIO1_D7 V7 DIFFIO_TX_RX_B5P DIFFIO_TX_RX_B41P AA17 GPIO0_D3
CAP_SENSE_I2C_SDA 23 GPIO1_D5 V8 DIFFIO_TX_RX_B7N DIFFIO_TX_RX_B43N Y17 GPIO0_D40
GPIO1_D18 R9 DIFFIO_TX_RX_B7P DIFFIO_TX_RX_B43P V15 GPIO0_D12
B B
GPIO1_D20 P9 DIFFIO_TX_RX_B9N DIFFIO_TX_RX_B45N W16 GPIO0_D17
AA3 DIFFIO_TX_RX_B9P DIFFIO_TX_RX_B45P Y19 GPIO0_D2
TEMP_CS_n AB4 VREFB3N0 DIFFIO_TX_RX_B49N W18 GPIO0_D0
IO_BANK3 DIFFIO_TX_RX_B49P AA13 GPIO0_D25
VREFB4N0 AB14 GPIO0_D22
IO_BANK4

10M50DAF484C6GES
Micro SD Card
14 SD_SEL

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B MAX 10 Bank 3 & 4 C

Date: Wednesday, March 11, 2015 Sheet 4 of 25

5 4 3 2 1
 5 4 3 2 1

DDR3_CK_p 13
DDR3_CK_n 13

DDR3_CKE 13
DDR3_RESET_n 13
D VCC1P5_DDR3 U1C DDR3_WE_n 13 D
DDR3_RAS_n 13
MAX 10 RIGHT BANKS DDR3_CAS_n 13
R229
BANK-5 BANK-6 DDR3_CS_n 13
VCCIO = 1.5V VCCIO = 1.5V
DDR3_RESET_n U19 H21 KEY0 DDR3_ODT 13
49.9 DDR3_A6 V18 DIFFIO_RX_R19N DIFFIO_RX_R39N H22 KEY1
U18 DIFFIO_RX_R19P DIFFIO_RX_R39P J21 SW0
U17 DIFFIO_RX_R1P/RUP DIFFIO_RX_R41N J22 SW1 13 DDR3_A[14..0]
DDR3_A9 W22 DIFFIO_RX_R1N/RDN DIFFIO_RX_R41P G19
R217 DDR3_A11 Y22 DIFFIO_RX_R20N DIFFIO_RX_R42N G20 13 DDR3_DM[1..0]
DDR3_A14 W20 DIFFIO_RX_R20P DIFFIO_RX_R42P F22 DDR3_CS_n
DDR3_BA1 W19 DIFFIO_RX_R21N DIFFIO_RX_R43N G22 DDR3_ODT 13 DDR3_BA[2..0]
DDR3_A4 Y21 DIFFIO_RX_R21P DIFFIO_RX_R43P M14 DDR3_DQ5
49.9 DDR3_A8 Y20 DIFFIO_RX_R22N DIFFIO_RX_R44N/DQ2R M15 DDR3_DQ3
DDR3_A7 U20 DIFFIO_RX_R22P DIFFIO_RX_R44P/DQ2R E21 DDR3_A0 DDR3_DQ[ 15..0] 13
Micro SD Card DDR3_A1 V20 DIFFIO_RX_R23N DIFFIO_RX_R45N E22 DDR3_WE_n
SD_DAT[3..0] DDR3_A13 V22 DIFFIO_RX_R23P DIFFIO_RX_R45P N19 DDR3_DM0 DDR3_DQS_p[1..0] 7,13
14 DIFFIO_RX_R24N DIFFIO_RX_R46N/DM2R
DDR3_A2 V21 N18 DDR3_A12
AUDIO_BCLK R14 DIFFIO_RX_R24P DIFFIO_RX_R46P/DQ2R M20 DDR3_DQ6 DDR3_DQS_n[1..0] 7,13
SD_CMD AUDIO_WCLK R15 DIFFIO_RX_R25N/DQ1R DIFFIO_RX_R47P/DQ2R N20 DDR3_DQ7
14 DIFFIO_RX_R25P/DQ1R DIFFIO_RX_R47N/DQ2R
SD_D0_DIR T22 F20
SD_CMD T21 DIFFIO_RX_R26N DIFFIO_RX_R48N F21
C SD_CLK DIFFIO_RX_R26P DIFFIO_RX_R48P C
SD_DAT1 T18 C22 DDR3_A10
14 DIFFIO_RX_R27N/DM1R DIFFIO_RX_R49N
SD_DAT2 T19 D22 DDR3_RAS_n
SD_DAT3 R20 DIFFIO_RX_R27P/DQ1R DIFFIO_RX_R49P L18 DDR3_DQ2
SD_D0_DIR SD_CLK T20 DIFFIO_RX_R28N/DQ1R DIFFIO_RX_R51N/DQ2R M18 DDR3_DQ4
14 DIFFIO_RX_R28P/DQ1R DIFFIO_RX_R51P/DQ2R
SD_CMD_DIR U22 L20 DDR3_DQ0
SD_D123_DIR SD_D123_DIR U21 DIFFIO_RX_R29N DIFFIO_RX_R52N/DQ2R L19 DDR3_DQ1
14 DIFFIO_RX_R29P DIFFIO_RX_R52P/DQ2R
AA22 F18
SD_CMD_DIR AA21 DIFFIO_RX_R2N DIFFIO_RX_R53N E19
14 DIFFIO_RX_R2P DIFFIO_RX_R53P
AUDIO_MCLK P14 E20 DDR3_CAS_n
SD_FB_CLK AUDIO_DIN_MFP1 P15 DIFFIO_RX_R30N/DQ1R DIFFIO_RX_R54N F19 DDR3_BA2
14 AUDIO_SPI_SELECT N22 DIFFIO_RX_R30P/DQ1R DIFFIO_RX_R54P K15 DDR3_DQS_n1
AUDIO_SDA_MOSI P21 DIFFIO_RX_R31N DIFFIO_RX_R55N/DQSN3R K14 DDR3_DQS_p1
AUDIO_DOUT_MFP2 P18 DIFFIO_RX_R31P DIFFIO_RX_R55P/DQS3R D19 DDR3_BA0
Audio CODEC Interface SD_DAT0 R18 DIFFIO_RX_R32N/DQSN1R DIFFIO_RX_R56N C20 DDR3_A3
AUDIO_MCLK AUDIO_SCL_SS_n P20 DIFFIO_RX_R32P/DQS1R DIFFIO_RX_R56P J18 DDR3_DQ10
17 AUDIO_SCLK_MFP3 DIFFIO_RX_R33N/DQ1R DIFFIO_RX_R57N/DQ3R DDR3_DQ9
P19 K18
AUDIO_BCLK L22 DIFFIO_RX_R33P/DQ1R DIFFIO_RX_R57P/DQ3R K20 DDR3_DQ11
17 AUDIO_RESET_n M21 DIFFIO_RX_R34N DIFFIO_RX_R58N/DQ3R K19 DDR3_DQ8
AUDIO_WCLK AUDIO_GPIO_MFP5 M22 DIFFIO_RX_R34P DIFFIO_RX_R58P/DQ3R E17 VCC1P5_DDR3
17 AUDIO_MISO_MFP4 N21 DIFFIO_RX_R35N DIFFIO_RX_R59N F17
AUDIO_DIN_MFP1 DDR3_VREF P22 DIFFIO_RX_R35P DIFFIO_RX_R59P B21
17 VREFB5N0 DIFFIO_RX_R60N
SD_FB_CLK R22 B22 DDR3_CKE
AUDIO_DOUT_MFP2 IO_BANK5 DIFFIO_RX_R60P J15 DDR3_DM1
17 DIFFIO_RX_R61N/DM3R
B J14 DDR3_A5 C89 DNI R167 B
DIFFIO_RX_R61P/DQ3R A21
DIFFIO_RX_R62N 1K
B20 0.1u
DIFFIO_RX_R62P H18 DDR3_DQ12
Audio Control Interface DIFFIO_RX_R63N/DQ3R H19 DDR3_DQ15
AUDIO_SCLK_MFP3 DIFFIO_RX_R63P/DQ3R DDR3_VREF
H20 DDR3_DQ14
17 DIFFIO_RX_R64N/DQ3R J20 DDR3_DQ13
AUDIO_SCL_SS_n DIFFIO_RX_R64P/DQ3R E18 DDR3_CK_n C195 C102 R177
17 DIFFIO_RX_R70N/CK#_6 D18 DDR3_CK_p 1K
AUDIO_SDA_MOSI DIFFIO_RX_R70P/CK_6 D21 DDR3_VREF 0.1u 0.1u
17 VREFB6N0 C21
AUDIO_MISO_MFP4 IO_BANK6
17
AUDIO_SPI_SELECT 10M50DAF484C6GES
17
AUDIO_RESET_n
17
AUDIO_GPIO_MFP5
17

SWITCH
SW[1..0]
23
A A
KEY
KEY[1..0] Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
23 All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B MAX 10 Bank 5 & 6 C

Date: Thursday, May 21, 2015 Sheet 5 of 25

5 4 3 2 1
 5 4 3 2 1

U1D
D D

USB PHY MAX 10 TOP BANKS

19 USB_CLKOUT_NOPLL BANK-7 BANK-8
USB_DATA[7..0] VCCIO = 1.8V VCCIO = 1.2V
19
MIPI Interface HDMI_TX_D9 A17 C7 LED0
USB_NXT HDMI_TX_D22 A18 DIFFIO_RX_T10N DIFFIO_RX_T39N C8 LED1
19 DIFFIO_RX_T10P DIFFIO_RX_T39P
19 USB_DIR MIPI_LP_MD_p[3..0]
15 HDMI_TX_D11 C15 A6 LED2
USB_STP HDMI_TX_D17 C16 DIFFIO_RX_T15N DIFFIO_RX_T41N B7 LED3
19 DIFFIO_RX_T15P DIFFIO_RX_T41P
USB_CS MIPI_LP_MD_n[3..0] HDMI_TX_D15 A16 D8 USB_FAULT_n
19 15 DIFFIO_RX_T16N DIFFIO_RX_T42P
19 USB_RESET_n HDMI_TX_D10 B16 A4 MIPI_LP_MD_p0
USB_DIR J13 DIFFIO_RX_T16P DIFFIO_RX_T43N A5 LED5
USB_FAULT_n USB_DATA4 H14 DIFFIO_RX_T17N DIFFIO_RX_T43P E9 G_SENSOR_CS_n
19 DIFFIO_RX_T17P DIFFIO_RX_T44N
HDMI_TX_D23 C13 A2 MIPI_LP_MD_n3
HDMI_TX_D8 C14 DIFFIO_RX_T18N DIFFIO_RX_T45P A3 MIPI_LP_MD_n0
LED HDMI_TX_D21 B14 DIFFIO_RX_T18P DIFFIO_RX_T45N B3 MIPI_LP_MD_p3
LED[7..0] HDMI_TX_D12 A14 DIFFIO_RX_T19N DIFFIO_RX_T46P B4 LED6
HDMI TX 23
USB_DATA6 E15 DIFFIO_RX_T19P DIFFIO_RX_T46N B5 G_SENSOR_SCLK
16 HDMI_TX_D[23..0] USB_RESET_n E16 DIFFIO_RX_T1N DIFFIO_RX_T47P C4 LED4
USB_DATA1 E13 DIFFIO_RX_T1P DIFFIO_RX_T47N E8 G_SENSOR_INT1
6,7,16 HDMI_TX_CLK HDMI_TX_D4 D14 DIFFIO_RX_T20N DIFFIO_RX_T48P D5 G_SENSOR_SDO
USB_DATA0 E12 DIFFIO_RX_T20P DIFFIO_RX_T49N C5 LED7
16 HDMI_TX_HS Accelerometer HDMI_TX_D6 D13 DIFFIO_RX_T21P DIFFIO_RX_T49P B1 MIPI_LP_MD_p2
G_SENSOR_SDI 21 USB_STP J12 DIFFIO_RX_T21N DIFFIO_RX_T51N B2 MIPI_LP_MD_n2
C 16 HDMI_TX_VS DIFFIO_RX_T22N DIFFIO_RX_T51P C
USB_DATA2 H13 C2 MIPI_LP_MD_n1
G_SENSOR_SCLK 21 HDMI_TX_D14 A12 DIFFIO_RX_T22P DIFFIO_RX_T53N C3 MIPI_LP_MD_p1
16 HDMI_TX_DE HDMI_TX_D16 A13 DIFFIO_RX_T23N DIFFIO_RX_T53P D7 G_SENSOR_INT2
HDMI_SCLK D12 DIFFIO_RX_T23P VREFB8N0 C6 G_SENSOR_SDI
HDMI_TX_INT G_SENSOR_INT1 21 HDMI_TX_D18 C12 DIFFIO_RX_T24N IO_BANK8
G_SENSOR_INT2 21 HDMI_LRCLK A10 DIFFIO_RX_T24P
HDMI_I2S1 A11 DIFFIO_RX_T25N
16 HDMI_I2C_SDA G_SENSOR_CS_n 21 HDMI_I2C_SCL C10 DIFFIO_RX_T25P
HDMI_TX_VS C11 DIFFIO_RX_T26N
16 HDMI_I2C_SCL G_SENSOR_SDO 21 HDMI_TX_HS B11 DIFFIO_RX_T26P
HDMI_TX_D20 B12 DIFFIO_RX_T27N
6,7,16 HDMI_TX_CLK USB_CS J11 DIFFIO_RX_T27P
USB_NXT H12 DIFFIO_RX_T28N
HDMI_I2S3 B8 DIFFIO_RX_T28P
HDMI Audio Interface HDMI_I2S0 A9 DIFFIO_RX_T31N
16 HDMI_I2S[3:0] HDMI_TX_D2 C17 DIFFIO_RX_T31P
HDMI_TX_D1 D17 DIFFIO_RX_T2N
16 HDMI_MCLK HDMI_TX_DE C9 DIFFIO_RX_T2P
HDMI_TX_INT B10 DIFFIO_RX_T30N
16 HDMI_LRCLK HDMI_MCLK A7 DIFFIO_RX_T30P
HDMI_I2S2 A8 DIFFIO_RX_T29P
16 HDMI_SCLK USB_DATA7 F15 DIFFIO_RX_T29N
USB_CLKOUT_NOPLL F16 DIFFIO_RX_T5N
HDMI_TX_D5 B19 DIFFIO_RX_T5P
B B
HDMI_TX_D3 C19 DIFFIO_RX_T6N
HDMI_TX_D19 B17 DIFFIO_RX_T6P
HDMI_TX_D0 C18 DIFFIO_RX_T7N
HDMI_TX_D7 A19 DIFFIO_RX_T7P
HDMI_TX_CLK R168 0 A20 DIFFIO_RX_T8N
USB_DATA3 E14 DIFFIO_RX_T8P
USB_DATA5 D15 DIFFIO_RX_T9N
HDMI_I2C_SDA B15 DIFFIO_RX_T9P
HDMI_TX_D13 A15 VREFB7N0
IO_BANK7

10M50DAF484C6GES

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B MAX 10 Bank 7 & 8 C

Date: Thursday, March 19, 2015 Sheet 6 of 25

5 4 3 2 1
 5 4 3 2 1

DDR3
DDR3_DQS_p0 13
Ethernet USB PHY
USB_CLOCK R169 0 USB_CLKOUT
DDR3_DQS_n0 19
13 NET_RX_CLK DNI
18 JTAG Interface
DDR3_CLK_50 10 NET_RESET_n
Header GPIO R170 0 USB_CLKIN JTAG_TCK 11
18
12 GPIO1_D14 JTAG_TMS 11
NET_TX_EN 18 12 GPIO1_D8 JTAG_TDO 11
12 GPIO1_D21 JTAG_TDI 11
NET_TX_CLK 18 12 GPIO0_D13 MIPI Interface JTAG_EN 11
D D
MAX10_CLK1_50 10 NET_PCF_EN MIPI_MC_p
18 15
MAX10_CLK2_50 10 HDMI TX MIPI_MC_n
ADC_CLK_10 10 6,16 HDMI_TX_CLK 15 MAX10 CONFIG Status
MIPI_LP_MC_p
15 11 NCONFIG
U1E
MIPI_LP_MC_n
15 11 NSTATUS
MAX 10 CLOCK
11 CONF_DONE
BANK-2 VCCIO = 2.5V VCC2P5
MIPI_MC_n N4 P3 NET_TX_EN
MIPI_MC_p N5 DIFFIO_RX_L28N/CLK0N DIFFIO_RX_L38N/DPCLK0 R3 NET_RESET_n
MAX10_CLK1_50 M8 DIFFIO_RX_L28P/CLK0P DIFFIO_RX_L38P/DPCLK1 T5 NET_TX_CLK
ADC_CLK_10 M9 DIFFIO_RX_L36N/CLK1N DIFFIO_RX_L59N/PLL_L_CLKOUTN T6 NET_RX_CLK U1F
DIFFIO_RX_L36P/CLK1P DIFFIO_RX_L59P/PLL_L_CLKOUTP R257R258R259

10K 10K 10K

MAX 10 Configuration
BANK-3 VCCIO = 3.3V BANK-1B BANK-8
NET_PCF_EN V9 VCCIO = 2.5V VCCIO = 1.2V
GPIO1_D14 V10 DIFFIO_TX_RX_B18N/CLK6N
GPIO1_D8 R11 DIFFIO_TX_RX_B18P/CLK6P JTAG_EN K9 H9 NCONFIG
MAX10_CLK2_50 P11 DIFFIO_TX_RX_B20N/CLK7N JTAG_TCK G2 DIFFIO_RX_L15P/JTAGEN NCONFIG H10 BOOT_SEL
C DIFFIO_TX_RX_B20P/CLK7P DIFFIO_RX_L17P/TCK BOOT_SEL C
JTAG_TMS H2 D9
JTAG_TDO L4 DIFFIO_RX_L17N/TMS DIFFIO_RX_T42N/DEV_CLRN D10
R256 JTAG_TDI M5 DIFFIO_RX_L18N/TDI DIFFIO_RX_T44P/DEV_OE F7
1K DIFFIO_RX_L18P/TDO DIFFIO_RX_T48N/CRC_ERROR G9 NSTATUS
BANK-4 VCCIO = 3.3V DIFFIO_RX_T50P/NSTATUS
W17 GPIO0_D13 F8 CONF_DONE
DIFFIO_TX_RX_B57N/PLL_B_CLKOUTN V17 GPIO1_D21 DIFFIO_RX_T50N/CONF_DONE
DIFFIO_TX_RX_B57P/PLL_B_CLKOUTP

BANK-6 VCCIO = 1.5V 10M50DAF484C6GES

DDR3_CLK_50 N15 L15 DDR3_DQS_n0
N14 DIFFIO_RX_R38N/CLK2N DIFFIO_RX_R50N/DPCLK2/DQSn2R L14 DDR3_DQS_p0
K21 DIFFIO_RX_R38P/CLK2P DIFFIO_RX_R50P/DPCLK3/DQS2R G17
K22 DIFFIO_RX_R40N/CLK3N DIFFIO_RX_R69N/PLL_R_CLKOUTN H17 USB_CLKOUT
DIFFIO_RX_R40P/CLK3P DIFFIO_RX_R69P/PLL_R_CLKOUTP

BANK-8 VCCIO = 1.2V

MIPI_LP_MC_n E10
MIPI_LP_MC_p E11 DIFFIO_RX_T38N/CLK4N
J10 DIFFIO_RX_T38P/CLK4P E6
USB_CLKIN H11 DIFFIO_RX_T40P/CLK5P DIFFIO_RX_T52N/PLL_T_CLKOUTN D6 R171 0 HDMI_TX_CLK SW2
DIFFIO_RX_T40N/CLK5N DIFFIO_RX_T52P/PLL_T_CLKOUTP 1 2 BOOT_SEL R195 10K

ON
VCC1P2

1
B DNI B
10M50DAF484C6GES SW-DIP2

MIPI_MC_p

R218

100
MIPI_MC_n

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B MAX 10 Clocks & Configuration C

Date: Thursday, March 19, 2015 Sheet 7 of 25

5 4 3 2 1
 5 4 3 2 1

VCC1P2_VCC VCC1P2_VCCD
L21 30ohm, 3A

C230 C242
10u
0.1u
D D
U1G U1H
Place filter close to VCCIO1A pins
VCC1P2_VCC
MAX 10 POWER VCC2P5
MAX 10 GROUND
K12
N12 L6 L17 Y9 GND K10
N10 VCC VCCIO1A K7 VCC2P5 0.35ohm, 0.3A Y15 GND GND K3
VCC2P5 VCC2P5_VCCA M13 VCC VCCIO1A M6 C163 Y12 GND GND J6
L26 30ohm, 3A M12 VCC VCCIO1B L7 W21 GND GND J2
M11 VCC VCCIO1B 0.1u V6 GND GND J19
L12 VCC R6 V2 GND GND J16
C260 C219 L11 VCC VCCIO2 P7 VCC2P5 V19 GND GND G8
10u L10 VCC VCCIO2 N7 U13 GND GND G6
0.1u K13 VCC VCCIO2 N6 U10 GND GND G21
K11 VCC VCCIO2 T8 GND GND G18
VCC1P2_VCCD VCC U9 T4 GND GND G15
VCCIO3 U8 T16 GND GND F13
T7 VCCIO3 T9 VCC3P3 T14 GND GND F10
G16 VCCD_PLL1 VCCIO3 T11 R21 GND GND E7
G7 VCCD_PLL2 VCCIO3 T10 R19 GND GND E2
VCC1P2_VCC 1.2V_VDDADC U16 VCCD_PLL3 VCCIO3 P6 GND GND D4
L8 30ohm, 3A VCC2P5_VCCA VCCD_PLL4 U14 P2 GND GND D20
VCCIO4 U12 P17 GND GND D16
C VCCIO4 GND GND C
R8 U11 VCC3P3 N13 D11
C41 C181 H15 VCCA1 VCCIO4 T13 N11 GND GND B9
10u H8 VCCA2 VCCIO4 T12 M7 GND GND B6
0.1u T15 VCCA3 VCCIO4 M19 GND GND B18
1.2V_VDDADC VCCA4 T17 M16 GND GND B13
VCCIO5 R17 M10 GND GND AB22
J7 VCCIO5 R16 VCC1P5_DDR3 L5 GND GND AB1
H7 VCCINT VCCIO5 P16 L21 GND GND AA4
VCC2P5_VCCAADC VCCA_ADC VCCIO5 GND GND
N16 L17 AA18
VCCIO5 L13 GND GND A22
VCC2P5 VCC2P5_VCCAADC H6 N17 REFGND2 GND GND A1
VCC2P5_VREF ADC_VREF VCCIO6 GND
L16 30ohm, 3A M17 DNI
VCCIO6 L16
ANAIN1 20 G5 VCCIO6 K17 L3 E5
C164 C143 ANAIN2 20 J5 ANAIN1 VCCIO6 K16 VCC1P5_DDR3 REFGND H5 DNU NC1 F6
10u ANAIN2 VCCIO6 J17 REFGND NC2
0.1u VCCIO6 H16
VCCIO6 10M50DAF484C6GES
G14
VCCIO7 G13
VCCIO7 G12 VCC1P8
VCCIO7 F14
VCCIO7 F12
VCCIO7
B B
G11
VCCIO8 G10 VCC1P2
VCCIO8 F9
VCCIO8 F11
VCCIO8 Place this FB close to MAX10 ADC_VREF

10M50DAF484C6GES L15 30ohm, 3A

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B MAX10 Power & GND C

Date: Wednesday, March 11, 2015 Sheet 8 of 25

5 4 3 2 1
 5 4 3 2 1

VCC1P2_VCC VCC1P5_DDR3
D D

C208 C209 C202 C161 C159 C201 C200 C199 C198 C180 C179 C157 C160 C158 C38 C135 C154 C178 C155 C217 C197 C196 C156

10u 10u 1u 1u 1u 1u 1u 1u 1u 1u 22n 22n 10n 10n 10u 1u 1u 1u 1u 1u 1u 10n 10n

VCC1P2

VCC1P2_VCCD

C121 C119 C141 C120 C118

C122 C136 C228 C218 4.7u 0.1u 0.1u 0.1u 0.1u

4.7u 0.1u 0.1u 0.1u

VCC1P8
C C

C90 C114 C117 C140 C116 C115 C138

VCC2P5_VCCA
10u 0.1u 0.1u 0.1u 0.1u 10n 10n

C221 C259 C137 C204 C227 C220 C139 C162

1u 1u 1u 1u 1u 1u 10n 10n
VCC2P5

C261 C262 C229 C206 C203 C207 C205

10u 0.1u 0.1u 0.1u 0.1u 10n 10n

B B

VCC3P3

C222 C226 C223 C224 C225

4.7u 0.1u 0.1u 0.1u 0.1u

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B MAX10 Decoupling C

Date: Wednesday, March 11, 2015 Sheet 9 of 25

5 4 3 2 1
 5 4 3 2 1

VCC3P3_CLKGEN VCC2P5

C64 C63
D 0.1u 0.1u D
VCC3P3_CLKGEN

VCC3P3 L25
0.35ohm, 0.3A VCC3P3_CLKGEN VCC2P5
U24
1 VCCA VCCB 6

11
10
18
14
20
U20 3 A B 4 7 MAX10_CLK2_50
5 2

VDDOA
VDDOB
VDDOC
VDDOD
VDD
DIR GND

SN74AVC1T45
VCC3P3_CLKGEN 13 7 MAX10_CLK1_50
3 CLK0 12
4 GND CLK1
5 GND 9 UB2_CLK_24
11
C258 Y1 7 GND CLK2 8 NET_CLK_25 VCC3P3_CLKGEN VCC1P5_DDR3
18
1 4 GND CLK3 U33
0.1u EN VCC 19 USB_CLK_19 1 VCCA VCCB 6
19 19.2MHz
2 3 R105 24.9 6 CLK4 17 3 A 4 DDR3_CLK_50
B 7
GND OUT CLKIN CLK5 5 2

GND_EP
501BAB25M0000CAFR 1 16 7 ADC_CLK_10 DIR GND
XA CLK6 15 UB2_CLK_50 SN74AVC1T45
25.00MHz CLK7
11
2
XB
C C
Si5350C-B03812-GM

21
VCC3P3_CLKGEN VCC1P5_DDR3

C43 C42

0.1u 0.1u
VCC3P3_CLKGEN

C256 C268 C255 C269 C257

0.47u 0.47u 0.47u 0.47u 0.47u

B B

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B Oscillator, Clock Generator C

Date: Wednesday, March 11, 2015 Sheet 10 of 25

5 4 3 2 1
 5 4 3 2 1

J10 VCC3P3 U21-1 CPLD ISP VCC3P3

1 VCC5_USB
VBUS 2 FX2_D_N U39 5M570ZM100
D- 3 FX2_D_P 3
D+ VCC Bank 1
4 FX2_PA2 B1 VCCIO = 3.3V K3 FX2_PB1 TP1 DNI
ID 5 C271 2 FX2_RESETn FX2_FLAGC C2 IOB1_1 IOB1_16 L3 FX2_PB3
GND U36 0.1u RESET FX2_PA7 C1 IOB1_2 IOB1_17 K4 FX2_SCL
6 1 10V 1 FX2_FLAGA D3 IOB1_3 IOB1_18 L4 FX2_PD6 C_USB_MAX_TCK TP2 DNI
SHIELD1 7 3 D+ 2 GND R242 FX2_PA3 D2 IOB1_4 IOB1_19 K5 FX2_PD4 C_USB_MAX_TDO TP3 DNI
SHIELD2 GND D- TLV809K33DBVR 100K FX2_PA4 D1 IOB1_5 IOB1_20 L5 FX2_SLWRn C_USB_MAX_TMS TP4 DNI
D Mini-USB-B TPD2EUSB30DRTR FX2_PB4 F1 IOB1_6 IOB1_21 L6 FX2_PD7 D
FX2_PA6 G1 IOB1_7 IOB1_22 K6 FX2_PD5 C_USB_MAX_TDI TP5 DNI
FX2_PB2 G2 IOB1_8 IOB1_23 J6 FX2_PA5
VCC3P3 FX2_FLAGB F3 IOB1_9 IOB1_24 L7 FX2_SLRDn
U19 VCC3P3 FX2_PB0 IOB1_10 IOB1_25
R93 1M H1 K7 TP6 DNI
D1 B8 FX2_RESETn FX2_PA1 H3 IOB1_11 IOB1_26 L9
D2 AVCC RESET F3 FX2_SCL R239 2K FX2_PB5 H2 IOB1_12 IOB1_27 K9
AVCC SCL G3 FX2_SDA R238 2K FX2_PB6 L1 IOB1_13 IOB1_28 L10 CLK_12MHz
C50 4.7n G1 SDA L2 IOB1_14 IOB1_29 K10 JTAG_TX
50V A5 VCC B7 FX2_WAKEUP IOB1_15 IOB1_30 L11 JTAG_RX
B5 VCC WAKEUP USB_CLK F2 IOB1_31
C5 VCC H7 FX2_FLAGA FX2_PB7 E1 IOB1/CLK0 K1 C_USB_MAX_TCK R247 0 FX2_PD0
E7 VCC CTL0 G7 FX2_FLAGB IOB1/CLK1 TCK K2 C_USB_MAX_TDO R108 0 FX2_PD3
E8 VCC CTL1 H8 FX2_FLAGC FX2_SDA L8 TDO J1 C_USB_MAX_TMS R109 0 FX2_PD1
VCC CTL2 FX2_RESETn K8 IOB1/DEV_OE TMS J2 C_USB_MAX_TDI R110 0 FX2_PD2
E1 A1 FX2_SLRDn IOB1/DEV_CLRN TDI
E2 DMINUS RDY0 B1 FX2_SLWRn R101 1K
DPLUS RDY1 VCC3P3
EPM570GM100C5N
USB_CLK G2 B2 R248 1K
UB2_CLK_24 R82 10 C1 IFCLK CLKOUT
C2 XTALIN U21-2
XTALOUT
G8 H3 FX2_PB0 5M570ZM100
FX2_PA1 G6 PA0 PB0 F4 FX2_PB1
C PA1 PB1 Bank 2 C
FX2_PA2 F8 H4 FX2_PB2 K11 VCCIO = 2.5V B10 R118 0 JTAG_TCK
FX2_PA3 F7 PA2 PB2 G4 FX2_PB3 J10 IOB2_1 IOB2_18 A11 R119 0 JTAG_TDO
FX2_PA4 F6 PA3 PB3 H5 FX2_PB4 J11 IOB2_2 IOB2_19 A10 R120 0 JTAG_TMS
FX2_PA5 C8 PA4 PB4 G5 FX2_PB5 H9 IOB2_3 IOB2_20 B9 R121 0 JTAG_TDI
FX2_PA6 C7 PA5 PB5 F5 FX2_PB6 H10 IOB2_4 IOB2_21 A9
FX2_PA7 C6 PA6 PB6 H6 FX2_PB7 H11 IOB2_5 IOB2_22 B8 JTAG_EN
PA7 PB7 G10 IOB2_6 IOB2_23 A8 NCONFIG_MAX10
H2 A8 FX2_PD0 F9 IOB2_7 IOB2_24 B7 NSTATUS_MAX10
VCC5_USB R245 10K FX2_WAKEUP RESERVED PD0 A7 FX2_PD1 F11 IOB2_8 IOB2_25 A7 CONF_DONE_MAX10
F1 PD1 B6 FX2_PD2 E11 IOB2_9 IOB2_26 C6
F2 AGND PD2 A6 FX2_PD3 E10 IOB2_10 IOB2_27 B6
R246 C270 AGND PD3 B3 FX2_PD4 D9 IOB2_11 IOB2_28 A6
20K 0.1u H1 PD4 A3 FX2_PD5 D11 IOB2_12 IOB2_29 A5
10V A4 GND PD5 C3 FX2_PD6 D10 IOB2_13 IOB2_30 B5 CONF_DONE_DISP
B4 GND PD6 A2 FX2_PD7 C11 IOB2_14 IOB2_31 B4
C4 GND PD7 C10 IOB2_15 IOB2_32 A3
D7 GND B11 IOB2_16 IOB2_33 B3
D8 GND IOB2_17 IOB2_34 A2
GND UB2_CLK_24 R117 10 F10 IOB2_35 B2
JTAG Interface CY7C68013A_VFBGA DNI UB2_CLK_50 G11 IOB2/CLK2 IOB2_36 A1
JTAG_TCK IOB2/CLK3 IOB2_37
7
JTAG_TMS 7
JTAG_TDO 7 EPM570GM100C5N
B JTAG_TDI 7 VCC3P3 B
Place Near CY7C68013A
JTAG_EN 7 VCC2P5 VCC3P3 VCC1P8
Place near MAX V Place near MAX V
C49 C55 C244 C243 C250 C249 C245 C246
MAX10 CONFIG Status 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u U21-3
10V 10V 10V 10V 10V 10V 10V 10V C265 C272 C251 C267 C252 C253 C254 C266 C263 C264 VCC1P8
NCONFIG
7 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 5M570ZM100
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V Power
NSTATUS 7 VCC3P3 C7 C5
E9 VCCINT GND D5
CONF_DONE G3 VCCINT GND D7
7 VCCINT GND
VCC3P3 J7 E8
D5 LEDG VCCINT GND G8
JTAG_RX 1 2 R216 120 E3 GND H7
UB2 Clock J4 VCCIO1 GND J5
UB2_CLK_24 J8 VCCIO1 GND H5
10
D7 LEDG VCCIO1 GND G4
UB2_CLK_50 JTAG_TX 1 2 R228 120 VCC1P2 VCC1P2 VCC2P5 C4 GND E4
10
C8 VCCIO2 GND E2
VCC2P5 VCCIO2 GND
G9 A4
CLK_12MHz D8 LEDG VCCIO2 GND
16
CONF_DONE_DISP 1 2 R234 120
R188 R197 R206 R113 R114 R122 EPM570GM100C5N
A 10K 10K 10K 10K 10K 10K A
1

Q9
AO3400
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
NCONFIG 2 3 NCONFIG_MAX10 All rights reserved.
3

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

CONF_DONE R102 1K 1 Q4 Q1 AO3400 Title

DNI UTC8050 NSTATUS 2 3 NSTATUS_MAX10
DECA
1

DNI
2

Q8 AO3400 Size Document Number Rev

CONF_DONE 2 3 CONF_DONE_MAX10 B USB Blaster II C

Date: Thursday, May 07, 2015 Sheet 11 of 25

5 4 3 2 1
 5 4 3 2 1

D D

VCC3P3
P8 VCC5 VCC3P3 P9 VCC3P3 VCC5

Header GPIO P8 P9
1 2 R20 1 2
4,7 GPIO0_D[43..0] GPIO0_D0 3 4 GPIO0_D1 10K 3 4
GPIO0_D2 5 6 GPIO0_D3 5 6
4,7 GPIO1_D[22..0] GPIO0_D4 7 8 GPIO0_D5 7 8
GPIO0_D6 9 10 GPIO0_D7 PWR_BUT 9 10 SYS_RESET_n
4 SYS_RESET_n GPIO0_D8 11 12 GPIO0_D9 GPIO1_D0 11 12 GPIO1_D1
GPIO0_D10 13 14 GPIO0_D11 GPIO1_D2 13 14 GPIO1_D3
PWR_BUT GPIO0_D12 15 16 GPIO0_D13 GPIO1_D4 15 16 GPIO1_D5
4
GPIO0_D14 17 18 GPIO0_D15 GPIO1_D6 17 18 GPIO1_D7
C C
GPIO0_D16 19 20 GPIO0_D17 GPIO1_D8 19 20 GPIO1_D9
GPIO0_D18 21 22 GPIO0_D19 GPIO1_D10 21 22 GPIO1_D11
GPIO0_D20 23 24 GPIO0_D21 GPIO1_D12 23 24 GPIO1_D13
Header Analog Input GPIO0_D22 25 26 GPIO0_D23 GPIO1_D14 25 26 GPIO1_D15
AIN[6..0] GPIO0_D24 27 28 GPIO0_D25 GPIO1_D16 27 28 GPIO1_D17 VCC1P8_VCCADC VCC1P8
3
GPIO0_D26 29 30 GPIO0_D27 GPIO1_D18 29 30 GPIO1_D19 L4 30ohm, 3A
GPIO0_D28 31 32 GPIO0_D29 GPIO1_D20 31 32
GPIO0_D30 33 34 GPIO0_D31 AIN6 33 34
GPIO0_D32 35 36 GPIO0_D33 AIN4 35 36 AIN5
GPIO0_D34 37 38 GPIO0_D35 AIN2 37 38 AIN3 C1 C4
GPIO0_D36 39 40 GPIO0_D37 AIN0 39 40 AIN1 0.1u 10u
GPIO0_D38 41 42 GPIO0_D39 GPIO1_D21 41 42 GPIO1_D22 10V 6.3V
GPIO0_D40 43 44 GPIO0_D41 43 44
GPIO0_D42 45 46 GPIO0_D43 45 46

HEADER 23x2 HEADER 23x2

GPIO1_D21 is connected to MAX 10 PLL output pin

B B

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B Expansion Headers - BBB Headers C

Date: Wednesday, March 11, 2015 Sheet 12 of 25

5 4 3 2 1
 5 4 3 2 1

R213 4.7K DDR3_CKE

FLASH_DCLK 4
R90 2K DDR3_RESET_n FLASH_NCSO 4
VCC1P5_DDR3 VCC1P5_DDR3
U12 FLASH_DATA[3..0] 4
DDR3_CK_p R215 100 DDR3_CK_n B2 J2
D9 VDD VSS J8
place close to DDR3 chip G7 VDD VSS A9 FLASH_RESET_n 4
D K2 VDD VSS M1 D
K8 VDD VSS M9
N1 VDD VSS B3
N9 VDD VSS P1
R1 VDD VSS P9 U37
R9 VDD VSS E1 FLASH_DATA3 1 16 FLASH_DCLK
VDD VSS T1 2 HOLD_n/DQ3 C 15 FLASH_DATA0
DDR3_A[14..0] 5 VSS VCC3P3 VCC DQ0
A1 T9 FLASH_RESET_n 3 14
A8 VDDQ VSS G8 4 DNU_1 DNU_8 13
C1 VDDQ VSS 5 DNU_2 DNU_7 12
C9 VDDQ B1 6 DNU_3 DNU_6 11
DDR3_DQ[ 15..0] 5 D2 VDDQ VSSQ B9 FLASH_NCSO 7 DNU_4 DNU_5 10
E9 VDDQ VSSQ D1 FLASH_DATA1 8 S_n VSS 9 FLASH_DATA2
F1 VDDQ VSSQ D8 DQ1 W_n/Vpp/DQ2
H2 VDDQ VSSQ E2
DDR3_BA[2..0] 5 VDDQ VSSQ N25Q512A83GSF40F
H9 E8 GND
VDDQ VSSQ F9
DDR3_VREF H1 VSSQ G1
DDR3_DQS_p[1..0] 5,7 M8 VREFDQ VSSQ G9
VREFCA VSSQ
DDR3_A0 N3
DDR3_DQS_n[1..0] 5,7 DDR3_A1 P7 A0
DDR3_A2 P3 A1
DDR3_A3 N2 A2 E3 DDR3_DQ0 R92 10K FLASH_DCLK
C DDR3_DM[1..0] 5 A3 DQ0 C
DDR3_A4 P8 F7 DDR3_DQ1
DDR3_A5 P2 A4 DQ1 F2 DDR3_DQ2
DDR3_A6 R8 A5 DQ2 F8 DDR3_DQ3
DDR3_A7 R2 A6 DQ3 H3 DDR3_DQ4 VCC3P3 GND
DDR3_A8 T8 A7 DQ4 H8 DDR3_DQ5
VCC1P5_DDR3 DDR3_A9 R3 A8 DQ5 G2 DDR3_DQ6
DDR3_A10 L7 A9 DQ6 H7 DDR3_DQ7 C60
DDR3_A11 R7 A10/AP DQ7 D7 DDR3_DQ8 0.1u
DDR3_A12 N7 A11 DQ8 C3 DDR3_DQ9 10V
DDR3_A13 T3 A12/BC_n DQ9 C8 DDR3_DQ10
C239DNI R81 DDR3_A14 T7 A13 DQ10 C2 DDR3_DQ11
A14 DQ11 A7 DDR3_DQ12 GND
1K DQ12
0.1u DNI DDR3_CK_p 5 J7 A2 DDR3_DQ13
DDR3_CK_n 5 K7 CLK DQ13 B8 DDR3_DQ14 R107 DNI FLASH_NCSO
CLK_n DQ14 VCC3P3
DDR3_VREF DDR3_CKE 5 K9 A3 DDR3_DQ15
CKE DQ15 R111 2k FLASH_RESET_n
DDR3_CS_n 5 L2
R227 DDR3_RESET_n 5 T2 CS F3 DDR3_DQS_p0 R91 DNI FLASH_DATA0
DDR3_WE_n 5 L3 RESET LDQS G3 DDR3_DQS_n0
1K WE LDQSn
DNI DDR3_RAS_n 5 J3 C7 DDR3_DQS_p1 R106 DNI FLASH_DATA1
DDR3_CAS_n 5 K3 RAS UDQS B7 DDR3_DQS_n1
CAS UDQSn R235 DNI FLASH_DATA2
DDR3_BA0 M2
DDR3_BA1 N8 BA0 J1 R112 DNI FLASH_DATA3
B B
DDR3_BA2 M3 BA1 NC1 J9
BA2 NC2 L1
DDR3_DM0 E7 NC3 L9 Note: place a pull down resistor on the FLASH_DCLK wire at the Master
DDR3_DM1 D3 LDM NC4 M7
UDM NC5
DDR3_ODT 5 K1 L8 DDR3_RZQ R214
ODT ZQ 240
MT41K256M16HA-125 IT:E

VCC1P5_DDR3

C174 C216 C133 C173 C175 C194 C152 C176 C134 C153 C214

2.2n 2.2n 2.2n 2.2n 2.2n 2.2n 3.3n 4.7n 10n 10n 10n

VCC1P5_DDR3 DDR3_VREF

C151 C150 C132 C241 C193 C240

C177 C215
A 0.1u 0.1u 0.1u 0.47u 0.47u 0.47u A
0.1u 0.1u
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B DDR3 SDRAM, QSPI Flash C

Date: Wednesday, March 11, 2015 Sheet 13 of 25

5 4 3 2 1
 5 4 3 2 1

SD_SEL = 0, VCCIO_SD = 3.3V

VCC3P3 SD_SEL = 1, VCCIO_SD = 1.8V
VCC2P8 R127 0 VCCIO_SD
D U26 D
Micro SD Card R128 0 A2 A1
5 SD_DAT[3..0] VIN VOUT VCCIO_SD VCC3P3 VCC3P3_SD
DNI
B2 B1 C65 L9 30ohm, 3A
ON GND 10u
5 SD_CMD TPS22910AYZVR
R126 VCC1P8 C68 C67
0 U25 0.1u
5 SD_CLK VCC1P8 A2 A1 10u 10V
VIN VOUT
R250 1K B2 B1
5 SD_FB_CLK DNI ON GND
TPS22912CYZVR

3
5 SD_D0_DIR SD_SEL R252 1K 1 Q10
DNI UTC8050
5 SD_D123_DIR DNI

2
R130
5 SD_CMD_DIR 1K
VCCIO_SD
RN1
4 SD_SEL 8 1 ex_SD_DAT1
7 2 ex_SD_DAT0
6 3 ex_SD_DAT3
C C
5 4 ex_SD_DAT2

10K
R129 10K ex_SD_CMD

VCC1P5_DDR3 U22 VCCIO_SD

A5 D5 VCC3P3_SD J11
VCCA VCCB
C66 C61 ex_SD_DAT2 1
0.1u 0.1u ex_SD_DAT3 2 DAT2

SOCKET-SD_CARD_3
10V 10V ex_SD_CMD 3 DAT3
4 CMD
SD_DAT0 B2 D2 ex_SD_DAT0 ex_SD_CLK 5 VCC
SD_DAT1 A2 DATA0A DATA0B D1 ex_SD_DAT1 6 CLK
SD_DAT2 B4 DATA1A DATA1B C4 ex_SD_DAT2 ex_SD_DAT0 7 VSS
SD_DAT3 A4 DATA2A DATA2B D4 ex_SD_DAT3 ex_SD_DAT1 8 DAT0
SD_D0_DIR C5 DATA3A DATA3B DAT1
SD_D123_DIR C1 DATA0_dir 9

VSS
VSS
VSS
VSS
VSS
VSS
DATA123_dir 10 CD
SD_CMD B1 C2 ex_SD_CMD CD2
SD_CMD_DIR B5 CMDA CMDB
B B
CMD_dir

11
12
13
14
15
16
SD_CLK A3 D3 ex_SD_CLK
SD_FB_CLK A1 CLKA CLKB
CLK-f
B3
C3 GND
GND

SN74AVCA406L

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B SD Card C

Date: Friday, March 20, 2015 Sheet 14 of 25

5 4 3 2 1
 5 4 3 2 1

VCC1P8 VCC1P8 VCC1P8

MIPI Interface
3 MIPI_MD_p[3..0] VCC2P5 VCC2P5

1
3 MIPI_MD_n[3..0] D10 D2 D11

SD107WS-TP SD107WS-TP SD107WS-TP

7 MIPI_MC_p R132 R133 R159 R158

2
D 150 150 150 150 MIPI_RESET_n R134 49.9 MIPI_RESET_n_T D
7 MIPI_MC_n
MIPI_MCLK R150 49.9 MIPI_MCLK_T
MIPI_LP_MD_p0 R7 0 MIPI_MD_p0 MIPI_LP_MD_p1 R34 0 MIPI_MD_p1
MIPI_LP_MD_p[3..0] MIPI_LP_MD_n0 R8 0 MIPI_MD_n0 MIPI_LP_MD_n1 R35 0 MIPI_MD_n1 MIPI_WP R15 49.9 MIPI_WP_T
6
MIPI_LP_MD_n[3..0]
6 VCC1P8 VCC1P8
R3 R6 R33 R36
49.9 49.9 49.9 49.9
MIPI_LP_MC_p
7

1
MIPI_LP_MC_n D1 D12
7
SD107WS-TP SD107WS-TP

2
MIPI Control Interface MIPI_CORE_EN R148 49.9 MIPI_CORE_EN_T
VCC2P5 VCC2P5
MIPI_RESET_n MIPI_I2C_SCL R152 49.9 MIPI_I2C_SCL_T
3
3 MIPI_MCLK

MIPI_WP R137 R131 R138 R149

3 VCC2P5 DOVDD
150 150 150 150
3 MIPI_CORE_EN
C DOVDD C

MIPI_LP_MD_p2 R4 0 MIPI_MD_p2 MIPI_LP_MD_p3 R13 0 MIPI_MD_p3

R25 R140
MIPI_LP_MD_n2 R1 0 MIPI_MD_n2 MIPI_LP_MD_n3 R14 0 MIPI_MD_n3
Q7

1
AO3400
560 560
3 MIPI_I2C_SDA R5 R2 R11 R12
49.9 49.9 49.9 49.9 MIPI_I2C_SDA 3 2 MIPI_I2C_SDA_T
3 MIPI_I2C_SCL

R163 0
DNI

VCC2P5

GND
R141 R153 VCC2P8 J4
150 150 L1 30ohm, 3A AFVCC 1 16
2 17 MIPI_MD_n1 R139 0 MIPI_MCLK_T
AVDD 3 18 MIPI_MD_p1
B MIPI_LP_MC_p R9 0 MIPI_MC_p 4 19 C71 B
MIPI_LP_MC_n R23 0 MIPI_MC_n C69 C70 MIPI_RESET_n_T 5 20 MIPI_MC_n 33p
10u 0.1u 6 21 MIPI_MC_p 50V
6.3V 10V MIPI_MD_p2 7 22 DNI
R10 R24 MIPI_MD_n2 8 23
49.9 49.9 9 24 MIPI_WP_T
MIPI_MD_p0 10 25 MIPI_I2C_SCL_T R136 0 VCC1P8
MIPI_MD_n0 11 26 MIPI_I2C_SDA_T
12 27 MIPI_CORE_EN_T R135 0 VCC2P8
MIPI_MD_p3 13 28 DOVDD DNI
MIPI_MD_n3 14 29
15 30 AVDD12 L2 30ohm, 3A VCC1P2

HEADER 15X2 C72 C73

0.1u 10u
VCC2P5 10V 6.3V

GND GND
R26 R151
2K 2K
DNI

A MIPI_I2C_SDA A

MIPI_I2C_SCL
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B MIPI Interface C

Date: Thursday, March 19, 2015 Sheet 15 of 25

5 4 3 2 1
 5 4 3 2 1

HDMI TX U5 HDMI TX
HDMI_TX_D0 62 18 TMDS_TXC_p
6 HDMI_TX_D[23..0] HDMI_TX_D1 61 D0 TXC+ 17 TMDS_TXC_n J6
HDMI_TX_D2 60 D1 TXC- VCC1P8 VCC3P3_DVDD
HDMI_TX_D3 59 D2 21 TMDS_TX_p0 D3 RClamp0514P
HDMI_TX_D4 58 D3 TX0+ 20 TMDS_TX_n0 TMDS_TX_p2 1 10 TMDS_TX_p2 1
6 HDMI_TX_HS HDMI_TX_D5 57 D4 TX0- 24 TMDS_TX_p1 TMDS_TX_n2 2 9 TMDS_TX_n2 3
D2+

HDMI_TX_D6 56 D5 TX1+ 23 TMDS_TX_n1 R156 R154 3 8 2

D2-
6 HDMI_TX_VS HDMI_TX_D7 55 D6 TX1- 27 TMDS_TX_p2 2K 27K TMDS_TX_p1 4 7 TMDS_TX_p1 4
GND
D D7 TX2+ 26 TMDS_TX_n2 DNI TMDS_TX_n1 5 6 TMDS_TX_n1 6
D1+ D
6 HDMI_TX_DE HDMI_TX_D8 54 TX2- 5
D1-

HDMI_TX_D9 52 D8 28 HDMI_TX_INT TMDS_TX_p0 1 10 TMDS_TX_p0 7

GND
6 HDMI_TX_INT HDMI_TX_D10 50 D9 INT TMDS_TX_n0 2 9 TMDS_TX_n0 9
D0+

HDMI_TX_D11 49 D10 36 HDMI_I2C_SDA_T D13 3 8 8

D0-

HDMI_TX_D12 48 D11 SDA 35 HDMI_I2C_SCL DFLS1150-7 TMDS_TXC_p 4 7 TMDS_TXC_p 10

GND

HDMI_TX_D13 47 D12 SCL 34 DDCSDA DNI TMDS_TXC_n 5 6 TMDS_TXC_n 12

CK+
From MAX HDMI_TX_D14 46 D13 DDCSDA 33 DDCSCL D4 RClamp0514P 11
CK-
11 CLK_12MHz HDMI_TX_D15 45 D14 DDCSCL 30 CEC_IO R165 0 CEC 13
GND
D15 CEC 32 CEC_CLK DNI R52 2K DDCSCL 15
CEC
CEC_CLK SCL
HDMI_TX_D16 44 R53 2K DDCSDA 16
D16 VCC5 SDA
I2C Interface HDMI_TX_D17 43 17
D17 GND
HDMI_TX_D18 42 R155 R157
6 HDMI_I2C_SDA HDMI_TX_D19 41 D18 29 0 0 18
D19 DVDD_3V VCC3P3_DVDD +5V
HDMI_TX_D20 40 R59 10K HDMI_HPD 19
6 HDMI_I2C_SCL HDMI_TX_D21 39 D20 1
HPD
D21 DVDD1 VCC1P8_DVDD
HDMI_TX_D22 38 11
HDMI_TX_D23 37 D22 DVDD2 31 SHELL
D23 DVDD3 51

23
22
21
20
R161 49.9 HDMI_TX_CLK_T 53 DVDD4 U31
DNI HDMI_TX_DE 63 CLK 12 CEC 1 VCC5
DE PVDD VCC1P8_PVDD
HDMI_TX_HS 64 DDCSCL 3 R62 1M
HDMI_TX_VS 2 HSYNC 13 CLK_12MHz R142 22 CEC_CLK 2 5
HDMI Audio Interface R176 887 14 VSYNC BGVDD DNI DDCSDA 4 C32 0.1u
C 6 HDMI_I2S[3:0] R_EXT C
HDMI_HPD 16 15 HDMI_HPD 6 25V
HPD AVDD1 VCC1P8_AVDD
HDMI_SPDIF 3 19
6 HDMI_MCLK HDMI_MCLK 4 SPDIF AVDD2 25 TPD4E001_0 GND_EXT
MCLK AVDD3
6 HDMI_LRCLK HDMI_I2S0 5
HDMI_I2S1 6 I2S0
6 HDMI_SCLK HDMI_I2S2 7 I2S1 VCC1P8
HDMI_I2S3 8 I2S2 65 VCC1P8 VCC3P3_DVDD
I2S3 EPAD_GND
HDMI_SCLK 9
HDMI_LRCLK SCLK R19 VCC1P8
10
LRCLK R30 R18
22
PD Q6 DNI DNI
4.99K

1
Default : AO3400
4.99K 4.99K
ADV7513BSWZ
I2C Address 0x72/0x73 HDMI_I2C_SCL HDMI_I2C_SDA 2 3 HDMI_I2C_SDA_T

R160 2K R166 2K VCC1P8_AVDD

DNI R421 0
VCC1P8 L10 10uH VCC1P8_DVDD
74479777310 C74 C77 C101 C100 C76
10u 0.1u 0.1u 0.1u 0.1u
B 6.3V 10V 10V 10V 10V B

Note:
Place Capacitor near ADV7513 DVDD pins
VCC1P2 VCC3P3 L11 10uH
VCC1P8 VCC1P8_AVDD
74479777310 C98 C83 C88 C99
C19 C9 10u 0.1u 0.1u 0.1u
6.3V 10V 10V 10V
0.1u 0.1u

Note:
Place Capacitor near ADV7513 AVDD pins

R162 0 VCC1P8 L12 10uH VCC1P8_PVDD

VCC1P2 VCC3P3 74479777310 C111 C113 C112
U4 DNI 10u 0.1u 0.1u
6,7 1 VCCA VCCB 6 6.3V 10V 10V
HDMI_TX_CLK 3 A B 4 HDMI_TX_CLK_T
5 2
DIR GND
Note:
A SN74AVC1T45 Place Capacitor near ADV7513 PVDD and BGVDD pin A

VCC3P3 L3 10uH VCC3P3_DVDD Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
All rights reserved.
74479777310 C6 C15 No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

10u 0.1u Title

6.3V 10V
DECA
Note: Size Document Number Rev
Place Capacitor near ADV7513 DVDD_3V B HDMI TX C

Date: Thursday, March 19, 2015 Sheet 16 of 25

5 4 3 2 1
 5 4 3 2 1

VCC1P5_DDR3 VCC_AUD_IO VCC3P3 VCC_AUD

Audio CODEC Interface L19 30ohm, 3A L7 30ohm, 3A VCC2P5_VCCAADC
5 AUDIO_MCLK LINE-IN for ADC VCC5_ADC
5 AUDIO_BCLK C210 C145 C184 C166 VCC5_ADC
10u 0.1u 22u 0.1u R192 R183 0 LINE_AC_L C23
5 AUDIO_WCLK 6.3V 10V 6.3V 10V DNI 47K U8A 0.1u

8
C129 1u 10V
5 AUDIO_DIN_MFP1 R255 LINE_IN_L
3
D LINE_IN_L_ADC + D
10 R253 0 1 10V DNI
5 AUDIO_DOUT_MFP2 2 R182 47K
VCC_AUD_IO VCC_AUD -
C280 VCC2P5_VCCAADC
R191 OPA1612AIDR DNI

4
1p DNI 47K R193 47K
Audio Control Interface DNI
5 AUDIO_SCLK_MFP3
C183 C182 C168 C167 R55 0 R54 0
5 AUDIO_SCL_SS_n 0.1u 10u 22u 0.1u DNI
10V 6.3V 6.3V 10V

29

26

24
6
5 AUDIO_SDA_MOSI U9

DVDD

IOVDD

LDOIN

AVDD
5 AUDIO_MISO_MFP4

5 AUDIO_SPI_SELECT AUDIO_MCLK 1 13
MCLK IN1_L
5 AUDIO_RESET_n AUDIO_BCLK 2 14
BCLK IN1_R
5 AUDIO_GPIO_MFP5 AUDIO_WCLK 3
WCLK 15 LINE_IN_L_AUD
AUDIO_DIN_MFP1 4
DIN/MFP1
IN2_L
16 LINE_IN_R_AUD
LINE IN
AUDIO_DOUT_MFP2 5 IN2_R J2
C DOUT/MFP2 VCC2P5_VCCAADC C
Audio LINE-IN to MAX10 ADC PHONE JACK B
AUDIO_SCLK_MFP3 8 19
SCLK/MFP3 MICBIAS

GND
NCR
NCL
3 LINE_IN_L_ADC AUDIO_SCL_SS_n 9 20
SCL/SS IN3_L

L
R184
AUDIO_SDA_MOSI 10 21 47K

5
2
4
1
3
SDA/MOSI IN3_R
AUDIO_MISO_MFP4 11
MISO/MFP4 22 LINE_OUT_L C97 1u
AUDIO_SPI_SELECT 12 LOL VCC5_ADC LINE_IN_R_AUD LINE_IN_R
VCC_AUD_IO SPI_SELECT 23 LINE_OUT_R 10V
AUDIO_GPIO_MFP5 32 LOR U8B
GPIO/MFP5

8
C96 1u
25 C130 1u 5 LINE_AC_L LINE_AC_L LINE_IN_L
AUDIO_RESET_n HPL LINE_IN_L_AUD +
31 7 10V
R57 R58 RESET 27 10V 6
HPR -
2K 2K VCC_AUD R66 4.7K 30
LDO_SELECT OPA1612AIDR R185

4
IOVSS
DVSS

PPAD

AVSS
18 47K
REF
LINE OUT
AUDIO_SDA_MOSI TLV320AIC3254_0 J1
28

33

17

Default : C146 C128 PHONE JACK G

B AUDIO_SCL_SS_n 10u 0.1u B
I2C Address 0x30/31 6.3V 10V

GND
NCR
NCL
DNI

L
5
2
4
1
3
VCC_AUD_IO
LINE_OUT_R C109 1u R187 100
10V

R67 R56 LINE_OUT_L C107 1u R186 100

10K 10K 10V
DNI

AUDIO_RESET_n
AUDIO_SPI_SELECT R175 C108 R174 C106
47K 47n 47K 47n
DNI 25V DNI 25V
R190
1K

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B Audio CODEC C

Date: Friday, March 13, 2015 Sheet 17 of 25

5 4 3 2 1
 5 4 3 2 1

NET_TXD[3..0]
3
NET_TX_CLK 7
NET_TX_EN 7
D D
NET_RESET_n 7
Analog interface , so using 3.3v
NET_VCC3P3
NET_RXD[3..0] NET_VCC3P3 NET_VCC3P3
3
NET_RX_CLK 7 R210 R225
NET_RX_ER NET_VCC3P3
3
NET_RX_DV 3 C46 R71 R70 R65 R64 C33
NET_COL 3 0 0
NET_CRS 3 0.1u 0.1u R201 R202 R233 R232
C186 C212
NET_MDIO 3 49.9 49.9 49.9 49.9
NET_MDC 3 GND GND 0.1u 0.1u 110 2.2K 110 2.2K

NET_CLK_25 10 J7
GND GND
NET_PCF_EN 7 ETD_P 3 12
ETD_N 4 TD+ LA 11 LED_LINK
5 TD- LC
CTT 1 R260 0
ERD_P 7 RA 2 SPEED
U14 ERD_N 8 RD+ RC
6 RD-
C CTR C
NET_TX_CLK 1 17 R45
TX_CLK TD+ 16 10 13 R261 0
NET_TXD0 3 TD- 9 CHS_GND SHIELD1 14 LED_ACTIVE
NET_TXD1 4 TXD_0 14 CHS_GND SHIELD2 0
NET_TXD2 5 TXD_1 RD+ 13 DNI
NET_TXD3 6 TXD_2 RD- GND
TXD_3 480749001
26 LED_ACTIVE R80 2.2K
LED_ACT NET_VCC3P3
NET_TX_EN 2 27 GND_S GND
TX_EN LED_SPEED/FX_SD 28
NET_RX_CLK 38 LED_LINK
RX_CLK 34 NET_CLK_25
NET_RXD0 46 X1 33
NET_RXD1 45 RXD_0 X2 24
NET_RXD2 44 RXD_1 CLK_OUT
NET_RXD3 43 RXD_2 21 R231 2.2K
RXD_3 CLK_OUT_EN GND
22 R237 2.2K
NET_RX_ER 41 PCF_EN
NET_RX_DV 39 RX_ER 23 R74 2.2K
RX_DV RESERVED1 NET_VCC3P3
25 DNI
NET_COL 42 RESERVED2 36
NET_CRS 40 COL RESERVED3 37 NET_PCF_EN
CRS/CRS_DV RESERVED4
NET_VCC2P5 R241 2.2K NET_RESET_n 29 12
R207 2.2K 7 RESET_N TDI 11
B B
PWR_DOWN/INTN TRST# 10
R236 1.5K NET_MDIO 30 TMS 9
NET_MDC 31 MDIO TDO 8
MDC TCK
NET_VCC3P3 19 35
32 ANA33VDD IO_CORE_VSS 47
NET_VCC2P5 IO_VDD IO_VSS
48 15
IO_VDD CD_VSS 18
R224 4.87K 20 ANAVSS 49
GND VREF DAP
DP83620_3
GND

VCC3P3 NET_VCC3P3 VCC2P5 NET_VCC2P5

L24 BEAD L23 BEAD

C211 C235 C185 C234 C233

A 0.1u 10u 0.1u 0.1u 10u A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
GND GND No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B Ethernet C

Date: Wednesday, March 11, 2015 Sheet 18 of 25

5 4 3 2 1
 5 4 3 2 1

D VCC1P2 VCC5 USB_VCC5 D

U17
6 1
R79 C238 IN OUT C237
10k
0.1u 0.1u
GND
USB_REG3P3 3 2
VCC1P8_USB FAULT_n ILIM GND
4 5 R226
USB_REG1P5 USB_FAULT_n EN GND 7 20K
VCC1P2 VCC1P8_USB 6 EP_GND
VBAT CPEN1
TPS2553DRVR
DNI
C131 C110 USB_DATA[7..0]
6
GND

12

20

28
30

32

21
0.1u 0.1u U13
USB_DATA0 3

VDDIO
VDD15

VDD33

VDD18
VDD18

VBAT
USB_DATA1 4 DATA0 USB_VCC5
USB_DATA2 5 DATA1
USB_DATA3 6 DATA2 17 C236
USB_CLKOUT_NOPLL R208 0 USB_DATA4 7 DATA3 CPEN 4.7u
6 DATA4
DNI USB_DATA5 9
VCC1P2 VCC1P8_USB USB_DATA6 10 DATA5 R83 Jack-Mini-USB-AB_3
C DATA6 C
U10 USB_DATA7 13 22 820 GND 1
1 VCCA VCCB 6 DATA7 VBUS 19 USB_DM 2
VBUS

USB_CLOCK 3 A B 4 R68 0 R69 22 26 DM 18 USB_DP 3

D-

7 CLOCK DP D+ Mini-USB AB
5 2 6 USB_NXT 2 23 R73 0 4
R61 DIR GND
USB_DIR 31 NXT ID VCC1P8_USB 5
ID

6 DIR GND
SN74AVC1T45 6 USB_STP 29 DNI R212
DNI STP 14 10K J8
CFG

6
1
2
3
5
4

6
7
6 USB_CS 11 1
2K R60 0 USB_RESET_n 27 CS REFCLK R209

VBUS

D-
ID
NC
GND
D+
6 RESETB
0 GND GND

GND

NC1
NC2
NC3
NC4
NC5
R205 R63
TUSB1210 DNI 0 C281 C282

33

8
15
16
24
25
U34 1M
CAD Notes: GND TPD4S012 1n 0.1u
Put the TUSB1210 close to FPGA.
GND CAD Notes:
VCC1P8 VCC1P8_USB GND Put the TPD4S012 close to each USB connector.
R211 USB_CLK_19
Default Connection: ULPI with clock output mode TUSB1210_CLK_R R196 0 10
0 GND

C187 C170 C169 USB_REG3P3 USB_REG1P5

B 4.7u 0.1u 0.1u B

C191 C171
C192 C172
4.7u 0.1u 4.7u 0.1u
GND

GND GND
VCC3P3 VBAT

L20 60ohm 3A

C188 C190 C213

C189
4.7u 0.1u 0.1u 0.1u

GND

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B USB PHY C

Date: Thursday, March 19, 2015 Sheet 19 of 25

5 4 3 2 1
 5 4 3 2 1

VCC5 VCC5_ADC

L13 60ohm 3A

VCC5_ADC

D D
C105 C104

10u 0.1u

U7

7
5

V+
SENSE R46
2
J5 IN- 6 ANAIN1_VOUT2 10 ANAIN1
OUT 8
ANAIN1_SMA 3 VCC2P5_VREF
IN+ 1 C27
REF1 8 CAD Notes:

V-
Analog IN REF2 1p Put the 1pF caps
INA159AIDGKR close to MAX10 pin.

4
Notes: C103 C95
the input voltage Vin range (-6.25V --- 6.25V) 10u
1u Notes:
the output voltage Vo range (0.0V --- 3.0V)
C Notes: C

Amplifier output voltage Vo=(6.25+Vin)/5

VCC5_ADC

C87 C86

10u 0.1u

U3 R44
7
V+ 5 ANAIN2_VOUT2 10 ANAIN2 8
2 SENSE
J3 IN- 6
OUT C28
B ANAIN2_SMA 3 VCC2P5_VREF CAD Notes: B
IN+ 1 1p Put the 1pF caps
REF1 8 close to MAX10 pin.
V-

Analog IN REF2
INA159AIDGKR
4

C94 C93 Notes:

Notes: 10u the output voltage Vo range (0.0V --- 3.0V)
the input voltage Vin range (-6.25V --- 6.25V) 1u

Notes:
Amplifier output voltage Vo=(6.25+Vin)/5

VCC3P3
VCC2P5_VREF
R189
U32
1 2 1
A
VIN VOUT A
C165
3 C127 C144 C142
0.47u GND 10u
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
All rights reserved.

REF3125 0.1u 1u No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B SMA Connectors & Difference Amplifier C

Date: Friday, May 15, 2015 Sheet 20 of 25

5 4 3 2 1
 5 4 3 2 1

D
Digital Gsensor D

VCC2P5_Gsensor
VCC2P5

Accelerometer L28 VCC2P5_Gsensor

0.35ohm, 0.3A

C284 C283 C285

G_SENSOR_SDI 6 10u 0.1u 0.1u

10
9
G_SENSOR_SCLK 6 U6

Vdd

Vdd_IO
G_SENSOR_INT1 6
G_SENSOR_INT2 6 G_SENSOR_SCLK_E 1
G_SENSOR_SDI_E 4 SCL/SPC 12 G_SENSOR_INT1_E
G_SENSOR_CS_n 6 G_SENSOR_CS_n_E 2 SDA/SDI/SDO INT1 11 G_SENSOR_INT2_E
G_SENSOR_SDO_E 3 CS INT2
C SDO/SA0 C
G_SENSOR_SDO 6 5
Res

GND
GND
GND
LIS2DH12TR

6
7
8
VCC1P2 VCC2P5_Gsensor

C418 0.1u
R408
200K
R409R410R411R412R413R414 R415R416R417R418R419R420
B 560 560 560 560 560 560 U30 560 560 560 560 560 560 B
1 20 C419 0.1u
2 GND EN 19
G_SENSOR_INT2 3 Vref_A Vref_B 18 G_SENSOR_INT2_E
G_SENSOR_INT1 4 A1 B1 17 G_SENSOR_INT1_E
G_SENSOR_SCLK 5 A2 B2 16 G_SENSOR_SCLK_E
G_SENSOR_CS_n 6 A3 B3 15 G_SENSOR_CS_n_E
G_SENSOR_SDO 7 A4 B4 14 G_SENSOR_SDO_E
G_SENSOR_SDI 8 A5 B5 13 G_SENSOR_SDI_E
9 A6 B6 12
10 A7 B7 11

EP
A8 B8

21
LSF0108

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B Accelerometer C

Date: Thursday, April 23, 2015 Sheet 21 of 25

5 4 3 2 1
 5 4 3 2 1

Si1143
D LIGHT_I2C_SCL 4 D

LIGHT_I2C_SDA 4
VCC3P3_HDC1000
LIGHT_INT 4

VCC5

VCC3P3 VCC3P3 VCC3P3_Si1143 VCC3P3_Si1143

R204 R194 R203
"T" formation 2.2K 2.2K 2.2K
C10
L5 BEAD configuration R249
0.1u U11
LED＊s are ~ 1.4" to 47
RH_TEMP_I2C_SCL A1 B1
R41 R43 R42 1.6" 4 SCL VDD VCC3P3_HDC1000
4 RH_TEMP_I2C_SDA A2 B2
SDA GND
away from the sensor 4 RH_TEMP_DRDY_n D2
DRDYn DNC
C2
U28 DS1 C1 D1
4.99K 4.99K 4.99K ADR0 ADR1
3 9 1 2
VDD LED1
HDC1000YPAR
LIGHT_I2C_SCL 2 6 SFH4056NQ
LIGHT_I2C_SDA 1 SCL LED2 DS2 VCC3P3_HDC1000 Default : I2C Address 0x80/0x81
LIGHT_INT 4 SDA 7 1 2 L14 BEAD
INT LED3
C VCC3P3 C
5 SFH4056NQ Note:keep the seneor away from heat area
10 DNC_1 8 DS3 C149
O-R1
DNC_2 GND 1 2
Si1143 0.1u
SFH4056NQ
C273
Isolation O-ring Default : I2C Address 0xB4/0xB5
(1/4" dia, 3/32" tall) 100u

or place some other ICs to Isolate it?

U35 VCC3P3_LM71 L22

TEMP_CS_n 4 1 5 VCC3P3
CS_n VCC BEAD
TEMP_SIO 4 3 C248
SIO
TEMP_SC 4 2 0.1u
Proximity/Ambient Light Sensor 4 SC GND

LM71CIMF

B Note:keep the seneor close to the "hot" area on board B

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B Gesture,Humidity,Temperature Sensors C

Date: Wednesday, March 11, 2015 Sheet 22 of 25

5 4 3 2 1
 5 4 3 2 1

VCC3P3_CS

VCC3P3 L27
220 ohm, 0.3A
C274 C275 C276

VCC3P3_CS 1u 0.1u 0.1u

3
D U38 D
R100 R99

VDD

VCC
B1

6 R244 560 1 Sensor Shield 2

2K 2K CS1/PS1/GPO0/SH
CAP_SENSE_I2C_SCL 1 7 R243 560 DNI
4 I2C_SCL CS0/PS0
CAP_SENSE_I2C_SDA 8 CapSense Button 8mm Round
4 I2C_SDA B0
2
CMOD 1 2
Sensor Shield

VSS
C277
DNI
2.2n
CY8CMBR3102-SX1I CapSense Button 8mm Round

5
CSSH1

DNI 1
Default : I2C Address 0x37
CapSense Shield Electrode

C C

VCC3P3

VCC1P5_DDR3 VCC1P5_DDR3

2
SW0 SW1 LED0 LED1 LED2 LED3
4 4 LEDB LEDB LEDB LEDB
SW0 R173 120 1 1
2 2
SW1 R164 120 3 3 RN2

1
5 5 LED0 1 8
LED1 2 7
SLIDE SW SLIDE SW LED2 3 6
LED3 4 5

120
VCC3P3

B LED B

2
VCC1P5_DDR3
LED[7..0] LED4 LED5 LED6 LED7
6
LEDB LEDB LEDB LEDB

SWITCH R124 R251 RN3

1
SW[1..0] 100K 100K LED4 1 8
5
LED5 2 7
LED6 3 6
KEY KEY0 LED7 4 5
KEY1
KEY[1..0] 120
5
KEY0 KEY1
4 3 4 3

C278 C279 1 2 1 2
1u 1u
10V 10V TACT SW TACT SW

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B CapSense Controller, Buttons, Switchs C

Date: Wednesday, March 11, 2015 Sheet 23 of 25

5 4 3 2 1
 5 4 3 2 1

5V Power from USB Port

Power up Sequence:
5V -->3.3V--->1.5V--->1.8V 1.8V / 1.5A
D17
VCC5_USB --->2.5V--->1.2V--->2.8V
PMEG2010AEB Ramp Time = 1.2 msec
VCC3P3 U27 VCC1P8
D16
13 7 VCC1P8
PMEG2010AEB 14 PVIN VOUT 8
DC 5V Power Input PVIN VOUT
VCC5 C12 C79 R144 R37
D J9 DC_5V C11 C20 C85 D
Overvoltage Protection
1 Q5 Threshold Voltage : 5.45V Q3 10u 680p 10 22u 22u
2 AO3415 AO3415 VCC5 10 5p 6.3V 6.3V
3 4 AVIN1 5 237K
AVIN2 VFB
C51 12 11
R94 10V R16 ENABLE POK R38

AGND

PGND
PGND
R103 806 R95 47u 4.7K 1P8_POK
30K 100K C75

2
R84 6.8K 1 Q2 Delay Enable signal 1u EP53F8QI R27 118K

2
3
HE8550G 2.59 msec than AVIN
C2 100K

3
3
D9
PCB1 R123 1u
30K
R85 VCC3P3
BZX84C5V1 6.8K

1.5V / 1.5A
1

2
10-31409160-C0
Ramp Time = 1.2 msec
VCC3P3 U2 VCC1P5_DDR3
C C

13 7 VCC1P5_DDR3
14 PVIN VOUT 8
C78 C13 R28 PVIN VOUT R39
1P8_POK 25 C14 C84 C21
10u 680p 10 22u 22u
10 5p 6.3V 6.3V
4 AVIN1 5 237K
1P2_POK 25 AVIN2 VFB
12 11
VCC1P2 R17 ENABLE POK R29

AGND

PGND
PGND
2P5_POK 25 L18 30ohm, 3A 2K
C5

Delay Enable signal 1u EP53F8QI R143 158K

1.2V / 3A

2
3
VCC5 1.1 msec than AVIN
U16 C3 100K
19 5 Ramp Time = 1.2 msec DNI
20 PVIN_1 VOUT_1 6 VCC1P2_VCC 1u
C44 C39 21 PVIN_2 VOUT_2 7
PVIN_3 VOUT_3 R72
2P5_POK 27 8 VCC3P3
ENABLE VOUT_4 VCC1P2_VCC
22u 0.1u 33 9
AVIN VOUT_5 0.003
10 R88 R223 R222 VCC3P3
C52 26 VOUT_6 11 C54 C45 C40
B B
LLM/SYNC VOUT_7 GND1
DNI 0.1u NC(SW):1-2, 12, 31 15p 47u 47u
30
34-38 VFB 200K 2.2 2.2
29 SS NC: 3-4, 22-25 28 R75
RLLM POK C232 0.1u
1P2_POK R87 120
PGND_1
PGND_2
PGND_3
PGND_4
PGND_5
PGND_6

C53
MTG2 MTG3 MTG1 MTG4
AGND

13

12

2
15n R86 U18 GND GND GND GND D6
EP

332K VCC3P3
IN+ IN-
EN6337QI POWER LEDB
32

13
14
15
16
17
18

39

100K 11 9
R96 0 2 BUS Vs
R89 0 1 A0 C231

1
VCC3P3 A1
PMONITOR_I2C_SCL 5 0.1u
PMONITOR_I2C_SDA 4 SCL 10 FID11 FID9 FID8 FID5 FID1 FID10 FID2 FID12 FID7 FID6 FID3 FID4
PMONITOR_ALERT 3 SDA GND 17
ALERT EP
R240 R98 R97 INA230AIRGTR

I2C ADDRESS = 1000000

PMONITOR_I2C_SCL 4
A PMONITOR_I2C_SDA 4 2K 2K 2K A
PMONITOR_ALERT 4
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
All rights reserved.
VCC3P3 No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B Power - 1.2V, 1.5V, 1.8V, 5V, Power Monitor C

Date: Friday, March 20, 2015 Sheet 24 of 25

5 4 3 2 1
 5 4 3 2 1

Power up Sequence:
5V -->3.3V--->1.5V--->1.8V 2.5V / 1A
--->2.5V--->1.2V--->2.8V Ramp Time = 1.18msec
D D
VCC2P5
VCC3P3 U23 VCC2P5

9 1
10 VIN_1 VOUT_1 2
2P5_POK 24 C57 VIN_2 VOUT_2 C59 C56
R104 C58 22u
10u 7 6.3V 2.2u
EN 3 82p
VFB
2.61K
1P8_POK 24 R254 0 6 4
SS POK

GND
C62 8 2P5_POK R115

EP
NC
EY1501DI-ADJ

11
R125
3.3V / 4A 4.7n 649
VCC5
U15 Ramp Time = 1.2msec
19 5 VCC3P3 VCC3P3 100K
20 PVIN_1 VOUT_1 6
C35 C34 21 PVIN_2 VOUT_2 7
C PVIN_3 VOUT_3 C
27 8 VCC3P3
47u 0.1u 33 ENABLE VOUT_4 9
AVIN VOUT_5 10 C36 C37
26 VOUT_6 11
LLM/SYNC VOUT_7 47u 47u GND2
NC(SW):1-2, 12, 31
30
SS
34-38 VFB 2.8V / 1A
29 NC: 3-4, 22-25 28
RLLM POK Ramp Time = 1.18msec
PGND_1
PGND_2
PGND_3
PGND_4
PGND_5
PGND_6

C47 R76 R78 191K VCC2P8

AGND

100K VCC3P3 U29 VCC2P8

15n DNI
EP

R77 9 1
EN6347QI C48 10p 10 VIN_1 VOUT_1 2
32

13
14
15
16
17
18

39

C91 VIN_2 VOUT_2 C81 C82

VCC3P3 R147 C80 22u
56.2K 10u 7 6.3V 2.2u
EN 3 82p
VFB
4.3K
1P2_POK 24 R172 0 6 4
SS POK

GND
C18 8 DNI R146

EP
B B
NC R145
EY1501DI-ADJ

11
4.7n 931
100K

VCC3P3

A A

Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.

All rights reserved.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

Title
DECA
Size Document Number Rev
B Power - 2.5V, 2.8V, 3.3V C

Date: Wednesday, March 11, 2015 Sheet 25 of 25

5 4 3 2 1