Term End Examination - November 2013

Course : ECE508 - VLSI Testing and Testability Slot: D2

Class NBR : 5347

Time : Three Hours Max.Marks:100

(Show the necessary steps for every problem in order to ensure partial marks)
Answer any TEN Questions
(10 X 10 = 100 Marks)

1. a) What are the two possible fault MODELS that we consider at transistor level (fault
models, NOT defects).
b) What is the test time for applying 5 test patterns to an ASIC with 10 scan-flip flops,
which are formed as a single scan-chain.
c) List and motivate two advantages with scan-chains.
d) Fault equivalence reduces the number of fault sites. How many equivalent fault sites
under the stuck-at fault assumption exists for a two-input AND gate.
e) Please explain what a redundant fault is, and what an untestable fault is. Are they
equivalent?

2. Perform the full fault collapsing of the circuit depicted in Fig. 2.1. Follow the steps given
under the Figure.

Fig. 2.1 Circuit

(i) How many potential faults has this circuit?

(ii) Apply equivalence fault collapsing to the circuit in Fig.2.1. Write your results on
the Figure.
(iii) Apply dominance fault collapsing to the circuit in Fig. 2.1. Explain briefly, in
plain text, the steps to be applied in this technique. Write your results on Figure.
(iv) How performance of fault collapsing measured is (name the measurement unit,
and give its formal definition)? What are the performance results in both cases of
equivalence and dominance fault collapsing?

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3. Perform an on-paper parallel simulation of the circuit presented in Fig. 3.1, assuming an
input pattern abcde = 10010.

a f
b h

c g j
d
e

Fig. 3.1 Boolean circuit.

Instead of writing the solutions on the circuit schematic, use a more practical approach,
filling Table 3.1, where ff means fault-free, and a0 means a s-a-0.

Table 3.1 Parallel simulation results.

Which faults can be detected using this vector?

4. Compute the combinational SCOAP testability measures for the circuit presented in Fig. 4.1.
Does SCOAP produce accurate controllability results in this case?

B
C
Z
D

Fig. 4.1 Circuit to perform combinational SCOAP testability

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5. Use Roth’s D-ALG to perform ATPG for the s-a-1 fault on the fan-out branch h in the
circuit shown in Fig. 5.1.

Fig.5.1

6. a) For each of the configurations shown in Fig. 6.1, state whether it satisfies the LSSD [5]
design rules and which rules, if any, it violates?

(a) (b)

Fig.6.1

b) A complete BIST architecture consists of the circuit under test, plus additional hardware [5]
to perform BIST tasks. Within this architecture, LFSRs (Linear Feedback Shift Registers)
can be used to achieve two main different functions, also corresponding to two different
positions in the architecture of a system that has BIST.
Can you please explain the two different ways to take benefit of LFSRs in BIST? Please
explain the advantages/drawbacks of using LFSRs over alternate techniques.

7. Design a 4-bit internal-XOR (modular) LFSR pattern generator implementing the

characteristic polynomial 1+x+x4. Express the linear system of matrix equations describing
this pattern generator. Check if any particular I/P pattern would detect the fault ‘m’ S@1 for
CUT shown in Fig. 7.1 .(LFSR’s clk signal control’s the flop in the CUT).

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 Fig. 7.1

8. Explain any two linear-decompression

decompression-based
based compression schemes used in the current EDA
industries.
9. The following questions deal with IEEE 1149.1.
(i) Discuss how the on-chip
on test bus circuitry can be tested?
(ii) Suggest several uses for an identification test data register.

10. Given a printed-circuit

circuit board that has four chips built with a boundary scan, such as the one
shown in Figure 10.1, describe a test procedure via the boundary scan to test each chip and
the interconnects between chips. Also, describe the instruction(s) used in each step of your
procedure for each chip. Assume external ATE is used to provide and receive test data.

Fig.10.1

11. Draw the general structure for an LSSD double-latch

double latch design. Explain how it will be used to
test the circuit. What advantages/limitations, if any, do this double-latch
double latch LSSD have over the
other designs?
12. How analog and mixed-signal
signal circuits are tested with static ADC and DAC methods?
methods
Explain in detail.

⇔⇔⇔

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