UNIVERSITY : UNIVERSITY OF ENGINEERING & MANAGEMENT

DEPARTMENT : CS DEPARTMENT

WORKBOOK FOR : LABORATORY

COURSE : B.TECH

SEMESTER : 4th SEMESTER

SUBJECT with CODE : Computer Organization & Architecture Lab (PCC CS493)

PREPARED BY : APARAJITA MUKHERJEE

ASSISTANT PROFESSOR
CSE DEPARTMENT
Course Objectives

To understand the structure, function and characteristics of computer systems. To

understand the design of the various functional units and components of computers. To
identify the elements of modern instructions sets and their impact on processor design.

Course Outcomes

The ability to apply knowledge of mathematics, science, and engineering.

Pre-requisite: The hardware based design has been done in the Digital Electronics laboratory
All laboratory assignments are based on Hardware Description Language (VHDL or Verilog)
Simulation.
 SYLLABUS
Subject Code : PCC CS493
Subject Name: Computer Organization & Architecture Lab
Branch: B.TECH Semester: 4th Credit: 1

Hardware Part:

1. Familiarity with IC-chips, e.g.

Multiplexer b) Decoder, c) Encoder b) Comparator
2. Truth Table verification and clarification from Data-book.
3. Design an Adder/Subtractor composite unit.
4. Design a BCD adder.
5. Design of a ‘Carry-Look-Ahead’ Adder circuit.
6. Use a multiplexer unit to design a composite ALU .
7. Use ALU chip for multibit arithmetic operation.
8. Implement read write operation using RAM IC.
& Cascade two RAM ICs for vertical and horizontal expansion.

Software Part:

9. HDL introduction
10. Basic digital logic base programming with HDL
11. 8-bit Addition, Multiplication, Division
12. 8-bit Register design
13. Memory unit design and perform memory operatons.
14. 8-bit simple ALU design
15. 8-bit simple CPU design
16. Interfacing of CPU and Memory
 LESSON PLAN

HARDWARE PART:

Week Design Problem Contact Hours

1.Design a single memory unit -shift Register based

Week 1 operation(SISO,SIPO,PIPO,PISO) 2
2.Design an 4 bit adder-subtractor unit using IC4008

3.Implementation of ALU circuit using Multiplexer

Week 2 2
4.Implementation of parallel adder

5.Design of BCD Adder using logic gates and IC4008

Week 3 2
6.Design of 4 bit carry look ahead adder

7.Implement Read and Write operation using RAM

Week 4 2
8. Horizontal and Vertical expansion of RAM

Week 5 9. Bus Design using Multiplexer 2

SOFTWARE PART:
Week Design Problem Contact Hours
1. Write a VHDL program to implement all GATES using data flow
modeling.
2. Write a VHDL code to implement half and full ADDER circuits using
data flow modeling.

Week 1 3. Write a VHDL code to implement half and full SUBTRACTOR circuits 2
using data flow modeling.
4. Write a VHDL code to implement 4x1, 8x1 and 16x1 MULTIPLEXER
using data flow modeling.

5. Write a VHDL code to implement 1x4, 1x8 and 1x16

DEMULTIPLEXER using data flow modeling.
6. Write a VHDL code to implement 4:2, 8:3 and 16:4 ENCODER using
data flow modeling.
7. Write a VHDL code to implement 2:4, 3:8 and 4:16 DECODER using
Week 2 2
data flow modeling.
8. Write a VHDL program to implement all GATES using behavioral
modeling.
 9. Write a VHDL code to implement 4x1, 8x1 and 16x1 MULTIPLEXER
using behavioral modeling.
10. Write a VHDL code to implement 1x4, 1x8 and 1x16
DEMULTIPLEXER using behavioral modeling.
11. Write a VHDL code to implement 4:2, 8:3 and 16:4 using ENCODER
Week 3 2
behavioral modeling.
12. Write a VHDL code to implement 2:4, 3:8 and 4:16 DECODER using
behavioral modeling.

13. Write a VHDL code to implement SR, D, T, and JK F/F using event
attribute.
14. Write a VHDL code to design a 8 bit register.
15. Write a VHDL code to implement 8 bit addition operation.
Week 4 2
16. Write a VHDL code to implement 4 bit binary multiplier using arithmetic
addition operator.

17. Write a VHDL code to implement restoring and non restoring division
algorithm for division operation.
18. Write a VHDL code to design a 8 bit simple ALU.
19. Write a VHDL code to design a 8 bit simple CPU.
Week 5 2
20. Write a VHDL code to design a memory unit and perform memory
design operation.
21. Write a VHDL code to implement interfacing of CPU and memory.