FINAL YEAR PROJECT REPORT

ALTERNATE
ENERGY BASED
POWER SOLUTION
 DEPARTMENT OF ELECTRONIC ENGINEERING

GROUP MEMBERS

MOHAMMAD ZOHAIB NAEEM EL-073

NAEEMUDDIN HASAN EL-078

TAHA BHATTI EL-081

ABDUL SAMAD EL-099

SYED HUZAIF ALI EL-113

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TABLE OF CONTENTS

1 Contents 
TABLE OF CONTENTS ........................................................................................................................ I
TABLE OF FIGURES ...........................................................................................................................III
ABSTRACT ......................................................................................................................................... IV
COMMENTS FROM CLD..................................................................................................................... V
DR. SHOAIB ZAIDI ........................................................................................................................... v
COMMENTS FROM INTERNAL FYP SUPERVISOR......................................................................... VI
MR. MUHAMMAD JAVED................................................................................................................ vi
MR. ASIM AHMED ........................................................................................................................... vi
1 OVERVIEW.......................................................................................................................................... 1
1.1 HARDWARE ARCHITECTURE................................................................................................... 2
1.1.1 INVERTER DESIGN.............................................................................................................. 2
1.1.2 CHARGE CONTROLLER...................................................................................................... 3
1.2 FLOWCHART .............................................................................................................................. 5
1.3 SYSTEM ARCHITECTURE......................................................................................................... 6
1.4 SOLAR ENERGY ........................................................................................................................ 8
1.4.1 SELECTION OF SOLAR CELLS........................................................................................... 8
1.4.2 EFFICIENCY IMPROVEMENT.............................................................................................. 8
2 INPUT BLOCK ............................................................................................................................. 10
2.1 AC-DC CONVERSION BLOCK ................................................................................................. 10
2.1.1 INTRODUCTION ................................................................................................................. 10
2.1.2 DESIGN OBJECTIVES........................................................................................................ 10
2.1.3 WIND TURBINE CHARACTERISTICS ............................................................................... 11
2.1.4 AC GENERATOR DESCRIPTION (ELECTRICAL)............................................................. 11
2.1.5 SCHEMATIC........................................................................................................................ 12
2.1.6 TESTING ............................................................................................................................. 12
2.2 MPPT......................................................................................................................................... 13
2.3 DUAL INPUT DC-DC CONVERTER ......................................................................................... 14
2.3.1 CIRCUIT DESCRIPTION..................................................................................................... 15
2.3.2 SCHEMATIC AND PROTOTYPE........................................................................................ 16
2.3.3 PROTOTYPE IMPLEMENTATION: .................................................................................... 16
2.3.4 EXPERIMENTAL DATA ...................................................................................................... 17
2.3.5 CONCLUSION..................................................................................................................... 17
3 INVERTER DESIGN..................................................................................................................... 18
3.1 POWER INVERTER STAGE ..................................................................................................... 18
3.1.1 ASYMMETRICAL MULTILEVEL CONVERTERS ............................................................... 19
3.1.2 DESIGN REQUIREMENTS ................................................................................................. 20
3.1.3 SIMULATION AND RESULTS............................................................................................. 21
3.1.4 PROTOTYPE DEVELOPMENT .......................................................................................... 24
3.1.5 DESIGN TEST ..................................................................................................................... 26
3.2 HARMONIC ELIMINATION ....................................................................................................... 27
3.3 PROTECTION CIRCUITRY DESIGNING ................................................................................. 29
3.3.1 OVERVOLTAGE PROTECTION......................................................................................... 29
3.3.2 SHORT CIRCUIT PROTECTION ........................................................................................ 29
3.3.3 TEMPERATURE SENSING & THERMAL SHUTDOWN .................................................... 30
3.4 GATE DRIVE DESIGN .............................................................................................................. 30
3.4.1 HIGH SIDE N-CHANNEL MOSFET GATE DRIVE ............................................................. 30
3.4.2 HIGH SIDE MGD FOR 1ST STAGE ................................................................................... 31
3.4.3 SIMULATION AND RESULTS............................................................................................. 33
3.4.4 PROTOTYPE DEVELOPMENT .......................................................................................... 34
3.4.5 HIGH SIDE MGD FOR 2ND STAGE................................................................................... 35
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3.4.6 MGD FOR DC/DC CONVERTERS ..................................................................................... 37

3.5 BATTERY POWER SIMULATION............................................................................................. 38
3.6 DC-DC CONVERTER – IV............................................................................................................. 39
3.6.1 INTRODUCTION ................................................................................................................. 39
3.6.2 ACCEPTED TECHNICAL DESIGN..................................................................................... 40
3.6.3 BLOCK DIAGRAM............................................................................................................... 44
3.6.4 FINAL SCHEMATIC ............................................................................................................ 46
3.6.5 CONTROL CIRCUITRY....................................................................................................... 47
3.6.6 TEST PROCEDURES ......................................................................................................... 48
3.6.7 SIMULATION RESULTS ..................................................................................................... 49
3.6.8 PROTOTYPE IMPLEMENTATION ..................................................................................... 50
3.7 DC-DC CONVERTER – III ......................................................................................................... 51
3.8 DC-DC CONVERTER -II AND -I ................................................................................................ 52
3.9 VARIOUS SIMULATED DC-DC CONVERTER DESIGNS........................................................ 52
4 CHARGE CONTROLLER DESIGN ............................................................................................. 54
4.1.1 BATTERY BANK SELECTION ............................................................................................ 54
4.1.2 CHARGE CONTROLLER.................................................................................................... 55
4.1.3 GOALS................................................................................................................................. 56
4.1.4 OBJECTIVES ...................................................................................................................... 56
4.1.5 SALIENT FEATURES.......................................................................................................... 56
4.2 THE BATTERY BANK CHARGER ............................................................................................ 57
4.2.1 DESIGN REQUIREMENTS ................................................................................................. 57
4.2.2 DESIGN OF 12V 7AMPS & 12V 12AMPS CHARGE CONTROLLERS ............................. 58
4.2.3 DESIGN & CALCULATIONS ............................................................................................... 58
4.2.4 PROTOTYPE IMPLEMENTATION ..................................................................................... 59
4.2.5 EXPERIMENTAL RESULTS ............................................................................................... 60
4.2.6 DESIGN OF 36V 800 AMPS CHARGE CONTROLLER ..................................................... 61
CHARGING LARGE SERIES STRINGS OF LEAD-ACID CELLS.................................................. 61
4.2.7 SCHEMATIC........................................................................................................................ 62
4.2.8 PROTOTYPE: 36V 7AMP ................................................................................................... 63
4.3 CONTROLLING CIRCUITRY .................................................................................................... 64
4.3.1 CENTRAL CONTROLLING ................................................................................................. 64
4.3.2 EQUAL VOLTAGE DISTRIBUTION ON SERIES CONNECTED BATTERIES .................. 64
4.3.3 TEMPERATURE CONTROL CIRCUITRY .......................................................................... 65
4.3.4 VOLTAGE MONITORING CIRCUITRY............................................................................... 65
4.3.5 CHARGE STATE INDICATION ........................................................................................... 66
4.4 PROTECTION CIRCUITRY....................................................................................................... 66
4.4.1 OVER-DISCHARGE PROTECTION ................................................................................... 66
4.4.2 REVERSE CURRENT PROTECTION ................................................................................ 67
4.5 FUTURE AMENDMENTS.......................................................................................................... 67
5 BIBLIOGRAPHY ............................................................................................................................. I
6 APPENDIX .................................................................................................................................... III
6.1 GATE DRIVE SIMULATION RESULTS...................................................................................... III
6.2 WIND TURBINE CHARACTERISTICS .......................................................................................V
6.3 COMPARISON BETWEEN SOLAR CELL TYPES ..................................................................................VI
6.3.1 Crystalline silicon Types .......................................................................................................VI
6.3.2 Thin film Types .....................................................................................................................VI
6.4 DUAL DC-DC CONVERTER SIMULATION SCHEMATIC ........................................................VII
6.5 DUAL LEVEL FLOAT CHARGER ............................................................................................VIII
6.6 DUAL STEP CURRENT CHARGER...........................................................................................X 
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TABLE OF FIGURES
Figure 1-1 Flow Chart of AEPS ............................................................................................................................................5
Figure 2-4: Block Diagram comparison between Conventional and Multiport structure ............................................14
Figure 2-5 Proposed Dual Converter for AEPS................................................................................................................15
Figure 3-1 : Basic element (one stage) of asymmetric multilevel inverter ..................................................................19
Figure 3-2 : New asymmetric multilevel configuration....................................................................................................20
Figure 3-3 : Final Inverter Schematic ................................................................................................................................22
Protootype 1........................................................................................................................................................24
Prototype 2 ..........................................................................................................................................................24
Prototype 3 ..........................................................................................................................................................25
Control Circuitry .................................................................................................................................................................25
Figure 3-4: Classification of multilevel modulation methods........................................................................................28
Figure 3-6 : Waveforms for Turn-On .................................................................................................................................31
Figure 3-7 : Waveforms for Turn-Off .................................................................................................................................31
Figure 3-8: A basic form of the circuit ..............................................................................................................................32
Figure 3-9: Simulated Circuit ............................................................................................................................................33
Figure 3-10: Gate-to-source voltage across high side MOSFET ....................................................................................33
Figure 3-11: Detailed waveform of VGS...........................................................................................................................33
Figure 3-12: Load voltage waveform.................................................................................................................................34
Figure 3-13 MGD for each switch ......................................................................................................................................35
Figure 3-14 Block Diagram of IR2110................................................................................................................................36
Figure 3-15. ..........................................................................................................................................................................40
Figure 3-15 Full-Bridge DC/DC Converter ........................................................................................................................40
Figure 3-16 Software calculation.......................................................................................................................................43
Figure 3-17 Winding Diagram Result ................................................................................................................................43
Figure 3-18 Block Diagram of DC-DC converter ..............................................................................................................44
Figure 3-20 Control Circuitry for DC-DC FB Converter ...................................................................................................48
Figure 4-1 : 36V 800A Battery bank...................................................................................................................................55
Figure 4-2 : Snap of 12V 7A Dual Level Float Battery Charger.......................................................................................59
Figure 4-3: Schematic of 36V 800A Dual Step Current Charger.....................................................................................62
Figure 4-4: Battery Bank of 36V 7A for testing Prototype Charger................................................................................63
Figure 4-5: schematic of Temperature Control Circuitry ................................................................................................65
Figure 4-6: Schematic of Voltage Monitoring Circuitry...................................................................................................66
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ABSTRACT

Alternate Energy Based Power Solution (AEPS) is a power solution targeting the prevalent power

crisis in PAKISTAN and the desire for Green Energy. The scope of the project covers efficient

delivery of 5KVA power from wind and solar hybrid system, to household load, providing 1 phase

220VAC as output. The system also covers improved design for charging batteries to provide backup

in case of absence of input power. AEPS incorporates hybrid input from solar panels and wind

turbine to generate electrical output compliant with universal standards. Harmonics elimination and

charge equalization of series connected batteries lie as future amendments in the proposed design.
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COMMENTS FROM CLD

DR. SHOAIB ZAIDI
 V I

COMMENTS FROM INTERNAL FYP

SUPERVISOR
MR. MUHAMMAD JAVED

MR. ASIM AHMED

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C H A P T E R 1
OVERVIEW

1
Chapter

1 OVERVIEW
In this chapter we will discuss the basics architecture of AEPS and its design aspects,
their necessity, design requirements, simulation results and prototype.

A lternate Energy Based Power Solution (AEPS) is a complete offline power

system that solves the problem of power crisis through utilizing alternate green energy, namely

wind and solar. The system ensures that the input power is efficiently converted to international

electrical standards, acceptable for electrical devices. Moreover the system incorporates

functionality to handle proper energy storage in batteries for backup and maximize the life.

Complete development and installation of the system would depict an ultimate solution to power

crisis situation, although at a high initial investment, but a return on investment within 3 years of

installation.

PURPOSE

The primary reason for the selection of project was the prevalent power crisis that has struck the

world. The world now knows that the fossil fuels, which where relied upon for many years, will

become extinct soon and is putting earnest effort to create some new sources of energy which are

more reliable, renewable and are environmental friendly. Wind and Solar are one of the most

popular choices for a designer to work with, since they satisfy all the characteristics, although still

being expensive.

PROJECT DESCRIPTION

AEPS is a power solution targeting the prevalent power crisis in PAKISTAN and the desire for

Green Energy. The scope of the project covers generation of 5kVA power from hybrid system and

providing 1 – Φ 220VAC as output. Our project comprises of the following parts:

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C H A P T E R 1
OVERVIEW

PART A. Design, simulation, implementation and instrumentation of Asymmetric Hybrid

Multilevel inverter using DsPIC, 16-bit Digital Signal Controller, based on several research papers;

and it’s monitoring via Computer Interface.

PART B. Design, simulation, implementation and instrumentation of 5kVA Hybrid source fed

charge controller with charge monitoring, and input power suitable energy conversion.

1.1 HARDWARE ARCHITECTURE

1.1.1 INVERTER DESIGN

This stage involves the generation of Pure Sine Wave* from VRLA battery. This would be

accomplished by implementing and blending 2 research papers, namely [1] and [2], using dsPIC®

DSC High-Performance 16-Bit Digital Signal Controller. The inverter will be designed for 5KVA

output with design goal efficiency of 85 percent.

Features include:

1. Multi Level asymmetric hybrid inverter design with 49 Voltage levels [1]

2. True Sine wave generation (THD<3%)

3. Modulation using dsPIC digital signal processing controller

4. Strategy: Selective Harmonic Elimination [2]

5. Sensor less voltage control

6. Different operator keypads available for RUN/STOP control and setting parameters

7. Built-in RS-232 communication interface to allow configuration from a PC

8. Output Voltage level (220 +/- 2.5% VAC)

9. Cooling fan has ON/OFF selection to provide longer life

10. Protections

10.1. Overload

10.2. Over temperature

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C H A P T E R 1
OVERVIEW

10.3. Output short circuit

10.4. Inverter fault

10.5. Alarm for Inverter fault and DC input under Voltage

1.1.2 CHARGE CONTROLLER

The electrical output of the solar panel (DC) and wind turbine (AC) would be stored in valve

regulated Lead Acid (VRLA) type battery bank, consisting of 12 x 12VDC 200Ah batteries. The

power rating of the battery would depend upon the backup time required.

The charge controller is further divided in two parts:

1. AC-DC Conversion (Wind)

2. MPPT (Solar)

3. DC-DC Conversion (Solar + Wind)

4. Power Circuitry Design

5. Control and Monitoring circuit

Charge controller will be fed with stabilized 36VDC input (from Input Block*) and 4 outputs to 4

battery banks. 4 Battery banks would assist in providing power to Asymmetric Hybrid Modified

Cascaded Inverter. The charging is performed through Switch mode charging technique to ensure

and regulate proper charging current.

Features include:

1. 3 stage PWM based charge controlling

2. MPPT

3. Battery Overcharge protection

4. Control Depth of Discharge (DOD) to a maximum of 30%

5. Monitoring and Control (LCD 2 line display) with buttons; monitoring includes

5.1. Total amp-hours in and out of the batteries

5.2. Battery Bank’s state of charge
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C H A P T E R 1
OVERVIEW

5.3. measure total solar input and wind input independently

6. Equalization

7. Audible and visual alarms for high and low battery conditions

REQUIREMENTS

The project requires IGBTs, Power MOSFETS, Capacitors, Inductor, transformer, DsPIC Digital

Signal Controller, LCD Displays, sensors, PCB manufacturing facility, relays and magnetic contact

breakers, Batteries, Wind power generator, solar panel etc.

AVAILABILITY

Most of the items listed above are locally available, however some, like DsPIC, needs to be

imported. IGBTs are available but at a higher price.

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C H A P T E R 1
OVERVIEW

1.2 FLOWCHART

Figure 1-1 Flow Chart of AEPS

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C H A P T E R 1
OVERVIEW

1.3 SYSTEM ARCHITECTURE

AEPS architecture includes three major blocks namely input block, inverter block and the charge

controller. Since AEPS is a hybrid system, it incorporating circuitry to handle variable frequency

and amplitude AC electrical signal from wind generator and variable DC voltage and current signal

from solar panel arrays.

The design of input block includes the circuit to efficiently handle incoming electrical power and

transform it into a specific voltage that is fit for Charge controller and Inverter blocks. The output

voltage of this block is 42VDC, in accordance with maximum voltage rating of charge controller’s

IC. Input block consists of an AC-DC converter for rectifying output from wind turbine, and a

Dual DC-DC converter, which is used to stabilize the output of solar cells and AC-DC module,

into a constant DC value at high efficiency.

The charge controller block is designed to effectively charge the battery bank (36V 200Ah). Charge

controller features constant current 2 stages charging, to charge a string of 3 series connected

batteries. The capacity of charge controller allows paralleling the batteries for greater power backup

(up to 800Ah).

The inverter design is based on a research paper that suggested implementation of a multilevel

inverter with 49 level of output voltage for better THD and sine wave output without

incorporating harmonic filter circuit, which becomes very bulky and expensive when higher power

levels are desired. According to the paper, 4 independent DC voltage sources were required of

different values to form an asymmetric multilevel inverter. Thus the inverter block of AEPS also

incorporates 4 independent isolated DC-DC converters of different power and voltage ratings to

suffice the inverter requirements.

The detailed description of all modules is provided in their respective chapters, present in this

report.
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C H A P T E R 1

WIND GENERATOR
OVERVIEW
SOLAR PANEL AEPS
220Vac 400 Vdc
ARCHITECTURE

DC – DC INVERTER
CONVERTER
AC-DC 42V => 13V
Converter
Drive Circuit I

DC – DC
DC-DC Converter - I CONVERTER
200-450VDC =>42VDC 42V => 27V

Drive Circuit II

DC – DC
CONVERTER
42V => 93V
Power Charge BATTERY BANK 36V
Circuit 800Ahr Drive Circuit
III Drive
12VDC  12VDC  12VDC 
DC – DC Circuit
12VDC  12VDC  12VDC  CONVERTER
Controller Circuit 42V => 187V
12VDC  12VDC  12VDC 
Drive Circuit
12VDC  12VDC  12VDC  IV
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C H A P T E R 1
OVERVIEW

1.4 SOLAR ENERGY

The world-wide demand for solar electric power systems has grown steadily over the last 20 years.

The need for reliable and low cost electric power in isolated areas of the world is the primary force

driving the world-wide Solar Power industry today. For a large number of applications, solar

technology is simply the least-cost option. Typical applications of solar in use today include stand-

alone power systems for cottages and remote residences, navigational aids for the Coast Guard,

remote telecommunication sites for utilities and the military, water pumping for farmers, and

emergency call boxes for highways and college campuses, to name just a few.

1.4.1 SELECTION OF SOLAR CELLS

In the world of photovoltaic (PV) solar power, the two most widely used types are: crystalline

silicon and thin film. A brief comparison of major classification is given in Appendix.

Selection of Multi-crystalline Solar cell was made based on the following reasons:

• Energy Performance: It has less temperature-related loss than crystalline silicon due to a

lower temperature coefficient. It also provides superior energy output in low, indirect, and

diffuses light conditions, producing more electricity on cloudy days.

• Economical: It enables high-volume, low-cost production.

PV System Voltage – Modern systems without batteries are typically wired to provide from

235V to 600V. AEPS require 300-400V Solar Cell array as the input for the input stage.

1.4.2 EFFICIENCY IMPROVEMENT

Material Level of efficiency in % Level of efficiency in % Production

Lab

Monocrystalline Silicon approx. 18 13 to 15

Polycrystalline Silicon approx. 24 14 to17
Amorphous Silicon approx. 13 5 to 7
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C H A P T E R 1
OVERVIEW

Factors that can increase solar panel’s efficiency are:

1. MPPT - This topic is covered in detail in section 2.2

2. Solar Concentrators

Solar Concentrator

A Solar Concentrator is a device used to optimize the efficiency of solar power. Solar concentrators

work by means of a Fresnel lens on top of the photovoltaic cell or parabolic mirrors along with

prism, to concentrate the light into a strong beam into one part of the cell. The concentration of

light increases the efficiency and output of the pv cell making the solar arrays smaller in size and

reducing their cost as fewer pv cells need to be used in each array.

Solar Tracker: It is a mechanical assembly with electronic tracking system that track the array

along with the sun, thus increasing the amount of time that full sunlight is shined on the array.
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C H A P T E R 2
INPUT BLOCK

2
Chapter

2 INPUT BLOCK
In this chapter we will discuss the basics of Multi-level inverter; their necessity,
design requirements, simulation results and prototype.

T he input block of AEPS is comprised of the following individual modules namely AC-DC

Conversion for wind input, MPPT fro solar input and Dual DC-DC converter for both

inputs. The following chapter covers these sections in detail.

Primarily, the input from solar and wind energy are fed into AEPS. The AC input from Wind and

Solar input from solar panels are then converter into stabilized 36VDC at the output of input

block. Selection of 36Vdc as the output voltage is based on the fact that the charge controller IC

works on maximum 42V input.

2.1 AC-DC CONVERSION BLOCK

2.1.1 INTRODUCTION

The output of AC wind generator is variable (both in freq and amplitude), therefore cannot be used

directly as an AC supply to derive loads. This varying AC voltage from wind generator is first

converted into constant DC using MDS 100A, which will be used to charge batteries or routed

directly to DC-DC converters accordingly which will on next level feed inverter.

2.1.2 DESIGN OBJECTIVES

The first goal of our design is to collect the wind energy from wind generator which is converted

into electrical energy i.e. an AC voltage and to convert it into stabilized DC. The MDS 100A

rectifier module is used for electrical conversion from AC to DC.

The next goal is to design a filter at the output stage of rectifier to ensure minimal voltage ripple

thus blocking AC.

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C H A P T E R 2
INPUT BLOCK

2.1.3 WIND TURBINE CHARACTERISTICS

The wind turbine selected for AEPS is FD6.0-5000W permanent magnet Wind Generator. The

features of this turbine are given in appendix A. However the design of input block is dependant

upon the technical specifications of wind generator, mentioned in table2-1.

Table 2-1 Technical Specification of Wind Generator

Power(w) 5000
Blade diameter (m) 6
Rated Rotated speed(r/m) 220
Rated wind speed (m/s) 7
Rated power(w) 5000
Max power(w) 7000
Output voltage(v) 220V
Start up wind speed(m/s) 3
Operating wind speed(m/s) 3-25
Security wind speed(m/s) 40
Height of tower (m) 9
Weight of top section (kg) 120
tower pole type(mm) 159*5

2.1.4 AC GENERATOR DESCRIPTION (ELECTRICAL)

Since wind energy is a mechanical energy therefore it is need to be converted into electrical energy

so that it can be utilized as an alternate to direct electrical energy. FD6.0-5000W permanent magnet

Wind Generator (proposed) is used for this purpose. The generator has a rated power of 5kW at

operating wind speed of (3-25 m/s). The rated voltage of generator is 220V. The relation for

converting wind energy into electrical energy is:

P = (1/2) ρ * A * Cp * v3 [1]

Where;

P= wind generator output power

ρ= air density in kg/m^3
A= area of wind generator rotor
Cp= power co-efficient
v= wind speed in m/s
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C H A P T E R 2
INPUT BLOCK

2.1.5 SCHEMATIC

Table 2-2 Schematic and snapshot of prototype implementation

D1, D2, D3 and D4 = MDS100A (1600V, PROTOTYPE IMPLEMENTATION

100Amp)
L= under study
C= under study
Vripple=Iload/fC; Where I is the DC load
current in amps, ƒ is the frequency of the ripple
or twice the input frequency in Hertz, and C is
the capacitance in Farads.

2.1.6 TESTING

AC generator (simulator) is currently being imported for

Electrical labs, therefore no simulation data can be collected, in

market scaled down versions of AC generator of ratings 400W

and 800W are available, which use different technology and hence

data collected from them will not be beneficial.

A typical wind power against wind speed curve is illustrated in

figure 2-1, which allows us to estimate the output power,

Figure 2-1 Power output curve with
knowing that the average wind speed in Karachi is nearly 3-5m/s. respect to wind speed for wind generator

Some data collected from internet from ac generator vendor is given below:

Table 2-3 5 kW Wind turbine power curve data

M/S MPH Watts
1 2.24 6
2 4.48 51
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C H A P T E R 2
INPUT BLOCK

3 6.72 173
4 8.96 409
5 11.20 2,194
6 13.44 3,274
7 15.68 4,662
8 17.92 6,395
9 20.16 8,512

In order to test the input block of AEPS, the coupled DC motor and AC generator set of Electrical

labs will be used.

2.2 MPPT

A MPPT, or maximum power point tracker is an electronic DC to DC converter that optimizes the

match between the solar array (PV panels), and the battery bank or utility power. Maximum Power

Point Tracking is electronic tracking, and has nothing to do with moving the panels. Instead, the

controller looks at the output of the panels, and compares it to the battery voltage. It then figures

out what is the best power that the panel can put out to

charge the battery. It takes this and converts it to best voltage

to get maximum AMPS into the battery. (Remember, it is

Amps into the battery that counts). Most modern MPPT's are

around 92-97% efficient in the conversion. You typically get a

20 to 45% power gain in winter and 10-15% in summer.

Actual gain can vary widely depending weather, temperature,

battery state of charge, and other factors.

PV cells have a single operating point where the values of the current (I) and Voltage (V) of the cell

result in a maximum power output. These values correspond to a particular load resistance, which

is equal to V/I as specified by Ohm's Law. A PV cell has an exponential relationship between

current and voltage, and the maximum power point (MPP) occurs at the knee of the curve, where

the resistance is equal to the negative of the differential resistance (V/I = -dV/dI). Maximum
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C H A P T E R 2
INPUT BLOCK

power point trackers utilize some type of control circuit or logic to search for this point and thus to

allow the converter circuit to extract the maximum power available from a cell.

Traditional solar inverters perform MPPT for an entire array as a whole. In such systems the same

current, dictated by the inverter, flows though all panels in the string. But because different panels

have different IV curves, i.e. different MPPTs, this architecture means some panels will be

performing below their MPP, resulting in the loss of energy.

2.3 DUAL INPUT DC-DC CONVERTER

A multiple-input dc–dc converter is useful to obtain the regulated output voltage from several input

power sources such as a solar array, wind generator, fuel cell, and so forth. The conventional

methods of combining input power through various sources includes multiple dc-dc converters for

every voltage source and a DC Bus as shown in diagram below. On the other hand, designing a

multilevel DC-DC converter offers many advantages which are illustrated in figure and table 2-4.

Figure 2-4: Block Diagram comparison between Conventional and Multiport structure

Table 2-4 Comparison of conventional and multi-port structure

Conventional Multi-port
structure structure
Need a common dc bus? yes No
Conversion steps more than one Minimized
Control scheme separated control centralised control
Power flow management complicated, slow simple, fast
Transformer multiple single, multiwinding
Implementation effort High low
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C H A P T E R 2
INPUT BLOCK

Utilizing the design approaches as proposed by [1] and [2], the design of dual input DC-DC

converter is possible. The proposed and tested design in [2], which is dual input (fuel cell and AC

line) single output converter, can be implemented in AEPS since the input sources used are AC

voltage from Wind generator and DC voltage from solar cells. The design is described in Fig 2-5.

Figure 2-5 Proposed Dual Converter for AEPS

2.3.1 CIRCUIT DESCRIPTION

The circuit basically a merger of 2 isolated buck-boost type dc-dc converters, connected together

through a single transformer, having 2 primary and single secondary winding. The topology along

with the controlling scheme as provided in paper, appears as the perfect circuitry to handle the

incoming wind and solar energies with high efficiency. The AC line as mentioned in diagram can be

replaced by an AC generator in wind turbine while solar array exist as the second input. The further

study, the circuit was simulated on ORCAD and a small scale prototype was implemented to test

the logic.
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C H A P T E R 2
INPUT BLOCK

2.3.2 SCHEMATIC AND PROTOTYPE

Table 2-5 Schematic and Snapshot of prototype implementation

Enlarged schematic is present in Appendix.

2.3.3 PROTOTYPE IMPLEMENTATION:

MOSFET Gate waveforms for high side Output of High frequency transformer with
MOSFET in fly-back topology from IR2118, single input voltage source
according to paper
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INPUT BLOCK

2.3.4 EXPERIMENTAL DATA

Table 2-6 Experimental results of Dual Converter and inferences

Vin D Vo1 Vo2 I Inferences
Effect of Duty cycle on Vout
60.7 3/22 7.6 5.57 0.01 The output voltage of converter increased
4/20 9.9 6.47 0.01 proportionally with respect to to duty cycle.
6/20 40 12.51 0.05
6/14.5 56.5 19.92 0.19
7/14.5 60 23.2 0.25
Circuit Variation to improve efficiency
40 7/25 19.6 0.17 56.5 Single diode bridge Paralleling
7/25 19.2 0.20 46 Parallel diode bridge the diode
decreased
the
Variation in input voltage and Duty cycle to improve efficiency (Rload=100)
Vin Duty Iin Vo Io Efficiency The practical calculated losses of
20 3/37 0.05 7.4 0.074 55.6 power MOSFET switching and
40 10/25 0.23 22 0.22 52.6 steady state were negligible because
40 5/27 0.15 20 0.2 66.66 the gate drive waveforms were almost
“ideal Square wave”. Hence it was
concluded that power transformer
was working at much lower efficiency
than expected due to inefficient
coupling

2.3.5 CONCLUSION

The successful prototype testing proved that the topology is capable of delivering high power

output at higher efficiency compared to traditional techniques.

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3
Chapter

3 INVERTER DESIGN
In this chapter we will discuss the inverter block in detail covering aspects of its
necessity, design requirements, simulation results, prototype implementation with test
results and future improvements.

T he AEPS architecture has different modules under the block namely, four DC-DC

Converters with unique design requirements and the power inverter stage which is based

upon the topology proposed in research paper[3]. Moreover, the controlling mechanism for

stabilized voltage outputs of converters and staircase waveform corresponding to sine wave with

very low THD will also be explored.

The proposed power inverter is designed to produce a 49 level staircase waveform which closely

approximate a pure sine wave. The inverter is capable of achieving desirable waveform without the

use of any harmonic filter at the output, thus reducing design cost. The Inverter designing is

covered in detail in section 3.1

High side gate drive design was necessary to implement the proposed inverter topology. The

design, simulation and test results of gate drive are covered in section 3.2. DC-DC converter

design’s objectives, implementation and test procedures are discussed in sections 3.3, 3.4, 3.5 and

3.6. The implementation of all four DC converters is beyond the scope of the project; yet,

complete analysis and design procedure are discussed in these chapters. One DC-DC converter

was implemented as a prototype to test the theoretical calculations and results are documented.

3.1 POWER INVERTER STAGE

The poor quality of current and voltage waveforms of a power system fed by a classical two level

inverter has been witnessed in many designs. As a result, a multilevel power converter structure has

been introduced being the alternative in high power and medium voltage situations. Several

multilevel converter topologies have been developed [1] [2].

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A multilevel converter has several advantages over a conventional two-level converter that uses

high switching frequency pulse width modulation (PWM). Advantages of this multilevel approach

include good power quality, good electromagnetic compatibility (EMC), low switching losses, and

high voltage capability with lower stress on the switches. The attractive features of a multilevel

converter can be briefly summarized as follows. Unfortunately, multilevel converters do have some

disadvantages. One particular disadvantage is the greater number of power semiconductor switches

needed. Although lower voltage rated switches can be utilized in a multilevel converter, each switch

requires a related gate drive circuit.

3.1.1 ASYMMETRICAL MULTILEVEL CONVERTERS

In all well-known multilevel inverter topologies, the required number of power devices depends on

the output voltage level. However, increasing the number of power semiconductor switches also

increase the inverter circuit size, cost, installation area and control complexity.

Figure 3-1 shows basic element, which is used to implement asymmetric multilevel inverter. The

circuit consists of K dc voltage sources (cells) and 2(K+1) bi-directional switches. Since, the dc

voltage sources are different; this multilevel inverter is termed as Asymmetrical multi-level

converter. With suitable toggling of switches, the number of output voltage levels is:

n = 1 + K (K + 1) [1]

Using the basic element in N stages Asymmetric multilevel

inverter, Figure 3-2 shows the new converter in details. Each

stage (basic element) can generate a stepped voltage waveform.

The sum of these stepped voltages would result in a high quality

overall output voltage of multi-stage inverter. [3].

Figure 3-1 : Basic element
(one stage) of asymmetric
multilevel inverter
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Figure 3-2 : New asymmetric multilevel configuration

3.1.2 DESIGN REQUIREMENTS

In summary, our objective was to inspect and experiment with the proposed inverter design in [3].

The design performance will further be enhanced by using the Harmonic elimination technique as

stated in [4]. Such efforts will ensure a better and robust inverter design.

Table 3.1 Requirements of the experimental circuit

Characteristics and Ratings

Total DC Voltage levels 49

Total DC Voltage sources 4
Vdc,1 13 V
Vdc,2 26 V
Vdc,3 96 V
Vdc,4 178 V
Total Power switches 12 Bi-directional
Stage 1 6
Stage 2 6

Table 3.2 Technical characteristics of the experimental prototype

Max total output Pout, max 5kW ; Z = 9.68 Ω
power
Output Voltage Vac 220 V ± 10%
Short circuit output Iac, sc 22.75 A
Current
Max allowable THD < 6..6% Iac, sc = 62A ;
Vac = 220V
Power loss Ploss < 600 W

Switching frequency ƒs Variable ; 50 ≤ ƒs ≤ 2740 Hz

The Power switches are switched in such fashion that generates 49 levels sinusoid output

waveform however, to achieve this we incorporated back – to – back 2 HEXFET® per switch.
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Also, due to higher current requirements and lower resistance, such switches need to be

quadrupled. This enhances the ability to fully replicate an ideal controllable switch. Currently, we

used in all 24 HEXFET® IRF2907 for stage – 1 and 24 HEXFET® IRFP260 for stage – 2.

3.1.3 SIMULATION AND RESULTS

HEXFET® is chosen for the design and the simulated circuit as shown in the Figure 3-3 is found

with satisfactory results leading to the final prototype. The major calculation involved was for

estimating power loss. We calculated it using equation (1) & (2).

Plosses = I2R (1)

For stage 1: Taking parallel switch and associated body
diode resistance into account
I = 22.7 A
R = 2mΩ + 8.67mΩ
Plosses =2x22.7x22.7(2+8.67)(1m)
Plosses = 11W
For stage 2: Taking parallel switch and associated body
diode resistance into account
I = 22.7 A
R = 20mΩ + 23.2mΩ
losses = 2x22.7x22.7(20+23.37)(1m)
Plosses = 44.6 W
Hence; Total Power loss = 11 + 44.6 = 55 W [switching losses are neglected due to (2)
lower ƒs]

Table 3-1 shows the complete schematic of power stage and its simulated results. The simulation is

made using MGD as described in chapter 3.4. Simulated results show that the inverter is generating

multilevel staircase waveform as expected. Capacitor addition parallel to load is made, as contrary to

research design, and the observed results depicted that there was no substantial improvement in

waveform as far as smoothing was concerned.

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Table 3-1 Schematic of Power Stage along with simulation results and inferences

Figure 3-3 : Final Inverter Schematic

The simulation
proved that the
solid state switches
(Power MOSFET
switch) worked
perfectly fine with
MGD at converter’s
frequency.
However, further
simulation and
practical testing
proved that the gate
drive was not
feasible for higher
voltage(>40V) due
to transistor’s Vce
limitation
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Effect of capacitor
addition on inverter
output

Continuous First
stage stabilized
operation
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3.1.4 PROTOTYPE DEVELOPMENT

Different developed prototypes and their test results are stated in Table 3-2.

Table 3-2 Prototype results

Prototype 1

This was the first prototype build

to test the MOSFET bidirectional
switches and overall operation of
inverter. Test was done using
10W 100Ohm load, using 12V
12Ah dry batteries. The test was
partially successful; problems
were encountered due to
improper connections.

Prototype 2

Due to improper response of first

prototype, 2nd prototype was built.
The test was conducted using 10W
100Ohm Load, while inputs were 9V
batteries for 1VDC and 2VDC both.
The testing was successful and 3 step
and 7 step waveforms were observed
and recorded.
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Prototype 3

Successful implementation of 2nd

prototype resulted in PCB
fabrication of 3rd prototype. It
was designed to cater to at least
1KW load, under controlled
conditions. Transistors were
replaced to withstand high
voltage and short circuit/
overload protection was also
incorporated in design. Heat
sinks and cooling fan was also
brought into consideration.

Control Circuitry

The controlling algorithm was

implemented through μC PIC
16F877. Complete trainer was
built for the controller with RS-
232 outputs, buffered outputs,
LED indicators, pots and
controller protection circuits.
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3.1.5 DESIGN TEST

The final prototype developed was used to test 3 stage and 7 stage waveform. Table 3-3 shows test

results under different input conditions.

Table 3-3 Practical test results

3 step waveform

Prototype2

VDC=9V battery

Output voltage= +9V, 0, -9V

Load=100ohm 10W

7 step waveform

Prototype 2

1VDC=2VDC=9V Battery

Output voltages=-27, -18, -9, 0, 9, 18,

27

Load=100ohm 10W

Final Design Test 1: Under observation

14VDC=18v, 7VDC=9V (Power Plus battery)

2VDC=2.5V, 1VDC=1.2V(Ni MH Nikon Cell)

Objective:

Check proper gate drive operation

Check switching control strategy using controller
Generate 21 level waveform
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I N V E R T E R

Adjust switching angles to generate near sine wave

Final Design Test 2: Under observation

14VDC=168V, 7VDC=84V (EZ Power Supply)

2VDC=24V, 1VDC=12V(VRLA battery)

Objective:

Check proper gate drive operation

Check switching control strategy using controller
Generate 49 level waveform
Adjust switching angles to generate near sine wave
Final Design Test 3: Under observation

Vo=220VAC;
Load= Resistive (400W)- Power Electronics Lab

Objectives:
Check system stability at 500W load
Check heat dissipation in switching elements
Check perfect sinusoidal waveform generation

3.2 HARMONIC ELIMINATION

By the very design of circuit in Table 3-1, it produces less than 10% THD at full load. With an

increasing number of DC voltage sources, the output voltage waveform approaches a nearly

sinusoidal waveform while using a fundamental frequency switching scheme, resulting in lower

switching losses, and because of several DC sources, the switches experience a lower dV/dt.

Figure 7 shows the major types of switching techniques and established harmonic elimination

techniques associated with them.

So, in order to achieve the near sinusoidal shape of output voltage waveform and thus the

efficiency of the overall inverter it was found a prospect of further research to use a proper

Harmonic Elimination switching algorithm for the correct timing of the gating signals to the

control terminals of the switches.

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I N V E R T E R

Figure 3-4: Classification of multilevel modulation methods

The major problem faced in the harmonic elimination is the solution of transcendental equation of

the switching angles of the switches. In our design, if amplitude of all the stepped waveforms is

taken equal, the expression of the amplitude of the fundamental and all harmonic contents will be

follows as (3) & (4):

(3)

where E is the amplitudes of the stepped waveforms, S the number of levels and αj is the
optimized harmonic switching angles. The angles αj are expressed by the following equation:

(4)

Now, in order to solve these transcendental equations we first need to find the equation

satisfying 4 different voltage source levels and then employ resultant theory. Further, in order

to alleviate the complex calculation, we established our solution for proper switching on the

dissertation of Prof. Zhong Du entitled “Active Harmonic Elimination in Multilevel

Converters”.[4]

However, as mentioned before, this prospect of increasing the efficiency by eliminating high

order harmonics is future research aspect.

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3.3 PROTECTION CIRCUITRY DESIGNING

In order to maintain safe and trouble free operation of all the modules and the whole system, it is

highly demanding to provide sufficient instrumentation and protection of each part. We have

implemented basic protection circuitry which detects the fault and announces to the control loop,

so that corresponding centralized fault routines are initiated:

1. Over voltage protection

2. Over current / short circuit protection
3. Temperature Sensing & shutdown

3.3.1 OVERVOLTAGE PROTECTION

It is very intrigue task to protect the appliances connected at the load terminals from

overshoot/over voltage. Generally, such type of protection is implemented through passive

snubber (RCD) circuits. However, in our design the inverter is fed through four different dc-dc

converters which continuously monitor their output voltage and control the gating pulses

accordingly. Therefore, the control loop ensures minimal chances of over voltages. In case of

uncontrolled voltage development in DC-DC converter, the converter will shut down the output,

indicating fault condition, thus forcing inverter as well to halt functioning.

3.3.2 SHORT CIRCUIT PROTECTION

It is quite obvious that a fast acting Miniature Circuit Breaker is protecting the whole circuitry from

driving over current and melting down, and maintaining safe operation without any short circuit. In

case of short circuit the MCB will be immediately switched off and the control loop will detect a

fault thereby shutting down the dc-dc converters.

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3.3.3 TEMPERATURE SENSING & THERMAL

SHUTDOWN

The temperature sensing element is CdS based NTC that provides a very rough estimate of its

ambient temperature. Our aim is to employ thermal/over heat protection to ensure the reliability of

the whole system, therefore an ingenuous design have been implemented for temperature sensing

and therefore triggering the fault routing through control loop. Highly sophisticated thermal

protection can be implemented however; they might be beyond our scope.

3.4 GATE DRIVE DESIGN

3.4.1 HIGH SIDE N-CHANNEL MOSFET GATE DRIVE

The discussed multi level inverter design requires a

medium speed high side MOSFET gate drives. Since,

the inverter comprises of floating switches at each side

of the input dc-voltages therefore, a cheaper solution

has to be devised. There were variety of options

available in terms of both discrete and ICs. Figure 3-5: MOSFET with stray
inductances at its terminals
We employed both type of solution depending on the feasibility. When switch mode operation of

the MOSFET is considered, the goal is to switch between the lowest and highest resistance states

of the device in the shortest possible time. Now by considering the circuit as shown in Figure 3.6

that the unclamped inductance or stray inductance and the packaging source inductance slow down

the rate of charging Cgs. [1]

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I N V E R T E R

Figure 3-6 : Waveforms for Turn-On Figure 3-7 : Waveforms for Turn-Off
Similar considerations apply to the turn-off interval. Figure 3-7 shows

theoretical waveform for the MOSFET during the turn-off interval.

3.4.2 HIGH SIDE MGD FOR 1ST STAGE

Table 3-4: Shows the requirements of the proposed high side gate drive circuit Stage 1
inverter design:
Characteristics and Ratings
Gate Threshold Voltage VGS(on) 2 - 4V ; VDS = VGS, ID = 250μA

Max Gate – to – source VGS ± 20V

voltage
On-Resistance RDS(on) Max 8.0mΩ ; VGS = 10V, ID = 62A
Forward Transconductance gfs Min 44S ; VDS = 25V ; ID = 62A_

Input Capacitance Ciss Typ 3247pF VGS = 0V ; VDS =

25V ;
Output Capacitance Coss Typ 781pF ƒ = 1.0MHz
Reverse Transfer Crss Typ 211pF
Capacitance
Total Gate Charge Qg Typ 146nC ID = 62A ; VDS =
44V ;
Gate-to-Source Charge Qgs Typ 35nC VGS = 10V
Gate-to-Drain ("Miller") Qgd Typ 54nC
Charge
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I N V E R T E R

The following drive circuitry will not be applicable for stage 2 of the said inverter due to higher

drain voltages.

With the above mentioned characteristics, starting with the design of MGD, the supply voltages

must be kept in mind. Where input voltage levels prohibit the use of direct gate drive circuits for

high side N-channel MOSFET, the principle of bootstrap gate drive technique can be considered.

This method utilizes a gate drive and accompanying bias circuit, both referenced to the source of

the main MOSFET transistor. Both the driver and the bias circuit swing between the two input

voltage rails together with the source of the device.

Discrete solution is preferred since we require only high side MGDs as per 1st stage inverter design

with reasonably lesser supply voltage rails.

Figure 3-8: A basic form of the circuit

The major calculation was of the boost strap capacitor. We calculated it through equation (5) & (6).

(5)

(6)

QG = Total gate charge

QRR = Reverse recovery charge
ILK,D = Leakage current of the bootstrap diode [neglected]
IQ,LS = Quiescent current of the level shifter [neglected]
IQ,DRV = Gate driver current [Dominant]
IGS = Gate-to-source current [neglected]

With 10% or 1V voltage ripple on the boost strap cap the desirable value = CBOOS T ≥ 4.7uF.
 3 3

I N V E R T E R

3.4.3 SIMULATION AND RESULTS

We designed our own bootstrap MGD based on the previously discussed design. Figure 3-9 shows

the schematic of the design.

Figure 3-9: Simulated Circuit

Following are the simulation results obtained:

Figure 3-10: Gate-to-source voltage across Figure 3-11: Detailed waveform of VGS
high side MOSFET
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Figure 3-12: Load voltage waveform

3.4.4 PROTOTYPE DEVELOPMENT

Prototype 1:

When the complete inverter was tested unfortunately, the circuit failed to deliver the required

performance and therefore, we replaced it with 6 individual circuits of IRS 2186.

The IR2118(S) is a high voltage, high speed power MOSFET and IGBT driver. Proprietary HVIC

and latch immune CMOS technologies enable rugged monolithic construction. It features

1. Floating channel designed for bootstrap operation

2. Fully operational to +600V

3. Tolerant to negative transient voltage dV/dt immune

4. Under voltage lockout

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I N V E R T E R

5. CMOS Schmitt-triggered inputs with pull-down

6. Output out of phase with input (IR2118)

The bootstrapping principles will be discussed in detail in the next section. The basic aim of using

IR 2118 was to keep the MGD design simple, robust and cheap. The basic design used is shown in

Figure 3-13 which will be replicated for each individual circuit and also, repeated for 2nd stage.

Figure 3-13 MGD for each switch

3.4.5 HIGH SIDE MGD FOR 2ND STAGE

Table 3-5 shows the requirements of the proposed high side gate drive circuit for driving

IRFP260N HEXFET® Power MOSFET in stage 2 of the said inverter design:

Table 3-5 MGD Rating

Characteristics and Ratings
Gate Threshold Voltage VGS(on) 2 - 4V ; VDS = VGS, ID = 250μA

Max Gate – to – source VGS ± 20V

voltage
On-Resistance RDS(on) Max 40mΩ ; VGS = 10V, ID = 28A

Forward Transconductance gfs Min 27S ; VDS = 50V, ID = 28A

Input Capacitance Ciss Typ 4057pF VGS = 0V ; VDS = 25V ;

ƒ = 1.0MHz
Output Capacitance Coss Typ 603pF

Reverse Transfer Capacitance Crss Typ 161pF

Total Gate Charge Qg Typ 234nC ID = 28A ; VDS = 160V ;

VGS = 10V
Gate-to-Source Charge Qgs Typ 38nC

Gate-to-Drain ("Miller") Qgd Typ 110nC

Charge

Now, while designing a suitable MGD for the 2nd stage, we employed an IC namely

IR2110.International Rectifier’s IRS2110 integrate most of the functions required to drive one
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I N V E R T E R

high-side and one low-side power MOSFET or IGBT in a compact, high performance package.

With the addition of few components, they provide very fast switching speeds and low power

dissipation. Used in the bootstrap mode, they can operate in most applications from frequencies in

the tens of Hz up to hundreds of kHz.

The bootstrapping principle is used due to its ease and symmetry from the previous stage. In

Figure 3-14, the block diagram of the IR2110 shows the typical IC structure. It comprises a drive

circuit for a ground referenced power transistor, another for a high-side one, level translators and

input logic circuitry.

Figure 3-14 Block Diagram of IR2110

Also, the precise application of the circuit is visible in the diagram. We have used the IC in same

configuration. The calculation of bootstrap capacitor was done using equation (7)

(7)

where:

Qg = Gate charge of high-side FET

f = frequency of operation
ICbs (leak) = bootstrap capacitor leakage current
Iqbs (max) = Maximum VBS quiescent current
VCC = Logic section voltage source
Vf = Forward voltage drop across the bootstrap diode
VLS = Voltage drop across the low-side FET or load
VMin = Minimum voltage between VB and VS.
Qls = level shift charge required per cycle (typically 5nC for 500 V)

By choosing appropriate values the value come out to be CBOOST ≥ 10uF and the max peak current

for charging is 1A so 1N4001 diode is used as bootstrap diode.

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Prototype 2:

Prototype 3:

3.4.6 MGD FOR DC/DC CONVERTERS

The approach towards designing MGD for our four separate DC/DC converters was same as they

are quite symmetrical. The Basic design of full bridge converters was adopted which encompass at

least two high side N-channel MOSFETs. From designing point of view, the major difference was

of frequency ranges.
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The DC/DC converters will operate at a maximum of about 300 KHz frequency for efficient

power transfer and require low primary side voltages (42VDC), therefore our previously designed

discrete components based MGD for 1st stage of inverter are be incorporated for DC conversion,

with minor adjustments and modifications.

3.5 BATTERY POWER SIMULATION

An important aspect of inverter was to determine the input power requirement from the 4

independent battery sources attached to multilevel inverter. Since these sources were made of

different voltage levels and each had different on times in one complete period, simulation were

conducted to ensure the peak instantaneous and average power of the sources. These results were

used to calculate the design requirements for the dc-dc converter, explained in later chapter.

Table 3-6 shows the simulated results.

Table 3-6 Battery Power simulations and results

Battery Power
simulation
The 4 independent
voltage sources required
by the inverter needs to
be designed by using
DC-DC converters.
However the design
requirements for DC-DC
converter can only be
calculated by observing
the power delivered by
individual source
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Simulation proved that the

4 batteries will contribute
evenly for the inverter load,
delivering power equivalent
to their respective voltage.
Whereas the current
following from the
batteries will be same. This
simulation was used to
determine the
specifications for 4 dc-dc
converters.

3.6 DC-DC Converter – IV

3.6.1 INTRODUCTION

Goals: The AEPS requires a 4.235kW DC/DC converter to provide power to the inverter and

ultimately to the load. The team requires a constant 186.6V DC 4.2kW output with a varying 32.4-

39.6V DC (10% variance over 36VDC) input.

Objectives: Our objectives are to design a converter with the following requirements:

1. Cost efficient DC/DC converter

2. Design product with minimum Mean Time To Failure rate of approximately 10 years

3. 4.235kW power output

4. 186.6V DC output with varying 36 +/-10% VDC input

5. Output voltage tolerance within +/-2.5% (+/-4.665V)

Constraints: The defined input voltage will vary between 32.4 and 39.6 VDC and the permissible

output voltage will be ±2.5 percent of the stated regulated voltage of 186.6V DC. The DC/DC

converter will be required to provide 4.2kW of power with a DC output voltage between 181.9 -191.3V.
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DESIGN REQUIREMENTS

1. 4.235kW nominal power output with 90% efficiency

2. 186.6V DC output with a varying 32.4-39.6 VDC input

3. Output ripple voltage less than 1 percent

4. High frequency transformer to minimize power loss

5. Control circuit to maintain consistent output

6. Cooling solutions: Heat sinks and Cooling Fans

7. Circuit protection devices to limit current

8. Output voltage tolerance within ±2.5%.

3.6.2 ACCEPTED TECHNICAL DESIGN

The accepted topology for this project is the Full-Bridge DC/DC converter shown in Figure 3-15.

Figure 3-15 Full-Bridge DC/DC Converter

The Full-Bridge DC/DC converter will have to maintain a constant 400V DC output with a

varying 21-48V DC (29V DC nominal) input. This is accomplished by using Pulse Width

Modulation (PWM) control. By increasing or decreasing the duty cycle (D) of the square-wave
 4 1

I N V E R T E R

pulses to the switches M1-M4, the output voltage can be held constant with a varying input

voltage. The output voltage can be calculated as follows:

(8)

Where T is the switching time or the inverse of the frequency, Np/Ns is the transformer
turns ratio and t is the pulse width time.

(9)

(10)

The Full-Bridge DC/DC converter topology was chosen for several reasons. These are as follows:

1. High power handling capabilities

2. Stability
3. Symmetry
4. Highly efficient high frequency transformer design; It is one of the most efficient ways to
step up the voltage and to transfer the 3.1 kW of power to the full-wave rectifier circuit.
The high frequency transformer is also much smaller and lighter than a standard 60 Hz
transformer.

The input power for a 4.235k W Full-Bridge DC/DC converter with 90 percent efficiency is

calculated as follows:

Pin (kW) = P out / η =4.235K/0.90 =4.7KW (11)

With knowledge of the input power, the worst-case input current (21V input) can be calculated as

follows:

Iworst = Pin / V worse =4.7K/32.4 = 145.26A (12)

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SWITCH SELECTION:

For this type of application, there are two types of switches to choose from, one being the

Insulated Gate Bipolar Transistor (IGBT), and the other a Metal Oxide Semiconductor Field

Effect Transistor (MOSFET).

MOSFET IGBT
Fs Fs>>20Khz (100-500Khz) Fs<20Khz
Voltage V<250V V>1000V
Temperature Temp~ Ambient Temp>100°C
Conduction Losses(at low Medium High
temp)

The MOSFET switch was chosen for the Full-Bridge DC/DC converter since it will be utilized in

a low voltage application (32.4 and 39.6 V) and a low temperature situation. To minimize switching

losses 5 or 6 MOSFETs will be placed in parallel for each switch. The MOSFET chosen for the

implementation is IRF2907 which has an On-Resistance of 4.5m . Using 4x 2907 for a single

switch, the MOSFET losses are calculated as:

P MOSFET, switching losses =2(I2R) = 2(145.26)2(1.125m) = 47.48Ω (13)

TRANSFORMER DESIGN:

After inverting the DC input voltage into an AC voltage, an efficient way to step up the voltage is

necessary. The high frequency transformer was specially designed for frequency range of 100K-

300 kHz applications, which minimized Hysteresis-losses. The transformer was designed using a

software names “Magnetics Designer 4.1, which is specially made for inductor and transformer

design implementation.
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Figure 3-16 Software calculation Figure 3-137 Winding Diagram Result

The nominal efficiency of transformer is 98%, according to the software calculation. The power

loss of the high frequency transformer can be calculated as follows:

P LOSS, Transformer =PIN, Transformer (1- η) = (4706.5-47.48)(1-0.98)= 93W (14)

The high frequency transformer isolates the input from the output which is a must requirement of

our inverter stage.

RECTIFICATION:

To convert the AC voltage from the secondary terminal of the transformer to a DC voltage, a full-

wave rectifier configuration was chosen. The full-wave rectifier configuration will produce a higher

average voltage than a half-wave rectifier. To determine the switching losses of the diodes, the

output current and switching resistance

of the diodes must be calculated. The output current is calculated as shown below:

Iout =P out/V out =4.2KW/186.6=22.7A (15)

The switching resistance of the diodes is approximately 0.1Ω per diode. The diode switching losses

can then be calculated as follows:

PLOSS, Diodes = 2(I2RON) = 2(22.7)2 x (0.1) = 103W (16)

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OVERALL EFFICIENCY

After calculation all of the individual losses, the total power losses and overall efficiency can be

determined. Since the controls circuit is mostly comprised of circuitry that consumes very little

power, their power losses will be neglected.

P loss total=P loss mosfets+ P loss transformer+ P loss diodes= 47.48 +93 +103 =243.5W (17)

The overall efficiency is approximated as follows:

η= Pout / (P out +P loss total)=4.235KW/(4.235KW+ 243.5)= 94.56% (18)

The overall efficiency of 94.56 percent is based on worst-case conditions with a duty cycle of 0.45.

The duty cycle will decrease as the input voltage increases from 32.4 volts. A lower duty cycle will

result in a higher efficiency with lower switching power loss.

3.6.3 BLOCK DIAGRAM

36VDC DC-AC High AC-DC Regulated

Input Conversion Frequency Conversion 186.6VDC
from Full Bridge Transformer Full Bridge at 3.1KW
Input Configuratio Isolation Rectifier Power
Block n

Control Circuit
Variable Frequency and Duty Cycle Control

Figure 3-18 Block Diagram of DC-DC converter

The input for the stage is from the DC-DC converter of Input Block which produces a stabilized

voltage of 36VDC at output with a ripple of 1%. For the input voltage supply, a capacitor C1 and

inductor L1 filter must be determined. This will keep the supply regulated at the designated value.

The capacitor for the input is based on the extreme case where the voltage is 32.4V and the current

is at maximum (145.26). The IRMS for the input is calculated.

IRMS= IIN /2D = 145.26/2(0.45) = 164.4A (19)

 4 5

I N V E R T E R

With this value, the current through the capacitor can be calculated using [3] and the capacitor can

be determined using [4]

ICAP=√ (Irms2 – Iin2) (20)

(21)

ICAP =69.64A; C1=69.64/ (2*pi*300K*0.324) =114uF

Where DV is the percent ripple. It is determined as DV = (32.4V) (0.01) with 1% ripple factor.

The input inductance L1 is chosen to be very small based on the fact that the input voltage source

will be pure DC. An inductance of 10nH will suffice for this use, but not for sources other than a

pure DC.

The inductance L2 and capacitance C2 values on the output side are to be determined for a ripple

of less than 1%. With a duty cycle of 0.45 and load resistance of 8.22Ω, the critical inductance is

calculated below.

Lcritical = (1-D)*R*T/2D = (1-0.45)*(8.22)/2(0.45)(300K)= 16.7uH (22)

where T, D and R are the period, duty ratio, load resistance respectively. The output inductance is

desired to be:

L > 10xLCRITICAL (23)

∴ L=167uH

That value will help determine the minimum capacitance for the filter system of the rectified DC

voltage. The capacitance C2 can be calculated using (24).

(24)

=> 0.01 = (1-0.45) / (8*167u*C2*4*(200K) 2) =>C2=0.257uF (25)

where

L2, C2 and f are the output inductance, output capacitance, and frequency respectively. Since the

minimum value must be 0.257uF, the chosen value will be 1mF for a better filter system.
 4 6

I N V E R T E R

(26)

PCB design incorporates all the MOSFETS to be fixed to two aluminum sheets, each with 8

MOSFETS. Therefore, the thermal resistance calculation of the designated heat sink can be

calculated using (27).

Q= (75-30)*2/ (47.48) = 1.895oC/W (27)

Where Q is the power dissipated, DT is the change in temperature of a maximum of 75o and R is

the thermal resistance.

3.6.4 FINAL SCHEMATIC

Figure 3-19 Final Schematic of the dc-dc converter

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I N V E R T E R

3.6.5 CONTROL CIRCUITRY

The controls circuit is shown in Figure 3-20. This circuit is primarily composed of 3 integrated

circuits (IC’s), the PIC16F877 microcontroller, IL300 Optocoupler, LM324 and the gate drives.

Although the primary functions of a full bridge DC-DC converter can be controlled by dedicated

ICs like UC3825BN or TL494, but due to their unavailability in Pakistan and limited functionality,

PIC microcontroller along with dedicated comparator ICs was used for controlling the circuit.

Moreover in order to test the control algorithm proposed by Wensong Yu and Jih-Sheng Lai in the

research paper “Ultra High Efficiency Bidirectional DC-DC Converter with Multi-Frequency Pulse

Width Modulation”, use of a high speed programmable device was compulsory.

The PIC microcontroller chip adjusts the duty cycle of the high and low side outputs to the Gate

drive Circuit achieving the 186.6VDC output. The 186.6VDC output voltage is monitored by PIC

using LM324 opamp, sensing output voltage through the optoisolator IC. The Optoisolator

provides isolation from the output and the input circuits. The voltage divider circuit consisting of

resistors is used to set the desired value of 5V for optoisolator. The differential isolated voltage is

amplified using LM324 and is fed to ADC of PIC. Zener diode is placed for protection against

voltage > 5V.

The PIC controller also monitors the input current to the DC/DC converter. This is done through

sensing the differential voltage developed across the RSENSE, which is calculated to give a minimum

power dissipation of less than 2W. This voltage is again fed into PIC through differential amplifier.
 4 8

I N V E R T E R

Figure 3-20 Control Circuitry for DC-DC FB Converter

The Schottky diodes will prevent ringing below ground; these are connected to the output pins

(portb.7-portb.4). The Schottky diodes will also damp any parasitic inductive kicks from the gates

of the MOSFETS.

The next part of the controls circuit is the gate driver circuit. For details on gate drive circuit

development, refer to section 3.4.

3.6.6 TEST PROCEDURES

1. ORCAD Simulation

2. Transformer Design and testing

3. Control Circuit operation testing

3.1. Microcontroller PWM variation

3.2. Gate Drive operation

3.3. Mosfet Switching test

4. Complete operational tests

 4 9

I N V E R T E R

3.6.7 SIMULATION RESULTS

Table 3-7 summarizes the simulation results of DC-DC Converter module. It can be seen that the

converter depicted stabilized operation using designed gate drive.

Table 3-7 Simulated Circuit and Results

Schematic of
FB DC-DC
converter that
was simulated
and tested.

The diagram
shows the
transience
response of the
system and it
was noted that
the circuit
stabilized in
nearly 80us to
nominal
voltage.
 5 0

I N V E R T E R

D=2/5

F=200Khz

Vo, RMS = 192V

Vo, RIPPLE = 13V

RIPPLE=6.7%

3.6.8 PROTOTYPE IMPLEMENTATION

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I N V E R T E R

3.7 DC-DC CONVERTER – III

The design procedure of this converter was very similar to the previous one; hence the details are

omitted due to report length restriction. The design requirements are presented here while the

calculations are attached in appendix for review. The implementation of this stage is beyond the

scope of FYP. Since DC-DC converter IV has been implemented successfully, this module is

implementable given sufficient time.

Goals: The AEPS requires a 2.1kW DC/DC converter to provide power to the inverter and

ultimately to the load.

Objectives and design requirements: Design requirements are as follows:

1. Cost efficient DC/DC converter

2. Design product with minimum Mean Time To Failure rate of approximately 10 years

3. 2.1kW nominal power output with 90% efficiency

4. 93.3V DC output with varying 36 +/-10% VDC input

5. Output voltage tolerance within +/-2.5% (+/-2.3325V)

6. Output ripple voltage less than 1 percent

7. High frequency transformer to minimize power loss

8. Control circuit to maintain consistent output

9. Cooling solutions: Heat sinks and Cooling Fans

10. Circuit protection devices to limit current

Constraints: The defined input voltage will vary between 32.4 and 39.6 VDC and the

permissible output voltage will be ± 2.5 percent of the stated regulated voltage of 93.3V

DC. The DC/DC converter will be required to provide 2.1kW of power with a DC output

voltage between 90.9-95.63V.

 5 2

I N V E R T E R

3.8 DC-DC CONVERTER -II AND -I

The implementation of these two modules is beyond the scope of our FYP, due to insufficient

time, although study on its implementation has been conducted.

Goals: The AEPS requires 650W and 325W DC/DC converters to provide power to the inverter.

Objectives: Design requirements are depicted in table 3-8.

Table 3-8 Design Requirements of DC-DC converter II and I

Parameters DC-DC –II DC-DC –I

power output 650W 325W

Output 26.6V DC +/-2.5% 13.3VDC +/- 2.5%

Input 42 +/-10% VDC 42 +/- 10% VDC

Output voltage tolerance +/-2.5% +/-2.5%

efficiency 90% 90%

Output ripple voltage less than 1 percent less than 1 percent

Implementation: Since the power requirements of these two converters are below 1KW,

other dc-dc converter strategies like Push-Pull Configuration, Fly-Back Converter, Buck-

Boost or CUK’ converter can be used to implement the module. However, the efficiency

requirement will be difficult to be met with transformer less topology. Moreover, high

frequency transformer conversion is required to provide isolated power output to inverter.

3.9 VARIOUS SIMULATED DC-DC CONVERTER

DESIGNS
The selection of Full bridge DC-DC converter was made after a lot of research on all other possibilities.

Many of the converter strategies like Buck, Boost, CUK, Lu converter, Push-Pull were simulated to estimate

their efficiencies and technical requirements. Some of the results are shown in Table 3-9.
 5 3

I N V E R T E R

Boost Converter
Simulation:

Boost converter output

Boost Converter was
simulated to provide 96VDC
to inverter. However the
efficiency of the design
appeared nearly 60-70% after
a lot of research in design
values. Thus Boost converter
implementation was not the
choice for DC-DC converter
III and IV modules

Buck Converter Simulation

for 13VDC voltage source.
The simulation after
maximum tweaking of
parameter gave nearly 75
percent efficiency in design,
which was not acceptable
according to our design goal
of 90% efficiency
 5 4

4
C H A R G E C O N T R O L L E R
Chapter

4 CHARGE
CONTROLLER DESIGN
In this chapter we will discuss the charge controller and the battery bank design
according to the requirements of AEPS

T
he charge controller design according to the AEPS architecture is primarily divided into 2

portions, battery bank selection and Charge controller design in accordance. These

portions are described in detail in the following portion.

4.1.1 BATTERY BANK SELECTION

The battery bank needed to be selected in such a way that a single charge controller is sufficient

enough to deal with the bank. The DC-DC converters to provide the inverter with different voltage

levels are to take the DC voltage either from the battery bank or from the converter at the input of

the charge controller. In this way the charger and the DC converters along with inverter are

connected in parallel.

We are using 12v, 200Ahr batteries to ensure a longer backup time. We cannot use a large

combination of series connected batteries as:

1. UC3906 can work for input voltage less than 45v, so the bank voltage with batteries in

series should also be less than 45v

2. More series connected batteries increases the minimum requirement of batteries to be used

for the proper working of the system i.e. if we connect 5 batteries in series then we always

require at least 5 batteries to make the system work, and to increase the backup time we

would have to add 5 more batteries, no less is useful.

Large number of batteries in parallel increases the amount of current in the system, thereby

increasing the power losses. Hence, we have to select battery bank in such a way so as to minimize
 5 5

C H A R G E C O N T R O L L E R

power losses as well as the number of batteries required by the system for its performance. We

have proposed the following design after optimizing the power losses and the battery requirement.

Figure 4-1 : 36V 800A Battery bank

The proposed design meets all the requirements:

1. It provides a maximum backup time of 9 hrs.

2. UC3906 can charge this bank easily.

3. The system needs three batteries to start performing

4. Backup time can be increased just by adding three more batteries.

4.1.2 CHARGE CONTROLLER

The charging of batteries is always an issue of debate when we are talking about the usage of

batteries in any power backup or alternate energy systems. Batteries must be charged in such a way

that minimum of the system power is lost while they are charging and the charging time also

needed to be as small as possible. Furthermore, overcharging the batteries and letting them to be

discharged below a particular point (DOD (Depth of Discharge) point) also decreases the battery

life.
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C H A R G E C O N T R O L L E R

To overcome all of these problems, and for increasing the efficiency of the system, the need of a

charge controller is evident. A charge controller, also known as charge regulator or battery regulator

limits the rate at which electric current is added to or drawn from electric batteries. It prevents

overcharging and may prevent against over voltage, which can reduce battery performance or

lifespan, and may pose a safety risk. It may also prevent completely draining ("deep discharging") a

battery, or perform controlled discharges, depending on the battery technology, to protect battery

life. The accepted design will provide this output with the least amount of total losses. The design is

to be tested with batteries of different ratings for the verification that it meets all the needs.

4.1.3 GOALS

Alternate Energy Systems comprise of batteries for increasing the backup time, in the absence of

the sources of power (wind & solar energy). We are using 12v 200Ahr batteries connected in series

and parallel to provide the maximum backup time of 9hrs. The battery bank acts a unit of 36v

800Ahr battery.

We need to charge the 12v 800Ahr battery bank in minimum time without trading off for the

battery life for our 5kw system. The batteries can be charged by a current ranging from 15-40

Amps taking the charging time from 13 hr 20 min to a minimum of 5 hrs for one battery. The

battery life is reduced by over charging and also by discharging it below the DOD (Depth of

Discharge) point. We have connected the batteries in series, so the battery equalization also needed

to be maintained for a longer battery life.

4.1.4 OBJECTIVES

The primary objective for charge controller designing was to develop efficient charging mechanism

for the rated battery bank of 36V 800Ah, along with providing sufficient protection circuitry.

4.1.5 SALIENT FEATURES

1. Intelligent charging of the battery bank 
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C H A R G E C O N T R O L L E R

2. No PWM based charging required as the Charge Controller provides the appropriate 

analogue voltage to control the pass element. 

3. Reverse current protection 

4. Over charge protection 

5. Over discharge protection (Deep discharge) 

6. Temperature monitor and control of the battery bank 

7. Charge Equalization of series connected batteries. 

8. Voltage monitor of individual batteries in the bank. 

9. Charge status indication 

4.2 THE BATTERY BANK CHARGER

For charging the battery bank of 36V 800A, we need a charger that meets all the following design

requirements:

4.2.1 DESIGN REQUIREMENTS

1. Over charging of battery and prolonged charging rates significantly above C/500 will result

in dehydration, accelerated grid corrosion, and reduced service life.

2. At charge rates of >C/5, less than 80% of the cell’s previously discharged capacity will be

returned as the over-charge reaction begins. For over-charge to coincide with 100% return

of capacity, charge rates must typically be reduced to less than C/100.

3. To accept higher rates the battery voltage must be allowed to increase as over-charge is

approached. The over-charge reaction begins when the cell voltage rises sharply, and

becomes excessive when it levels out and starts down again.

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C H A R G E C O N T R O L L E R

4. The charger needs to provide the battery with the correct float charge level by applying a

constant voltage to it. This should be large enough to compensate for self-discharge

without degrading the battery from excessive overcharging.

5. With the proper float charge, sealed lead-acid batteries are expected to give standby service

for 6 to 10 years. Errors of just five percent in a float charger’s characteristics can halve this

expected life.

4.2.2 DESIGN OF 12V 7AMPS & 12V 12AMPS CHARGE

CONTROLLERS

Before design and implementation of the charge controller of the battery bank, we designed a low

power charge controller for 12v 7Ahrs & 12v 12Ahrs batteries to check the design and its pros and

cons.

We have used UC3906 designed as a dual level float charger. It starts charging the battery in bulk

charge mode, until it reaches the over charge voltage where charger decreases it current and over

charge the battery upto an extent while working in over charge mode. After the charging of

battery, it enters float charge mode to protect battery from low self discharge.

The state diagram of dual level float charger design is given in Appendix 6.5.

4.2.3 DESIGN & CALCULATIONS

The deign procedure in mentioned in Appendix 6.5.

CALCULATIONS

Overcharge Voltage, VOC = 14.7v

Float Voltage, VF = 13.9v

Trickle Bias Voltage, VT = 10v

Assuming divider current, ID = 85.185μA

Taking IMAX = 2.5A (charging current in bulk charging mode)

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C H A R G E C O N T R O L L E R

R c = 27kΩ

R sum = 136.17kΩ

RD = 391.5kΩ = [(1M II 560k) + 33k]Ω

Rx = 25.258kΩ

RA = 124.30kΩ = [(220k II 270k) + 3.3k]Ω

RB = 11.87kΩ = [(56k II 22k II 47k) + 56]Ω

Rs = 0.1Ω (Current sensing resistance) ; for 12Αh battery

RT = 100Ω (Trickle Bias resistance) ; for IT = 125mA (Trickle bias current)

V12 = 13.96v

V31 = 12.51v

IOCT = 250mA (Trickle bias current)

4.2.4 PROTOTYPE IMPLEMENTATION

Figure 4-2 : Snap of 12V 7A Dual Level Float Battery Charger

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C H A R G E C O N T R O L L E R

4.2.5 EXPERIMENTAL RESULTS

The prototype was monitored under different battery conditions to test its reliability. The

table 4-1, 4-2 and 4-3 show the observed charging curves for batteries with different initial

voltage conditions. All batteries used were 12V 7Ah.

Table 4-1: Test1: VIN = 17.8; VBATTERY = 9.7 initially

Time I(current)
1:10 0.23
12V 7A Battery Charger Test # 1 results
1:25 0.32
I(current)
0.35
1:45 0.25 0.3
0.25
2:10 0.20
Current

0.2
0.15
2:50 0.10
0.1
0.05
3:10 0.09
0
1:10 1:25 1:45 2:10 2:50 3:10
Time

Table 4-24: Test 2: VIN = 19.5V; VBATTERY = 10.59V

T(PST) I(A)
10:00 0.31
12V 7A Battery Charger Test # 2 results
10:25 0.45
I(A)
10:55 0.39 0.5

0.4
11:10 0.41
Current

0.3
12:00 0.26
0.2
1:55 0.37
0.1
2:55 0.29
0
3:30 0.09 10:00 10:25 10:55 11:10 12:00 1:55 2:55 3:30 6:50
Time
6:50 0.01
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C H A R G E C O N T R O L L E R

Table 4-3: Test 3: (faulty battery) VIN=19.5; VBATTERY=6.67

T(PST) I(A)

735 0.05
12V 7A Battery Charger Test # 3 results
745 0.1 I(A)
0.12
755 0.09 0.1
0.08

Current
830 0.05
0.06
0.04
1115 0.05
0.02
0
7:35 7:45 7:55 8:30 11:15
Time

4.2.6 DESIGN OF 36V 800 AMPS CHARGE

CONTROLLER

CHARGING LARGE SERIES STRINGS OF LEAD-ACID CELLS

When large series strings of batteries are to be charged, a dual step current charger has certain

advantages over the float charger. A state diagram of this type of charger with explanation is

given in Appendix 6.6.

CALCULATIONS FOR THE 36V 800AMP BATTERY BANK CHARGER:

The design procedure is given in Appendix 6.6.

Taking the charging current IMAX = 80A (Bulk charge Current)

Holding current IH = 0.0005C = 0.0005*800 = 0.4A

RSM = 3.125mΩ

RSH = 62.5mΩ

VREF = 2.3v (typical value taken from data sheet)

V12 = 41.4v

V21 = 34.5v (considering the discharge depth)

VF = 39.33v
 6 2

C H A R G E C O N T R O L L E R

RA = 103.4kΩ = (100k + 3.3k)Ω

RC = 6.5kΩ = (5k + 1.5k)Ω

RD = 56kΩ

RE = 90Ω (value selected so as to minimize the losses)

SELECTION OF PASS ELEMENT:

As we are charging the batteries with 80A current therefore the pass element we are using is

IRFP 2907. UC306 cannot drive the MOS pass element, so for that purpose we are using gate

drive.

4.2.7 SCHEMATIC

Figure 4-3: Schematic of 36V 800A Dual Step Current Charger

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C H A R G E C O N T R O L L E R

4.2.8 PROTOTYPE: 36V 7AMP

Figure 4-4: Battery Bank of 36V 7A for testing Prototype Charger

It is too expensive for us to purchase the battery bank proposed, so to test the charging of

batteries in series, we have used a prototype charger (36v 7A) with proto type battery bank (3

series connected batteries of 12v 7A). Its design calculations are given below:

Taking the charging current IMAX = 700mA (Bulk charge Current)

Holding current IH = 0.0005C = 0.0005*7 = 3.5mA

RSM = 3.125mΩ

RSH = 62.5mΩ

RE = 12.kΩ (value selected so that the losses are less 0.2 W)

Other design elements and values are similar to the 36v 800A bank charger.

Pass element is TIP 147 since bulk charge current is only 700mA.
 6 4

C H A R G E C O N T R O L L E R

4.3 CONTROLLING CIRCUITRY

4.3.1 CENTRAL CONTROLLING

A 500v 100A relay connects the battery bank terminals either to the charge controller input

during the charging time and to the inverter input terminals, to the DC-DC converters while

the batteries are discharging.

To control the timings of utilization of battery bank power backup, input and output powers

are monitored to determine the power requirements. A CT (current transformer) monitors the

input current from wind turbine and solar voltage and output voltage are directly viewed

continuously. When any power demand is observed for any reason, batteries are shifted to

discharge mode until deep discharge starts when relay switches back to charging mode, giving

a backup time of 5 hrs from batteries in worst case.

4.3.2 EQUAL VOLTAGE DISTRIBUTION ON SERIES

CONNECTED BATTERIES

A problem may arise in a series connected battery bank that during discharging the voltages of

batteries may differ from each other, specially the battery on top discharges more than the

other in series. When we charge the batteries, the difference in their voltage is still maintained

as all the batteries are charged with the same current, so rise in their voltages is also same.

To overcome this issue, we will continuously monitor the voltages of all batteries, connected

with each other through relays, and stop charging the bank if any difference in battery voltage

is observed. The battery with lower voltage will then be charged with a single battery charger

until its voltage matches the others’, then charging of bank is sustained. The single battery

charger is the one similar to our proto type of 12v 12A with RS = 12.5mΩ to enable it to be

used with 12v 200Ahr battery.

 6 5

C H A R G E C O N T R O L L E R

4.3.3 TEMPERATURE CONTROL CIRCUITRY

During charging the temperature of the batteries rise and if the battery reaches to a very high

temperature, normally of the range 45 – 55 oC, then the battery damages. We will continuously

monitor the temperature of the bank using NTC as a temperature sensor and LM 324 (quad

op amp) for signal conditioning, and if reaches the threshold after which damage occur, we

will stop the charging process.

Figure 4-5: schematic of Temperature Control Circuitry

4.3.4 VOLTAGE MONITORING CIRCUITRY

Voltage monitoring circuitry is quite simple as we have just use op amps to scale down

voltages to the level where PIC μ-C can take analog voltages. When the μ-C senses the lower

voltage than other batteries, it will stop the bank charging and charges the battery with lower

voltage.
 6 6

C H A R G E C O N T R O L L E R

Figure 4-6: Schematic of Voltage Monitoring Circuitry

4.3.5 CHARGE STATE INDICATION

3 LEDs red, blue and green indicate the bulk, overcharge and float charge states respectively

in Dual Level Float Charger, while red and blue LEDs indicate the bulk and holding charge

state in Dual Level Current Charger.

4.4 PROTECTION CIRCUITRY

4.4.1 OVER-DISCHARGE PROTECTION

We have connected the load to battery bank terminal through a relay which is switched off

when load is getting power from the hybrid supply. RC is connected to power indication pin

i.e. pin 7, whereas relay’s supply is connected to pin11 of UC3906 (as shown in figure 4-4).

When primary power is available Q2 is on via D5. The battery is charging, or charged, and the

trickle bias output at PIN 11 is off. When hybrid supply is unable to provide sufficient power

to load, Q2 is switched off while switching on the relay which connects the battery bank to

load. UC3906 will draw a very small current, typically less than 2mA, and continue monitoring
 6 7

C H A R G E C O N T R O L L E R

battery voltage. When battery bank reaches its depth of discharge DOD, pin 11 will go high,

switching on Q2 and turning off relay, thus providing over discharge protection.

4.4.2 REVERSE CURRENT PROTECTION

By using a diode in series with the pass element, and referencing the divider string to the

power indicate pin, pin 7(as shown in figure 4-4), reverse current into the charger, (when the

charger is tied to the battery with no input power), can be eliminated.

4.5 FUTURE AMENDMENTS

In future, we intend to use PIC 16F84a micro-controller instead of UC3906 as it gives us

more space to use a wider range of battery bank and input power as UC3906 cannot bear

input voltage higher than 45v. Due to which losses occur at pass element and at DC-Dc

converters contributing to the major losses of the system.

We intend to focus on using a more appropriate approach of charge equalization of series

connected batteries. The one we would like to use in future or recommend to anyone is

proposed by Yao-Ching Hsieh*, Kong-Soon Ng, Su-Ping Chou, and Chin-Sien Moo in their

research paper published in Journal of the Chinese Institute of Engineers, Vol. 31, No. 6, pp.

1083-1087 (2008).
 I

B I B L I O G R A P H Y & A P P E N D I X

5 BIBLIOGRAPHY
CHAPTER 1 OVERVIEW

[1] Power Electronics Handbook; Muhammad H. Rashid; chapter 24, 26 & 27

CHAPTER 2 INPUT BLOCK

[1] Family of multiport bidirectional DC–DC converters; H. Tao, A. Kotsopoulos, J.L. Duarte
and M.A.M. Hendrix

[2] Characteristics of the Multiple-Input DC–DC Converter; Hirofumi Matsuo, Fellow, IEEE,
Wenzhong Lin, Fujio Kurokawa, Senior Member, IEEE, Tetsuro Shigemizu, and Nobuya
Watanabe

CHAPTER 3.1 POWER INVERTER STAGE

[1] S. Khomfoi, L. M. Tolbert, "Multilevel Power Converters," Power Electronics

Handbook,2nd Edition Elsevier, 2007, ISBN 978-0-12-088479-7, Chapter 17, pp. 451-482.

[2] J. Rodriguez, J. S. Lai and F. Z. Peng, “Multilevel Inverters: Survey of Topologies,

Controls, and Applications,” IEEE Transactions on Industry Applications, vol. 49, no. 4,
Aug. 2002, pp. 724-738.

[3] E. Babaei , S.H. Hosseini , G.B. Gharehpetian , M. Tarafdar Haquea, M. Sabahi,

“Reduction of dc voltage sources and switches in asymmetrical multilevel converters using
a novel topology”

[4] Z. Du, “Active Harmonic Elimination in Multilevel Converters,” Ph.D. Dissertation, The
University of Tennessee, 2005, pp. 33-36.

[5] Power Electronics Handbook; Muhammad H. Rashid; chapter 17

3.2 HARMONIC ELIMINATION

[1] Harmonic Elimination for Multilevel Converter with Programmed PWM Method by
Zhong Du, Leon M. Tolbert, John N. Chiasson; The University of Tennessee, Department
of Electrical and Computer Engineering; Knoxville, Tennessee 37996-2100

[2] J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, Z. Du, “A Complete Solution to the

Harmonic Elimination Problem,” IEEE Transactions on Power Electronics, March 2004,
vol. 19, no. 2, pp. 491-499.

[3] J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, Z. Du, “Control of a Multilevel Converter

Using Resultant Theory,” IEEE Transactions on Control System Theory, vol. 11, no. 3,
May 2003, pp. 345-354.
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B I B L I O G R A P H Y & A P P E N D I X

[4] J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, Z. Du, “A New Approach to Solving the

Harmonic Elimination Equations for a Multilevel Converter,” IEEE Industry Applications
Society Annual Meeting, October 12-16, 2003, Salt Lake City, Utah, pp. 640-645.

3.4 GATE DRIVE REFERENCES

[1] Intl. Rectifiers © Application Note AN-937, Gate Drive Characteristics and Requirements
for HEXFET® Power MOSFET.

[2] Design and Application Guide for High Speed MOSFET Gate Drive Circuits by Laszlo
Balogh [http://focus.ti.com/lit/ml/slup169/slup169.pdf]

[3] Intl. Rectifiers © Application Note AN-978, HV Floating MOS-Gate Driver ICs Rev D

3.5 DC-DC CONVERTERS

[1] Power Electronics Handbook; Muhammad H. Rashid; chapter 13 & 14

[2] DC/DC Converter, Project Design Report, Design Team 7 by Dan Burger, Eric Dougan,
Joe Oberle and Sean Periyathamby under Faculty Advisor Dr. Iqbal Husain; Date
Submitted: November 21, 2003

[3] A Novel Topology for Photovoltaic Series Connected DC/DC Converter with High
Efficiency Under Wide Load Range by Jong Pil Lee, Byung Duk Min, Tae Jin Kim, Dong
Wook Yoo and *Byung Kuk Lee; Power Conversion & System for RES Group, Korea
Electrotechnology Research Institute, Changwon, Korea; *School of information and
Communication Engineering, Sungkyunkwan University

[4] Converter for Fuel Cell based UPS system; AALBORG UNIVERSITET, Institute of
Energy Technology, 7. Semester Article; Prepared by group 710, Fall 2006

[5] EWB DC-DC CONVERTER PROJECT; ECE 445 Senior Design Project (29 Apr 2007)
by Qian Liu, Joel Lau, Mark Wong, TA: Wayne Weaver; Project Team: 7

[6] Digital Signal Controller; Introduction to Switch Mode Power Supplies(SMPS); Microchip
webseminars

[7] Switching Power Supply Design; Third Edition by Abraham I. Pressman, Keith Billings,
Taylor Morey; Chapter 3
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6 APPENDIX
6.1 GATE DRIVE SIMULATION RESULTS

Gate Drive
Simulation

Gate Drive simulation

Results
Plot of input versus
output for mosfet gate
drive.
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MGD simulation
The gate drive worked
fine and gave sharp
outputs to high side
MOSFET’s with low
tr and tf. However,
the drive was not
functional at very high
frequencies(>300Khz)
due to parasitic
capacitive effects in
transister’s switching.
Although this design
can be further worked
to improve
performance even
above 300Khz.
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6.2 WIND TURBINE CHARACTERISTICS

This Permanent magnet Wind Generator features the following:

1. The wind turbine has a stable output power and safe running and is maintenance free.
2. Wind rotor never goes to over speed even encounter to variable wind speed and strong
gale.
3. Low wind speed start up, safe system.
4. Long acting anticorrosive treats, no corrosion in 15 year.

Use of rare earth permanent magnet materials

5. professional magnetic circuit design
6. easy to low-wind start
7. automatically adjust the facing wind direction
8. use of closed power transmission slip ring
9. cables are not enwind
10. careful anti-corrosion treatment
11. Stable operation, without special maintenance, long service life.
Test Results:

Load RPM Voltage Current Power

Currently under observation in Electrical labs on the 800W coupled AC generator and
Motor set. The data will be updated in the final report.
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6.3 Comparison between Solar Cell types

Crystalline Silicon Thin Film

Crystalline silicon panels are constructed by Thin film solar panels are made by placing thin
first putting a single slice of silicon through layers of semiconductor material onto various
a series of processing steps, creating one surfaces, usually on glass. The term thin film
solar cell. These cells are then assembled refers to the amount of semiconductor material
together in multiples to make a solar panel. used, which is thinner than the width of a
Crystalline silicon, also called wafer silicon, human hair. Contrary to popular belief, most
is the oldest and the most widely used thin film panels are not flexible. Thin film solar
material in commercial solar panels. panels offer the lowest manufacturing costs, and
are becoming more prevalent in the industry

6.3.1 Crystalline silicon Types

Monocrystalline Silicon Multicrystalline Silicon

Monocrystalline (single crystal) Multicrystalline (polycrystalline)

grown from a single, uniform crystal. Cut from multifaceted silicon crystals.
most efficient Most common
most expensive less expensive
Less efficient, though the
performance gap has begun to
close in recent years.

6.3.2 Thin film Types

Cadmium Telluride Amorphous Silicon Copper, Indium, Gallium,

(CdTe) Selenide
semiconductor compound Amorphous silicon is the non- CIGS is a compound semiconductor
formed from cadmium and crystalline form of silicon that can be deposited onto many
tellurium Can be deposited in thin layers onto a different materials. CIGS has only
Manufactured on glass. Most variety of surfaces recently become available for small
common type of thin film offers lower costs than traditional commercial applications
Most cost effective crystalline silicon
not as efficient as crystalline Less efficient at converting sunlight
silicon into electricity.
better performance at high
temperatures
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6.4 DUAL DC-DC CONVERTER SIMULATION

SCHEMATIC
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6.5 DUAL LEVEL FLOAT CHARGER

Explanation: Dual Level Float Charger

A. Input power turns on, battery charges at trickle current rate.

B. Battery voltage reaches VT enabling the driver and turning off the trickle bias output, battery

charges at lMAX rate.

C. Transition voltage V12 is reached and the charger indicates that it is now in the over-charge

state, state 2.

D. Battery voltage approaches the over-charge level VOC and the charge current begins to taper.

E. Charge current tapers to lOCT. The current sense amplifier output, in this case tied to the OC

TERMINATE input, goes high. The charger changes to the float state and holds the battery

voltage at VF.

F. Here a load (>lMAX) begins to discharge the battery.

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G. The load discharges the battery such that the battery voltage falls below V31. The charger is

now in state 1, again.

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6.6 DUAL STEP CURRENT CHARGER

Explanation: Dual Step Current Charger

A. Input power turns on, battery charges at a rate of IH + IMAX.

B. Battery voltage reaches V12 and the voltage loop switches to the lower level VF. The

battery is now fed with the holding current IH.

C. An external load starts to discharge the battery.

D. When VF is reached the charger will supply the full current IMAX + IH.

E. The discharge continues and the battery voltage reaches V21 causing the charger to switch

back to state 1.

DESIGN CRITERIA: