MODULE 3 : CENTRAL PROCESSING UNIT

3.1 CENTRAL PROCESSING UNIT

1. Stack Organization
 A stack is a storage device that stores information in such a manner that the item stored last is
the first item retrieved.
 The stack in digital computers is essentially a memory unit with an address register that can
count only. The register that holds the address for the stack is called a stack pointer (SP)
because its value always points at the top item in the stack.
 The physical registers of a stack are always available for reading or writing. It is the content
of the word that is inserted or deleted.

Register Stack

Fig: Block Diagram of a 64-word stack

 A stack can be placed in a portion of a large memory or it can be organized as a collection of

a finite number of memory words or registers.
 The stack pointer register (SP) contains a binary number whose value is equal to the address
of the word that is currently on top of the stack.
 To remove the top item, the stack is popped by reading the memory word and decrementing
the content of SP.
 To insert a new item, the stack is pushed by incrementing SP and writing a word in the next-
higher location in the stack.
 The one-bit register FULL is set to 1 when the stack is full, and the one-bit register EMTY is
set to 1 when the stack is empty of items.
 DR is the data register that holds the binary data to be written into or read out of the stack.

PUSH
 If the stack is not full (FULL = 0), a new item is inserted with a push operation. The push
operation consists of the following sequences of microoperations:
SP  SP + 1 Increment stack pointer
M[SP]  DR Write item on top of the stack
IF (SP = 0) THEN (FULL  1) Check if stack is full
EMPY  0 Mark the stack not emptyl

POP
 A new item is deleted from the stack if the stack is not empty (if EMTY = 0). The pop
operation consists of the following sequences of microoperations:
DR  M[SP] Read item on top of the stack
SP  SP – 1 Decrement stack pointer
IF (SP = 0) THEN (EMTY  1) Check if stack is empty
FULL  0 Mark the stack not full

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Memory Stack

Fig: Computer memory with program, data and stack Block Diagram of a 64-word stack

 The implementation of a stack in the CPU is done by assigning a portion of memory to a

stack operation and using a processor register as a stack pointer.
 The program counter PC points at the address of the next instruction in the program which is
used during the fetch phase to read an instruction.
 The address register AR points at an array of data which is used during the execute phase to
read an operand.
 The stack pointer SP points at the top of the stack which is used to push or pop items into or
from the stack.
 The three registers are connected to a common address bus, and either one can provide an
address for memory.

Reverse Polish Notation

A+B Infix Notation

+AB Prefix or Polish Notation
AB+ postfix or Reverse Polish Notation

 The postfix notation, referred to as reverse Polish Notation (RPN), places the operator after
the operands.
 The RPN is in a form suitable for stack manipulation.
The expression: A*B+C*D
Is written in RPN as: AB*CD*+
 The conversion from infix notation to RPN must take into consideration the operational
hierarchy adopted for infix notation.
This hierarchy dictates that we first perform all arithmetic inside inner parentheses,
then inside outer parentheses, and do multiplication and division operations before addition
and subtraction operations.
 Evaluation of Arithmetic Expressions
(3 * 4) + (5 * 6)  3 4 * 5 6 * +

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2. Instruction Formats
 A computer has a variety of instruction code formats. It is the function of the control unit
within the CPU to interpret each instruction code and provide the necessary control functions
needed to process the instruction.
 The instruction is divided into fields. The most common fields are:
o An operation code field that specifies the operation to be performed.
o An address field that designates a memory address or a processor register.
o A mode field that specifies the way the operand or the effective address is
determined.
 There are five types of instruction formats: Three-address instructions, two-address
instructions, One-address instructions, Zero address instructions and RISC instructions.
 Consider the expression:
X = (A + B) * (C + D)
Assembly language program for this expression will be explained using the different
instruction formats.

 Three Address Instructions

o Computers with three-address instruction formats can use each address field to
specify either a processor register or a memory operand.
o Program
ADD R1, A, B R1  M[A] + M[B]
ADD R2, C, D R2  M[C] + M[D]
MUL X, R1, R2 M[X]  R1 * R2

o The advantage of three-address format is that it results in short programs when

evaluating arithmetic expressions.
o The disadvantage is that the binary-coded instructions require too many bits to
specify there addresses.

 Two Address Instructions

o Two-address instructions are the most common in commercial computers. Here again
each address field can specify either a processor register or a memory word.
o Program
MOV R1, A R1  M[A]
ADD R1, B R1  R1 + M[B]
MOV R2, C R2  M[C]
ADD R2, D R2  R2 + M[D]
MUL R1, R2 R1  R1 * R2
MOV X, R1 M[X]  R1

o The MOV instruction moves or transfers the operands to and from memory and
processor registers. The first symbol listed in an instruction is assumed to be both a
source and the destination where the result of the operation is transferred.

 One Address Instructions

o One-address instructions use an implied accumulator (AC) register for all data
manipulation. For multiplication and division there is a need for a second register.
o Program
LOAD A AC  M[A]
ADD B AC  AC + M[B]
STORE T M[T]  AC
LOAD C AC  M[C]
ADD D AC  AC + M[D]

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MUL T AC  AC * M[T]
STORE X M[X]  AC

o All the operations are done between the AC register and a memory operand. T is the
address of the temporary memory location required for storing the intermediate result.

 Zero Address Instructions

o A stack-organized computer does not use an address field for the instructions ADD
and MUL. The PUSH and POP instructions, however, need an address field to
specify the operand that communicates with the stack.
o Program
PUSH A TOS  A
PUSH B TOS  B
ADD TOS  (A + B)
PUSH C TOS  C
PUSH D TOS  D
ADD TOS  (C + D)
MUL TOS  (C + D) * (A + B)
POP X M[X]  TOS

o To evaluate arithmetic expressions in a stack computer, it is necessary to convert the

expression into Reverse Polish Notation (RPN).

 RISC Instructions
o All other instructions executed within the registers of the CPU without referring to
memory. A program for a RISC type CPU consists of LOAD and STORE
instructions that have one memory and one register address.
o Program
LOAD R1, A R1  M[A]
LOAD R2, B R2  M[B]
LOAD R3, C R3  M[C]
LOAD R4, D R4  M[D]
ADD R1, R1, R2 R1  R1 + R2
ADD R3, R3, R4 R3  R3 + R4
MUL R1, R1, R3 R1  R1 * R3
STORE X,R1 M[X]  R1

o The load instructions transfer the operands from memory to CPU register.
o Add and Multiply operations are executed with data in the registers without accessing
memory.
o The result of the computations is then stored in memory with a store instruction.

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3. Addressing Modes
The operation field of an instruction specifies the operation to be performed. This operation will
be executed on some data which is stored in computer registers or the main memory. The way any
operand is selected during the program execution is dependent on the addressing mode of the
instruction. The purpose of using addressing modes is as follows:
1. To give the programming versatility to the user.
2. To reduce the number of bits in addressing field of instruction.

Types of Addressing Modes

 Immediate Mode
In this mode, the operand is specified in the instruction itself. An immediate mode instruction has
an operand field rather than the address field.
For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand here.

 Register Mode
In this mode the operand is stored in the register and this register is present in CPU. The
instruction has the address of the Register where the operand is stored.

Advantages
 Shorter instructions and faster instruction fetch.
 Faster memory access to the operand(s)
Disadvantages
 Very limited address space
 Using multiple registers helps performance but it complicates the instructions.

 Register Indirect Mode

In this mode, the instruction specifies the register whose contents give us the address of operand
which is in memory. Thus, the register contains the address of operand rather than the operand
itself.

 Auto Increment/Decrement Mode

In this the register is incremented or decremented after or before its value is used.

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 Direct Addressing Mode

In this mode, effective address of operand is present in instruction itself.
 Single memory reference to access data.
 No additional calculations to find the effective address of the operand.

For Example: ADD R1, 4000 - In this the 4000 is effective address of operand.
NOTE: Effective Address is the location where operand is present.

 Indirect Addressing Mode

In this, the address field of instruction gives the address where the effective address is stored in
memory. This slows down the execution, as this includes multiple memory lookups to find the
operand.

 Displacement Addressing Mode / Indexed Addressing Mode

In this the contents of the indexed register is added to the Address part of the instruction, to obtain
the effective address of operand.
EA = A + (R), In this the address field holds two values, A(which is the base value) and R(that
holds the displacement), or vice versa.

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 Relative Addressing Mode

It is a version of Displacement addressing mode.
In this the contents of PC(Program Counter) is added to address part of instruction to obtain the
effective address.
EA = A + (PC), where EA is effective address and PC is program counter.
The operand is A cells away from the current cell (the one pointed to by PC)

 Base Register Addressing Mode

It is again a version of Displacement addressing mode. This can be defined as EA = A + (R),
where A is displacement and R holds pointer to base address.

 Stack Addressing Mode

In this mode, operand is at the top of the stack. For example: ADD, this instruction will POP top
two items from the stack, add them, and will then PUSH the result to the top of the stack.

Numerical
An instruction is stored at location 300 with its address field at location 301.The addresses field has the value
400.A processor register R1 contains the number 200.Evaluate the effective address if the addressing mode of
the instruction is
(a) Direct
(b) Immediate
(c) Relative
(d) Register indirect
(e) Index with R1 as the index register

Solution:
The description given in the question can be represented like:
Location Contents Remarks
300 Opcode The instruction operation code
301 400 Address field of the above instruction

(a) Direct Addressing

Direct addressing means that the address field contains the address of memory location at which the instruction is
supposed to work with i.e. where the operand is.
Therefore, Effective Address = 400

(b) Immediate Addressing

Immediate addressing means that the address field contains the operand itself.
Therefore, Effective Address = 301

(c) Relative Address

Relative addressing means that the address field contains offset to be added to the program counter to address a
memory location of the operand.
Therefore, Effective Address = 301 + 400 = 701

(d) Register Indirect Address

Register indirect addressing means that the address of an operand is in the register. The address field in this case
contains just another operand.
Therefore, Effective Address (be in R1) = 200

(e) Index Addressing

In Index addressing mode, the effective address is calculated by taking the contents of the address field and adding
the contents of the index register.
Therefore, Effective Address = 400 + r1 = 400 + 200 = 600

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4. Data Transfer and Manipulation

Computers provide an extensive set of instructions to give the user the flexibility to carry out
various computational tasks. Most computer instructions can be classified into three categories:
i. Data transfer instructions
ii. Data manipulation instructions
iii. Program control instructions

Data Transfer Instructions

 Data transfer instructions move data from one place in the computer to another without
changing the data content.
 The most common transfers are between memory and processor registers, between processor
registers and input or output, and between the processor registers themselves.

NAME MNEMONICS
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

1. The load instruction has been used mostly to designate a transfer from memory to a processor
register, usually an accumulator.
2. The store instruction designates a transfer from a processor register into memory.
3. The move instruction has been used in computers with multiple CPU registers to designate a
transfer from one register to another. It has also been used for data transfers between CPU
registers and memory or between two memory words.
4. The exchange instruction swaps information between two registers or a register and a
memory word.
5. The input and output instructions transfer data among processor registers and input or output
terminals.
6. The push and pop instructions transfer data between processor registers and a memory stack.

Data Manipulation Instructions

 Arithmetic Instructions

NAME MNEMONICS
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with carry ADDC
Subtract with borrow SUBB
Negate (2’s complement) NEG

1. The increment instruction adds 1 to the value stored in a register or memory word.
2. The decrement instruction subtracts 1 from a value stored in a register or memory word.
3. The add, subtract, multiply and divide are binary instructions.
4. The instruction add with carry performs the addition on two operands plus the value of the
carry from the previous computation.

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5. The subtract with borrow instruction subtracts two words and a borrow which may have
resulted from a previous subtract operation.
6. The negate instruction forms the 2’s complement of a number, effectively reversing the sign
of an integer when represented in the signed-2’s complement form.

 Logical and Bit manipulation instructions

NAME MNEMONICS
Clear CLR
Complement COM
AND AND
OR OR
Exclusive-OR XOR
Clear carry CLRC
Set carry SETC
Complement carry COMC
Enable interrupt EI
Disable interrupt DI

1. The clear instruction causes the specified operand to be replaced by 0’s.

2. The complement instruction produces the 1’s complement by inverting all the bits of the
operand.
3. The AND, OR and XOR instructions produce the corresponding logical operations on
individual bits of the operands.

 Shift instructions

NAME MNEMONICS
Logical shift right SHR
Logical shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate right through carry RORC
Rotate left through carry ROLC

1. The logical shift inserts 0 to the end bit position. The end position is the leftmost bit for shift
right and rightmost bit position for the shift left.
2. Arithmetic shifts usually conform to the rules for signed 2’s complement.
3. The rotate instructions produce a circular shift.
4. The rotate through carry instruction treats a carry bit as an extension of the register whose
word is being rotated. Thus a rotate-left through carry instruction transfers the carry bit into
the rightmost bit position of the register, transfers the leftmost bit position into the carry and
at the same time, and shifts the entire register to the left.

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5. Program Control
Status Register Bits
 It is sometimes convenient to supplement the ALU circuit in the CPU with a status register
where status bit conditions be stored for further analysis. Status bits are also called condition-
code bits or flag bits.

Fig: Status Register Bits

 In the given circuit, the four status bits are symbolized by C, S, Z, and V. the bits are set or
cleared as a result of an operation performed in the ALU.
1. Bit C (Carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is 0.
2. Bit S (Sign) is set to 1 if the highest-order F7 is 1. It is set to 0 if the bit is 0.
3. Bit Z (Zero) is set to 1 if the output of the ALU contains all 0’s. It is cleared to 0
otherwise. In other words, Z = 1, if the output is zero and Z = 0, if the output is not
zero.
4. Bit V (Overflow) is set to 1 if the exclusive-OR of the last two carries is equal to 1,
and cleared to 0 otherwise. This is the condition for an overflow when negative
numbers are in 2’s complement.
 The status bits can be checked after an ALU operation to determine certain relationships that
exist between the values of A and B.
 If bit V is set after the addition of two signed numbers, it indicates an overflow condition.
 If Z is set after an exclusive-OR operation, it indicates that A = B.
 A single bit in A can be checked to determine if it is 0 or 1 by masking all bits except the bit
in question and then checking the Z status bit.

Program Interrupt
 The concept of program interrupt is used to handle a variety of problems that arise out of
normal program sequence.
 Program interrupt refers to the transfer of program control from a currently running program
to another service program as a result of an external or internal generated request. Control
returns to the original program after the service program is executed.
 After a program has been interrupted and the service routine been executed, the CPU must
return to exactly the same state that it was when the interrupt occurred.
Only if this happens will the interrupted program be able to resume exactly as if
nothing had happened.
 The state of the CPU at the end of the execute cycle ( when the interrupt is recognized) is
determined from:
1. The content of the program counter
2. The content of all processor registers
3. The content of certain status conditions

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 The interrupt facility allows the running program to proceed until the input or output device
sets its ready flag. Whenever a flag is set to 1, the computer completes the execution of the
instruction in progress and then acknowledges the interrupt.
The result of this action is that the return address is stored in location 0. The
instruction in location 1 is then performed; this initiates a service routine for the input or
output transfer.

 The service routine must have instructions to perform the following tasks:
1. Save the contents of processor registers
2. Check which flag is set
3. Service the device whose flag is set
4. Restore contents of processor registers
5. Turn the interrupt facility On
6. Return to the running program

 Types of Interrupts
1. External interrupts
 External interrupts come from input-output (I/O) devices, from a timing device, from
a circuit monitoring the power supply, or from any other external source.
 Examples that cause external interrupts are I/O device requesting transfer of data, I/O
device finished transfer of data, elapsed time of an event, or power failure. Timeout
interrupt may result from a program that is in an endless loop and thus exceeded its
time allocation.
 Power failure interrupt may have as its service routine a program that transfers the
complete state of the CPU into a non-destructive memory in the few milliseconds
before power ceases.
 External interrupts are synchronous. External interrupts depend on external
conditions that are independent of the program being executed at the time.

2. Internal interrupts
 Internal interrupts arise from illegal or erroneous use of an instruction or data.
Internal interrupts are also called traps.
 Examples of interrupts caused by internal error conditions are register overflow,
attempt to divide by zero, an invalid operation code, stack overflow, and protection
violation. These error conditions usually occur as a result of a premature termination
of the instruction execution. The service program that processes the internal interrupt
determines the corrective measure to be taken.

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 Internal interrupts are synchronous with the program. If the program is rerun, the
internal interrupt will occur in the same place each time.

3. Software interrupts
 A software interrupt is a special call instruction that behaves like an interrupt rather
than a subroutine call. It can be used by the programmer to initiate an interrupt
procedure at any desired point in the program.
 The most common use of software interrupt is associated with a supervisor call
instruction. This instruction provides means for switching from a CPU user mode to
the supervisor mode. Certain operations in the computer may be assigned to the
supervisor mode only, as for example, a complex input or output transfer procedure.
A program written by a user must run in the user mode.
 When an input or output transfer is required, the supervisor mode is requested by
means of a supervisor call instruction. This instruction causes a software interrupt that
stores the old CPU state and brings in a new PSW that belongs to the supervisor
mode.
 The calling program must pass information to the operating system in order to specify
the particular task requested.

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6. CISC & RISC

 Reduced Set Instruction Set Architecture (RISC) –
The main idea behind is to make hardware simpler by using an instruction set composed of a few
basic steps for loading, evaluating and storing operations just like a load command will load data,
store command will store the data.

 Complex Instruction Set Architecture (CISC) –

The main idea is to make hardware complex as a single instruction will do all loading, evaluating
and storing operations just like a multiplication command will do stuff like loading data,
evaluating and storing it.

 Both approaches try to increase the CPU performance

1. RISC: Reduce the cycles per instruction at the cost of the number of instructions per
program.
2. CISC: The CISC approach attempts to minimize the number of instructions per
program but at the cost of increase in number of cycles per instruction.

Earlier when programming was done using assembly language, a need was felt to make
instruction do more task because programming in assembly was tedious and error prone due
to which CISC architecture evolved but with uprise of high level language dependency on
assembly reduced RISC architecture prevailed.

Characteristic of RISC –
1. Simpler instruction, hence simple instruction decoding.
2. Instruction come under size of one word.
3. Instruction take single clock cycle to get executed.
4. More number of general purpose register.
5. Simple Addressing Modes.
6. Less Data types.
7. Pipeling can be achieved.

Characteristic of CISC –
1. Complex instruction, hence complex instruction decoding.
2. Instruction are larger than one word size.
3. Instruction may take more than single clock cycle to get executed.
4. Less number of general purpose register as operation get performed in memory itself.
5. Complex Addressing Modes.
6. More Data types.

Example – Suppose we have to add two 8-bit number:

 CISC approach: There will be a single command or instruction for this like ADD
which will perform the task.
 RISC approach: Here programmer will write first load command to load data in
registers then it will use suitable operator and then it will store result in desired
location.
So, add operation is divided into parts i.e. load, operate, store due to which RISC programs are
longer and require more memory to get stored but require less transistors due to less complex
command.

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Difference –
RISC CISC

Focus on software Focus on hardware

Transistors are used for storing complex

Transistors are used for more registers Instructions

Code size is large Code size is small

A instruction execute in single clock Instruction take more than one clock
cycle cycle

Instruction are larger than size of one

A instruction fit in one word word

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