IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO.

2, FEBRUARY 2007 131

A 0.8-V 0.25-mW Current-Mirror OTA With

160-MHz GBW in 0.18-m CMOS
Tsung-Hsien Lin, Member, IEEE, Chin-Kung Wu, and Ming-Chung Tsai

Abstract—A low-voltage low-power CMOS operational

transconductance amplifier (OTA) with near rail-to-rail output
swing is presented in this brief. The proposed circuit is based
on the current-mirror OTA topology. In addition, several circuit
techniques are adopted to enhance the voltage gain. Simulated
from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB
dc gain and a gain–bandwidth product of 160 MHz while driving
a 2-pF load. The OTA is designed in a 0.18- m CMOS process.
The power consumption is 0.25 mW including the common-mode
feedback circuit.
Index Terms—Current mirror, gain–bandwidth product (GBW),
operational transconductance amplifier (OTA).

I. INTRODUCTION

PERATIONAL transconductance amplifiers (OTAs) are

O important building blocks for various analog circuits and
systems. Depending on system needs, an OTA must satisfy
many design requirements. As CMOS technologies evolves
well into the ultra-deep-submicrometer regime, the supply
voltage decreases and device characteristics deteriorate. These
conditions pose severe challenges in amplifier designs. For
example, the transistor intrinsic gain in deep-sub-
micrometer processes is typically low due to inferior device
output impedance. Cascoding transistors can raise the circuit
impedance and thereby boost the gain. However, this is at the
cost of reduced output swing, and such circuit becomes infea-
sible if the supply voltage is further decreased. Alternatively,
a cascade multistage amplifier is often used in low-voltage
operation. Although a multistage OTA is seemingly suitable
for low-voltage operation, it incurs higher power consumption.
This is attributed to increased numbers of amplifying stages and
the need of frequency compensation to ensure closed-loop sta-
bility [1]. To address this issue, this brief proposes a low-power
CMOS OTA that is capable of producing large output swing
under low supply voltage, while still achieving high gain and
wide bandwidth.
Manuscript received March 27, 2006; revised August 6, 2006. This work was
supported in part by the National Science Council under Grant NSC 95-2220-E-
002-014. This paper was recommended by Associate Editor A. M. Klumperink.
T.-H. Lin is with the Graduate Institute of Electronics Engineering and the
Department of Electrical Engineering, National Taiwan University (NTU),
Taiwan, R.O.C. (e-mail: thlin@cc.ee.ntu.edu.tw).
C.-K. Wu was with the Graduate Institute of Electronics Engineering, Na-
tional Taiwan University, Taiwan, R.O.C. He is now with Sitronix Technology
Corp., Taipei 114, Taiwan, R.O.C.
M.-C. Tsai is with the Graduate Institute of Electronics Engineering, National
Taiwan University, Taiwan, R.O.C.
Digital Object Identifier 10.1109/TCSII.2006.886465
1057-7130/$25.00 © 2007 IEEE
Fig. 1. Large-swing OTAs. (a) Two-stage OTA. (b) CMOTA.
This brief is organized as follows. In Section II, conventional
large-swing CMOS OTAs are described. In Section III, we will
introduce the proposed OTA. The detailed circuit analysis is dis-
cussed in Section IV. The circuit performance is next presented
in Section V, with conclusions given in Section VI.
II. LARGE-SWING OTA ARCHITECTURES
A. Two-Stage OTA
A single-stage cascode topology is not suitable for designing
a large-swing high-gain amplifier under low-voltage operation.
Instead, a two-stage topology, as illustrated in Fig. 1(a), is often
adopted to attain both the desired gain and output swing.
For a two-stage amplifier, the second stage is designed to en-
able a large output swing while the first stage contributes to the
total gain. A two-stage amplifier is stabilized by the compensa-
tion capacitors . A left-half-plane zero can be added to the
amplifier by connecting a resistor in series with the capacitor
to improve the frequency response [1].
To evaluate the power consumption of this amplifier, we con-
sider a desired gain-bandwidth product and load capac-
itance . Assuming all transistors have the same overdrive
voltage, , and the nondominant pole at the
output is at least three times of the , it can be shown that
the core current consumption of the two-stage OTA is [2]
(1)

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 132 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 2, FEBRUARY 2007

Fig. 2. Simplified current-shunt CMOTA.

Fig. 3. Current-shunt CMOTA with proposed current-reuse input stage.

From (1), it is readily seen that a significant portion of the cur-
rent is spent on driving the compensation capacitors.

B. CMOTA
Another large-swing amplifier topology that avoids the
compensation capacitors is the current-mirror OTA (CMOTA),
which is depicted in Fig. 1(b). Because of the low impedance
seen at the drain of the diode-connected transistor, , the
associated pole frequency of the first stage is fairly far and
has little effect on the amplifier phase margin and bandwidth.
Therefore, frequency compensation is not required. For the
same design conditions as the previous two-stage OTA, the
current consumed by a CMOTA can be expressed as [2]

(2) Fig. 4. Current-shunt CMOTA with current reuse and body inputs.

where is the size ratio between mirroring devices, and grades [4]. In addition, the nondominant pole frequency is low-
. Comparing with (1), eliminating the compensation ca- ered. This effect will be discussed in Section IV.
pacitors results in considerable power reduction. However, the
III. PROPOSED OTA ARCHITECTURE
major drawback of a CMOTA is its low voltage gain.
A. CMOTA With Current Reuse
C. Current-Shunt CMOTA
In Fig. 2, the currents flowing into ground can serve mul-
The voltage gain of a CMOTA can be improved by raising
tiple functions. In fact, it can be utilized as the second input stage
the circuit output impedance. In addition to cascoding transis-
of the OTA. As shown in Fig. 3, the two shunting current sources
tors, using longer channel devices or lowering the transistor bias
are replaced with the circuit encircled by the dotted line. Tran-
current also boosts the impedance. In [3], a circuit technique is
sistors form the second input pair, where provide
employed to lower the bias current of the output branch. As de-
necessary level shifting for low-voltage operation. The tail cur-
picted in Fig. 2, by shunting partial bias current ( , )
rent of the second input pair is to maintain the same level of
of the first stage to ground, less dc current is mirrored to the
current shunting as in Fig. 2. If the transconductance is
output branches, while the ac signal current is unaffected. The
designed to be roughly equal to , the current-reuse tech-
output bias current is now . This method enhances
nique provides an additional 6-dB gain with small current in-
the output impedance, and hence the voltage gain, by
crease (two bias currents for level shifters).
times. The voltage gain of a current-shunt CMOTA is
formulated as B. Body Inputs
In Fig. 3, the body terminals of are connected to their
source nodes to avoid the body effect. Since a body terminal
can also behave as a second gate [5]–[7], we can apply the
level-shifted inputs (at nodes and ) to the body terminals
(3) of , as shown in the dashed lines of Fig. 4. Since the dc
voltages of nodes and are comparable to
and are the transistor output resistances, and the those of the node , the body-source junctions of will
and are the channel-length modulation coefficients not enter the forward-biased region. The body-drain transcon-
for transistors and . For a fixed current-mirror ductance of the pMOS transistors contributes to the
ratio , as increases, the gain improves but the slew rate de- overall and thereby increases the voltage gain.

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 LIN et al.: A 0.8-V 0.25-mW CMOTA 133

Fig. 5. Schematic of the proposed OTA.

The body terminals of can also serve as inputs, if a major parasitic poles are located at nodes and in Fig. 5. The
deep-Nwell process option is available. These body nodes are pole frequencies associated with these two nodes are
connected to and , as shown in the dotted lines of Fig. 4.
The dc levels of and are below , (6)
which are comparable to those of the source voltages of tran-
sistors . Hence, the body-source junctions of will (7)
not conduct.
and represent the total capacitance at nodes and ,
C. Overall Proposed OTA
respectively. These frequencies are typically designed to be at
The complete proposed current-mirror-based OTA is shown least three times the GBW frequency [10]. As approaches
in Fig. 5. With a push-pull output stage [8], [9], the voltage 1, the OTA achieves a higher gain. However, the transconduc-
gain is further increased (by roughly a factor of 2 in this work). tances of and ( and ) decrease, so are
This topology also makes the biasing of the output stage some- and , which degrades the frequency response. There-
what simpler. The common-mode feedback (CMFB) network fore, these design parameters must be selected with care.
consists of resistors , error amplifier cm , and transistors Compared with the current-shunt approach, the current-reuse
. Resistors are chosen to be large k to technique not only increases the effective input trans-conduc-
avoid degrading the OTA gain. The error amplifier also employs tance, but it may also be advantageous in lowering the parasitic
the current-shunt technique to enhance its voltage gain. capacitance at node . The reason is that the transistors
are usually designed with minimum channel length to maxi-
IV. CIRCUIT ANALYSIS mize the transconductance; while in the case of current sources
, longer channel length is typically required to minimize the
A. Voltage Gain and GBW channel-length modulation effect.
The total voltage gain of the proposed OTA of Fig. 5
can be expressed as
B. Noise Analysis

The input-referred noise of the proposed OTA also benefits

(4)
where represents the total input transconductance, and the
factor of 2 comes from the output stage. Compared with (3), a
considerable gain enhancement is obtained with only fractional
extra current. The GBW of the proposed OTA is expressed as
from the improved voltage gain. In the following noise analysis,
the noise contribution from the second stage is neglected for
simplicity (assuming the first-stage gain is sufficiently high).
For the current-shunt CMOTA, the input-referred white-noise
spectral density V Hz can be shown as
(8)

(5) where is the transconductance of the current-shunting

transistors. The input transistors usually dictate
To maintain the one-dominant-pole characteristic and avoid the noise performance. In the current-reuse topology, the cur-
frequency compensation, other parasitic poles should be ade- rent-shunting transistors are replaced with source followers
quately far away from the dominant pole at the OTA output. The (SFs) and . Again, neglecting the second-stage noise,

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 134 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 2, FEBRUARY 2007

the input-referred noise of the current-reuse CMOTA

can be simplified as

(9)
Fig. 6. Simplified transfer characteristic model of the proposed OTA.

where is the current-source transconductance of the SF.

The last term in the square bracket denotes the noise contribu-
tion from the SFs, which can be substantial if is small. A
proper selection of (at the cost of larger device and bias
current) can minimize their noise contribution. Furthermore,
since the first-stage transconductance of the current-reuse OTA
is increased to , the input-referred noise of the
current-reuse CMOTA can be lower than that of a current-shunt
CMOTA. In addition, if the second-stage noise is considered, the
proposed OTA has less second-stage noise contribution since it
has a higher first-stage gain.
Finally, as the inputs are applied to the body terminals in
the proposed OTA, the MOS devices channel noise remains the
same while the total transconductance of the OTA is further in-
creased. Additional noise introduced by the bulk series resis- Fig. 7. Open-loop gain and phase responses of the proposed OTA.
tance may be alleviated by careful layout with large number of
bulk contacts [6]. Ignoring the bulk resistor thermal noise, the
total input-referred noise of the proposed OTA is ex-
The significant PZP is the one from the first stage. Considering
pressed as
the PZP associated with the SFs and ignoring other nondomi-
nant poles and zeros, the frequency response of the proposed
OTA can be modeled as the one depicted in Fig. 6 for the fre-
(10) quency range of interests below the GBW.
In Fig. 6, is the dominant-pole frequency at the OTA
C. Additional Pole–Zero Pairs output. The level shifters add a PZP to the transfer function of
the proposed OTA. If the transconductance
Multiple signal paths from input to output introduce zeros to is designed roughly equal to , the additional
a circuit’s transfer function. In the input stage of the proposed PZP has frequencies close to that expressed in (11). This
OTA, the current-reuse technique incorporates level shifters to doublet degrades the circuit settling behavior, even though it
adjust the input dc level for . The transfer function of the only causes minor change to the OTA’s open-loop frequency
pMOS source follower consists of a pole–zero pair (PZP) and response [12]. Note that if the proposed OTA operates from a
can be approximated as [12] higher supply voltage (e.g., 1.2 V), the input common-mode
level can be raised and the level shifters for can be
where removed. In this case, the PZP and extra noise contribution are
eliminated, and the circuit settling time and noise performance
are both improved.
(11)

and are the gate–source capacitance and the total V. RESULTS

capacitance at the source node of transistors , respec-
tively. Since the bias currents of the SFs are usually designed
small to reduce the current consumption, the transconductance
of the SFs are also small. Hence, the pole/zero frequen-
cies can be quite low. The second stage also contributes a PZP,
where the pole frequency is shown in (7), and the left-half-plane
zero is found to be at
(12)
The proposed OTA is designed in the TSMC 0.18- m CMOS
technology with deep-Nwell process. The circuit can operate
from a 0.8-V supply voltage. In this design, is chosen to be
0.85 and is set to 3 according to previous analysis. The bias
current, , is 180 A. Each output branch current is 40 A, and
the current via is about 10 A. With a 2-pF load, the cir-
cuit achieves a 62-dB gain with a GBW of 160 MHz. The phase
margin is 67 . The proposed OTA is capable of achieving more
than 60-dB dc gain for an input common-mode (CM) ranging
from 140 to over 200 mV.

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 LIN et al.: A 0.8-V 0.25-mW CMOTA
Fig. 8. Step response settling behavior waveforms.
TABLE I
PERFORMANCE SUMMARIES OF THE PROPOSED OTA AND COMPARISON
WITH OTHER LOW-VOLTAGE OTA DESIGNS
The simulated open-loop gain and phase response is shown in
Fig. 7. The additional PZP contributed by the level shifters can
be observed in Fig. 7. To examine the effect of this doublet on
the circuit settling behavior, the OTA is configured as a closed-
loop unity-gain amplifier, and a 10-mV step is applied to the
amplifier input. Fig. 8 shows the simulated output waveforms.
Even though the unity-gain amplifier has a 3-dB frequency
over 160 MHz, the circuit still takes about 10.9 ns
to settle to within 1% accuracy. The settling time exceeds the
value of predicted by the simple linear
model [1] and shows the slow-settling behavior. To observe the
effect of the level shifters on the settling time, a comparison
is performed where the level shifters in the OTA are replaced
with ideal behavioral models (hence eliminating the PZP). The
simulated waveform is also plotted in Fig. 8. The 1% settling
time is reduced to 7.3 ns. These results indicate the PZP plays
an important role in the settling behavior [12].
The proposed OTA employs body-input topology which gives
rise to small input current through the reversed-biased junctions.
The leakage current in general rises with temperature. The sim-
ulated value is less than 10 pA under worst corner. The nonzero
input current results in an input resistance on the order of 10 G .
The effective input capacitance is estimated at about 0.4 pF. The
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135
simulated performance of the proposed circuit and comparison
with other low-voltage OTA designs is summarized in Table I.
These OTAs are designed for a variety of applications with dif-
ferent performance target. The proposed OTA design techniques
are suitable for a wide range or low-voltage, low-power analog
applications.
VI. CONCLUSION
A low-voltage low-power CMOS OTA is introduced in
this brief. The proposed circuit is based on the current-mirror
topology. To circumvent the low-gain problem of a CMOTA,
several design techniques are employed. First, the output
impedance is increased by reducing the bias currents of the
output branches, which is realized by shunting partial mirror
currents away. These shunt currents are then reused to realize
the second input stage. In addition, body terminals are uti-
lized as inputs to augment the transconductance. Finally, the
push-pull output stage further enhances the gain. The criteria
for determining the circuit bandwidth and gain parameters are
discussed. The noise and settling behavior of the proposed
circuit are also analyzed in this brief. It is identified that the
level shifter contributes considerable noise and adds a PZP to
the OTA transfer function, which prolongs the circuit settling
time. These level shifters are required for a low-voltage (0.8 V)
operation. In the case where supply voltage requirement is
relaxed, the level shifters can be eliminated. Thus, the noise and
settling behavior of the proposed OTA can be further improved.
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