Embedded Systems Module II: Communication Protocols

MODULE II

COMMUNICATION PROTOCOLS

A communications channel is classified as one of three types(depending on the direction of

transfer)
 Simplex
o Unidirectional communication
 Full Duplex
o Both devices or device and computer system simultaneously communicate each
other
 Half Duplex
o Only one device can communicate with another at an instance

Serial Communication

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Embedded Systems Module II: Communication Protocols

Parallel Communication

 Parallel transmission allows transfers of multiple data bits at the same time over
separate media

Bus Protocol

 A set of formal rules that describe how to exchange data

 Bus protocol refers to the set of rules agreed upon by both the bus master and bus
slave
o Synchronous bus transfers occur in relation to successive edges of a clock
o Asynchronous bus transfers bear no particular timing relationship
o Semisynchronous bus Operations/control initiate asynchronously, but data
transfer occurs synchronously

Serial Communication Parallel Communication

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Embedded Systems Module II: Communication Protocols

Serial Communication Standards and Devices

UART (Universal Asynchronous Receiver Transmitter) Protocol

In UART communication, two UARTs communicate directly with each other. The transmitting
UART converts parallel data from a controlling device like a CPU into serial form, transmits it in
serial to the receiving UART, which then converts the serial data back into parallel data for the
receiving device. Only two wires are needed to transmit data between two UARTs. Data flows
from the Tx pin of the transmitting UART to the Rx pin of the receiving UART.

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Embedded Systems Module II: Communication Protocols

UARTs transmit data asynchronously, which means there is no clock signal to synchronize the
output of bits from the transmitting UART to the sampling of bits by the receiving UART.
Instead of a clock signal, the transmitting UART inserts start and stop bits to the data packet
being transferred. These bits define the beginning and end of the data packet so the receiving
UART knows when to start reading the bits.

When the receiving UART detects a start bit, it starts to read the incoming bits at a
specific frequency known as the baud rate. Baud rate is a measure of the speed of data
transfer, expressed in bits per second (bps). Both UARTs must operate at about the same baud
rate.

The UART that is going to transmit data receives the data from a data bus. The data bus is used
to send data to the UART by another device like a CPU, memory, or microcontroller. Data is
transferred from the data bus to the transmitting UART in parallel form. After the transmitting
UART gets the parallel data from the data bus, it adds a start bit, a parity bit, and a stop bit,
creating the data packet. Next, the data packet is output serially, bit by bit at the Tx pin. The
receiving UART reads the data packet bit by bit at its Rx pin. The receiving UART then converts
the data back into parallel form and removes the start bit, parity bit, and stop bits. Finally, the
receiving UART transfers the data packet in parallel to the data bus on the receiving end:

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Embedded Systems Module II: Communication Protocols

UART transmitted data is organized into packets. Each packet contains 1 start bit, 5 to 9 data bits
(depending on the UART), an optional parity bit, and 1 or 2 stop bits.

START BIT

The UART data transmission line is normally held at a high voltage level when it’s
not transmitting data. To start the transfer of data, the transmitting UART pulls the transmission
line from high to low for one clock cycle. When the receiving UART detects the high to low
voltage transition, it begins reading the bits in the data frame at the frequency of the baud rate.

DATA FRAME

The data frame contains the actual data being transferred. It can be 5 bits up to 8 bits long if a
parity bit is used. If no parity bit is used, the data frame can be 9 bits long. In most cases, the data
is sent with the least significant bit first.

PARITY

The parity bit is a way for the receiving UART to tell if any data has changed during
transmission. Bits can be changed by electromagnetic radiation, mismatched baud rates, or long
distance data transfers. After the receiving UART reads the data frame, it counts the number of

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Embedded Systems Module II: Communication Protocols

bits with a value of 1 and checks if the total is an even or odd number. If the parity bit is a 0
(even parity), the 1 bits in the data frame should total to an even number. If the parity bit is a 1
(odd parity), the 1 bits in the data frame should total to an odd number. When the parity bit
matches the data, the UART knows that the transmission was free of errors. But if the parity bit
is a 0, and the total is odd; or the parity bit is a 1, and the total is even, the UART knows that bits
in the data frame have changed.

STOP BITS

To signal the end of the data packet, the sending UART drives the data transmission line from a
low voltage to a high voltage for at least two bit durations.

SPI (Serial Peripharal Interface) PROTOCOL

 Synchronous serial communication interface specification used for short distance

communication.
 Used by microcontrollers for communicating with one or more peripheral devices quickly
over short distances.
 Can also be used for communication between two microcontrollers.
 SPI devices communicate
 in full duplex mode
 using a master-slave architecture
 Only one master device (usually a microcontroller) which controls the peripheral devices.
 Multiple slave devices are supported through selection with individual slave select (SS)
lines.

The SPI bus specifies four logic signals

 Typically there are three lines common to all the devices
 SCLK -Serial Clock (output from master).
 MOSI -Master Output, Slave Input (output from master).
 MISO -Master Input, Slave Output (output from slave).
 SS -Slave Select (active low, output from master).one line specific for every device

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Embedded Systems Module II: Communication Protocols

Operation

 The master configures the clock.

 The master selects the slave device with a logic level 0 on the select line.
 During each SPI clock cycle, a full duplex data transmission occurs.
 The master sends a bit on the MOSI line and the slave reads it
 Simultaneously the slave sends a bit on the MISO line and the master reads it.
 This sequence is maintained even when only one-directional data transfer is intended.

If multiple slave devices exist, the master generates a separate slave select signal for
each slave.

HDLC (High Level Data Link Control) Bus Protocol

• Bit-oriented protocol.
• Developed by the ISO.
• Specifies packetization standard for serial links.
• Supports half-duplex and full-duplex communication lines

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Embedded Systems Module II: Communication Protocols

• Supports point-to-point and multi-point networks.

HDLC Stations
• Primary Station
• Controls all other stations on the link
• Primary station issues commands and secondary issues responses.
• Responsible for the organization of data flow and error recovery at the data link
level.
• Secondary Station
• Under the control of the primary station.
• No control over the link.
• Activated when requested by the primary station.
• It only responds to the primary station.
• Combined Station
• Combination of a primary and secondary station.
• All combined stations are able to send and receive commands and responses
without any permission from any other stations on the link.
• Each combined station is in full control of itself.
• No other stations can control any combined station.
• May issue both commands and responses.

HDLC Configurations

• Unbalanced Configuration
• Consists of a primary station and one or more secondary stations.
• The unbalanced condition arises because one station controls the other stations.
• In an unbalanced configuration, any of the following can be used:
• Full-Duplex or Half-Duplex operation
• Point to Point or Multi-point networks

• Balanced Configuration
• Consists of two or more combined stations.
• Each of the stations has equal and complimentary responsibility compared to each
other.
• Balanced configurations can use only the following:
• Full - Duplex or Half - Duplex operation
• Point to Point networks

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Embedded Systems Module II: Communication Protocols

• Symmetrical Configuration
• Consists of two independent point-to-point, unbalanced station configurations.
• In this configuration, each station has a primary and secondary status.
• Each station is logically considered as two stations.

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Embedded Systems Module II: Communication Protocols

HDLC Frame Structure

• HDLC uses synchronous transmission.

• All transmissions are in the form of frames
• The flag, address and control fields are known as header.
• The FCS and flag fields are referred to as trailer.

• Flag
– It identifies the beginning and end of the frame.
– unique 8 bit sequence.
• Address -Typically source or destination
• Control - Status or commands
• Info – not always present
• Flow Control
– Mechanism by which a slow receiver prevents it from being swamped with
transmission from a fast transmitter.
• CRC/FCS
– The Frame Checksum field is a minor variation on the cyclic redundancy
code.

• 3 types of control frames

• I – frame (Information frames)
• S – frame (Supervisory frames)
• U – frame (Unnumbered frames)

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Embedded Systems Module II: Communication Protocols

I2C (Inter Integrated Circuit) Bus Protocol

• Serial communication bus Invented by Philips in early 1980’s

• Consists of 2 active wires & ground connection
• Active wires:
• SDA (Serial DAta Line)
• SCL (Serial CLock Line)
• Both are bi-directional
• Data transfer rates up to 100 kbits/s and 7-bit addressing possible in normal mode
• 3.4 Mbits/s and 10-bit addressing in fast-mode
• Common devices capable of interfacing to I2C bus:
• EPROMS, Flash memory, real-time clocks, watchdog timers and microcontrollers
• I2C is a multi-master bus
• more than one device capable of controlling the bus can be connected to it
• Master-Slave and receiver-transmitter relationship are not permanent, but only
depend on direction of data transfer

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Embedded Systems Module II: Communication Protocols

• Each device hooked up to the bus has its own unique address (whether it is MCU, LCD
Driver, memory or ASIC)
• Each of these can act as receiver and /or transmitter
• Devices can be considered as masters or slaves

I2C Bus Events

START

• Generated by master
• Acts as a signal to all connected ICs that something is about to be transmitted. All
connected ICs will listen to the bus
• Bus is considered to be busy after Start condition
• A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition

STOP

• Generated by master
• Acts as a signal for all devices on the bus that the bus is available again
• Bus is considered to be idle after Stop condition
• A LOW to HIGH transition on the SDA line while SCL is HIGH indicates STOP
condition

The bus stays busy if a repeated START is generated instead of a STOP condition.

Transmission of data

If microcontroller A wants to send information to microcontroller B:

 microcontroller A (master), addresses microcontroller B (slave)

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Embedded Systems Module II: Communication Protocols

 microcontroller A (master-transmitter), sends data to microcontroller B (slave- receiver)

 microcontroller A terminates the transfer

If microcontroller A wants to receive information from microcontroller B:

 microcontroller A (master) addresses microcontroller B (slave)

 microcontroller A (master- receiver) receives data from microcontroller B (slave-
transmitter)
 microcontroller A terminates the transfer.

Here the master (microcontroller A) generates the timing and terminates the transfer.

CAN (Controlled Area Network) Bus

 It was created in mid-1980s for automotive applications by Robert Bosch.

 Design goal was to make automobiles more reliable, safer, and more fuel efficient.
 CAN (Controller Area Network) bus is a standard bus in distributed network
 It is mainly used in automotive electronics
 It is also used in medical electronics and industrial plant controllers
 The CAN bus network has a serial line which is bi-directional
 A CAN device using a CAN controller receives or sends a bit at any instance by
operating at a maximum rate of 1 Mbps
 It employs a twisted pair connection of 120 ohm line impedence at each controller node
 The pair can run upto a maximum length of 40 m
 CAN serial line is pulled to logic level 1 by a resistor between the line and the positive
supply voltage
 Line is at logic 1 in its idle state, also called the recessive state
 A node gets the input at any instance from the line after sensing that instant when the line
is pulled down to logic 0. This state is called the dominant state
 The node sends a bit to the line by pulling the line 0 by its driver for a bit period

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Embedded Systems Module II: Communication Protocols

CAN Networks

 A CAN network is made up of a group of “Nodes”

 Each node can communicate with any other node
 Communication is handled with extremely robust packet called “Messages”
 CAN is designed for data communication over a short distance.
 CAN protocol does not specify what medium to use for data communication.
 Using a shielded or unshielded cable is recommended for a short distance communication.
 A typical CAN bus setup using a cable is shown in Fig.

node node node node

1 2 3 n

CAN_H

RT
RT = 120 
(120 
CAN_L

A typical CAN bus setup using cable

Universal Serial Bus

Introduction

 Usb is a serial bus standard to connect devices to a host computer.

 Usb 1.0 specification was introduced in 1996.
 Usb was intended to replace the multitude of connectors at the back of PCs.
 To simplify software configuration of communication devices
 Powerful, versatile and simple communication interface
 Created by companies that consisted of intel, compaq, microsoft, digital, ibm and
northern telecom

Features

Serial Bus (4 Wire) Standard With A Maximum Range Of 5m

Supports 4 Data Rates:
 Low Speed (1.5 Mbps)
 Full Speed (12 Mbps)
 High Speed (480 Mbps)
 Super Speed (5 Gbps)

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Embedded Systems Module II: Communication Protocols

Uses A Tiered- Star Topology With Upto 127 Devices Connected To A Single Host
Controller.
Hot Swappable
 Plug ‘N’ Play
Usb Hub Enable Rapid And Seamless Port Expansion.
Capable Of Sourcing Upto 500 Ma Current At +5v.
Guaranteed Bandwidth And Low Latencies.
Eliminating The Need For External Power Supply
Attachment Is Detected And Device Is Configured Automatically.
Single Standard Connector.
Error Detection/ Recovery Is Automatic
Individual Usb Cables Can Run As Long As 5 Meters; With Hubs, Devices Can Be Upto
30 Meters Away From The Host
 Many Usb Devices Can Be Put To Sleep By The Host Computer When The Computer
Enters A Power Saving Mode.

INSIDE A USB CABLE:

 There Are Two Wires For Power- +5v (Red) And Ground (Brown)
 A Twisted Pair (Yellow And Blue) Of Wires To Carry Data.
 The Cable Is Also Shielded

USB PROCESS

 When the host powers up, it queries all of the devices connected to the bus and assigns
each one an address.this process is called enumeration.
 Devices are also enumerated when they connect to the bus.
 The host also finds out from each device what type of data transfer it wishes to perform
 When a usb device is first connected to a usb host, the usb device enumeration is started.
 The Enumeration Starts By Sending A Reset Signal To The Usb Device.
 The speed of the usb device is determined during the reset signaling.
 After reset, the usb device’s information is read by the host, then the device is assigned a
unique 7-bit address
 If the device is supported by the host, the device drivers needed for communicating with
the device are loaded and the device is set to a configured state

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 If the usb host is restarted, the communication process is repeated for all connected
devices. In the enumeration process, data structures (transfer descriptors) contain
information needed by the host to generate transactions.

This information includes:

 Usb device address
 Type of transfer
 Direction of transfer ( write or read )
 Transfer size(# of bytes)
 Speed
 Address of the device driver’s memory buffer

Parallel Communication Standards

ISA (Industry Standard Architecture) Bus

 ISA bus architecture was first introduced in IBM PC in 1981.
 Allows additional expansion cards to be connected to a computer’s mother board.
 ISA bus was designed to support the Intel 8088 microprocessor for IBM’s first-
generation PC.
 In the late 1990s the faster PCI bus was introduced and most IBM boards were designed
with PCI slots.
 ISA bus is now obsolete.
 The ISA bus allowed the computer to automatically detect and stup computer ISA
peripharals, such as modem or sound card.
 Two types of ISA bus – 8 bit ISA and 16 bit ISA
 Features -8 bit ISA
◦ 62 pins
◦ 8 data lines
◦ 20 address lines
◦ 6 interrupt request pins
◦ 3 DMA pins
◦ Speed upto 5MBps
 Features - 16 bit ISA
◦ 98 pins
◦ 16 data lines
◦ 20 address lines
◦ 11 interrupt request pins
◦ 7 DMA pins
◦ Speed upto 10MBps

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PCI Bus and PCI-X Bus

PCI(Peripheral Component Interconnect) bus is based on ISA (Industry Standard
Architecture) Bus and VL (VESA Local) Bus.
Introduced by Intel in 1992 .Revised twice into version 2.1 which is the 64bit standard that it
is today. Great feature of PCI Bus was that it was invented as an industry standard
PCI provides direct access to system memory for the devices that are connected to the bus
which is then connected through a bridge that connects to the front side bus.
This configuration allowed for higher performance without slowing down the processor
PCI is a synchronous bus architecture with all data transfers being performed relative to a
system clock (CLK).
PCI implements a 32-bit multiplexed Address and Data bus (AD[31:0]).
The multiplexed Address and Data bus allows a reduced pin count on the PCI connector that
enables lower cost and smaller package size for PCI components.
Data is transferred between an initiator which is the bus master, and a target which is the bus
slave.
PCI supports a rigorous auto configuration mechanism.
Each PCI device includes a set of configuration registers that allow identification of the type
of device and the company that produced it. Other registers allow configuration of the
device’s I/O addresses, memory addresses, interrupt levels, etc.
PCI bus architecture is processor independent.
PCI signal definitions are generic allowing the bus to be used in systems based on other
processor families.

Types of PCI
 Original PCI
 PCI 2.3
 PCI-X
 PCI Express

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Embedded Systems Module II: Communication Protocols

Comparison of PCI and ISA

Bus Bus Bus Advantage

MB/sec Disadvantages
Type Width Speed s

Low speed
low cost
16 Jumpers & DIP
ISA 16 bits 8MHz compatibilit
MBps switches.
y
becoming obsolete
widely used

very high
speed,
incompatible with
Plug &
PCI 64 bits 133 MHz 1 GBps older systems,
Play,
can cost more
dominant
board-level
bus

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