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y.sathish
Phone: 7981193557
Address :
B.cherlopalli(vil),Simhadripuram(mandal),Kadapa(dis),
Door no.4-81,Pin code 516454. E-Mail: yanamalasathish6@gmail.com
Education
Qualifications Qualification School/Colleg Board/University Year of Percentage
e Passing
(chitoor)
Project Title: System Verilog Based Verification for Serial peripheral interface Protocol
to get maximum Coverage:
Brief: This project is to established the communication between two units such
as master and slave in full duplex mode. Communication interface is very much
important for communicating with various subsystem of Embedded system and
with the external world.Embedded product comprises different types of
components arranged on PCB board. The communication channel which makes
bridge connection between the various components which resides in embedded
system product is referred as board level /communication interface .SO SPI is the
one of the protocol which can provides communication between different
peripheral devices with one master and many slaves devices. So project is been
done using verilog and system verilog to get maximum coverage. Finding a bug is
very important before product coming to the market. So proper environment
and test cases created using System verilog and try to get maximum coverage.
Software used: Xilinx ,Diamond.
Language: verilog,System Verilog
Role: Programmer
Project Title: Verification of UART (Universal Asynchronous Receiver and Transmitter
and )Protocol:
Brief: This Project is develop a verilog based UART (Universal asynchronous
Receiver Transmitter) and demonstrates its working by interfacing it to Microsoft
Windows hyper terminal.So UART is device that has capability to both receive
and transmit serial data. For transmission the UART protocol wraps this 8 bit
data.
Software used:VERILOG, SYSTEM VERILOG.
Role:Programmer
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I, hereby declare that the information furnished above is correct to the best of my knowledge.
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