Guruprakashkumar Peta

National Institute of Technology

Farmagudi, Ponda, Goa
Mobile: 9490781726
E-mail:petaguruprakash@gmail.com

C AREER O BJECTIVE
Looking for a responsible position as a teacher with a view to utilize and enhance my research
and technical skills in a dynamic, growth oriented and technologically driven organization.

S UMMARY
• Pursuing M.Tech.
• Worked on Pulse Position Modulation Analog to Digital Converter.
• Worked on Time to Digital Converter.
• Design of two-stage Opamp with gain of 92 dB and Unity Gain Bandwidth of 100 MHz.
• Worked on ”Delta Modulator” in SCL 180 nm technology.
• A seminar report on scrolling of roll numbers on basys 3 FPGA board using verilog.
• A seminar on ”Fault Simulation” using verilog.

R ESEARCH I NTERESTS
Analog and mixed signal design.

P ROJECTS
M.T ECH
T ITLE A 1-V, 5-bit, 115-µW, Pulse Position Modulation ADC in 65-nm CMOS Process
T OOL Cadence - Virtuoso
D ESCRIPTION This paper proposes a dual ramp, pulse position modulation analog-to-digital
converter. A delay cell is proposed in this work, which effectively converts the
timing information into a thermometric code. The architecture uses a dual ramp,
which initiates the time to digital quantization from both Most Significant Bit
(MSB) and Least Significant Bit (LSB) ends. This technique leads to an increase
in the sampling frequency by a factor of 2. The proposed design digitizes the
input with a sampling rate of 100 MHz. It is designed and implemented in a 65-
nm CMOS technology with a supply voltage of 1 V. The architecture consumes a
power of 115 µW with an effective number of bits of 4.51 bits.
B.T ECH
T ITLE Memory based multiplication using APC
T OOL Xilinx Hlx
D ESCRIPTION Using Anti-symmetric Product Coding Technique, a soft multiplier was imple-
mented. The project was focused on halving the memory needed for the multi-
plier while trying to prevent the compromise in speed.

T ECHNICAL SKILLS
L ANGUAGES c language,Verilog.
A UTOMATION TOOLS Cadence-Virtuoso,Xilinx HLX, Visual TCAD
E DUCATIONAL QUALIFICATIONS

Y EAR D EGREE AND I NSTITUTE G RADE

Master of Technology in VLSI
2018 - present CGPA: 8.6/10
National Institute of Technology, Goa
Bachelor of Technology in ECE
2012 - 2016 Percentage:72.32 %
Audisankara Engineering College, Nellore,Andhra Pradesh.
Intermediate (MPC)
2010 - 2012 Percentage: 92.7 %
Narayana Junior College, Nellore, Andhra Pradesh.
S.S.C
2002 - 2007 Percentage: 86 %
Sidhartha English High School,Nellore,Andhra Pradesh

H OBBIES
• Playing and Watching cricket
• Playing badminton

R EFERENCES
• Dr. Y.B.Nitin Kumar
Assistant Professor and Head
Department of Electronics and Communication Engineering,
National Institute of Technology Goa
Email: nitin.shastri@gmail.com

• Dr. M.H.Vasantha
Associate Professor and Registrar
Department of Electronics and Communication Engineering,
National Institute of Technology Goa
Email: vasanthmh@nitgoa.ac.in

D ECLARATION
I hereby declare that the above mentioned information is correct to the best of my knowledge.

P Guruprakash