UVM-AMS based Sub-System Verification of
Wireless Power Receiver SoC
Chao Liang*, Geng Zhong, Song Huang, Bei Xia
Microcontroller, Freescale , Suzhou 215011, China
*Email:Angela.Liang@freescale.com
signal verification methodology for wireless power receiver
Abstract— Mixed-signal design becomes more and more sub-system is presented in this paper.
popular nowadays, designers are required to quickly integrate
IPs and run through the design flow to tape out in short time, so
a fast and accurate design flow will be critical to ensure the
success of the project. In this paper, a UVM-based methodology
for mixed-signal sub-system verification of wireless power
receiver family MCU is introduced. As standard digital
functional verification method, UVM co-works with analog
design which greatly improves the verification efficiency and
quality. The model-based verification approach also helps build a
scalable and re-usable framework, in which coverage driven
verification (CDV) is achieved with automatic stimulus
generation, analog assertions are also used to monitor and verify
mixed-signal system behavior automatically.
Keywords—UVM; mixed signal verification; wireless power
receiver sub-system ; analog assertion;
I. INTRODUCTION
Mixed-signal applications are among the fastest growing
market segments in the electronics and semiconductor industry.
Most systems-on-chip (SoC) today are mixed signal designs,
and all SoCs will be mixed signal at advanced process nodes in
the near future. Designers of system that incorporates analog
components can’t ignore analog functionality. Some dramatic
methodology changes have happened in AMS IP designs over
the past few years. Significant amounts of digital logic are now
integrated into analog blocks, also mixed signal designs have
multiple feedback loops through the analog and digital
domains. It is impractical to decompose them into independent
functions without losing essential system behavior. An
integrated mixed-signal simulation and verification
environment is needed for mixed signal design verification [1].
The Universal Verification Methodology (UVM) has become a
de facto standard in today’s functional verification of digital
designs[2]. It is also widely used in mixed signal designs based
on logic models. However UVM is rarely used for mixed
signal designs when verilogAMS models or even transistor
level netlist are used to represent the analog behavior. To
expand UVM into mixed signal testbench, two kinds of
difficulties need to be resolved. The First one is how to create
analog UVC(Universal Verification Component) to achieve
common analog function for each analog IP, then UVM
component could directly communicate with analog part of the
mixed signal design without extra verilogAMS files. The
second one is how to collect analog functional coverage in
order to conduct on randomized stimulus generation and
evaluate verification quality. In order to resolve these
difficulties, a practical implementation of UVM-based mixed-
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II. WIRELESS POWER RECEIVER SUBSYSTEM
As the increasing demand for power of mobile devices,
new method is needed to manage the battery time. Wireless
power receiver is one of them, it provides a charging platform
to contactless charge portable battery powered devices, such as
mobile phone, tablet, portable devices, power tools and battery
packs, music players, etc.
Freescale Wireless power receiver Product family MCU is
an integrated receiver for wireless power transfer. It is based
on ARM Cortex™-M0+ core with built-in DSP functionality
for industrial and Multi-Market business. Wireless power
receiver function is implemented by three mixed signal IPs
and one digital IP. The Power management controller contains
voltage regulators which provide internal power to other
analog modules. The linear low dropout voltage regulator
controller module is designed to deliver power to wireless
power receiver loads with the external N-FET power devices.
The communication and clamp controller is designed for
WPC-Qi compliant wireless power receiver. It acts as a
communication and control unit of the power receiver.
Frequency-shift keying demodulation timer is a digital module
which enables the wireless power receiver to demodulate the
message sent by WPC-Qi medium power specification
compliant transmitter.
III. VERIFICATION ENVIRONMENT
Since the four wireless charging IPs co-work with each
other, a sub-system verification environment was built up to
verify the wireless power receiver system. The testbench is a
layered and configurable framework, not only the single IP
function could be verified in this system, but also the
interactions between multiple IP blocks, which is key for sub-
system verification. The test-bench architecture presented in
the work paves way for extending the digital verification
concepts to the analog verification environment. It also
provides a framework to achieve coverage-driven verification
(CDV) by combining automatic stimuli generation, self-
checking, and coverage metrics to significantly improve the
efficiency to verifying a DUT [4].
A. Testbench Architecture
The UVM-based testbench could be divided into three major
parts. The first is the top module which simply instantiates the
DUT and interfaces for communication with components in
main testbench. The second is the testbench which is the main
part and includes all testbench components such as various
functional UVM verification component (UVC), register model
ICSICT2014, Guilin, China
 and scoreboard. The third is the test scenario, which defines the signal changes more than the configurable value vdelta. So
input stimulus based on UVM virtual sequences. Figure 1 is vdelta make the sampling accuracy from continuous type signal
testbench architecture of the sub-system. value to discrete type signal value configurable. One interface
virtual bridge is needed between each electrical to real
connection.
V_seqr

BUS UVC Analog UVC Common Digital UVC

Agent Agent Agent

Coverage
TEST BEN CH
Seqr Seqr Seqr An alo g UV C I nter face
Com pon ent
Drv Drv Drv
Scoreboard
r eal
Mon Mon Mon

BUS IF Analog IF Digital IF r eal el e c tr i c al

el ect rica l
Inte rfa ce V irt ual Powe r ma nag emen t
B ridg e c ontr oll er
Harness
DUT

DUT

Figure 3 Interface Connectivity Diagram

Figure 1 Testbench Architecture
• Scoreboard and functional coverage
• Universal Verification Component(UVC) As a self-checking component, scoreboard is used to
The UVCs are encapsulated, ready-to-sue, configurable verify the proper operation of the wireless power receiver sub
verification environment, which can be fully reused from block system at a functional level. Besides normal digital function
level to sub system level or SoC level [7]. There are three checking in traditional UVM testbench, it also provides analog
UVCs which are configured for a desired function. Bus UVC is voltage checking function. Each time any of the control signal
configured for bus access, digital UVC is configured for changes, the voltage checking should be triggered
normal digital function like reset and clk generation, low power automatically. Figure 4 is the voltage check flow.
mode entry etc. Analog UVC is configured for analog function
like voltage drive and voltage monitor. Analog UVC support
various functions, there are two kinds of basic functions:
voltage ramp up and voltage ramp down. Any other complex No Yes
functions like voltage ramp down and up for low voltage flag=1? Voltage<0.05 PASS
detection can also be implemented based on them. Take Yes
voltage ramp up for example. In Figure 2, if enough points are FAIL
configured between voltage_level1 and voltage_level2, the Voltage>LOW
Voltage<HIGH
discrete voltage ramp up looks quite approximate to the
continuous analog ramp up. Yes No

PASS FAIL
Voltage_level2

Figure 4 Voltage Check Flow

Configurable points

Voltage_level1

Besides checkers, coverage is also crucial for CDV flow.

Functional coverage is performed on user defined functional
coverage points. Functional coverage can be implemented
Figure 2 Analog UVC Voltage Ramp Up using SystemVerilog covergroups. In this wirless power
receiver sub system testbench, real type signals are used in
• Interface covergroup for analog signal functional coverage which
greatly improved mixed signal verification quality. The main
For UVM based mixed signal testbench, interface virtual purpose of below code is for vref5v low voltage detection
bridge is needed to connect between analog UVC interface functional coverage.
component and DUT, See Figure 3. Take power management
Covergroup pmc_vref_lvw_cg @(posedge
controller(PMC) for example , as verilogAMS model is used to testbench.ipg_clk);
represent PMC, for electrical type design interface, the option.per_instance=1;
interface virtual bridge will do the conversion between coverpoint pmc_vif.vref_5v iff
electrical signal which is continuous analog value and real type (vref5v_ext_drv_vif.doo[0]) {
signal which is event-based discrete value. A system function bins vref_lvw1= {[3.40:3.55]};
bins vref_lvw2= {[3.55:3.65]};
called absdelta is used in the interface virtual bridge. It issues bins vref_lvw3= {[3.85:4.05]};
an event and thus updates the real value whenever the analog bins vref_lvw4= {[4.15:4.45]};

978-1-4799-3282-5/14/$31.00 ©2014 IEEE ICSICT2014, Guilin, China

 } verified in sub system testbench. The analog assertions
endgroup help to address the analog design issues that could not be
B. Analog Assertions found out with traditional analog verification method.
For example glitch on first FSK clock cycle. The three
Assertion checking is a simple addition to simulation-
analog IP were first represented as verilogAMS model,
based verification methodology. Assertions are monitors which
replaced with spice netlist latter in the same testbench.
checks for a specific condition or a specific sequence of events
Figure 6 is the Tx-to-Rx demodulation simulation
during simulation[5]. They generate warnings or errors if
waveform.
required conditions or sequences fail, or if forbidden conditions
or sequences occur. System Verilog Assertions are widely used
in digital verification, now it is extended to support real-valued
signals in mixed signal testbench. Below code is for power
management controller low voltage reset function check, it will
also contribute to functional coverage[6].

always @(vddx) begin

if((vddx < 3.06) && (vddx > 0.2))
vddx_lvr_assert <= 1'b1;
else if(vddx > 3.091) Figure 9 power Tx-Rx demolation
vddx_lvr_assert <= 1'b0;
end
property p_vddx_lvr_assert_func;
disable iff(pmc_sva_disable)
Figure 6 Tx-to-Rx demodulation simulation waveform
$rose(vddx_lvr_assert) |->
Built confidence for the design, analog signal functional
(pmc_lv_reset_1p8_safed);
endproperty
coverage was collected through covergroups and analog
assertions, which was never noticed in traditional pure
a_vddx_lvr_assert_func: assert digital verification flow.
property(p_vddx_lvr_assert_func)
else `ERROR("When vddx_lvr_assert rise, Conclusion
pmc_lv_reset_1p8_safed is not set"); The importance of automating functional verification of
c_vddx_lvr_assert_func:cover
wireless power receiver SoC was addressed in this paper. One
The System Verilog Assertions need to bind to DUT UVM based mixed signal verification method was introduced
through harness, see Figure 5. for wireless power receiver sub-system, and it can also be
applied to any mixed signal SoC or module level verification
environment. It supports mixed AMS simulation with
Figure 7 Assertion binding verilogAMS models, can also be extended to transistor level
DUT
Assertions models.
PMC
PMC
The benefit of UVM mixed signal testbench is constrained
Harness
random stimulus generation, reusability of UVCs and mixed
LDO signal functional coverage. Implementing the methodology on
Assertions
LDO
a real system design provided us an evidence of how
effectively a UVM-based mixed signal verification approach
can help in refining the system performance and making it
Figure 5 Interface Connectivity Diagram much more robust.
C. Simulation Result References
Using methods reported in this paper, Freescale wireless [1] Jess Chen, Michael Henrie, Monte F.Mar, “Mixed-Signal Methodology
power receiver MCU verification quality and efficiency are Guide”, 2012, pp.20.
improved. The silicon result shows that these methods are best [2] Alexander W. Rath, Volkan Esen,Wolfgang EckerA, “A Transaction-
Oriented UVM-Based Library for Verification of Analog Behavior”,
choices for complex mixed-signal SoC. Compared to 2014,pp.1-2.
traditional verification methods, they have below advantages:
[3] Universal Verification Methodology(UVM) 1.1 User’s Guide, p10-

Improved verification efficiency. Compared to 20,2011
standalone IP verification environment, the bus UVC, [4] Y. Yun, J. Kim, N. Kim and B. Min, “ Beyond UVM for Practical SoC
analog UVC and digital UVC could be used by four new Verification,” SoC Design Conference (ISOCC), 158-162, 2011.
IPs to add stimulus and check expected behavior. These [5] Yunfeng Tao, “ An introduction to assertion based verification,”
ASICON’09, IEEE 8th International Conference, October 2009.
UVCs are also reused in Soc verification testbench, and
[6] Chao.Liang,. “Mixed-Signal Verification Methods for Multi-Power
could be reused to other projects. Mixed-Signal System-on-Chip (SoC) Design”, ASICON 2013, IEEE

Improved verification quality. With the stimulus from 10th International Conference, October,2013
[7] Geng Zhong, Jian Zhou, Bei Xia, “Parameter and UVM, Making a
analog UVC, wireless power Tx-to-Rx message Layered Testbench Powerful’, ASICON 2013, IEEE 10th International
demodulator function, low jitter on AC1 and AC2 Conference, October,2013.
voltage zero-cross comparator feature etc could be

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