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5 4 3 2 1

D D

Essentials Oak 14 Schematic


Haswell-ULT
C 2013-5-23 C

REV : A00

B B

A
DY : None Installed <Core Design> A

Wistron Corporation
UMA: UMA only installed 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

OPS: DISCRTE OPTIMUS installed Title

Cover Page
Size Document Number Rev
A3

5
sualaptop365.edu.vn
4 3 2
Date:
OAK14 Haswell
Thursday, May 23, 2013 Sheet
1
1 of 104
X00
5 4 3 2 1

CHARGER
BQ24717 44
Project code: 91.44L01.001 INPUTS OUTPUTS
PCB P/N : 12314
Revision: X00
Oak14 Block Diagram AD+
BT+
DCBATOUT

SYSTEM DC/DC
TPS51225 45
INPUTS OUTPUTS
3D3V_AUX_S5
D 5V_AUX_S5 D
DCBATOUT 5V_S5
3D3V_S5
DDR3L
1333/1600 CPU Core Power
Intel CPU DDR3L 1333/1600MHz Channel A ISL95813 46,47
33

GPU Haswell ULT SODIMM A


12
INPUTS OUTPUTS
DCBATOUT VCC_CORE
Nvidia 15W
VRAM(DDR3L) *4
PCIE x 4 DDR3L SUS
128M x 16b x 4(1GB) N14M-GE DDR3L
TPS51216 49
256M x 16b x 4(2GB) DDR3L 1333/1600
78,79,80,81 N14P-GV2 DDR3L 1333/1600MHz Channel B INPUTS OUTPUTS
73,74,75,76,77
SODIMM B
Lynx Point DCBATOUT 1D35V_S3
13
0D65V_S0
Switchable Graphic only 8 USB 2.0/1.1 ports
4 USB 3.0 ports CPU 1.05V
High Definition Audio RT8237 48
4 SATA ports INPUTS OUTPUTS
8 PCIE ports DCBATOUT 1D05V_S0
LPC I/F
HDMI ACPI 4.0a 10/100 LAN CPU 1D5V_S0
C HDMI V1.4a RJ45 TLV70215 51 C
54 PCIE x 1 RealTek
INPUTS OUTPUTS
8106EUS Conn. 31 1D5V_S0
30 3D3V_S5

14.0" LCD eDP/LVDS Converter Switches 36 83


Realtek eDP
(16:9) 52
RTD2136R 53 PCIE x 1
INPUTS OUTPUTS
Mini-Card 1D35V_S3 1D35V_S0
Touch Panel 802.11 b/g/n 5V_S5 5V_S0
USB2.0 x 1
USB2.0 x 1 BT V4.0 combo 3D3V_S5 0D675V_S0
58
VCCP_CPU 3D3V_S0
Camera 3D3V_S0 1D05V_VGA_S0
USB2.0 x 1 Left side
USB3.0 x 2 3D3V_VGA_S0
Digital MIC 52
1D35V_VGA_S0
USB3.0 Port x 2
USB2.0 x 2
HDA 34,35
PCB LAYER
MIC_IN/GND
CODEC USB Board
HDA L1:Top L5:VCC
HP_R/L Realtek Right side L2:GND L6:Signal
29 L3:Signal L7:GND
B Combo Jack ALC3223 27 L4:Signal L8:Bottom B

USB2.0 x 1 USB2.0 Port x 1


2CH SPEAKER
(2CH 2W/4ohm)

29
LPC debug port LPC BUS CardReader SD/SDHC/MS/MS Pro
USB2.0 x 1
65 RealTek Slot
33
RTS5176E 32

Thermal
NUVOTON SMBUS
NCT7718W 26 KBC
NUVOTON SPI SATA(Gen3) x 1 HDD
Fan Control NPCE985P 56
NUVOTON 24
NCT3940S-A 26
Flash ROM
PS2 8MB
Int. SATA(Gen1) x 1 ODD
Quad Read 25
FAN 26
A
KB 62 56 A

Touch PAD SMBUS


Image sensor <Core Design>

62
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Block Diagram

sualaptop365.edu.vn
Size Document Number Rev
C OAK14 Haswell X00
Date: Tuesday, February 26, 2013 Sheet 2 of 104
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: Thursday, January 10, 2013 Sheet 3 of 104
5 4 3 2 1
5 4 3 2 1

SSID = CPU
1D05S_VCCST

RN401
XDP_TMS 1 8
XDP_TDI 2 7
D 3 6 D
XDP_TDO 4
DY 5

SRN51J-1-GP

XDP_TRST# R402 1
DY 2 51R2J-2-GP
XDP_TCLK R406 1 2 51R2J-2-GP

Check TCLK Pull down Res.


1D05S_VCCST
HSW_ULT_DDR3L
CPU1B 2 OF 19
1

R401 TP401 1 SKTOCC# D61


62R2J-GP TP402 H_CATERR# PROC_DETECT# MISC
1 K61 CATERR#
N62 J62 XDP_PRDY# XDP_PRDY# 96
24 H_PECI PECI PRDY#
C K62 XDP_PREQ# XDP_PREQ# 96 C
2

PREQ# XDP_TCLK
PROC_TCK E60 XDP_TCLK 96
E61 XDP_TMS XDP_TMS 96
JTAG PROC_TMS
24,42,44,46 H_PROCHOT# 1 2 H_PROCHOT#_R K63 PROCHOT# PROC_TRST# E59 XDP_TRST# XDP_TRST# 96
R403 THERMAL F63 XDP_TDI XDP_TDI 96
PROC_TDI XDP_TDO
56R2J-4-GP PROC_TDO F62 XDP_TDO 96
Layout Note: TP403 1 H_CPUPWRGD C61 PROCPWRGD XDP_BPM[7:0]
Impedance control:50 ohm R405
PWR
XDP_BPM[7:0] 96
2 1 J60 XDP_BPM0
BPM#0 XDP_BPM1
10KR2J-3-GP BPM#1 H60
H61 XDP_BPM2
BPM#2 XDP_BPM3
BPM#3 H62
SM_RCOMP_0 AU60 K59 XDP_BPM4
SM_RCOMP_1 SM_RCOMP0 DDR3L BPM#4 XDP_BPM5
AV60 SM_RCOMP1 BPM#5 H63
SM_RCOMP_2 AU61 K60 XDP_BPM6
SM_DRAMRST# SM_RCOMP2 BPM#6 XDP_BPM7
AV15 SM_DRAMRST# BPM#7 J61
DDR_PG_CTRL AV61
12 DDR_PG_CTRL SM_PG_CNTL1

B B
HASWELL-6-GP

R407 1 2 200R2F-L-GP SM_RCOMP_0 1D35V_S3


Layout Note:
R408 1 2 120R2F-GP SM_RCOMP_1 Place close to DIMM
R409 1 2 100R2F-L1-GP-U SM_RCOMP_2 1 R410
470R2J-2-GP

R404
2

0R0402-PAD
SM_DRAMRST# 1 2 DDR3_DRAMRST# 12,13

Layout Note: <Core Design>


Design Guideline:
SM_RCOMP keep routing length less than 500 mils.
A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (THERMAL/MISC/PM)
Size Document Number Rev
A4 X00
OAK14 Haswell
sualaptop365.edu.vn Date: Monday, June 03, 2013 Sheet 4 of 104
5 4 3 2 1
5 4 3 2 1

SSID = CPU

D D
HSW_ULT_DDR3L 3 OF 19 HSW_ULT_DDR3L 4 OF 19
CPU1C CPU1D

M_A_DQ[63:0]
12 M_A_DQ[63:0] M_A_DQ0 M_B_DQ[63:0]
AH63 AU37 13 M_B_DQ[63:0]
M_A_DQ1 SA_DQ0 SA_CLK#0 M_A_DIMA_CLK_DDR#0 12 M_B_DQ0
AH62 AV37 AY31 AM38
M_A_DQ2 SA_DQ1 SA_CLK0 M_A_DIMA_CLK_DDR0 12 M_B_DQ1 SB_DQ0 SB_CK#0 M_B_DIMB_CLK_DDR#0 13
AK63 AW36 AW31 AN38
M_A_DQ3 SA_DQ2 SA_CLK#1 M_A_DIMA_CLK_DDR#1 12 M_B_DQ2 SB_DQ1 SB_CK0 M_B_DIMB_CLK_DDR0 13
AK62 AY36 AY29 AK38
M_A_DQ4 SA_DQ3 SA_CLK1 M_A_DIMA_CLK_DDR1 12 M_B_DQ3 SB_DQ2 SB_CK#1 M_B_DIMB_CLK_DDR#1 13
AH61 AW29 AL38
M_A_DQ5 SA_DQ4 M_B_DQ4 SB_DQ3 SB_CK1 M_B_DIMB_CLK_DDR1 13
AH60 AU43 AV31
M_A_DQ6 SA_DQ5 SA_CKE0 M_A_DIMA_CKE0 12 M_B_DQ5 SB_DQ4
AK61 AW43 AU31 AY49
M_A_DQ7 SA_DQ6 SA_CKE1 M_A_DIMA_CKE1 12 M_B_DQ6 SB_DQ5 SB_CKE0 M_B_DIMB_CKE0 13
AK60 AY42 AV29 AU50
M_A_DQ8 SA_DQ7 SA_CKE2 M_B_DQ7 SB_DQ6 SB_CKE1 M_B_DIMB_CKE1 13
AM63 AY43 AU29 AW49
M_A_DQ9 SA_DQ8 SA_CKE3 M_B_DQ8 SB_DQ7 SB_CKE2
AM62 AY27 AV50
M_A_DQ10 SA_DQ9 M_B_DQ9 SB_DQ8 SB_CKE3
AP63 AP33 AW27
M_A_DQ11 SA_DQ10 SA_CS#0 M_A_DIMA_CS#0 12 M_B_DQ10 SB_DQ9
AP62 AR32 AY25 AM32
M_A_DQ12 SA_DQ11 SA_CS#1 M_A_DIMA_CS#1 12 M_B_DQ11 SB_DQ10 SB_CS#0 M_B_DIMB_CS#0 13
AM61 AW25 AK32
M_A_DQ13 SA_DQ12 TP_M_A_DIMA_ODT0 TP501 M_B_DQ12 SB_DQ11 SB_CS#1 M_B_DIMB_CS#1 13
AM60 AP32 1 AV27
M_A_DQ14 SA_DQ13 SA_ODT0 M_B_DQ13 SB_DQ12 TP_M_B_DIMB_ODT0 TP503
AP61 AU27 AL32 1
M_A_DQ15 SA_DQ14 M_B_DQ14 SB_DQ13 SB_ODT0
AP60 AY34 M_A_RAS# 12 AV25
M_A_DQ16 SA_DQ15 SA_RAS# M_B_DQ15 SB_DQ14
AP58 AW34 M_A_WE# 12 AU25 AM35 M_B_RAS# 13
M_A_DQ17 SA_DQ16 SA_WE# M_B_DQ16 SB_DQ15 SB_RAS#
AR58 AU34 M_A_CAS# 12 AM29 AK35 M_B_WE# 13
M_A_DQ18 SA_DQ17 SA_CAS# M_B_DQ17 SB_DQ16 SB_WE#
AM57 AK29 AM33 M_B_CAS# 13
M_A_DQ19 SA_DQ18 M_B_DQ18 SB_DQ17 SB_CAS#
AK57 AU35 M_A_BS0 12 AL28
M_A_DQ20 SA_DQ19 SA_BA0 M_B_DQ19 SB_DQ18
AL58 AV35 M_A_BS1 12 AK28 AL35 M_B_BS0 13
M_A_DQ21 SA_DQ20 SA_BA1 M_B_DQ20 SB_DQ19 SB_BA0
AK58 AY41 M_A_BS2 12 AR29 AM36 M_B_BS1 13
M_A_DQ22 SA_DQ21 SA_BA2 M_B_DQ21 SB_DQ20 SB_BA1
AR57 AN29 AU49 M_B_BS2 13
M_A_DQ23 SA_DQ22 M_A_A0 M_A_A[15:0] 12 M_B_DQ22 SB_DQ21 SB_BA2
AN57 AU36 AR28
M_A_DQ24 SA_DQ23 SA_MA0 M_A_A1 M_B_DQ23 SB_DQ22 M_B_A0 M_B_A[15:0] 13
AP55 AY37 AP28 AP40
M_A_DQ25 SA_DQ24 SA_MA1 M_A_A2 M_B_DQ24 SB_DQ23 SB_MA0 M_B_A1
AR55 AR38 AN26 AR40
M_A_DQ26 SA_DQ25 SA_MA2 M_A_A3 M_B_DQ25 SB_DQ24 SB_MA1 M_B_A2
AM54 AP36 AR26 AP42
M_A_DQ27 SA_DQ26 SA_MA3 M_A_A4 M_B_DQ26 SB_DQ25 SB_MA2 M_B_A3
AK54 AU39 AR25 AR42
M_A_DQ28 SA_DQ27 SA_MA4 M_A_A5 M_B_DQ27 SB_DQ26 SB_MA3 M_B_A4
AL55 AR36 AP25 AR45
M_A_DQ29 SA_DQ28 SA_MA5 M_A_A6 M_B_DQ28 SB_DQ27 SB_MA4 M_B_A5
AK55 AV40 AK26 AP45
M_A_DQ30 SA_DQ29 SA_MA6 M_A_A7 M_B_DQ29 SB_DQ28 SB_MA5 M_B_A6
AR54 AW39 AM26 AW46
M_A_DQ31 SA_DQ30 DDR CHANNEL A SA_MA7 M_A_A8 M_B_DQ30 SB_DQ29 SB_MA6 M_B_A7
AN54 AY39 AK25 AY46
M_A_DQ32 SA_DQ31 SA_MA8 M_A_A9 M_B_DQ31 SB_DQ30 SB_MA7 M_B_A8
AY58 AU40 AL25 AY47
M_A_DQ33 SA_DQ32 SA_MA9 M_A_A10 M_B_DQ32 SB_DQ31 DDR CHANNEL B SB_MA8 M_B_A9
AW58 AP35 AY23 AU46
M_A_DQ34 SA_DQ33 SA_MA10 M_A_A11 M_B_DQ33 SB_DQ32 SB_MA9 M_B_A10
AY56 AW41 AW23 AK36
M_A_DQ35 SA_DQ34 SA_MA11 M_A_A12 M_B_DQ34 SB_DQ33 SB_MA10 M_B_A11
AW56 AU41 AY21 AV47
M_A_DQ36 SA_DQ35 SA_MA12 M_A_A13 M_B_DQ35 SB_DQ34 SB_MA11 M_B_A12
AV58 AR35 AW21 AU47
M_A_DQ37 SA_DQ36 SA_MA13 M_A_A14 M_B_DQ36 SB_DQ35 SB_MA12 M_B_A13
C AU58 AV42 AV23 AK33 C
M_A_DQ38 SA_DQ37 SA_MA14 M_A_A15 M_B_DQ37 SB_DQ36 SB_MA13 M_B_A14
AV56 AU42 AU23 AR46
M_A_DQ39 SA_DQ38 SA_MA15 M_B_DQ38 SB_DQ37 SB_MA14 M_B_A15
AU56 M_A_DQS#[7:0] 12 AV21 AP46
M_A_DQ40 SA_DQ39 M_A_DQS#0 M_B_DQ39 SB_DQ38 SB_MA15
AY54 AJ61 AU21 M_B_DQS#[7:0] 13
M_A_DQ41 SA_DQ40 SA_DQSN0 M_A_DQS#1 M_B_DQ40 SB_DQ39 M_B_DQS#0
AW54 AN62 AY19 AW30
M_A_DQ42 SA_DQ41 SA_DQSN1 M_A_DQS#2 M_B_DQ41 SB_DQ40 SB_DQSN0 M_B_DQS#1
AY52 AM58 AW19 AV26
M_A_DQ43 SA_DQ42 SA_DQSN2 M_A_DQS#3 M_B_DQ42 SB_DQ41 SB_DQSN1 M_B_DQS#2
AW52 AM55 AY17 AN28
M_A_DQ44 SA_DQ43 SA_DQSN3 M_A_DQS#4 M_B_DQ43 SB_DQ42 SB_DQSN2 M_B_DQS#3
AV54 AV57 AW17 AN25
M_A_DQ45 SA_DQ44 SA_DQSN4 M_A_DQS#5 M_B_DQ44 SB_DQ43 SB_DQSN3 M_B_DQS#4
AU54 AV53 AV19 AW22
M_A_DQ46 SA_DQ45 SA_DQSN5 M_A_DQS#6 M_B_DQ45 SB_DQ44 SB_DQSN4 M_B_DQS#5
AV52 AL43 AU19 AV18
M_A_DQ47 SA_DQ46 SA_DQSN6 M_A_DQS#7 M_B_DQ46 SB_DQ45 SB_DQSN5 M_B_DQS#6
AU52 AL48 AV17 AN21
M_A_DQ48 SA_DQ47 SA_DQSN7 M_B_DQ47 SB_DQ46 SB_DQSN6 M_B_DQS#7
AK40 M_A_DQS[7:0] 12 AU17 AN18
M_A_DQ49 SA_DQ48 M_A_DQS0 M_B_DQ48 SB_DQ47 SB_DQSN7
AK42 AJ62 AR21 M_B_DQS[7:0] 13
M_A_DQ50 SA_DQ49 SA_DQSP0 M_A_DQS1 M_B_DQ49 SB_DQ48 M_B_DQS0
AM43 AN61 AR22 AV30
M_A_DQ51 SA_DQ50 SA_DQSP1 M_A_DQS2 M_B_DQ50 SB_DQ49 SB_DQSP0 M_B_DQS1
AM45 AN58 AL21 AW26
M_A_DQ52 SA_DQ51 SA_DQSP2 M_A_DQS3 M_B_DQ51 SB_DQ50 SB_DQSP1 M_B_DQS2
AK45 AN55 AM22 AM28
M_A_DQ53 SA_DQ52 SA_DQSP3 M_A_DQS4 M_B_DQ52 SB_DQ51 SB_DQSP2 M_B_DQS3
AK43 AW57 AN22 AM25
M_A_DQ54 SA_DQ53 SA_DQSP4 M_A_DQS5 M_B_DQ53 SB_DQ52 SB_DQSP3 M_B_DQS4
AM40 AW53 AP21 AV22
M_A_DQ55 SA_DQ54 SA_DQSP5 M_A_DQS6 M_B_DQ54 SB_DQ53 SB_DQSP4 M_B_DQS5
AM42 AL42 AK21 AW18
M_A_DQ56 SA_DQ55 SA_DQSP6 M_A_DQS7 M_B_DQ55 SB_DQ54 SB_DQSP5 M_B_DQS6
AM46 AL49 AK22 AM21
M_A_DQ57 SA_DQ56 SA_DQSP7 M_B_DQ56 SB_DQ55 SB_DQSP6 M_B_DQS7
AK46 AN20 AM18
M_A_DQ58 SA_DQ57 SB_DQ56 SB_DQSP7
AM49 AP49 +V_SM_VREF_CNT +V_SM_VREF_CNT 37
M_B_DQ57 AR20
M_A_DQ59 SA_DQ58 SM_VREF_CA M_B_DQ58 SB_DQ57
AK49 AR51 DDR_WR_VREF01 12 AK18
M_A_DQ60 SA_DQ59 SM_VREF_DQ0 M_B_DQ59 SB_DQ58
AM48 AP51 DDR_WR_VREF02 13 AL18
M_A_DQ61 SA_DQ60 SM_VREF_DQ1 M_B_DQ60 SB_DQ59
AK48 AK20
M_A_DQ62 SA_DQ61 M_B_DQ61 SB_DQ60
AM51 AM20
M_A_DQ63 SA_DQ62 M_B_DQ62 SB_DQ61
AK51 AR18
SA_DQ63 M_B_DQ63 SB_DQ62
AP18
SB_DQ63

HASWELL-6-GP HASWELL-6-GP

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDR)
Size Document Number Rev
A2 X00

sualaptop365.edu.vn
OAK14 Haswell
Date: Thursday, March 07, 2013 Sheet 5 of 104
5 4 3 2 1
5 4 3 2 1

SSID = CPU

D D

CPU1S HSW_ULT_DDR3L 19 OF 19

CFG[19:0]
96 CFG[19:0]
CFG0 AC60 AV63
CFG1 CFG0 RSVD_TP#AV63
AC62 CFG1 RSVD_TP#AU63 AU63
CFG2 AC63
CFG3 CFG2
AA63 CFG3
CFG4 AA60 C63
CFG5 CFG4 RSVD_TP#C63
Y62 CFG5 RSVD_TP#C62 C62
CFG6 Y61 B43 EDP_SPARE 1 TP605
CFG7 CFG6 RSVD#B43
Y60 CFG7
CFG8 V62 A51
CFG9 CFG8 RSVD_TP#A51
V61 CFG9 RSVD_TP#B51 B51
CFG10 V60
CFG11 CFG10
U60 CFG11 RSVD_TP#L60 L60
CFG12 T63
CFG13 CFG12 RESERVED
T62 CFG13 RSVD#N60 N60 1127 add (follow EA40)
CFG14 T61
CFG15 CFG14
T60 CFG15 RSVD#W23 W23
Y22 PROC_OPI_COMP3 R606 1 DY 2 49D9R2F-GP
CFG16 RSVD#Y22
AA62 CFG16 PROC_OPI_RCOMP AY15 PROC_OPI_COMP R602 1 2 49D9R2F-GP
CFG18 U63
CFG17 CFG18
AA61 CFG17 RSVD#AV62 AV62
CFG19 U62 D58
C CFG19 RSVD#D58 C
1 2 CFG_RCOMP V63 P22
CFG_RCOMP VSS
N21
Layout Note:
R601 VSS
A5 RSVD#A5
1.Referenced "continuous" VSS plane only.
49D9R2F-GP P20 HVM_CLK# 1 2.Avoid routing next to clock pins or noisy
RSVD#P20
E1 R20 HVM_CLK 1 TP619
D1
RSVD#E1 RSVD#R20 TP620 signals.
RSVD#D1 3.Trace width: 12~15mil
J20 RSVD#J20
H18 RSVD#H18 4.Isolation Spacing: 12mil
1 2 TD_IREF B12 5.Max length: 500mil
TD_IREF
R603
8K2R2F-1-GP

CFG3
1

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)


R604
1KR2J-1-GP 0 : ENABLED
DY CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
2

1 : DISABLED

B B
CFG4
1

DISPLAY PORT PRESENCE STRAP


R605
1KR2J-1-GP 0 : ENABLED
CFG[4] AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT
2

1 : DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RESERVED)
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: Thursday, March 07, 2013 Sheet 6 of 104
5 4 3 2 1
5 4 3 2 1

SSID = CPU

VCC_CORE
HSW_ULT_DDR3L 12 OF 19
D CPU1L D

L59 RSVD#L59 VCC C36


1D35V_S3 J58 C40
RSVD#J58 VCC
C44
1D05S_VCCST 1127 Change net name of R703.2 AH26
VCC
C48
VDDQ VCC
from VR_SVID_ALERT# to AJ31
AJ33
VDDQ VCC C52
C56
R703 1 VDDQ VCC
2 75R2F-2-GP VR_SVID_ALERT#
H_CPU_SVIDALRT# AJ37
AN33
VDDQ VCC E23
E25
R704 1 VDDQ VCC
2 130R2F-1-GP H_CPU_SVIDDAT AP43 VDDQ VCC E27
VCC_CORE AR48 E29
VDDQ VCC
AY35 E31
Layout Note: AY40
VDDQ VCC
E33
1127 130R change to 110R 1. Place close to CPU AY44
VDDQ VCC
E35
VDDQ VCC

1
1203 110R change to 130R 2. VCC_SENSE/ VSS_SENSE AY50 VDDQ VCC E37
E39
impedance=50 ohm R702 F59
VCC
E41
VCC_CORE VCC VCC
3. Lwngth match<25mil 100R2F-L1-GP-U N58 E43
RSVD#N58 VCC
AC58 E45

2
RSVD#AC58 VCC
VCC E47
46 VCC_SENSE E63 VCC_SENSE VCC E49
AB23 RSVD#AB23 VCC E51
TP701 1 TP_VCCIO_OUT A59 VCCIO_OUT VCC E53
+VCCIOA_OUT E20 VCCIOA_OUT VCC E55
AD23 RSVD#AD23 VCC E57
AA23 RSVD#AA23 VCC F24
R701 AE59 F28
43R2J-GP RSVD#AE59 VCC
VCC F32
C
46 VR_SVID_ALERT# 1 2H_CPU_SVIDALRT# L62 VIDALERT# VCC F36 C
H_CPU_SVIDCLK N63 HSW ULT POWER F40
3D3V_S5 46 H_CPU_SVIDCLK VIDSCLK VCC
H_CPU_SVIDDAT L63 F44
46 H_CPU_SVIDDAT VIDSOUT VCC
H_VCCST_PW RGD B59 F48
VCCST_PWRGD VCC
1127_modify 46 H_VR_ENABLE F60 VR_EN VCC F52
R710 1 2 10KR2J-3-GP C59 F56
1D05S_VCCST
(follow EA40) IMVP_PW RGD_R DY VR_READY VCC
G23
VCC
1

D63 G25
C702 DY 96 PW R_DEBUG PW R_DEBUG H59
VSS VCC
G27
SCD1U10V2KX-5GP PWR_DEBUG# VCC
P62 G29
2

VSS VCC
1D05S_VCCST R705 1 2150R2J-L1-GP-U P60 RSVD_TP#P60 VCC G31
1 P61 RSVD_TP#P61 VCC G33
U701 R706 N59 G35
RSVD_TP#N59 VCC
1 5
DY 10KR2J-3-GP N61
T59
RSVD_TP#N61 VCC G37
G39
NC#1 VCC RSVD#T59 VCC
AD60 G41
2

RSVD#AD60 VCC
2 AD59 G43
36,48 1D05V_VTT_PW RGD A DY AA59
RSVD#AD59 VCC
G45
RSVD#AA59 VCC
3 GND Y 4 H_VCCST_PW RGD 96 AE60 RSVD#AE60 VCC G47
AC59 RSVD#AC59 VCC G49
AG58 RSVD#AG58 VCC G51
74LVC1G07GW -GP U59 G53
1D05S_VCCST RSVD#U59 VCC
73.01G07.0HG V59 RSVD#V59 VCC G55
VCC G57
AC22 VCCST VCC H23
AE22 VCCST VCC J23
1 2 VCC_CORE AE23 K23
R707 VCCST VCC
VCC K57
100KR2F-L1-GP AB57 L22
VCC VCC
1

B B
AD57 VCC VCC M23
R709 AG57 M57
47KR2F-GP VCC VCC
C24 VCC VCC P57
C28 VCC VCC U57
C32 W57
2

VCC VCC

HASW ELL-6-GP

1205 Add

1D05V_S0 1D05S_VCCST 1 2 IMVP_PW RGD_R


R711 24,46 IMVP_PW RGD
R713
1 2 100KR2F-L1-GP
1
SC22U6D3V5MX-2GP

SC1U6D3V2KX-GP
C701

C703

R712
0R0603-PAD-1-GP
1

47KR2F-GP

DY
2

A00 4/8 R711 down size to 0603


A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC CORE)


Size Document Number Rev

sualaptop365.edu.vn
A3 X00
OAK14 Haswell
Date: Monday, April 22, 2013 Sheet 7 of 104
5 4 3 2 1
5 4 3 2 1
SSID = CPU

D D

CPU1A HSW_ULT_DDR3L 1 OF 19

54 HDMI_DATA2# C54 DDI1_TXN0 EDP_TXN0 C45 EDP_TX0_DN 53


54 HDMI_DATA2 C55 DDI1_TXP0 EDP_TXP0 B46 EDP_TX0_DP 53
54 HDMI_DATA1# B58 A47
HDMI 54 HDMI_DATA1 C58
DDI1_TXN1
DDI1_TXP1
EDP_TXN1
EDP_TXP1 B47
EDP_TX1_DN
EDP_TX1_DP
53
53
54 HDMI_DATA0# B55 DDI1_TXN2
A55 C47 +VCCIOA_OUT
54 HDMI_DATA0 DDI1_TXP2 EDP_TXN2
54 HDMI_CLK# A57 C46 Design Guideline:
DDI1_TXN3 EDP_TXP2
C 54 HDMI_CLK B57 DDI1_TXP3 EDP_TXN3 A49 EDP_COMP keep routing length max 100 mils. C

1
DDI EDP B49 R801
EDP_TXP3 Trace Width:20 mils.
C51 24D9R2F-L-GP
DDI2_TXN0
C50 DDI2_TXP0 EDP_AUXN A45 EDP_AUX_DN 53
C53 DDI2_TXN1 EDP_AUXP B45 EDP_AUX_DP 53
B54

2
DDI2_TXP1 EDP_COMP
C49 DDI2_TXN2 EDP_RCOMP D20
B50 A43 EDP_BRIGHTNESS 1 TP801
DDI2_TXP2 EDP_DISP_UTIL
A53 DDI2_TXN3
B53 DDI2_TXP3

HASW ELL-6-GP

B B

A <Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDI/EDP)
Size Document Number Rev

sualaptop365.edu.vn A3

Date:
OAK14 Haswell
Thursday, March 07, 2013 Sheet 8 of 104
X00
5 4 3 2 1

SSID = CPU
CPU1P HSW_ULT_DDR3L 16 OF 19

VSS H17
D33 VSS VSS H57
D34 VSS VSS J10
D D35 J22 D
VSS VSS
D37 VSS VSS J59
D38 VSS VSS J63
D39 VSS VSS K1
D41 VSS VSS K12
D42 VSS VSS L13
D43 VSS VSS L15
D45 VSS VSS L17
D46 VSS VSS L18
D47 VSS VSS L20
D49 VSS VSS L58
D5 VSS VSS L61
D50 VSS VSS L7
D51 VSS VSS M22
D53 VSS VSS N10
D54 VSS VSS N3
D55 VSS VSS P59
D57 VSS VSS P63
D59 VSS VSS R10
D62 VSS VSS R22
C D8 R8 C
VSS VSS
E11 VSS VSS T1
E17 VSS VSS T58
F20 VSS VSS U20
F26 VSS VSS U22
F30 VSS VSS U61
F34 VSS VSS U9
F38 VSS VSS V10
F42 VSS VSS V3
F46 VSS VSS V7
F50 VSS VSS W20
F54 VSS VSS W22
F58 VSS VSS Y10
F61 VSS VSS Y59
G18 VSS VSS Y63
G22 VSS
G3 VSS
G5 VSS VSS V58
G6 VSS VSS AH46
G8 VSS VSS V23
B H13 E62 VSS_SENSE VSS_SENSE 46 B
VSS VSS_SENSE
VSS AH16

100R2F-L1-GP-U
1
HASWELL-6-GP
Layout Note:

R901
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE

2
impedance=50 ohm
3. Lwngth match<25mil

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)
Size Document Number Rev
A4 X00
OAK14 Haswell
sualaptop365.edu.vn Date: Thursday, March 07, 2013 Sheet 9 of 104
5 4 3 2 1
5 4 3 2 1

SSID = CPU

1D35V_S3

D D

SC10U6D3V3KX-GP

SC10U6D3V3KX-GP

SC10U6D3V3KX-GP

SC10U6D3V3KX-GP

SC10U6D3V3KX-GP

SC10U6D3V3KX-GP
C1001

C1002

C1003

C1004

C1005

C1006
Layout Note:
1

1
DY DY DY As close to CPU as possible
2

2
SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP
C1017

C1018

C1019

C1020
1

1
DY DY
2

Layout Note:
Direct tie to CPU VccIn/Vss balls

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: Thursday, April 25, 2013 Sheet 10 of 104
5 4 3 2 1
5 4 3 2 1

MAX: 1.92A

1.838A 41mA 42mA

D D
1D05V_HSIO +V1.05DX_MODPHY_PCH 1D05V_HSIO +V1.05S_ASATA3PLL
R1101 1D05V_HSIO +V1.05S_AUSB3PLL
1 2 L1102 1 2 0R3J-0-U-GP +V1.05S_ASATA3PLL

C1102
SC1U6D3V2KX-GP

C1101
SC1U6D3V2KX-GP
L1101 1 2 0R3J-0-U-GP +V1.05S_AUSB3PLL

C1105
SC1U6D3V2KX-GP

C1106
SC10U6D3V3KX-GP

C1107
SC10U6D3V3KX-GP
0R0805-PAD-1-GP

1
C1103
SC1U6D3V2KX-GP

C1104
SC10U6D3V3KX-GP

C1123
SC10U6D3V3KX-GP
1

1
DY DY

2
DY DY

2
2

2
CAP need close to pin K9 L10 CAP need close to pin B18 CAP need close to pin B11

57mA 62mA 200mA

1D05V_S0 +V1.05S_APLLOPI 1D05V_S0 +V1.05S_AXCK_DCB


R1102 3D3V_S5_PCH R1103 +V3.3A_PSUS
0R3J-0-U-GP 0R0603-PAD-1-GP L1103 1 2 IND-2D2UH-196-GP +V1.05S_AXCK_DCB
C 1 2 +V1.05S_APLLOPI 1 2 C
68.2R21D.10R

C1111
SC1U6D3V2KX-GP

C1112
SC10U6D3V3KX-GP

C1125
SC10U6D3V3KX-GP
1

1
C1109
SC1U6D3V2KX-GP

C1110
SC10U6D3V3KX-GP

C1124
SC10U6D3V3KX-GP
DY C1108
1

1
SC10U6D3V3KX-GP
DY
DY DY

2
DY
2

2
1205 Add
CAP need close to pin AA21 CAP need close to pin AC9 CAP need close to pin J18

31mA 658mA 1.632A 1mA

1D05V_S0 R1104 +1.05M_ASW 1D05V_S0 R1105 +V1.05S_CORE_PCH


1D05V_S0 IND-2D2UH-196-GP +V1.05S_AXCK_LCPLL 0R0603-PAD-1-GP 0R0805-PAD-1-GP RTC_AUX_S5
L1104 1 2 1 2
1 2
C1115
SC10U6D3V3KX-GP

C1116
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
C1117

SC1U6D3V2KX-GP
C1118

SC10U6D3V3KX-GP
C1119

C1120
SCD1U10V2KX-5GP

C1121
SCD1U10V2KX-5GP

C1122
SC1U6D3V2KX-GP
68.2R21D.10R
1

1
C1113
SC1U6D3V2KX-GP

C1114
SC10U6D3V3KX-GP
1

DY DY
DY DY
2

2
B B
2

CAP need close to pin A20 CAP need close to pin AE9 CAP need close to pin AE8 J11 CAP need close to pin AG10

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: W ednesday, May 15, 2013 Sheet 11 of 104
5 4 3 2 1
5 4 3 2 1

SSID = MEMORY

DM1
5 M_A_A[15:0]
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2
96
M_A_A3 A2
95 110 M_A_RAS# 5
M_A_A4 A3 RAS# SA0_DIMA
M_A_A5
92
A4 WE#
113 M_A_WE# 5
SA1_DIMA
Note:
D 91 115 M_A_CAS# 5 D
M_A_A6 A5 CAS# SA0 DIM0 = 0, SA1_DIM0 = 0
90
M_A_A7 A6
86 114 M_A_DIMA_CS#0 5 SO-DIMMA SPD Address is 0xA0

1
M_A_A8 A7 CS0# R1201 R1202
89 121 M_A_DIMA_CS#1 5
A8 CS1#
SO-DIMMA TS Address is 0x30

0R0402-PAD

0R0402-PAD
M_A_A9 85
M_A_A10 A9
107 73 M_A_DIMA_CKE0 5
M_A_A11 A10/AP CKE0
84 74 M_A_DIMA_CKE1 5
M_A_A12 A11 CKE1
83

2
M_A_A13 A12
119 101 M_A_DIMA_CLK_DDR0 5
M_A_A14 A13 CK0
80 103 M_A_DIMA_CLK_DDR#0 5
M_A_A15 A14 CK0#
78
A15
79 102 M_A_DIMA_CLK_DDR1 5
5 M_A_BS2 A16/BA2 CK1
104 M_A_DIMA_CLK_DDR#1 5
CK1#
109
5 M_A_BS0 BA0
108 11
5 M_A_BS1 BA1 DM0
5 M_A_DQ[63:0] 28
M_A_DQ13 DM1
5 46
M_A_DQ8 DQ0 DM2
7 63
M_A_DQ14 DQ1 DM3
15 136
M_A_DQ10 DQ2 DM4
17 153
M_VREF_CA_DIMMA Layout Note: M_A_DQ9 4
DQ3 DM5
170
M_A_DQ12 DQ4 DM6
Place these caps 6
DQ5 DM7
187
M_A_DQ15 16
close to VREF_CA M_A_DQ11 DQ6
18 200 PCH_SMBDATA 13,18,62,96
M_A_DQ29 DQ7 SDA
21 202 PCH_SMBCLK 13,18,62,96
M_A_DQ28 DQ8 SCL
23
M_A_DQ30 DQ9 3D3V_S0
33 198
1

M_A_DQ31 DQ10 EVENT#


35
M_A_DQ25 DQ11
C1201

C1218

C1202

22 199
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

M_A_DQ24 DQ12 VDDSPD


24
2

M_A_DQ27 DQ13 SA0_DIMA


34 197

1
M_A_DQ26 DQ14 SA0 SA1_DIMA C1203
36 201
M_A_DQ44 DQ15 SA1 SCD1U10V2KX-5GP
39
M_A_DQ41 41
DQ16
77 DY

2
M_A_DQ43 DQ17 NC#1
51 122
M_A_DQ47 DQ18 NC#2 1D35V_S3
53 125
M_A_DQ45 DQ19 NC#/TEST
40
M_A_DQ40 DQ20
42 75
M_A_DQ42 DQ21 VDD1
50 76
M_A_DQ46 52
DQ22 VDD2
81
Layout Note:
Layout Note: M_A_DQ51 57
DQ23 VDD3
82 Place Close SO-DIMMA.
M_A_DQ50 DQ24 VDD4
C Place these caps 59
DQ25 VDD5
87 C
M_A_DQ49 67 88
close to VREF_DQ M_A_DQ48 DQ26 VDD6 1D35V_S3
69 93
M_VREF_DQ_DIMMA M_A_DQ52 DQ27 VDD7
56 94
M_A_DQ53 DQ28 VDD8
58 99
M_A_DQ54 DQ29 VDD9
68 100
M_A_DQ55 DQ30 VDD10 DDR_VREF_S3 1D35V_S3
70 105
M_A_DQ0 DQ31 VDD11
129 106

ST330U2VDM-4-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
DQ32 VDD12 5 DDR_WR_VREF01
M_A_DQ1

TC1201

C1208

C1220

C1221

C1222
131 111

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
1

1
M_A_DQ2 DQ33 VDD13
141 112
1

1
M_A_DQ6 DQ34 VDD14

C1207

C1209
143 117 DY R1217
M_A_DQ5 DQ35 VDD15 DY DY
C1204

C1205

C1206

130 118 0R2J-2-GP R1211


DY
SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

2
M_A_DQ4 DQ36 VDD16 1K8R2F-GP
132 123
2

M_A_DQ3 DQ37 VDD17


140 124
M_A_DQ7 142
DQ38 VDD18 2R2F-GP DY

2
M_A_DQ21 DQ39 R1210
147 2
M_A_DQ20 DQ40 VSS
149 3 1 2 M_VREF_DQ_DIMMA
M_A_DQ17 DQ41 VSS
157 8
M_A_DQ16 DQ42 VSS
159 9

1
M_A_DQ18 DQ43 VSS C1219
146 13
0D675V_S0 M_A_DQ19 DQ44 VSS SCD022U16V2JX-GP R1213
148 14

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
M_A_DQ22 DQ45 VSS 1K8R2F-GP

C1210

C1211

C1212

C1213
158 19

2
1

1
M_A_DQ23 DQ46 VSS
160 20
M_A_DQ36 DQ47 VSS +V_VREF_PATH1
163 25 DY

2
1
M_A_DQ33 DQ48 VSS
165 26

2
M_A_DQ34 DQ49 VSS R1212
175 31
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

M_A_DQ38 DQ50 VSS


C1214

C1215

C1216

177 32 24D9R2F-L-GP
1

M_A_DQ37 DQ51 VSS


Layout Note: M_A_DQ32
164
166
DQ52 VSS
37
38
DY

2
M_A_DQ35 DQ53 VSS
Place these caps 174 43
2

M_A_DQ39 DQ54 VSS


close to VTT1 and 176 44
M_A_DQ62 DQ55 VSS
181 48
VTT2. M_A_DQ58 DQ56 VSS
183 49
M_A_DQ60 DQ57 VSS
191 54
M_A_DQ61 193
DQ58 VSS
55
Layout Note:
M_A_DQ63 DQ59 VSS
180
DQ60 VSS
60 Place these Caps near SO-DIMMA.
M_A_DQ59 182 61
M_A_DQ56 DQ61 VSS
192 65
M_A_DQ57 DQ62 VSS
194 66
DQ63 VSS
5 M_A_DQS#[7:0] 71
M_A_DQS#1 VSS
10 72
B M_A_DQS#3 DQS0# VSS B
27 127
M_A_DQS#5 DQS1# VSS
45 128
M_A_DQS#6 DQS2# VSS
62 133
M_A_DQS#0 DQS3# VSS 1D35V_S3
135 134
M_A_DQS#2 DQS4# VSS
152 138
M_A_DQS#4 DQS5# VSS
169 139
M_A_DQS#7 DQS6# VSS
186 144
DQS7# VSS
5 M_A_DQS[7:0] 145
M_A_DQS1 VSS
12 150

D
M_A_DQS3 DQS0 VSS
29 151
M_A_DQS5 DQS1 VSS Q1202
47 155
M_A_DQS6 DQS2 VSS 5V_S5
64 156 2N7002K-2-GP
M_A_DQS0 DQS3 VSS
137 161
M_A_DQS2 154
DQS4 VSS
162
84.2N702.J31
M_A_DQS4 DQS5 VSS 1D35V_S3 2ND = 84.2N702.031 R1206 M_A_DIMA_ODT0
171 167 1 2 66D5R2F-GP
M_A_DQS7 DQS6 VSS
188 168

1
DQS7 VSS R1207 M_A_DIMA_ODT1
172 1 2 66D5R2F-GP

S
M_A_DIMA_ODT0 VSS R1208
116 173
M_A_DIMA_ODT1 ODT0 VSS M_A_B_DIMM_ODT R1203
120 178 200KR2F-L-GP 1 2 66D5R2F-GP M_B_DIMB_ODT0 13
ODT1 VSS
179
VSS R1209
126 184 1 2 66D5R2F-GP

G
M_VREF_CA_DIMMA M_B_DIMB_ODT1 13

2
VREF_CA VSS
Layout Note: M_VREF_DQ_DIMMA 1
VREF_DQ VSS
185
189 R1205
VSS 0R0402-PAD
All VREF traces should 4,13 DDR3_DRAMRST#
30
RESET# VSS
190
195 1 2 DDR_PG_CTRL_R S D DDR_VTT_PG_CTRL
have width=20mil; VSS 4 DDR_PG_CTRL DDR_VTT_PG_CTRL 49
196

1
spacing=20 mil VSS
SCD1U10V2KX-5GP
C1217

0D675V_S0 203 205


1

VTT1 VSS R1204


204 206
VTT2 VSS Q1201 2MR2-GP
DY Q1201 Need check Vth=1V DMN5L06K-7-GP DY
2

84.05067.031

2
DDR3-204P-119-GP-U

close to dimm

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM1
Size Document Number Rev
A2 X00

sualaptop365.edu.vn
OAK14 Haswell
Date: Tuesday, May 28, 2013 Sheet 12 of 104
5 4 3 2 1
5 4 3 2 1

SSID = MEMORY

DM2
5 M_B_A[15:0]
D M_B_A0 98 NP1 D
M_B_A1 A0 NP1
97 NP2
M_B_A2 A1 NP2
96
M_B_A3 A2
95 110 M_B_RAS# 5
M_B_A4 A3 RAS#
92 113 M_B_WE# 5
M_B_A5 A4 WE#
91 115 M_B_CAS# 5
M_B_A6 A5 CAS#
90
M_B_A7 A6
86 114 M_B_DIMB_CS#0 5
M_B_A8 A7 CS0#
89 121 M_B_DIMB_CS#1 5
M_B_A9 A8 CS1#
85
M_B_A10 A9
M_B_A11
107
A10/AP CKE0
73 M_B_DIMB_CKE0 5 Note:
84 74 M_B_DIMB_CKE1 5
M_B_A12 A11 CKE1 SO-DIMMB SPD Address is 0xA4
83
M_B_A13 A12
119 101 M_B_DIMB_CLK_DDR0 5 SO-DIMMB TS Address is 0x34
M_B_A14 A13 CK0
80 103 M_B_DIMB_CLK_DDR#0 5
M_B_A15 A14 CK0#
78
A15
79 102 M_B_DIMB_CLK_DDR1 5
5 M_B_BS2 A16/BA2 CK1
104 M_B_DIMB_CLK_DDR#1 5
CK1#
109
5 M_B_BS0 BA0
108 11
5 M_B_BS1 BA1 DM0
5 M_B_DQ[63:0] 28
M_B_DQ8 DM1
5 46
M_VREF_CA_DIMMB M_B_DQ14 DQ0 DM2
7 63
M_B_DQ10 DQ1 DM3
15 136
M_B_DQ11 DQ2 DM4
17 153
M_B_DQ12 DQ3 DM5 3D3V_S0
4 170
Layout Note: M_B_DQ9 6
DQ4 DM6
187
M_B_DQ13 DQ5 DM7
Place these caps 16
1

M_B_DQ15 DQ6
close to VREF_CA 18 200 PCH_SMBDATA 12,18,62,96

1
M_B_DQ28 DQ7 SDA
C1301

C1302
EC1302

21 202
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

M_B_DQ29 DQ8 SCL PCH_SMBCLK 12,18,62,96


23 R1301
2

M_B_DQ26 DQ9 3D3V_S0 10KR2J-3-GP


33 198
M_B_DQ27 DQ10 EVENT#
35
M_B_DQ25 DQ11
22 199

2
M_B_DQ24 DQ12 VDDSPD
24

1
M_B_DQ30 DQ13 SA0_DIMB
34 197
M_B_DQ31 36
DQ14 SA0
201 SA1_DIMB C1303 DY
M_B_DQ40 DQ15 SA1 SCD1U10V2KX-5GP SA1_DIMB
39

2
M_B_DQ41 DQ16
41 77
M_B_DQ46 DQ17 NC#1 SA0_DIMB
51 122
M_B_DQ42 DQ18 NC#2 1D35V_S3
53 125
M_B_DQ45 DQ19 NC#/TEST
C 40 C

1
DQ20

0R0402-PAD
M_B_DQ44 42 75
M_B_DQ47 DQ21 VDD1

R1302
50 76
M_B_DQ43 DQ22 VDD2
52 81
M_B_DQ56 DQ23 VDD3
57 82
M_B_DQ57 DQ24 VDD4
59 87

2
M_B_DQ59 DQ25 VDD5
67 88
M_VREF_DQ_DIMMB Layout Note: M_B_DQ58 69
DQ26 VDD6
93
M_B_DQ61 DQ27 VDD7
Place these caps 56
DQ28 VDD8
94
M_B_DQ60 58 99
close to VREF_DQ M_B_DQ63 DQ29 VDD9
68 100
M_B_DQ62 DQ30 VDD10 1D35V_S3
70 105
1

M_B_DQ4 DQ31 VDD11


129 106
1

M_B_DQ1 DQ32 VDD12


C1304

131 111
SCD1U10V2KX-5GP

M_B_DQ3 DQ33 VDD13


C1305

C1306

141 112
DY
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP

M_B_DQ7 DQ34 VDD14


143 117
2

M_B_DQ5 DQ35 VDD15


130 118

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
M_B_DQ0 DQ36 VDD16

C1307

C1308

C1309

C1311
132 123

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
1

1
M_B_DQ2 DQ37 VDD17

C1312
140 124

1
M_B_DQ6 DQ38 VDD18

C1310
M_B_DQ32
142
DQ39 DY DY DY DY DY
147 2

2
M_B_DQ37 DQ40 VSS
149 3

2
M_B_DQ38 DQ41 VSS
157 8
M_B_DQ34 DQ42 VSS
159 9
M_B_DQ33 DQ43 VSS
146 13
M_B_DQ36 DQ44 VSS
148 14
M_B_DQ39 DQ45 VSS
158 19
0D675V_S0 M_B_DQ35 DQ46 VSS
160 20
M_B_DQ17 DQ47 VSS
163 25
Layout Note:

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
M_B_DQ16 DQ48 VSS

C1313

C1314

C1315

EC1301
165 26

1
M_B_DQ18 DQ49 VSS
Place these caps 175
DQ50 VSS
31
M_B_DQ19 177 32 DY
close to VTT1 and M_B_DQ20 DQ51 VSS
C1316

C1317

C1318

164 37
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

2
1

VTT2. M_B_DQ21 DQ52 VSS


166 38
M_B_DQ23 DQ53 VSS
174 43
DY M_B_DQ22 176
DQ54 VSS
44
Layout Note:
2

M_B_DQ52 DQ55 VSS


181 48
M_B_DQ49 DQ56 VSS
183
DQ57 VSS
49 Place Close SO-DIMMA.
M_B_DQ48 191 54
M_B_DQ53 DQ58 VSS
193 55
M_B_DQ51 DQ59 VSS
180 60
B M_B_DQ55 DQ60 VSS B
182 61
M_B_DQ54 192
DQ61 VSS
65
Layout Note:
M_B_DQ50 DQ62 VSS
194
DQ63 VSS
66 Place these Caps near SO-DIMMA.
71 DDR_VREF_S3 1D35V_S3
5 M_B_DQS#[7:0] VSS 5 DDR_WR_VREF02
M_B_DQS#1 10 72
M_B_DQS#3 DQS0# VSS
27 127

1
M_B_DQS#5 DQS1# VSS
45 128
M_B_DQS#7 DQS2# VSS R1312 R1306
62 133
M_B_DQS#0 DQS3# VSS 1K8R2F-GP
135 134
M_B_DQS#4 152
DQS4# VSS
138
0R2J-2-GP
DY
M_B_DQS#2 DQS5# VSS 2R2F-GP
169 139

2
M_B_DQS#6 DQS6# VSS R1305
186 144
DQS7# VSS
5 M_B_DQS[7:0] 145 1 2 M_VREF_DQ_DIMMB
M_B_DQS1 VSS
12 150
M_B_DQS3 DQS0 VSS
29 151

1
M_B_DQS5 DQS1 VSS C1321
47 155
M_B_DQS7 DQS2 VSS SCD022U16V2JX-GP R1303
64 156
M_B_DQS0 DQS3 VSS 1K8R2F-GP
137 161

2
M_B_DQS4 DQS4 VSS
154 162
M_B_DQS2 DQS5 VSS +V_VREF_PATH2
171 167

2
1
M_B_DQS6 DQS6 VSS
188 168
DQS7 VSS R1310
172
VSS 24D9R2F-L-GP
116 173
12 M_B_DIMB_ODT0 ODT0 VSS
120 178
12 M_B_DIMB_ODT1 ODT1 VSS
179

2
VSS
M_VREF_CA_DIMMB 126 184
VREF_CA VSS
M_VREF_DQ_DIMMB 1 185
VREF_DQ VSS
189
Layout Note: 30
VSS
190
4,12 DDR3_DRAMRST# RESET# VSS
All VREF traces should VSS
195
have width=20mil; 196
VSS
SCD1U10V2KX-5GP
C1319

0D675V_S0 203 205


1

spacing=20 mil VTT1 VSS


204 206
VTT2 VSS
DY
2

DDR3-204P-90-GP

A A
close to dimm

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM2
Size Document Number Rev
A2 X00

sualaptop365.edu.vn
OAK14 Haswell
Date: Tuesday, May 28, 2013 Sheet 13 of 104
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

M3
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: Thursday, January 10, 2013 Sheet 14 of 104
5 4 3 2 1
5 4 3 2 1

SSID = CPU

D D

3D3V_S0

1
2
RN1501
HSW_ULT_DDR3L 9 OF 19
CPU1I SRN2K2J-1-GP

4
3
53 eDP_BKLT_CTRL B8 EDP_BKLCTL DDPB_CTRLCLK B9 PCH_HDMI_CLK 54
TP1503 1eDP_BKLEN A9 C9
EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA PCH_HDMI_DATA 54
TP1502 1eDP_VDDEN C6 D9
EDP_VDDEN DDPC_CTRLCLK
DDPC_CTRLDATA D11
RN1503
1 4 DGPU_HOLD_RST#
2 OPS 3 DGPU_PW R_EN 20 PIRQA# U6
PIRQB# PIRQA#/GPIO77
P4 PIRQB#/GPIO78 DDPB_AUXN C5
PIRQC# N4 B6
SRN10KJ-5-GP PIRQD# PIRQC#/GPIO79 DISPLAY DDPC_AUXN
N2 PIRQD#/GPIO80 DDPB_AUXP B5
C R1509 1 DGPU_PW ROK
DY 2 10KR2J-3-GP TP1501 1 PCI_PME# AD4 A6 C
PME# PCIE DDPC_AUXP
U7 GPIO55
82,83 DGPU_PW R_EN L1 GPIO52
73 DGPU_HOLD_RST# L3 GPIO54 DDPB_HPD C8 HDMI_PCH_DET 54
82,83 DGPU_PW ROK R5 GPIO51 DDPC_HPD A8
L4 GPIO53 EDP_HPD D6 EDP_HPD 53

1
EC1501 EC1502
SC1KP25V2JX-GP SC1KP25V2JX-GP

2
3D3V_S0
HASW ELL-6-GP

RN1505
1 8 PIRQC#
2 7 PIRQD#
3 6 CLK_PCIE_W LAN_REQ3# 18,58
4 5 PIRQB#

SRN10KJ-6-GP

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH ( EDP/GPIO/DDI )
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: Thursday, March 07, 2013 Sheet 15 of 104
5 4 3 2 1
5 4 3 2 1

SSID = PCH
PCIE Table
Port Device Share BUS

1 TBD USB3.0_3
D D

2 TBD USB3.0_4
USB 2.0 Table
3 WLAN Pair Device

4 LAN 0 USB3.0 port1

5(4lane) GPU 1 USB3.0 Port2

6(4lane) TBD SATA0~3 HSW_ULT_DDR3L


2 USB2.0 Port3
CPU1K 11 OF 19

3 TBD
73 CPU_RXN_C_dGPU_TXN0 F10 PERN5_L0 USB2N0 AN8 USB_PN0 34
73 CPU_RXP_C_dGPU_TXP0 E10 PERP5_L0 USB2P0 AM8 USB_PP0 34
SCD1U10V2KX-5GP 4 CAMERA
73 dGPU_RXN_C_CPU_TXN0 C1606 1 2 dGPU_RXN_CPU_TXN0 C23 AR7 USB_PN1 34
dGPU_RXN_CPU_TXP0 C22 PETN5_L0 USB2N1
73 dGPU_RXP_C_CPU_TXP0 1 2 PETP5_L0 USB2P1 AT7 USB_PP1 34
C1605 5 WLAN
SCD1U10V2KX-5GP F8 AR8
73 CPU_RXN_C_dGPU_TXN1 OPS E8
PERN5_L1 USB2N2
AP8
USB_PN2 63
73 CPU_RXP_C_dGPU_TXP1 OPS PERP5_L1 USB2P2 USB_PP2 63
SCD1U10V2KX-5GP 6 Touch Panel
73 dGPU_RXN_C_CPU_TXN1 C1608 1 2 dGPU_RXN_CPU_TXN1 B23 AR10 USB_PN3 1 TP1601
dGPU_RXN_CPU_TXP1 A23 PETN5_L1 USB2N3 USB_PP3 TP1602
73 dGPU_RXP_C_CPU_TXP1 1 2 PETP5_L1 USB2P3 AT10 1
C C1607 7 Card Reader C
SCD1U10V2KX-5GP H10 GPU AM15
73 CPU_RXN_C_dGPU_TXN2 OPS G10
PERN5_L2 USB2N4
AL15
USB_PN4 52
73 CPU_RXP_C_dGPU_TXP2 OPS PERP5_L2 USB2P4 USB_PP4 52
SCD1U10V2KX-5GP
73 dGPU_RXN_C_CPU_TXN2 C1610 1 2 dGPU_RXN_CPU_TXN2 B21 AM13 USB_PN5 58
dGPU_RXN_CPU_TXP2 C21 PETN5_L2 USB2N5
73 dGPU_RXP_C_CPU_TXP2 1 2 PETP5_L2 USB2P5 AN13 USB_PP5 58
C1609
SCD1U10V2KX-5GP E6 AP11
73 CPU_RXN_C_dGPU_TXN3 OPS F6
PERN5_L3 USB2N6
AN11
USB_PN6 52
73 CPU_RXP_C_dGPU_TXP3 OPS PERP5_L3 USB2P6 USB_PP6 52
SCD1U10V2KX-5GP
73 dGPU_RXN_C_CPU_TXN3 C1612 1 2 dGPU_RXN_CPU_TXN3 B22 AR13 USB_PN7 32
dGPU_RXN_CPU_TXP3 A21 PETN5_L3 USB2N7
73 dGPU_RXP_C_CPU_TXP3 1 2 PETP5_L3 USB2P7 AP13 USB_PP7 32
C1611
SCD1U10V2KX-5GP G11
58 PCIE_PRX_W LANTX_N3 OPS F11
PERN3
G20
58 PCIE_PRX_W LANTX_P3 OPS PERP3 USB3RN1 USB3_PRX_CTX_N0 34
SCD1U10V2KX-5GP H20
C1601 1 PCIE_PTX_W LANRX_N3 USB3RP1 USB3_PRX_CTX_P0 34
58 PCIE_PTX_W LANRX_N3_C 2 C29 PETN3 WLAN PCIE USB
58 PCIE_PTX_W LANRX_P3_C 1 2 PCIE_PTX_W LANRX_P3 B30 C33 USB3_PTX_CRX_N0 34
C1602 PETP3 USB3TN1
USB3TP1 B34 USB3_PTX_CRX_P0 34
30 PCIE_PRX_LANTX_N4 SCD1U10V2KX-5GP F13 PERN4
30 PCIE_PRX_LANTX_P4 G13 PERP4 USB3RN2 E18 USB3_PRX_CTX_N1 34
SCD1U10V2KX-5GP LAN F18
C1603 1 PCIE_PTX_LANRX_N4 USB3RP2 USB3_PRX_CTX_P1 34
30 PCIE_PTX_LANRX_N4_C 2 B29 PETN4
30 PCIE_PTX_LANRX_P4_C 1 2 PCIE_PTX_LANRX_P4 A29 B33 USB3_PTX_CRX_N1 34
C1604 PETP4 USB3TN2
USB3TP2 A33 USB3_PTX_CRX_P1 34
SCD1U10V2KX-5GP G17 PERN1/USB3RN3
F17 PERP1/USB3RP3
C30
Layout Note:
B PETN1/USB3TN3 B
C31 AJ10 USB_COMP 1 2 1. USB_COMP using 50 ohm single-ended impedance
PETP1/USB3TP3 USBRBIAS# R1602
USBRBIAS AJ11 2. Isolation Spacing :15mil
F15 AN10 22D6R2F-L1-GP 3. Total trace length<500mil
PERN2/USB3RN4 RSVD#AN10
G15 PERP2/USB3RP4 RSVD#AM10 AM10

B31 PETN2/USB3TN4
A31 PETP2/USB3TP4
AL3 USB_OC#0_1 USB_OC#0_1 18,35
OC0/GPIO40# USB_OC#2_3
OC1/GPIO41# AT1 USB_OC#2_3 35
AH2 USB_OC#4_5 USB_OC#4_5 20
+V1.05S_AUSB3PLL R1601 OC2/GPIO42# USB_OC#6_7
E15 RSVD#E15 OC3/GPIO43# AV3
3KR2F-GP E13
PCIE_RCOMP RSVD#E13
1 2 A27 PCIE_RCOMP
B27 PCIE_IREF

3D3V_S5_PCH
RN1601
HASW ELL-6-GP USB_OC#2_3 8 1
USB_OC#6_7 7 2
Layout Note: 6 3
18 MCP_GPIO73
1. PCIE_RCOMP/ PCIE_IREF trace width=12~15mil 5 4
17 PM_SUSW ARN#_R
2. Isolation Spacing: 12mil
3. Total trace length<500mil
SRN10KJ-6-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (PCIE/USB)
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: Thursday, March 07, 2013 Sheet 16 of 104
5 4 3 2 1
5 4 3 2 1

SSID = PCH

RN1703
1 4 PM_RSMRST#
D
2 3 PM_PCH_PW ROK PCH strap pin: D

SRN10KJ-5-GP On Die DSW VR Enable R1720 RTC_AUX_S5


R1717 2 1 10KR2J-3-GP SYS_PW ROK 330KR2J-L1-GP
DY DSW ODVREN 1 2
Low = Disable
DSWODVREN High = Enable (default) 1
DY 2
* R1721
330KR2J-L1-GP

3D3V_S0

1
R1701
10KR2J-3-GP
CPU1H HSW_ULT_DDR3L 8 OF 19
2

SYSTEM POWER MANAGEMENT


X01 2/26 Add PH 10K on XDP_DBRESET#
R1704
PM_SUSACK#_R AK2 AW7 DSW ODVREN 0R0402-PAD
XDP_DBRESET# SUSACK# DSWVRMEN PCH_DPW ROK
AC3 AV5 1 2 PM_RSMRST#
96 XDP_DBRESET#
24,96 SYS_PW ROK SYS_PW ROK AG2
SYS_RESET# DPWROK
AJ5 PCH_W AKE# NON DS3
1 DY 2 PCIE_W AKE# 24,30
R1706 SYS_PWROK WAKE#
24,26,36 PCH_PW ROK 1 2 0R0402-PAD PM_PCH_PW ROK AY7
PCH_PWROK
R1705 X01 2/26 DY for OBFF disable
1 2 MPW ROK AB5 0R2J-2-GP
R1707 0R0402-PAD PCI_PLTRST# APWROK PM_CLKRUN# R1709 2 0R0402-PAD
AG7 PLTRST# CLKRUN#/GPIO32 V5 1 PM_CLKRUN#_EC 24
C AG4 PM_SUS_STAT#1 C
SUS_STAT#/GPIO61 SUS_CLK TP1702 R1710 2 0R0402-PAD
SUSCLK/GPIO62 AE6 1 PCH_SUSCLK_KBC 24
AP5 PM_SLP_S5# 1
PM_RSMRST# SLP_S5#/GPIO63 TP1703
AW6 RSMRST#
PM_SUSW ARN#_R AV4
16 PM_SUSW ARN#_R PM_PW RBTN# SUSWARN#/SUSPWRDNACK#/GPIO30 PM_SLP_S4#
24,96 PM_PW RBTN# AL7 PWRBTN# SLP_S4# AJ6 PM_SLP_S4# 24,49
24,76 AC_PRESENT AC_PRESENT AJ8 AT4 PM_SLP_S3# PM_SLP_S3# 24,36,48,49,51
BATLOW # ACPRESENT/GPIO31 SLP_S3# PM_SLP_A#
20 BATLOW # AN4 BATLOW#/GPIO72 SLP_A# AL5 1
1 PCH_SLP_S0# AF3 AP4 PM_SLP_SUS# TP1704 PM_SLP_SUS# 24,38
TP1706 PCH_SLP_W LAN# AM5 SLP_S0# SLP_SUS# PM_SLP_LAN# 1
1 SLP_WLAN#/GPIO29 SLP_LAN# AJ7
TP1705 TP1707

R1713
0R0402-PAD
24,30,58,65,73,96 PLT_RST# 1 2 PCI_PLTRST#
HASW ELL-6-GP
1

R1715 C1701
100KR2J-1-GP SC220P50V2KX-3GP
DY DY
2
2

3D3V_S5 PCH_DPW ROK R1718 1 2 0R2J-2-GP


RN1702 DY KBC_DPW ROK 24
RN1701 2 3 PM_SUSACK#_R
24 PM_SUSACK# DY

2
1 4 MCP_GPIO12 MCP_GPIO12 20 24 PM_SUSW ARN# 1 4 PM_SUSW ARN#_R
2 3 AC_PRESENT DYR1725
SRN0J-6-GP 100KR2F-L1-GP
SRN10KJ-5-GP
B B
X01 2/26 modify PCH_WAKE# PU to 1K

1
1 R1703 2 10KR2J-3-GP PCH_W AKE#
DS3
3D3V_S5_PCH 3D3V_S0
Non DS3 R1714
8K2R2F-1-GP
1 2 PM_SUS_STAT# PM_CLKRUN# 1 2
R1724 DY 10KR2J-3-GP 3D3V_AUX_S5 R1727
100KR2J-1-GP
1 2 PCH_SUSCLK_KBC
2

EMI 12/20

2
XDP_DBRESET# R1726
SYS_PW ROK 10KR2J-3-GP EC1701
PLT_RST# SC4D7P50V2CN-1GP DY

1
PCH_PW ROK 1KR2J-1-GP
Q1701
1

KBC_DPW ROK R1702


4 3 PM_RSMRST# 1 2 RSMRST#_KBC 24
R1728
3V_5V_POK# 5 2 3V_5V_POK_C 1 2 3V_5V_POK 45
1

6 1 0R2J-2-GP
EC1706 EC1702 EC1703 EC1704 EC1705 Non DS3
SC1KP25V2JX-GP

SC1KP25V2JX-GP

SC1KP25V2JX-GP

SC1KP25V2JX-GP

SC1KP25V2JX-GP

DY
2

2N7002KDW -GP R1729 1 PM_SLP_SUS#


2
0R2J-2-GP
A DS3 <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (PM)
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: Monday, June 03, 2013 Sheet 17 of 104
5 4 3 2 1
5 4 3 2 1

SSID = PCH

X02 4/16 Change value from test report

R1810
C1801
D 0R0402-PAD D
XTAL24_IN 1 2 XTAL24_IN_R 2 1

3D3V_S0 SC15P50V2JN-2-GP

1
RN1801
1 8 MCP_GPIO76 MCP_GPIO76 20 X1801

1
2 7 PEG_CLKREQ# XTAL-24MHZ-86-GP
3 6 CLK_PCIE_REQ# R1802
1MR2J-1-GP 82.30004.891
4 5 BOARD_ID1 20
CPU1F HSW_ULT_DDR3L 6 OF 19 2nd = 82.30004.841

4
SRN10KJ-6-GP
C1802

2
XTAL24_OUT 2 1

C43 A25 XTAL24_IN


CLKOUT_PCIE_N0 XTAL24_IN XTAL24_OUT SC15P50V2JN-2-GP
C42 B25
CLK_PCIE_REQ# CLKOUT_PCIE_P0 XTAL24_OUT +V1.05S_AXCK_LCPLL
U2
PCIECLKRQ0#/GPIO18
K21
RSVD#K21
B41 CLKOUT_PCIE_N1 RSVD#M21 M21
A41 C26 XCLK_BIASREF R1803 1 2 3KR2F-GP
CLK_PCIE_REQ# CLKOUT_PCIE_P1 DIFFCLK_BIASREF RN1803
Y5 PCIECLKRQ1#/GPIO19
C35 MCP_TESTLOW1 4 1
CLOCK TESTLOW_C35 MCP_TESTLOW2 RN1804
C41 C34 3 2
CLKOUT_PCIE_N2 TESTLOW_C34 MCP_TESTLOW3
B42 CLKOUT_PCIE_P2 TESTLOW_AK8 AK8 3 2
CLK_PCIE_REQ# AD1 SIGNALS AL8 MCP_TESTLOW4 SRN10KJ-5-GP 4 1
PCIECLKRQ2#/GPIO20 TESTLOW_AL8 SRN10KJ-5-GP
58 CLK_PCIE_WLAN_N3 B38 AN15 CLK_PCI_LPC_R R1804 1 DY 2 0R2J-2-GP CLK_PCI_LPC 65
CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_KBC_R R1805 1
C37 AP15 2 33R2J-2-GP
58 CLK_PCIE_WLAN_P3
15,58 CLK_PCIE_WLAN_REQ3# CLK_PCIE_WLAN_REQ3# N1
CLKOUT_PCIE_P3
PCIECLKRQ3#/GPIO21
WLAN CLKOUT_LPC_1 CLK_PCI_KBC 24
B35 PCIE_CLK_XDP_N 96
CLKOUT_ITPXDP#
30 CLK_PCIE_LAN_N4 A39 A35 PCIE_CLK_XDP_P 96
CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
B39
C
30 CLK_PCIE_LAN_P4
20,30 CLK_PCIE_LAN_REQ4# CLK_PCIE_LAN_REQ4# U5
CLKOUT_PCIE_P4
PCIECLKRQ4#/GPIO22
LAN C

EC1801
SC10P50V2JN-4GP

EC1802
SC10P50V2JN-4GP
73 CLK_PCIE_VGA# B37
CLKOUT_PCIE_N5

1
73 CLK_PCIE_VGA
PEG_CLKREQ#
A37
CLKOUT_PCIE_P5 GPU 1128 Add EC1801 EC1802(DY)
T2
73 PEG_CLKREQ# PCIECLKRQ5#/GPIO23 DY DY

2
HASWELL-6-GP
3D3V_S5_PCH

RN1807
LPC_AD[3..0] SML1_CLK 8 1
24,65 LPC_AD[3..0] HSW_ULT_DDR3L
RN1806 CPU1G 7 OF 19 SML1_DATA 7 2
LPC_AD0 8 1 SML0_DATA 6 3
LPC_AD2 7 2 LPC_LAD0_PCH AU14 AN2 MCP_GPIO11 SML0_CLK 5 4
LPC_AD1 LPC_LAD1_PCH LAD0 SMBALERT#/GPIO11 SMB_CLK
6 3 AW12 AP2
LPC_AD3 LPC_LAD2_PCH LAD1 SMBCLK SMB_DATA SRN2K2J-4-GP
5 4 AY12 LPC AH1
LPC_LAD3_PCH LAD2 SMBUS SMBDATA CARD_PWR_EN
AW11 AL2
SRN0J-7-GP LPC_LFRAME#_PCH LAD3 SML0ALERT#/GPIO60 SML0_CLK
AV12 LFRAME# SML0CLK AN1 SML0_CLK 53
AK1 SML0_DATA RN1809
SML0DATA SML0_DATA 53
AU4 MCP_GPIO73 MCP_GPIO73 16 SRN10KJ-6-GP
0R0402-PAD1 R1801 SML1ALERT#/PCHHOT#/GPIO73 SML1_CLK CARD_PWR_EN
24,65 LPC_FRAME# 2 SML1CLK/GPIO75 AU3 SML1_CLK 24,26,53,76 8 1
AH3 SML1_DATA 16,35 USB_OC#0_1 7 2
SML1DATA/GPIO74 SML1_DATA 24,26,53,76
24,25 SPI_CLK_R 33R2J-2-GP 1 2 R1806 PCH_SPI_CLK AA3 20,24 EC_SCI# 6 3
0R0402-PAD1 SPI_CLK
24,25 SPI_CS0#_R 2 R1807 PCH_SPI_CS0# Y7 AF2 TP_CL_CLK 1 TP1803 MCP_GPIO11 5 4
SPI_CS0# CL_CLK TP_CL_DATA1 TP1804
Y4 SPI_CS1# CL_DATA AD2
AC2 SPI C-LINK AF4 TP_CL_RST# 1 TP1805
0R0402-PAD1 R1808 PCH_SPI_SI SPI_CS2# CL_RST#
24,25 SPI_SI_R 2 AA2
0R0402-PAD1 R1809 PCH_SPI_SO SPI_MOSI RN1811
24,25 SPI_SO_R 2 AA4 SPI_MISO
0R0402-PAD1 2 R1811 PCH_SPI_DQ2 Y6 SMB_CLK 4 1
25 SPI_WP# SPI_IO2
0R0402-PAD1 2 R1812 PCH_SPI_DQ3 AF1 SMB_DATA 3 2
25 SPI_HOLD# SPI_IO3
B B
SRN2K2J-3-GP

3D3V_S5 3D3V_S0
1203 R1806 change to 33R
HASWELL-6-GP
RN1810
2
1

3 2 3D3V_S0
RN1802 4 1
SRN1KJ-11-GP-U
SRN10KJ-5-GP

Q1801
3
4

PCH_SPI_DQ3 SMB_DATA 6 1 PCH_SMBDATA 12,13,62,96


PCH_SPI_DQ2
5 2
84.2N702.A3F
4 3 2nd = 84.DM601.03F
3rd = 84.2N702.E3F
2N7002KDW-GP 4th = 84.2N702.F3F

PCH_SMBCLK 12,13,62,96

SMB_CLK

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
PCH (CLOCK/SMBUS/CL/LPC/SPI)Rev
Document Number
Custom X00
OAK14 Haswell
Date: Wednesday, April 17, 2013 Sheet 18 of 104
5
sualaptop365.edu.vn 4 3 2 1
5 4 3 2 1

SSID = CPU
RTC_X1

1 2 RTC_X2
R1915 10MR2J-L-GP
X01 3/7 Change value from test report
X1901

1 4

D
RTC_AUX_S5 D

2
2 3 C1904
C1903 SC15P50V2JN-2-GP
SC15P50V2JN-2-GP

1
X-32D768KHZ-65-GP X01 3/7 Change value from test report

1
RTC_AUX_S5 R1903 R1901 82.30001.A41
330KR2J-L1-GP 1MR2J-1-GP 2nd = 82.30001.841

2
2
1
RN1901
CPU1E HSW_ULT_DDR3L 5 OF 19
SRN20KJ-1-GP

RTC_X1 AW5

3
4
RTC_X2 RTCX1
AY5 RTCX2
Q1901 SM_INTRUDER# AU6 J5 SATA3_PRX_HDDTX_N0 56
PCH_INTVRMEN AV7 INTRUDER# SATA_RN0/PERN6_L3
24 RTCRST_ON G INTVRMEN SATA_RP0/PERP6_L3 H5 SATA3_PRX_HDDTX_P0 56
SRTC_RST# AV6 RTC B15 SATA3_PTX_HDDRX_N0 56
SRTCRST# SATA_TN0/PETN6_L3 HDD1
1

D RTC_RST# AU7 A15 SATA3_PTX_HDDRX_P0 56


R1902 RTCRST# SATA_TP0/PETP6_L3

2
10KR2J-3-GP S SATA_RN1/PERN6_L2 J8 SATA_PRX_ODDTX_N2 56

1
C1901 G1901 H8 SATA_PRX_ODDTX_P2 56
SATA_RP1/PERP6_L2 ODD

1
SC2D2U6D3V2MX-GP
2N7002K-2-GP C1902 A17 SATA_PTX_ODDRX_N2 56
2

SATA_TN1/PETN6_L2

GAP-OPEN
84.2N702.J31 SC1U6D3V2KX-GP B17 SATA_PTX_ODDRX_P2 56 0114 Change

2
C SATA_TP1/PETP6_L2 C
2ND = 84.2N702.031

2
3rd = 84.07002.I31 HDA_BITCLK AW8 J6
HDA_SYNC HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
AV11 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 H6
HDA_RST# AU8 B14
HDA_SDIN0 HDA_RST#/I2S_MCLK# AUDIO SATA SATA_TN2/PETN6_L1
27 HDA_SDIN0 AY10 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 C15
AU12 HDA_SDI1/I2S1_RXD
HDA_SDOUT AU11 F5
TP1902 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
1203 R1907 change from 0R to 33R 1TP_HDA_DOCK_EN# AW10 HDA_DOCK_EN#/I2S1_TXD# SATA_RP3/PERP6_L0 E5
AV10 HDA_DOCK_RST#/I2S1_SFRM# SATA_TN3/PETN6_L0 C17
AY8 I2S1_SCLK SATA_TP3/PETP6_L0 D17
27 HDA_CODEC_BITCLK R1907 1 2 33R2J-2-GP HDA_BITCLK

27 HDA_CODEC_SYNC R1908 1 2 0R0402-PAD HDA_SYNC V1 EC_SMI# EC_SMI# 24


SATA0GP/GPIO34 +V1.05S_ASATA3PLL
SATA1GP/GPIO35 U1 SATA_ODD_PRSNT# 56
27,29 HDA_CODEC_RST# R1911 1 2 0R0402-PAD HDA_RST# V6
SATA2GP/GPIO36 R1904
SATA3GP/GPIO37 AC1
X02 4/8 Change from 0 to 33 ohm TP1901 1 PCH_JTAG_TRST# AU62 0R2J-2-GP
PCH_JTAG_TCK PCH_TRST# SATA_IREF
AE62 PCH_TCK SATA_IREF A12 1 2
Flash Descriptor Security Overide/ 27 HDA_CODEC_SDOUT R1912 1 2 33R2J-2-GP HDA_SDOUT PCH_JTAG_TDI AD61 L11
PCH_JTAG_TDO PCH_TDI RSVD#L11
Intel ME Debug Mode AE61 PCH_TDO RSVD#K10 K10
24 ME_UNLOCK R1909 1 2 1KR2J-1-GP PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP 1 2
PCH_TMS SATA_RCOMP SATA_LED#
Low = Default * AL11 RSVD#AL11 SATALED# U3 SATA_LED# 61
HDA_SDOUT High = Enable AC4 R1906
XDP_TCK_JTAGX RSVD#AC4 3KR2F-GP
AE63 JTAGX
The internal pull-down is disabled after AV2 RSVD#AV2
PLTRST# deasserts

B Layout Note: B
R1913 HASW ELL-6-GP 4mil trace at break-out and 3
1 2 PCH_INTVRMEN 1D05S_VCCST 12-15mil trace with <0.2 ohms
DY and length total <= 500mils.
330KR2J-L1-GP
2
DY 1 PCH_JTAG_TDI
R1916 51R2J-2-GP
2 1 PCH_JTAG_TDO
Integrated SUS 1V VRM Enable R1917 DY 51R2J-2-GP 3D3V_S0
2 1 PCH_JTAG_TMS
Low = External VRs R1918 DY 51R2J-2-GP RN1902
INTVRMEN 2 1 XDP_TCK_JTAGX SATA_ODD_PRSNT# 1 4
High = Internal VRs* R1919 DY 1KR2J-1-GP EC_SMI# 2 3

SRN10KJ-5-GP

EC1901

1 2 HDA_CODEC_BITCLK
DY 1 2 PCH_JTAG_TCK
R1920 DY 51R2J-2-GP
SC10P50V2JN-L1-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (RTC/SATA/HDA/JTAG)
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: Thursday, April 25, 2013 Sheet 19 of 104
5 4 3 2 1
5 4 3 2 1

SSID = CPU 1D05S_VCCST

1
HSW_ULT_DDR3L 10 OF 19
CPU1J R2018
1KR2J-1-GP

2
18 MCP_GPIO76 MCP_GPIO76 P1 D60 PCH_THERMTRIP
MCP_GPIO8 BMBUSY#/GPIO76 THRMTRIP# H_RCIN#
AU2 GPIO8 RCIN#/GPIO82 V4 H_RCIN# 24
MCP_GPIO12 AM7 T4 INT_SERIRQ INT_SERIRQ 24
17 MCP_GPIO12 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ
D MCP_GPIO15 AD6 AW15 PCH_OPIRCOMP 1 2 D
GPIO15 MISC PCH_OPI_RCOMP
Y1 GPIO16 RSVD#AF20 AF20
3D3V_S5 T3 AB21 R2003
56 SATA_ODD_DA#
25 RTC_DET# RTC_DET# AD5
GPIO17 RSVD#AB21 49D9R2F-GP Layout Note:
RN2006 MCP_GPIO27 GPIO24
AN5 GPIO27
1.Referenced "continuous" VSS plane only.
1 4 BATLOW # BATLOW # 17 MCP_GPIO28 AD7 2.Avoid routing next to clock pins or noisy
MCP_GPIO27 MCP_GPIO26 GPIO28
2 3 AN3 GPIO26
R6
signals.
SRN10KJ-11-GP-U MCP_GPIO56 GSPI0_CS#/GPIO83 3. Trace width: 12~15mil
AG6 GPIO56 GSPI0_CLK/GPIO84 L6
MCP_GPIO57 AP1 GPIO57 GSPI0_MISO/GPIO85 N6 SATA_ODD_PW RGT 56 4. Isolation Spacing: 12mil
MCP_GPIO58 AL4 L8 LPSS_GSPI0_MOSI_BBS0_R 5. Max length: 500mil
W LAN_PLT_RST# GPIO58 GSPI0_MOSI/GPIO86
AT5 GPIO59 GSPI1_CS#/GPIO87 R7
MCP_GPIO44 AK4 GPIO L5
MCP_GPIO47 GPIO44 GSPI1_CLK/GPIO88
AB6 GPIO47 GSPI1_MISO/GPIO89 N7
18 BOARD_ID1 BOARD_ID1 U4 K2 KB_DET# 62
BOARD_ID2 GPIO48 GSPI_MOSI/GPIO90
Y3 GPIO49 UART0_RXD/GPIO91 J1
P3 GPIO50 UART0_TXD/GPIO92 K3 DBC_EN 52
3D3V_S5_PCH HSIOPC Y2 J2 3D3V_S0
21 HSIOPC HSIOPC/GPIO71 SERIAL IO UART0_RTS#/GPIO93
A00 4/9 MCP_GPIO13 AT3 G1 RN2002
MCP_GPIO14 GPIO13 UART0_CTS#/GPIO94 SRN10KJ-6-GP
AH4 GPIO14 UART1_RXD/GPIO0 K4
2

TP2002 1CAMERA_PW R_EN AM4 G2 H_RCIN# 8 1


R2013 MCP_GPIO45 GPIO25 UART1_TXD/GPIO1
AG5 GPIO45 UART1_RST#/GPIO2 J3 56 SATA_ODD_DA# 7 2
10KR2J-3-GP MCP_GPIO46 AG3 J4 BLUETOOTH_EN 58 INT_SERIRQ 6 3
GPIO46 UART1_CTS#/GPIO3 I2C0_SDA KB_DET#
I2C0_SDA/GPIO4 F2 5 4
24 EC_SW I# EC_SW I# AM3 F3 I2C0_SCL
1

EC_SCI# GPIO9 I2C0_SCL/GPIO5 I2C1_SDA


18,24 EC_SCI# AM2 GPIO10 I2C1_SDA/GPIO6 G4
0R0402-PAD-1-GP 1 2 R2001 MCP_GPIO58 TP2001 1HDD_DEVSLP P2 F1 I2C1_SCL
0R0402-PAD-1-GP 1 R2002 MCP_GPIO44 DEVSLP0/GPIO33 I2C1_SCL/GPIO7
2 C4 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 E3
MCP_R

0R0402-PAD-1-GP 1 2 R2004 MCP_GPIO46 L2 F4 3D3V_S0


C 0R0402-PAD-1-GP 1 R2009 MCP_GPIO26 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 LPSS_SDIO_D0_CMNHDR C
2 N5 DEVSLP2/GPIO39 SDIO_D0/GPIO66 D3
0R0402-PAD-1-GP 1 2 R2010 MCP_GPIO56 27 HDA_SPKR HDA_SPKR V2 E4 RN2007
0R0402-PAD-1-GP 1 R2015 MCP_GPIO45 SPKR/GPIO81 SDIO_D1/GPIO67 SRN10KJ-6-GP
2 SDIO_D2/GPIO68 C3
0R0402-PAD-1-GP 1 2 R2016 MCP_GPIO14 E2 I2C0_SCL 8 1
0R0402-PAD-1-GP 1 R2017 MCP_GPIO28 SDIO_D3/GPIO69 I2C0_SDA
2 7 2
0R0402-PAD-1-GP 1 2 R2019 MCP_GPIO8 I2C1_SCL 6 3
0R0402-PAD-1-GP 1 2 R2020 MCP_GPIO13 HASW ELL-6-GP I2C1_SDA 5 4
0R0402-PAD-1-GP 1 2 R2021 MCP_GPIO47
0R0402-PAD-1-GP 1 2 R2022 MCP_GPIO57 3D3V_S0
HSIOPC R2007 1 2
RN2011 100KR2J-1-GP
SRN10KJ-6-GP PCH strap pin:
3D3V_S5_PCH 1 8 CLK_PCIE_LAN_REQ4# 18,30
RN2012 2 7 PIRQA# PIRQA# 15 NO REBOOT
SRN10KJ-6-GP 3 6 DBC_EN 3D3V_S0
1 8 EC_SW I# 4 5 BLUETOOTH_EN 1KR2J-1-GP
2 7 Low = Disable (Default) R2006
3 6 RTC_DET#
USB_OC#4_5 16
HDA_SPKR
* 1 2 HDA_SPKR
4 5 W LAN_PLT_RST#
High = Enable DY
The internal pull-down is disabled after
PLTRST# deasserts

3D3V_S0

B
Top-Block Swap Override mode B

1
High = Enable "Top-Block swap" R2011
SDIO_D0 mode (Default)
DY 1KR2J-1-GP
/ GPIO66 Low = Disable "Top-Block swap" mode
*

2
LPSS_SDIO_D0_CMNHDR
The internal pull-down is disabled after
PLTRST# deasserts
BIOS strap pin:
3D3V_S0 Need SW double confirm if that's needed Top-Block swap
BIOS UMA/DIS Strap pin
1

3D3V_S5_PCH
BOARD_ID1 BOARD_ID2
OPS R2005
10KR2J-3-GP
TLS Confidentiality

1
UMA 1 0 *Low = Disable Intel ME Crypto TLS R2014
DY
2

GPIO15 High = Enable Intel ME Crypto TLS 1KR2J-1-GP


BOARD_ID2
DIS 1 1

2
The internal pull-down is disabled after MCP_GPIO15
1

R2008
RSMRST# deasserts.
10KR2J-3-GP
DY
2

A
3D3V_S0 <Core Design> A

Boot BIOS Strap Bit BBS


Wistron Corporation
1

Boot BIOS Low = SPI R2012 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
* DY 1KR2J-1-GP Taipei Hsien 221, Taiwan, R.O.C.
Destination High = LPC
Title
2

The internal pull-down is disabled after LPSS_GSPI0_MOSI_BBS0_R


PLTRST# deasserts
PCH (GPIO/CPU)
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Need double confirm, GPIO table set to GPI if that's needed PH or PL
Date: Monday, June 03, 2013 Sheet 20 of 104
5 4 3 2 1
5 4 3 2 1

SSID = CPU DSW 20121019


3D3V_S5_PCH

+3.3A_DSW _PRTCSUS 1 R2102 2


0R0402-PAD

1
D
+V1.05DX_MODPHY_PCH C2109 D
HSW_ULT_DDR3L 13 OF 19
CPU1M SC1U6D3V2KX-GP

2
+V1.05DX_MODPHY_PCH K9
1D05V_S0 R2105 VCCHSIO
L10 VCCHSIO
0R0402-PAD M9 RTC_AUX_S5
+V1.05S_AIDLE VCCHSIO HSIO RTC
1 2 N8 VCC1_05 VCCSUS3_3 AH11
P9 VCC1_05 VCCRTC AG10
+V1.05S_AUSB3PLL B18 AE7 +VCCRTCEXT C2110 1 2
VCCUSB3PLL DCPRTC

1
C2105
SC1U6D3V2KX-GP
+V1.05S_ASATA3PLL B11 VCCSATA3PLL SCD1U10V2KX-5GP 3D3V_S5
DY

2
TP2102 1 TP_VCCAPLLOPI_VAL Y20 SPI Y8
RSVD#Y20 VCCSPI
+V1.05S_APLLOPI AA21 VCCAPLL
OPI

1
W21 C2147
VCCAPLL SCD1U10V2KX-5GP
VCCASW AG14
AG13
DSW 20121019 1D05V_S0

2
VCCASW
TP2107 1 +V1.05A_VCCUSB3SUS J13 USB3
3D3V_S5_PCH +V3.3A_1.5A_HDA DCPSUS3
VCC1_05 J11 +V1.05S_CORE_PCH
VCC1_05 H11
1 R2108 2 +V3.3A_1.5A_HDA AH14 HDA H15
VCCHDA VCC1_05 R2110 C2114
VCC1_05 AE8

1
C2116
SC1U6D3V2KX-GP
0R0402-PAD AF22 5D1R2F-GP SC1U6D3V2KX-GP
TP2108 +V1.05A_USB2SUS VRM VCC1_05
1 AH13 DCPSUS2 DCPSUSBYP#AG19 AG19 +PCH_VCCDSW 1 2PCH_VCCDSW _R 1 2
CORE AG20

2
DCPSUSBYP#AG20
VCCASW AE9 +1.05M_ASW
VCCASW AF9
3D3V_S5 +V3.3A_DSW _P 3D3V_S0 AC9 AG8
+V3.3A_PSUS VCCSUS3_3 VCCASW
C AA9 VCCSUS3_3
GPIO/LPC
DCPSUS1#AD10 AD10 +V1.05A_SUS_PCH1 TP2106 C
1 R2101 2 +V3.3A_DSW _P +V3.3A_DSW _P AH10 VCCDSW3_3 DCPSUS1#AD8 AD8
1 R2112 2 +V3.3S_PCORE V8 VCC3_3
0R0402-PAD W9 3D3V_S0
VCC3_3
1

1
C2136 0R0402-PAD C2123 J15 1D5V_S0
THERMAL SENSOR VCCTS1_5
DY SCD1U10V2KX-5GP SC10U6D3V3KX-GP
VCC3_3 K14
K16
2

2
VCC3_3

C2128
SC1U6D3V2KX-GP
1
+V1.05S_AXCK_DCB J18 VCCCLK
1D05V_S0 +V1.05S_SSCF100 K19 SERIAL IO U8 +V3.3S_1.8S_LPSS_SDIO

2
VCCCLK VCCSDIO
+V1.05S_AXCK_LCPLL A20 VCCACLKPLL VCCSDIO T9
1 R2117 2 +V1.05S_SSCF100 +V1.05S_SSCF100 J17 VCCCLK
+V1.05S_SSCFF R21 VCCCLK
C2137
SC1U6D3V2KX-GP

0R0402-PAD T21 LPT LP POWER


VCCCLK
1

1 TP_V1.05S_SSCF100 K18 SUS OSCILLATOR AB8 +V1.05A_AOSCSUS 1 TP2109


TP2103 RSVD#K18 DCPSUS4
1 TP_V1.05S_AXCK_DCB M20 RSVD#M20
TP2104 1 TP_V1.05S_SSCFF V21
2

TP2101 RSVD#V21
+V3.3A_PSUS AE20 VCCSUS3_3 RSVD#AC20 AC20 TP_V1.05S_APLLOPI 1 TP2105
AE21 VCCSUS3_3 VCC1_05 AG16 1D05V_S0
USB2 AG17
VCC1_05

1
C2135
SC1U6D3V2KX-GP
2
HASW ELL-6-GP

1D05V_S0 +V1.05S_SSCFF

B B
1 R2118 2 +V1.05S_SSCFF
C2138
SC1U6D3V2KX-GP

0R0402-PAD
1

1D05V_S0 R2122 1D05V_HSIO


0R0805-PAD-1-GP
2

1 2
Non-HSIO

+V3.3S_1.8S_LPSS_SDIO 3D3V_S0
R2123
1 2 HSIOPC_R 1 R2103 2
20 HSIOPC
DY
0R0402-PAD

1
0R2J-2-GP 1D05V_HSIO
9

U2101 C2104
SC1U6D3V2KX-GP
ON

2
5V_S5 1 8 R2114
VDD GND HSIO_OUT
1D05V_S0 2 D#2 S#7 7 1 0R5J-5-GP
2
3 D#3 S#6 6
4 D#4 S#5 5 DY
DY

1
SLG59M1470VTR-GP C2142
DY 74.59147.093 SC10U6D3V5KX-1GP
1

2
C2141 DY
SC4D7U6D3V3KX-GP
A <Core Design> A
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (POWER2)
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: Monday, June 03, 2013 Sheet 21 of 104
5 4 3 2 1
5 4 3 2 1

SSID = PCH

D D

HSW_ULT_DDR3L
CPU1Q 17 OF 19

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3


DC_TEST_AY3_AW3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 TP_DC_TEST_A4 TP2202
AY3 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 A4 1
TP2201 1TP_DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY60
DC_TEST_AY61_AW61 AY61 A60 TP_DC_TEST_A60 1 TP2203
DC_TEST_AY62_AW62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 DC_TEST_A61_B61
AY62 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A61
TP2204 1TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 A62 TP_DC_TEST_A62 1 TP2205
DC_TEST_A3_B3 B3 AV1 TP_DC_TEST_AV1 1 TP2206
DC_TEST_A61_B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 TP_DC_TEST_AW1 TP2207
B61 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW1 1
DC_TEST_B62_B63 B62 AW2 DC_TEST_AY2_AW2
DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 DC_TEST_AY3_AW3
B63 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW3
DC_TEST_C1_C2 C1 AW61 DC_TEST_AY61_AW61
DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 DC_TEST_AY62_AW62
C2 DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW62
AW63 TP_DC_TEST_AW63 1 TP2208
C
DAISY_CHAIN_NCTF_AW63 C
HASWELL-6-GP

HSW_ULT_DDR3L
CPU1R 18 OF 19

RSVD#N23 N23
RSVD#R23 R23
RSVD#T23 T23
AT2 RSVD#AT2
RSVD#U10 U10
AU44 RSVD#AU44
AV44 RSVD#AV44
D15 RSVD#D15
RSVD#AL1 AL1
RSVD#AM11 AM11
RSVD#AP7 AP7
F22 RSVD#F22
RSVD#AU10 AU10
H22 RSVD#H22
B
RSVD#AU15 AU15 B
J21 RSVD#J21
RSVD#AW14 AW14
RSVD#AY14 AY14

HASWELL-6-GP

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4 X00
OAK14 Haswell
sualaptop365.edu.vn Date: Thursday, January 10, 2013 Sheet 22 of 104
5 4 3 2 1
5 4 3 2 1

SSID = PCH

D D

HSW_ULT_DDR3L 14 OF 19 HSW_ULT_DDR3L 15 OF 19
CPU1N CPU1O

A11 VSS VSS AJ35 AP22 VSS VSS AV59


A14 VSS VSS AJ39 AP23 VSS VSS AV8
A18 VSS VSS AJ41 AP26 VSS VSS AW16
A24 VSS VSS AJ43 AP29 VSS VSS AW24
A28 VSS VSS AJ45 AP3 VSS VSS AW33
A32 VSS VSS AJ47 AP31 VSS VSS AW35
A36 VSS VSS AJ50 AP38 VSS VSS AW37
A40 VSS VSS AJ52 AP39 VSS VSS AW4
A44 VSS VSS AJ54 AP48 VSS VSS AW40
A48 VSS VSS AJ56 AP52 VSS VSS AW42
A52 VSS VSS AJ58 AP54 VSS VSS AW44
A56 VSS VSS AJ60 AP57 VSS VSS AW47
AA1 VSS VSS AJ63 AR11 VSS VSS AW50
AA58 VSS VSS AK23 AR15 VSS VSS AW51
AB10 VSS VSS AK3 AR17 VSS VSS AW59
AB20 VSS VSS AK52 AR23 VSS VSS AW60
AB22 VSS VSS AL10 AR31 VSS VSS AY11
AB7 VSS VSS AL13 AR33 VSS VSS AY16
AC61 VSS VSS AL17 AR39 VSS VSS AY18
AD21 VSS VSS AL20 AR43 VSS VSS AY22
AD3 VSS VSS AL22 AR49 VSS VSS AY24
AD63 VSS VSS AL23 AR5 VSS VSS AY26
AE10 VSS VSS AL26 AR52 VSS VSS AY30
C AE5 AL29 AT13 AY33 C
VSS VSS VSS VSS
AE58 VSS VSS AL31 AT35 VSS VSS AY4
AF11 VSS VSS AL33 AT37 VSS VSS AY51
AF12 VSS VSS AL36 AT40 VSS VSS AY53
AF14 VSS VSS AL39 AT42 VSS VSS AY57
AF15 VSS VSS AL40 AT43 VSS VSS AY59
AF17 VSS VSS AL45 AT46 VSS VSS AY6
AF18 VSS VSS AL46 AT49 VSS VSS B20
AG1 VSS VSS AL51 AT61 VSS VSS B24
AG11 VSS VSS AL52 AT62 VSS VSS B26
AG21 VSS VSS AL54 AT63 VSS VSS B28
AG23 VSS VSS AL57 AU1 VSS VSS B32
AG60 VSS VSS AL60 AU16 VSS VSS B36
AG61 VSS VSS AL61 AU18 VSS VSS B4
AG62 VSS VSS AM1 AU20 VSS VSS B40
AG63 VSS VSS AM17 AU22 VSS VSS B44
AH17 VSS VSS AM23 AU24 VSS VSS B48
AH19 VSS VSS AM31 AU26 VSS VSS B52
AH20 VSS VSS AM52 AU28 VSS VSS B56
AH22 VSS VSS AN17 AU30 VSS VSS B60
AH24 VSS VSS AN23 AU33 VSS VSS C11
AH28 VSS VSS AN31 AU51 VSS VSS C14
AH30 VSS VSS AN32 AU53 VSS VSS C18
AH32 VSS VSS AN35 AU55 VSS VSS C20
AH34 VSS VSS AN36 AU57 VSS VSS C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
B B
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
AH51 VSS VSS AN48 AV33 VSS VSS D18
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
AH57 VSS VSS AN52 AV39 VSS VSS D23
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31

HASW ELL-6-GP

HASW ELL-6-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: Thursday, January 10, 2013 Sheet 23 of 104
5 4 3 2 1
SSID = KBC 5 4 3 2 1
VBAT 3D3V_AUX_KBC
VBAT MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
VBAT PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
R2402 UMA 100.0K 10.0K(64.10025.6DL) 3.0V
X02 4/8 Change to A00 X00 100.0K 10.0K 3.0V TBD 100.0K 13.7K(64.13725.6DL) 2.902V

1
VBAT 1 2 R2446 R2445 R2405 TBD 100.0K 17.8K(64.17825.6DL) 2.801V

1
X01 100.0K 20.0K 2.75V 64K9R2F-1-GP 57K6R2F-GP 10KR2F-2-GP TBD 100.0K 22.1K(64.22125.6DL) 2.702V

2
0R0603-PAD-1-GP R2404 TBD 100.0K 27.0K(64.27025.6DL) 2.598V
R2403 64K9R2F-1-GP X02 100.0K 33.0K 2.48V TBD 100.0K 32.4K(64.32425.6DL) 2.492V
N14P-GV2 N14M-GE DY
2D2R3-1-U-GP TBD 100.0K 37.4K(64.37425.6DL) 2.402V

2
X03 100.0K 47.0K 2.24V TBD 100.0K 43.2K(64.43225.6DL) 2.304V

2
3D3V_AUX_KBC_VCC DIS 100.0K 49.9K(64.49925.6DL) 2.201V

1
PCB_VER_AD A00 100.0K 64.9K 2.0V MODEL_ID_DET N14M-GE 100.0K 57.6K(64.57625.6DL) 2.093V
N14P-GV2 100.0K 64.9K(64.64925.6DL) 2.001V

1
Reserved 100.0K 76.8 1.87V TBD 100.0K 73.2K(64.73225.6DL) 1.905V

2
R2406 R2407 TBD 100.0K 82.5K(64.82525.6DL) 1.808V

2
1D05V_S0 100KR2F-L1-GP Reserved 100.0K 100.0K 1.65V C2403 100KR2F-L1-GP TBD 100.0K 93.1K(64.93125.6DL) 1.709V
DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP
C2404

C2405

C2406

C2407

C2408

C2409

C2410

C2411
R2401 C2402 SCD1U10V2KX-5GP TBD 100.0K 107K(64.10735.6DL) 1.594V
DY

1
1

1
D 1 2 EC_VTT SCD1U10V2KX-5GP Reserved 100.0K 143.0K 1.358V TBD 100.0K 120K(64.12035.6DL) 1.499V
D

2
0R0402-PAD-1-GP TBD 100.0K 137K(64.13735.6DL) 1.392V
DY DY DY
1
Reserved 100.0K 174.0K 1.204V TBD 100.0K 154K(64.15435.6DL) 1.299V

2
C2401
TBD 100.0K 200K(64.20035.6DL) 1.099V

SCD1U10V2KX-5GP
2 EC_AGND Reserved 100.0K 215.0K 1.048V EC_AGND TBD 100.0K 232K(64.23236.6DL) 0.994V

Layout Note:
Need very close to EC
EC_AGND

ECSCI#_KBC 0R0402-PAD-1-GP 1 2 R2408 EC_SCI# 18,20


KBC24
ECSMI#_KBC 0R0402-PAD-1-GP 1 2 R2409 EC_SMI# 19
KROW[0..7] 62
19 54 KROW0
VCC KBSIN0/GPIOA0/N2TCK KROW1 ECSWI#_KBC 0R0402-PAD-1-GP
46 55 1 2 R2410 EC_SWI# 20
VCC KBSIN1/GPIOA1/N2TMS KROW2
76 56
3D3V_S0 VCC KBSIN2/GPIOA2 KROW3
88 57
VCC KBSIN3/GPIOA3 KROW4
115 58
VCC KBSIN4/GPIOA4 KROW5
59
KBSIN5/GPIOA5 KROW6
102 60
AVCC KBSIN6/GPIOA6 KROW7
61
KBSIN7/GPIOA7
4 KCOL[0..16] 62
VDD
1

EC_VTT 12 53 KCOL0
44 AD_IA VTT KBSOUT0/GPOB0/SOUT_CR/JENK#
C2412 C2413 52 KCOL1
SCD1U10V2KX-5GP DY SC2D2U10V3KX-1GP KBSOUT1/GPIOB1/TCK
51 KCOL2
2

C2414 KBSOUT2/GPIOB2/TMS KCOL3


EC_AGND 1 2 SCD1U10V2KX-5GP 97 50
PCB_VER_AD GPIO90/AD0 KBSOUT3/GPIOB3/TDI KCOL4
98 49
GPIO91/AD1 KBSOUT4/GPOB4/JEN0# KCOL5
42 PSID_EC 99 48
GPIO92/AD2 KBSOUT5/GPIOB5/TDO KCOL6
58 CARD_WPAN_OUT# 100 47
GPIO93/AD3 KBSOUT6/GPIOB6/RDY# KCOL7 3D3V_AUX_KBC
17,38 PM_SLP_SUS# 108 43
GPIO5/AD4 KBSOUT7/GPIOB7 KCOL8
44 BOOST_MON 96 42 RN2401
GPIO4/AD5 KBSOUT8/GPIOC0 KCOL9
44 DIS_DTM 95 41
MODEL_ID_DET GPIO3/EXT_PURST#/AD6 KBSOUT9/GPOC1/SDP_VIS# KCOL10 BAT_SCL
94 40 3 2
GPIO7/AD7/VD_IN2 KBSOUT10/P80_CLK/GPIOC2 KCOL11 BAT_SDA
X01 3/5 move WPAN_LED# from GPIO85 to GPIO93 KBSOUT11/P80_DAT/GPIOC3
39 4 1
38 KCOL12
KBSOUT12/GPO64/TEST# KCOL13 SRN4K7J-8-GP
26 FAN1_DAC_1 101 37
GPIO94/DA0 KBSOUT13/GPI/O63/TRIST# KCOL14
44 AD_IA_HW 105 36
GPIO95/DA1 KBSOUT14/GPI/O62/XORTR# KCOL15
106 35
C 76 EC_FB_CLAMP_TGL_REQ#
7,46 IMVP_PWRGD 107
GPIO96/DA2
GPIO97/DA3
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
34
33
KCOL16 ECRST# R2418 1 2 10KR2J-3-GP C
BAT_SCL 70 LPC_AD[3..0] 18,65
43,44 BAT_SCL BAT_SDA GPIO17/SCL1/N2TCK LPC_AD0
43,44 BAT_SDA 69 126
GPIO22/SDA1/N2TMS LAD0/GPIOF1 LPC_AD1
18,26,53,76 SML1_CLK 67 127
GPIO73/SCL2/N2TCK LAD1/GPIOF2 LPC_AD2
18,26,53,76 SML1_DATA 68 128
GPIO74/SDA2/N2TMS LAD2/GPIOF3 LPC_AD3 3D3V_AUX_KBC
30 PM_LAN_ENABLE 119
GPIO23/SCL3/N2TCK LAD3/GPIOF4
1 A00 4/3 change R2414 from 100K to 10K
19 RTCRST_ON 120 2 CLK_PCI_KBC 18
PROCHOT_EC GPIO31/SDA3/N2TMS LCLK/GPIOF5 R2416 AC_IN# R2413 1
24 3 2 100KR2J-1-GP
52 LCD_TST_EN
LCD_TST_EN 28
GPIO47/SCL4/N2TCK LFRAME#/GPIOF6
7 PLT_RST#_EC
LPC_FRAME# 18,65
1 2 PLT_RST# 17,30,58,65,73,96
BAT_IN# R2414 1 DY 2 10KR2J-3-GP
GPIO53/SDA4/N2TMS LRESET#/GPIOF7 0R0402-PAD-1-GP
75,76,83 EC_FB_CLAMP 26
R2417 1 ECSWI#_KBC GPIO51/TA3/N2TCK AC_IN_KBC# R2426 1
52 LCD_TST 2 123 2100KR2J-1-GP

2
0R0402-PAD-1-GP GPIO67/N2TMS EC_SPI_CS#_C
90 2 R2419 1 33R2J-2-GP
F_CS0# EC_SPI_CLK_C 2 R2420 1 33R2J-2-GP
SPI_CS0#_R 18,25 0111 Add
72
F_SCK
92
109
SPI_CLK_R 18,25 DY C2415
SC220P50V2KX-3GP
62 TPCLK

1
GPIO37/PSCLK1 GPIO30/F_WP# CAP_LED# 62
71 80 BAT_IN#
62 TPDATA GPIO35/PSDAT1 GPIO41/F_WP# BAT_IN# 42,43,44 3D3V_S0
10 87 EC_SPI_DI_C 2 R2422 1 33R2J-2-GP
36 ALL_SYS_PWRGD GPIO26/PSCLK2 F_SDIO/F_SDIO0 SPI_SI_R 18,25
42 PWR_CHG_AD_OFF 11 86 EC_SPI_DO_C 2 R2423 1 33R2J-2-GP
GPIO27/PSDAT2 F_SDI/F_SDIO1 SPI_SO_R 18,25
44 AD_IA_HW2 25 91 PM_SUSACK# 17
GPIO50/PSCLK3/TDO GPIO81/F_WP#/F_SDIO2 FAN_TACH1 R2415 1
52 BLON_OUT 27 77 PCH_SUSCLK_KBC 17 2 10KR2J-3-GP
GPIO52/PSDAT3/RDY# GPIO0/EXTCLK/F_SDIO3 TOUCH_PANEL_INTR# R2443 1 2 10KR2J-3-GP
3D3V_AUX_S5
26 FAN_TACH1 31
GPIO56/TA1 PSL_IN1#/GPI70
73 PSL_IN1#
Layout Note: Power Switch Logic(PSL)
117 93 PSL_IN2#
17,96 PM_PWRBTN#

2
GPIO20/TA2/IOX_DIN_DIOPSL_IN2#/GPI6/EXT_PURST# PSL_OUT#
61 WLAN_LED# 63
GPIO14/TB1 PSL_OUT#/GPIO71
74 Need very close to EC
17,36,48,49,51 PM_SLP_S3# 64 R2425
GPIO1/TB2
330KR2J-L1-GP
29 ECSCI#_KBC 3D3V_S5
ECSCI#/GPIO54 ECRST# R2427
61 PWRLED# 32 85

1
GPIO15/A_PWM EXT_RST# PSL_IN2#
27 KBC_BEEP 118 122 H_RCIN# 20 61 KBC_PWRBTN# 1 2
GPIO21/B_PWM KBRST#/GPIO86
52 EC_BRIGHTNESS 62
65
GPIO13/C_PWM
75 SC1U25V3KX-1-GP
0R0402-PAD-1-GP LID_CLOSE# R2421 1 DY 2100KR2J-1-GP
42 AC_IN_KBC# GPIO32/D_PWM VSBY 3D3V_AUX_S5
22 114 EC_VBKUP R2428 1 2 C2416
76 OVER_CURRENT_P8# GPIO45/E_PWM VBKUP RTC_AUX_S5
16 44 KBC_VCORF 0R0402-PAD-1-GP 1 2 R2430
61 CHG_AMBER_LED# GPIO40/F_PWM/1_WIRE VCORF
Don't PD 17 KBC_DPWROK 81 13 PECI 1 2 44 AC_IN# 1 2 PSL_IN1#
GPIO66/G_PWM PECI H_PECI 4
66 125 INT_SERIRQ 20 R2429 0R0402-PAD-1-GP
GPO33/H_PWM/VD1_EN# SERIRQ/GPIOF0

C2422
SC100P50V2JN-3GP
6 ECSMI#_KBC 43R2J-GP

1
GPIO24
ALL_SYS_PWRGD assert, 17,26,36 PCH_PWROK 104
GPIO80/VD_IN1 GPIO36/TB3
15 BATT_WHITE_LED# 61
delay 10ms; PCH_PWROK assert. DY
35 USB_PWR_EN# 110 21 PM_SLP_S4# 17,49

2
B ALL_SYS_PWRGD de-assert, 17,76 AC_PRESENT 112
GPIO82/IOX_LDSH/VD_OUT1
GPIO84/IOX_SCLK/VD_OUT2
GPIO44/TDI
GPIO43/TMS
GPIO42/TCK
20
17
RSMRST#_KBC 17
LID_CLOSE# 64
B
delay 100ms; SYS_PWROK assert. 23 ME_UNLOCK 19
GPIO46/CIRRXM/TRST#
84
17,96 SYS_PWROK
58 CARD_WLAN_OUT# 83
GPIO77/SPI_MISO
113 PCIE_WAKE# 17,30
Layout Note:
GPIO76/SPI_MOSI GPIO87/CIRRXM/SIN_CR
LVDS backlight Control from PS8625 58 WIFI_RF_EN 82
GPIO75/SPI_SCK GPIO34/CIRRXL
14 S5_ENABLE 36 Need very close to EC
79 3D3V_AUX_S5 C2417 3D3V_AUX_S5
17 PM_SUSWARN# GPIO2/SPI_CS# C2422 PDG is 47p SCD1U10V2KX-5GP
A00 4/9 move PCIE_WAKE# from GPO33 to GPIO83

2
5
GND R2431
52 TOUCH_PANEL_INTR# 124 18 1 2
GPIO10/LPCPD# GND
121 45 330KR2J-L1-GP
GPIO85/GA20 GND
58 E51_TxD 111 78
R2444 L_BKLT_EN_EC GPIO83/SOUT_CR GND
53 L_BKLT_EN 1 2 9 89

S
1
GPIO65/SMI# GND R2432
0R0402-PAD-1-GP 116

2
GND PSL_OUT# KBC_ON#_GATE_L KBC_ON#_GATE
17 PM_CLKRUN#_EC 8 1 2 1 2 G
GPIO11/CLKRUN# G
R2434
30 103
eDP backlight Control from Travis
27 AMP_MUTE# GPIO55/CLKOUT/IOX_DIN_DIO AGND R2433 DY 0R2J-2-GP
1

1KR2J-1-GP 20KR2F-L-GP Q2402 D


Travis request response time < 1ms NPCE985PA0DX-1-GP R2435 DMP2130L-7-GP

1
D
0R0402-PAD-1-GP 84.02130.031
2ND = 84.03413.A31
71.00985.C0G
2

3D3V_AUX_KBC 3D3V_AUX_KBC
EC_AGND
Layout Note:

1
Connect GND and AGND planes via either
R2436
0R resistor or connect directly.
10KR2J-3-GP
Q2403
EC_AGND G

2
D S5_ENABLE

EC_GPIO47 High Active S


3D3V_AUX_S5
R2424 2N7002K-2-GP
R2438 0R2J-2-GP 84.2N702.J31
1

0R2J-2-GP 1 2 ECRST# 2ND = 84.2N702.031


1 2 R2439 DY 3rd = 84.07002.I31
DY 10KR2J-3-GP 4th = 84.2N702.W31

A Q2401 C2418
A
2

PROCHOT_EC G R2440 SC1U6D3V2KX-GP


E

0R0402-PAD-1-GP
D H_PROCHOT#_EC 1 2 H_PROCHOT# 4,42,44,46 26,36,76 PURE_HW_SHUTDOWN# B DY
2
1

R2442 S Q2404
C
1

100KR2J-1-GP C2421 MMBT3906-4-GP <Core Design>


DY 2N7002K-2-GP SC47P50V2JN-3GP 84.T3906.A11
84.2N702.J31 DY 2nd = 84.03906.F11
Wistron Corporation
2

2ND = 84.2N702.031
3rd = 84.07002.I31 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
4th = 84.2N702.W31 Taipei Hsien 221, Taiwan, R.O.C.

Title

KBC Nuvoton NPCE885


Size Document Number Rev

sualaptop365.edu.vn OAK14 Haswell


A2
X00
Date: Monday, June 03, 2013 Sheet 24 of 104

5 4 3 2 1
5 4 3 2 1

SSID = Flash.ROM

SPI Flash ROM(8M) for PCH 3D3V_S5 3D3V_S5

1
D
1203 RN2501 DY C2501 C2502
D

DY

4
3
SC10U6D3V5KX-1GP SCD1U10V2KX-5GP

2
R2501 RN2501
4K7R2J-2-GP
DY SRN4K7J-8-GP Single SPI shared flash connection (SPI Quad I/O mode)

1
2
SPI25 3D3V_S5

18,24 SPI_CS0#_R 1 CS# VCC 8


18,24 SPI_SO_R 2 DO/IO1 HOLD#/IO3 7 SPI_HOLD# 18
18 SPI_W P# 3 WP#/IO2 CLK 6 SPI_CLK_R 18,24
4 GND DI/IO0 5 SPI_SI_R 18,24
1

1
W 25Q64FVSSIQ-GP
EC2502 DY 72.25Q64.K01 EC2501 EC2503
SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP DY DY SC10P50V2JN-4GP
2

2
C C
3D3V_S5
SKT25
Source QUAD/DUAL fast read DUAL fast read
SPI_CS0#_R 1 8
SPI_SO_R 2 DY 7 SPI_HOLD#
SPI_W P# 3 6 SPI_CLK_R 72.25Q64.K01 O O
4 5 SPI_SI_R

SKT-G6179HT0321-001-GP 72.25Q64.F01 O O
62.10089.011 Refer to "NCPE985x/ NPCE995x board design reference guide"
72.25Q64.D01 O O

SSID = RBATT
+RTC_VCC 3D3V_AUX_S5 RTC_AUX_S5

B TPAD14-OP-GP TP2502 B
1 +RTC_VCC

D2501
1

RTC1 R2502 3
1KR2J-1-GP
1 2 1 RTC_PW R 2
PWR

1
2 C2503
GND BAS40-05-7-F-1-GP
NP1 NP1 SCD47U6D3V2KX-GP
NP2 NP2 2
75.00040.A7D
BAT-060003HA002M213ZL-GP-U1
1 TP2501 2nd = 75.00040.C7D
TPAD14-OP-GP
62.70014.001

Q2505
A G <Core Design> A
1

D RTC_DET# 20
R2504
10MR2J-L-GP S Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2N7002K-2-GP Taipei Hsien 221, Taiwan, R.O.C.
2

84.2N702.J31
2ND = 84.2N702.031 Title
3rd = 84.07002.I31
4th = 84.2N702.W31 Flash/RTC
Size Document Number Rev
A3

sualaptop365.edu.vn OAK14 Haswell X00


Date: Monday, June 03, 2013 Sheet 25 of 104
5 4 3 2 1
5 4 3 2 1

SSID = Thermal

Fan controller1
5V_S0
R2605 FAN261
0R2J-2-GP
3D3V_S0 3D3V_S0 1 2 FON# 1 8
D
DY D

SC4D7U6D3V3KX-GP
FSM# GND

C2605

C2611
2 7

SCD1U10V2KX-5GP
5V_S0 VIN GND
FAN_VCC1 3 6
VOUT GND

1
24 FAN1_DAC_1 4 VSET GND 5

1
2

2
RN2602 APL5606AKI-TRG-GP
SRN2K2J-1-GP 74.05606.A71
2nd = 74.02113.0E1
3D3V_S0 Layout Note:

4
3
Need 10 mil trace width.
6 1 THM_SML1_DATA
18,24,53,76 SML1_DATA
5 2 R2606 FAN1
SC10U6D3V3KX-GP

84.2N702.A3F
C2601

C2602

0R0402-PAD-1-GP 5
SCD1U10V2KX-5GP
1

4 3 2nd = 84.DM601.03F 24 FAN_TACH1 1 2 FAN_TACH1_C 3


DY 3rd = 84.2N702.E3F 2
Q2601 4th = 84.2N702.F3F
2

2N7002KDW -GP FAN_VCC1 1


THM_SML1_CLK 4

C2603
SC2200P50V2KX-2GP
2
ETY-CON3-8-GP

1
C2604 D2601 20.F1841.003
18,24,53,76 SML1_CLK Layout Note: SC4D7U6D3V3KX-GP
84.03904.L06 Signal Routing Guideline: DY DY DY

2
2ND = 84.03904.P11 Trace width = 15mil AFTP2803 1

1
NCT7718_DXP
C THM26 CH551H-30PT-GP C
3

1 8 THM_SML1_CLK 83.R5003.C8F
C2606 C2607 VDD SCL THM_SML1_DATA
1 2 D+ SDA 7 2ND = 83.R5003.H8H
Q2603 SC470P50V3JN-2GP SC2200P50V2KX-2GP 3 6 ALERT# 3rd = 83.5R003.08F
DY
2

PMBS3904-1-GP T_CRIT# D- ALERT#


4 5

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
2

T_CRIT# GND

1
C2608

C2609
NCT7718_DXN

2.System Sensor, Put on palm rest NCT7718W -GP DY DY

2
74.07718.0B9
1

AFTP2802 1FAN_TACH1_C
R2601 AFTP2801 1FAN_VCC1
0R0402-PAD-1-GP
1203 change to ALL_SYS_PWRGD
Q2602
Layout Note: 17,24,36 PCH_PW ROK G
2

C2812 close U2801


D
PURE_HW _SHUTDOW N# 24,36,76
THERM_SYS_SHDN# S
FAN_TACH1

1
Layout Note: 2N7002K-2-GP C2610 FAN_VCC1
Both DXN and DXP routing 10 mil trace width and 10 mil spacing. 84.2N702.J31 DY SCD1U10V2KX-5GP

2
2ND = 84.2N702.031

1
EC2602 EC2601
3rd = 84.07002.I31
4th = 84.2N702.W31

SC10P50V2JN-L1-GP

SCD1U10V2KX-5GP
2

2
3D3V_S0 A00 4/10 modify R2603 to 10.5K
B B

R2603 1 2 10K5R2F-GP ALERT#

R2604 1 2 2KR2F-3-GP T_CRIT#

DY DY

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3

5
sualaptop365.edu.vn 4 3 2
Date:
OAK14 Haswell
W ednesday, April 17, 2013 Sheet
1
26 of 104
X00
5 4 3 2 1

SSID = AUDIO

29 LINE1_VREFO_R MIC2_VREFO 29
D D
29 LINE1_VREFO_L AUD_AGND

SC2D2U6D3V2MX-GP
29 AUD_HP1_JACK_L
3D3V_S0 25mA +3V_AVDD
29 AUD_HP1_JACK_R
EC27071 2 SC1KP25V2JX-GP
R2701 EC27061 2 SC1KP25V2JX-GP

1 C2705
1 2 EC27051 2 SC1KP25V2JX-GP
SC1U10V2KX-1GP EC27041 2 SC1KP25V2JX-GP
0R0402-PAD-1-GP C2704 EC27031 2 SC1KP25V2JX-GP

1
1 2

1
C2701 C2702
SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP +5V_AVDD 5V_S0
2 Close pin36 AUD_AGND

2