Modbus 3720

3720 ACM
Advanced Digital Power

Instrumentation Package
3720 ACM / Modicon Modbus

Serial Communications Protocol
and Register Map
Version 1.3
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3720 ACM Modbus Protocol and Register Map Power Measurement Ltd.
Revision History
The following versions of this document have been released:
- Revision 1.0 March 5, 1996: Initial Release
- Revision 1.1 May 5, 1997: Minor errors corrected
- Revision 1.2 August 14, 1997: Added waveform recorder, MPCC/MPE
- Revision 1.3 May, 1998: Minor corrections

TABLE OF CONTENTS
1. INTRODUCTION..............................................................................................................................................................1
1.1 PURPOSE OF THE COMMUNICATIONS PROTOCOL...........................................................................................................1
2. MODBUS IMPLEMENTATION .....................................................................................................................................1
2.1 GROUND RULES ............................................................................................................................................................1
2.2 MODES OF TRANSMISSION ............................................................................................................................................1
2.3 DESCRIPTION OF THE MODBUS PACKET STRUCTURE .....................................................................................................2
2.3.1 Slave Address Field..............................................................................................................................................2
2.3.2 Function Field......................................................................................................................................................2
2.3.3 Data Field ............................................................................................................................................................2
2.3.4 Error Check Field (Checksum) ............................................................................................................................2
2.4 EXCEPTION RESPONSES ................................................................................................................................................3
2.5 BROADCAST PACKETS ..................................................................................................................................................3
3. PACKET COMMUNICATIONS .....................................................................................................................................4
3.1 FUNCTION 03: READ HOLDING REGISTERS (16-BIT)......................................................................................................4
3.2 FUNCTION 16: PRESET MULTIPLE REGISTERS (16-BIT) .................................................................................................5
3.3 EXTENDED (32-BIT) MODE PACKET COMMUNICATIONS ...............................................................................................6
3.4 32-BIT VALUE FORMAT: ...............................................................................................................................................6
3.4.1 Normal (Mod-10000) Format 32-bit Values........................................................................................................6
3.4.2 Special (Long word) Format 32-bit Values..........................................................................................................6
3.5 ENERGY HOUR VALUE FORMATS .................................................................................................................................9
3.5.1 16-Bit Mode Energy Hours Format .....................................................................................................................9
3.5.2 32-Bit Mode Energy Hours Format .....................................................................................................................9
3.6 PASSWORD PROTECTION ...............................................................................................................................................9
3.7 INVALID REGISTERS ......................................................................................................................................................9
3.8 16-/32-BIT MODE MISMATCH .....................................................................................................................................10
4. 3720 ACM MODBUS CONFIGURATION...................................................................................................................11
4.1 UNIT ID (REGISTER 43006) ........................................................................................................................................11
4.2 REGISTER SIZE (REGISTER 43064) ..............................................................................................................................11
4.3 BAUD RATE (REGISTER 43007)...................................................................................................................................11
4.4 INVALID OBJECTS (REGISTER 43065)..........................................................................................................................11
4.5 PASSWORD PROTECT (REGISTER 43066).....................................................................................................................11
4.6 TRANSMIT DELAY (REGISTER 43067) .........................................................................................................................11
5. 3720 ACM MODBUS REGISTERS...............................................................................................................................12
5.1 REAL TIME MEASUREMENTS ......................................................................................................................................12
5.1.1 Power Factor Representation ............................................................................................................................12
5.2 STATUS REGISTERS .....................................................................................................................................................12
5.2.1 Relay Status Registers ........................................................................................................................................12
5.2.2 Status Input Register ..........................................................................................................................................12
5.2.3 Setpoint Status Registers ....................................................................................................................................12
5.2.4 Status Input Counters.........................................................................................................................................12
5.3 HIGH SPEED REGISTERS ..............................................................................................................................................13
5.3.1 High Speed Polarity ...........................................................................................................................................13
5.4 WAVEFORM RECORDER ..............................................................................................................................................13
5.4.1 Waveform Recorder Reading Window ...............................................................................................................13
5.4.2 Loading the Waveform Reading Window...........................................................................................................13
5.4.3 WFR Log Counters: Calculating the WFR Log Index........................................................................................14
5.4.4 Interpreting the WFR Data ................................................................................................................................14
5.5 SETUP REGISTERS .......................................................................................................................................................14
5.5.1 Relay Operation Setup .......................................................................................................................................14
5.5.2 Log Status Input Transitions ..............................................................................................................................15
i
5.5.3 Trigger Waveform Capture ................................................................................................................................15

5.5.4 Preset Status Input Counters..............................................................................................................................15
5.5.5 Sliding Window Keys..........................................................................................................................................15
5.5.6 Modbus Protocol Setup......................................................................................................................................15
5.5.7 Status Input Counter Setup ................................................................................................................................15
5.5.8 Waveform Recorder Depth.................................................................................................................................15
5.5.9 Waveform Recorder Trigger/Rearm...................................................................................................................15
5.5.10 Event Counters...................................................................................................................................................15
5.5.11 Setpoint Registers...............................................................................................................................................16
5.6 WAVEFORM CAPTURE ................................................................................................................................................16
5.6.1 Waveform Read Request ....................................................................................................................................16
5.6.2 Compressed Sample Format ..............................................................................................................................17
5.7 EVENT LOG .................................................................................................................................................................17
5.8 REGISTERS WITH INVALID NUMBERS ..........................................................................................................................17
5.8.1 Representation of Invalid Numbers....................................................................................................................17
5.8.2 Min/Max Registers .............................................................................................................................................17
5.8.3 Sliding Window and Predicted Demand Registers.............................................................................................17
5.8.4 Time of Use Demand Registers ..........................................................................................................................17
APPENDIX A: CRC-16 CALCULATION ............................................................................................................................19
APPENDIX B: 3720 ACM REGISTER MAP.......................................................................................................................23
ii
LIST OF TABLES AND FIGURES
TABLE 2-1: MODBUS FUNCTION SUPPORTED BY THE 3720 ACM.................................................................................................2

TABLE 2-2: EXCEPTION CODES SUPPORTED BY THE 3720 ACM...................................................................................................3
TABLE 4-1: MODBUS CONFIGURATION PARAMETERS .................................................................................................................11
FIGURE 3-1: READ HOLDING REGISTERS (16-BIT MODE) .............................................................................................................4

FIGURE 3-2: PRESET MULTIPLE REGISTERS (16-BIT MODE) .........................................................................................................5
FIGURE 3-3: READ HOLDING REGISTERS (32-BIT MODE) .............................................................................................................7
FIGURE 3-4: PRESET MULTIPLE REGISTERS (32-BIT MODE) .........................................................................................................8
FIGURE 5-1: WAVEFORM CAPTURE PACKET ...............................................................................................................................16
iii
1. INTRODUCTION
2. MODBUS IMPLEMENTATION
The 3720 ACM performs Modbus communications by
emulating the Modicon 984 Programmable Controller. 2.1 Ground Rules
This document describes the Modbus communications
protocol employed by the 3720 ACM and how to pass
The 3720 ACM is capable of communication on both the
information into and out of the 3720 ACM in a Modbus
RS-232C and the RS-485 serial communication standards.
network.
The RS-485 medium allows for multiple devices on a
multi-drop network, whereas RS-232C allows for only a
This document provides information specific to the 3720
single device. The 3720 ACM Modbus protocol is
implementation of the Modbus protocol. For a more
identical for both environments.
detailed description of the Modbus protocol as used with
PML devices, consult the 3710 ACM Modbus protocol
The following rules define the protocol for information
document.
transfer between a Modbus Master device and the 3720
ACM.
It is assumed that the reader is familiar with the Modbus
protocol and serial communications in general.
1) All communications on the communications loop
conforms to a MASTER/SLAVE scheme. In this
scheme, information and data is transferred between a
Modbus MASTER device and up to 32 SLAVE
1.1 Purpose of the Communications monitoring devices for RS-485 and only one SLAVE
Protocol device for RS-232C.
The purpose of the 3720 ACM Modbus communications 2) The MASTER will initiate and control all information
protocol is to allow setup information and measured data transfer on the communications loop.
to be efficiently transferred between a Modbus Master
Station and a 3720 ACM. This includes: 3) Under no circumstances will a SLAVE device initiate
a communications sequence.
1) Allowing configuration and interrogation of all 3720
ACM set-up parameters from a Modbus Master 4) All communications activity on the loop occurs in the
Station. form of “PACKETS”, a packet being simply a serial
string of 8-bit bytes. The maximum number of bytes
2) Allowing interrogation of all data measured by a 3720 contained within one packet is 255.
ACM, including minimum and maximum real time
values and date stamps. 5) All PACKETS transmitted by the MASTER are
REQUESTS. All PACKETS transmitted by a SLAVE
3) Allowing the configuration and interrogation of 3720 device are RESPONSES.
ACM setpoint parameters.
6) At most one SLAVE can respond to a single request
4) Allowing control of the 3720 ACM relays from a MASTER.
5) Allowing the interrogation of the event log.

2.2 Modes of Transmission
The Modbus protocol uses ASCII and RTU modes of

transmission. The 3720 ACM supports only the RTU
mode of transmission, with 8 data bits, no parity, and one
stop bit.
1
2.3 Description of the Modbus packet Example 2.1:

structure
A 16-bit register contains the value 12AB Hex. This
register is transmitted:
Every Modbus packet consists of four fields: High order byte = 12 Hex
Low order byte = AB Hex
1) The Slave Address Field
2) The Function Field This register will be transmitted in the order 12 AB.
3) The Data Field
4) The Error Check Field (Checksum) Example 2.2:
A 32-bit register contains the value 0A1B2C3D Hex.

2.3.1 Slave Address Field This register is transmitted:
High order word: 0A1B Hex
The slave address field of a Modbus packet is one byte in High order byte = 0A Hex
length and uniquely identifies the slave device involved in Low order byte = 1B Hex
the transaction. Valid addresses range between 1 and 247. Low order word: 2C3D Hex
A slave device, when receiving a request packet with the High order byte = 2C Hex
slave address field matching its own address, will perform Low order byte = 3D Hex
the command specified in the packet. A response packet
generated by the slave will have the same value in the This register is transmitted in the order 0A 1B 2C 3D.
slave address field.
2.3.4 Error Check Field (Checksum)

2.3.2 Function Field
The checksum field allows the receiving device to
The function field of a Modbus request packet is one byte determine if a packet has been corrupted with
in length and tells the addressed slave which function to transmission errors. In Modbus RTU mode, a 16-bit
perform. Similarly, the function field of a response packet Cyclic Redundancy Check (CRC-16) is used.
tells the master what function the addressed slave has just
performed. Table 2-1 lists the Modbus functions The sending device calculates a 16-bit value, based on
supported by the 3720 ACM. every byte in the packet, using the CRC-16 algorithm.
The calculated value is inserted in the error check field.
2.3.3 Data Field The receiving device performs the same calculation on the
entire packet it receives, excepting the error check field.
The data field of a Modbus request is of variable length, The resulting value is compared to the error check field.
and depends upon the function. This field contains If the calculated checksum is not equal to the checksum
information required by the slave device to perform the stored in the incoming packet, transmission errors have
command specified in a request packet or data being occurred and corrupted the packet. A bad packet will be
passed back by the slave device in a response packet. ignored by the receiving device.
In general, data in this field are contained in either 16-bit The CRC-16 algorithm is detailed in appendix A of this
or 32-bit registers. In 16-bit mode, registers are document.
transmitted in the order of high-order byte first, low-order
byte second. In 32-bit mode, registers are transmitted in
the order of high-order word first, low-order word second.
This ordering of bytes is called “Big Endian” format.
FUNCTION MEANING ACTION

03 Read Holding Registers Obtains the current value in one or more holding registers of the 3720 ACM.
16 Preset Multiple Registers Places specific values into a series of consecutive holding registers of the 3720
ACM. The holding registers that can be written to a 3720 ACM are shown in the
register map.
Table 2-1: Modbus Function Supported by the 3720 ACM
2
2.4 Exception Responses 2.5 Broadcast Packets
If a Modbus master device sends an invalid command to a The 3720 ACM Modbus protocol supports the use of
3720 ACM or attempts to read an invalid holding register, broadcast request packets. The purpose of a broadcast
an exception response will be generated. The exception request packet is to allow all the Slave devices to receive
response follows the standard packet format. The high the same command from the Master station.
order bit of the function code in an exception response is
set to 1. A broadcast request packet is the same as a normal
request packet, except the slave address field is set to zero
The data field of an exception response contains the (0). All Modbus slave devices will receive and execute a
exception error code. Table 2-2 describes the exception broadcast request command, but no device will respond.
codes supported by the 3720 ACM and their possible
causes. The Preset Multiple Registers command is the only
command supporting broadcast packets.
CODE NAME MEANING

01 Illegal Function An Invalid command is contained in the function field of the request packet. The 3720 ACM
only support Modbus functions 3 and 16. This illegal function code could also indicate that an
incorrect password is used when the user attempts to perform a protected function.
02 Illegal Address The address referenced in the data field is an invalid address for the specified function. This
could also indicate that the registers requested are not within the valid register range of the 3720
ACM.
03 Illegal Value The value referenced in the data field is not allowable for the referenced register on the 3720
ACM.
Table 2-2: Exception Codes supported by the 3720 ACM
3
3. PACKET COMMUNICATIONS must send the slave device a Read Holding Registers
request packet.
This section will illustrate the Modbus functions
The Read Holding Registers request packet specifies a
supported by the 3720 ACM, first in standard (16-bit)
start register and a number of registers to read. The start
mode, then in extended (32-bit) mode.
register is numbered from zero (40001 = zero, 40002 =
one, etc.).
3.1 Function 03: Read Holding The 3720 ACM responds with a packet containing the
Registers (16-bit) values of the registers in the range defined in the request.
To read 3720 ACM parameter values, a Master station Figure 3-1 shows the Read Holding Registers request and
READ HOLDING REGISTERS (16-BIT MODE)
READ REGISTERS REQUEST PACKET READ REGISTERS RESPONSE PACKET

(Master station to 3720 ACM) (3720 ACM to Master station)
Unit ID/Slave Address (1 byte) Unit ID/Slave Address (1 byte)

03 (Function code) (1 byte) 03 (Function Code) (1 byte)
Start Register (sr) (2 bytes) Byte Count (2 x nr) (1 byte)
# of Registers to Read (nr) (2 bytes) First Register in range (2 bytes)
CRC Checksum (2 bytes) Second Register in range (2 bytes)
...
CRC Checksum (2 bytes)
Example 3.1:
A 3720 ACM, in 4-wire WYE volts mode, is configured as a Modbus slave device, with slave address 100. The Master
station requests to read realtime volts, phases A, B, and C. From the register map, those three parameters are Modbus
registers 40011, 40012, and 40013. In accordance with the Modbus protocol, register 40011 is numbered as 10 when
transmitted. The request must read 3 registers starting at 10.
Slave address: 100 = 64 (Hex) Start register: 10 = 000A (Hex)
Request Packet: (The white background denotes the DATA field of the packet.)
Slave Function Start Register (40011) # of Registers (3) CRC Checksum

64* 03 00 0A 00 03 2C 3C
* Note: the values shown in the illustrated packet are all represented in hexadecimal format.
Response Packet:
Slave Function Byte Count Register 1 Register 2

64 03 06 04 AE 04 B0
Register 3 CRC Checksum
04 B5 9D DB
The Master station retrieves the data from the response:

Register 40011: 04AE(hex) = 1198
Register 40012: 04B0(hex) = 1200
Register 40013: 04B5(hex) = 1205
Figure 3-1: Read Holding Registers (16-Bit Mode)
4
response packet formats, and an example transaction. The 3720 ACM responds with a packet indicating that a
write was performed to the range of registers specified in
the request.
3.2 Function 16: Preset Multiple
Registers (16-bit) Figure 3-2 shows the Preset Multiple Registers request
and response packet formats, and an example transaction.
The Preset Multiple Registers command packet allows a Note that, except for the function field, the Preset
Modbus master to configure the 3720 ACM. Registers Response packet is identical in format to the
Read Registers Request packet.
The Preset Multiple Registers request packet contains, as
the data field, a definition of a range of registers to write
to, and the values to write to those registers.
PRESET MULTIPLE REGISTERS (16-BIT MODE)
PRESET REGISTERS REQUEST PACKET PRESET REGISTERS RESPONSE PACKET


Start Register (sr) (2 bytes) Start Register (sr) (2 bytes)
# of Registers to Write (nr) (2 bytes) # of Registers Written (nr) (2 bytes)
Byte Count (2 x nr) (1 byte) CRC Checksum (2 bytes)
First Register in Range (2 bytes)
Second Register in Range (2 bytes)
...
Example 3.2:
A 3720 ACM is configured as a Modbus slave device, with slave address 200. The Master station requests to set the volts
full scale to 1200 and the auxiliary voltage scale to 1000. From the register map, those two parameters are Modbus
registers 43002 and 43003. Register 43002 is numbered 3001. The request must write 2 registers starting at 3001.
Slave address: 200 = C8 (Hex) Start register: 3001 = 0BB9 (Hex)

Value 1: 1200 = 04B0 (Hex) Value 2: 1000 = 03E8 (Hex)
Slave Function Start Register (43002) # of Registers (2) Byte Count

C8* 10 0B B9 00 02 04
Register 1 Register 2 CRC Checksum
04 B0 03 E8 99 77
Response Packet:
Slave Function Start Register (43002) # of Registers (2) CRC Checksum

C8 10 0B B9 00 02 83 90
Figure 3-2: Preset Multiple Registers (16-Bit Mode)
5
3.3 Extended (32-bit) Mode Packet High-Order Register = value

Communications 10000
Low-Order Register = value modulus 10000
Standard Modbus protocol supports only 16-bit registers. The 32-bit value can be retrieved by the following
Measurements and values used by the 3720 are capable of calculation:
exceeding the maximum value (65535) that can be
represented by 16 bits. To accomodate large numbers, an value = registerhigh x 10000 + registerlow
extended 32-bit register mode is implemented in the 3720
ACM. Example 3.3:
The 32-bit register mode in the 3720 ACM Modbus Value 12345678 is passed in normal 32-bit format.
protocol effectively doubles the accessible register map.
Each 32-bit register takes the logical space of two Registerhigh: 1234 = 04D2 Hex
contiguously located 16-bit registers. In 32-bit mode, Registerlow: 5678 = 162E Hex
each entry in the register map actually counts for two 16-
bit registers. Where the map specifies address 4xxxx in Real-time measurements and most setup parameters
16-bit mode, the 32-bit version of the same register map (except energy hour counters) are passed in this format.
entry can be considered to be two registers: 4xxxxhigh and
4xxxxlow. In 32-bit mode, the two 16-bit registers which This configuration is compatible with the Modicon PLC
comprise one 32-bit register can not be divided in floating point format.
communications.
For each 16-bit mode transaction as shown in the previous 3.4.2 Special (Long word) Format 32-bit Values
section, an equivalent 32-bit mode transaction can be
made by doubling the number of registers in the 16-bit
mode version and by doubling the length (in bytes) of A 32-bit register represented in Special format is passed
each register. This also means that the byte count field of via communications as two 16-bit registers:
any packet would also be doubled.
High-Order Register = value
Figure 3-3 on page 7 shows the 32-bit mode Read 65536
Holding Registers request and response packet formats, Low-Order Register = value modulus 65536
and an example transaction.
value = registerhigh x 65536 + registerlow, or
Figure 3-4 on page 8 shows the 32-bit mode Preset value = registerhigh|registerlow
Multiple Registers request and response packet formats,
and an example transaction. Example 3.4:
Value 12345678 is passed in special 32-bit format:
12345678 = 00BC614E Hex

3.4 32-Bit Value Format: Registerhigh = 00BC Hex = 188
Registerlow = 614E Hex = 24910
The 3720 ACM uses three different formats for expressing
values in 32-bit mode: Registers which are passed in Special format are those in
which individual bit-fields in the value have special
1) Normal (Mod-10000) format significance. These include:
2) Special (Long word) format
3) Energy Hours format Time values
Polarity registers
Setpoint setup/status
Counters
3.4.1 Normal (Mod-10000) Format 32-bit Values Status Input Counter Scales/Roll-Overs
Sliding Window Keys
A 32-bit register represented in Normal format is passed Event Logs
via communications two 16-bit registers:
6
READ HOLDING REGISTERS (32-BIT MODE)
READ REGISTERS REQUEST PACKET READ REGISTERS RESPONSE PACKET


Start Register (sr) (2 bytes) Byte Count (2 x nr)2 (1 byte)
# of 16-bit Registers to Read (nr)1 (2 bytes) First 32-bit Register in range:
CRC Checksum (2 bytes) High-Order 16-bit register (2 bytes)
Low-Order 16-bit register (2 bytes)
Second 32-bit Register in range:
High-Order 16-bit register (2 bytes)
...
1
Notes: : nr (# of 16-bit registers) = 2 x # of 32-bit registers
2
: byte count = 2 x nr = 4 x # of 32-bit registers
Example 3.5: (32-bit version of example 3.1)
A 3720 ACM, in 4-wire WYE volts mode, is configured as a Modbus slave device, with slave address 100. The Master
station requests to read realtime volts, phases A, B, and C. From the register map, those three parameters are Modbus
registers 40011, 40012, and 40013. The request must read three 32-bit registers (i.e. six 16-bit registers) starting at 40011
(numbered 10).
Slave address: 100 = 64 (Hex)

Start register: 10 = 000A (Hex)
Slave Function Start Register (40011) # of Registers (2 x 3 = 6) CRC Checksum

64* 03 00 0A 00 06 EC 3F
Response Packet:
Slave Function Byte Count Register 1high Register 1low

64 03 0C 00 00 04 AE
Register 2high Register 2low Register 3high Register 3low
00 00 04 B0 00 00 04 B5
CRC Checksum
40 C0
The Master station retrieves the data from the response:

Register 40011: high: 0000(hex) = 0, low: 04AE(hex) = 1198
Register 40012: high: 0000(hex) = 0, low: 04B0(hex) = 1200
Register 40013: high: 0000(hex) = 0, low: 04B5(hex) = 1205
Figure 3-3: Read Holding Registers (32-Bit Mode)
7
PRESET MULTIPLE REGISTERS (32-BIT MODE)
PRESET REGISTERS REQUEST PACKET PRESET REGISTERS RESPONSE PACKET


Start Register (sr) (2 bytes) Start Register (sr) (2 bytes)
# of 16-bit Registers to Write (nr)1 (2 bytes) # of 16-bit Registers Written (nr)1 (2 bytes)
Byte Count (2 x nr)2 (1 byte) CRC Checksum (2 bytes)
First 32-bit Register in Range:
Second Register in Range:
...
1
Notes: : nr (# of 16-bit registers) = 2 x # of 32-bit registers
2
: byte count = 2 x nr = 4 x # of 32-bit registers
Example 3.6: (32-bit version of example 3.2)
A 3720 ACM is configured as a Modbus slave device, with slave address 200. The Master station requests to set the volts
full scale to 1200 and the auxiliary voltage scale to 1000. From the register map, those two parameters are Modbus
registers 43002 and 43003. The request must write two 32-bit registers (i.e. four 16-bit registers) starting at 43002
(numbered 3001).
Slave address: 200 = C8 (Hex) Start register: 3001 = 0BB9 (Hex)

Value 1high: 0 = 0000 (Hex) Value 1low: 1200 = 04B0 (Hex)
Value 2high: 0 = 0000 (Hex) Value 2low: 1000 = 03E8 (Hex)
Slave Function Start Register (43002) # of 16-bit Registers (2x2) Byte Count
C8* 10 0B B9 00 04 08
Register 1high Register 1low Register 2high Register 2low
00 00 04 B0 00 00 03 E8
CRC Checksum
BB 65
Response Packet:
Slave Function Start Register (43002) # of 16-bit Registers (2x2) CRC Checksum
C8 10 0B B9 00 04 03 92
Figure 3-4: Preset Multiple Registers (32-Bit Mode)
8
3.5 Energy Hour Value Formats 3.6 Password Protection
Energy Hour integrator parameters (40051-40078) are The 3720 ACM supports a password protection mode,
always divided into two registers, regardless of whether which locks the 3720 ACM setup registers, allowing
the register size is set to 16-bit or 32-bit. The values for access only when a valid password has been provided. In
these registers are expressed in engineering units. password protection mode, the password register (address
43010) is protected for a read request, and all writeable
The first register of each pair is the “kilo” component of registers are protected for write requests.
the value. In 16-bit mode, the second register is the
“mega” component of the value, and in 32-bit mode, the Since there is no reserved password field in the Modbus
same register is the “giga” component. protocol, a special procedure is required to access
protected registers.
In 16-bit mode, the maximum expressable value for
energy hours is 65535 MWH/MVARH/MVAH. The correct password must first be written to the Packet
Password register (address 43051) using the Preset
In 32-bit mode, the maximum expressable value for Multiple Registers function. A response packet is always
energy hours is 1000 GWH/GVARH/GVAH. returned for this packet, regardless of whether or not the
password was correct. The user may then perform the
3.5.1 16-Bit Mode Energy Hours Format desired function. If the password previously transmitted
was incorrect, an illegal function (01) exception response
“Kilo” Register = value modulus 1000 is generated; otherwise, the 3720 ACM will perform the
“Mega” Register = value specified command.
1000
The password protection mode is selectable through the
Example 3.7: front panel programming mode and via communications.
kWh Import is reading 123456.

Value for register 40051 (kilo) = 456 kWh
Value for register 40052 (mega) = 123 MWh
3.7 Invalid Registers
Value = 123 MWh + 456 kWh = 123456 kWh.
In the 3720 ACM Modbus register map, there are gaps
between some registers. For example, the next register
3.5.2 32-Bit Mode Energy Hours Format after 40008 is 40011. The unmapped registers 40009 and
40010 are said to be INVALID. Invalid registers store no
32-bit “Kilo” Register = value modulus 1000000 information.
32-bit “Giga” Register = value
1000000 It is sometimes useful to request invalid registers. For
example, if one wishes to read all the real-time power
The 32-bit registers for energy hours are represented in measurements on the 3720 ACM, it is most efficient to
Mod-10000 format. read the whole range from 40011 to 40046 in one request.
Example 3.8: There are two ways that the 3720 ACM can be configured
to respond to a request which includes invalid registers:
kWh Net is reading 123456789.
32-bit “Kilo” Register (40057): 1) Skip Invalids
High Order 16-bit register: 45 2) Return Invalids
Low Order 16-bit register: 6789
32-Bit value = 45x10000 + 6789 = 456789 kWh. If the 3720 ACM is configured to skip invalid registers,
32-Bit “Giga” Register (40058): the next valid register is returned in place of an invalid
High Order 16-bit register: 0 register.
Low Order 16-bit register: 123
32-Bit value = 0 x 10000 + 123 = 123 GWh. If the 3720 ACM is configured to return invalid registers,
a value of zero is returned for an invalid register. This is
Value = 123 GWh + 456789 kWh = 123456789 kWh. the default configuration.
9
Example 3.9:
A request is made to read 6 registers, starting at 40026.

Registers 40027 and 40029 are invalid, according to the
register map. The following table describes the
information included in the response. The first column
shows the order in which the registers are returned. The
second and third columns indicate which register’s value
is returned for the corresponding position in the response.
The invalid registers (highlighted in grey) contain the
value 0.
i Skip Invalids Return Invalids

1 40026 40026
2 40028 (40027)
3 40029 40028
4 40031 40029
5 40032 (40030)
6 40033 40031
This feature of the 3720 ACM Modbus protocol is

configurable through communications and the front panel
programming menu.
3.8 16-/32-bit Mode Mismatch
If the 3720 ACM is configured to 16-bit mode, and a 32-

bit style Modbus request is received, the request will be
processed and responded to as if it is a 16-bit request.
That is, twice the number of 32-bit registers will be
transferred, in 16-bit format. If the response packet is
decoded in 32-bit format, the values extracted from the
packet will be incorrect.
If the 3720 ACM is configured to 32-bit mode, and a 16-

bit style Modbus request is received, the response depends
on how many registers are intended to be transferred.
If the 16-bit request is intended to transfer an even number

of 16-bit registers, then the 3720 ACM will process and
respond to the request as if it is a 32-bit request. That is,
½ the number of 16-bit registers will be transferred, in 32-
bit format. As with the above scenario, if the response
packet is decoded in 16-bit format, the values extracted
from the packet will be incorrect.
If the 16-bit request is intended to transfer an odd number

of 16-bit registers, then the 3720 ACM will see a violation
of the 32-bit request format and respond with an illegal
address exception response.
10
4. 3720 ACM MODBUS CONFIGURATION Via communications, baud rate is selectable by a value
indicating the ordinal position in the baud rate list:
The following setup options, relevant to the Modbus
0 = 300 baud, 1 = 1200 baud, 2 = 2400 baud, etc.
protocol, are available on the 3720 ACM.
PARAMETER NAME MODBUS ADDRESS

Unit ID 43006
4.4 Invalid Objects (Register 43065)
Register Size 43064
Baud Rate 43007 This parameter selects how the 3720 ACM handles a
Invalid Objects 43065 request for an invalid object.
Password Protect 43066
Transmit Delay 43067 If the value is “NO” (front panel) or 0 (communications),
the 3720 ACM will skip invalid registers.
Table 4-1: Modbus Configuration Parameters
If the value is “YES” (front panel) or 1 (communications),
All of these parameters can be accessed via the front panel the 3720 ACM will return invalid registers.
programming menu, as well as via communications.
The default value for this parameter is “YES”.
This option is detailed in section 3.7 of this document.

4.1 Unit ID (Register 43006)
4.5 Password Protect (Register 43066)
The Unit ID parameter defines the slave address used in
Modbus packets for the device in question. Valid range is
from 1 to 247. The Password Protect parameter sets the password
protection mode. Set to “YES” or value 1 enables
See section 2.3.1 for more detail. password protection. Set to “NO” or value 0 disables
password protection.
The default value for this parameter is “NO”.

4.2 Register Size (Register 43064)
See section 3.6 for more detail.
This parameter selects 16-bit or 32-bit register size. Via
communications, value 0 corresponds to 16-bit mode, and
value 1 corresponds to 32-bit mode. 4.6 Transmit Delay (Register 43067)
See section 3.3 for more detail.
The transmit delay parameter defines the time (in
milliseconds) that the 3720 ACM will wait before
transmitting a communications packet, once that packet is
4.3 Baud Rate (Register 43007) ready to send. In some cases it is possible for MPCC or
MPE to respond faster than some communication devices
The baud rate parameter defines the speed of serial can handle. It is recommended that if communication
communications. The following baud rates are supported problems occur to try increasing the transmit delay to see
by the 3720 ACM: if the problems disappear. The default setting is 20 ms.
Via ISOCOMM:
300, 1200, 2400, 4800, 9600, 19200
Via 3720 Multiport Communications Cards (MPCC or

MPE)1:
300, 1200, 2400, 4800, 9600, 19200, 38400, 57600,
115200
1
Contact PML for information regarding 3720 MPCC or
MPE.
11
5. 3720 ACM MODBUS REGISTERS 000000000000 B A
The 3720 ACM Modbus register map defines a set of READING WRITING
parameters which are treated as HOLDING REGISTERS A) 00 = Released 00 = Normal
of the Modicon 984 PLC, having addresses 4xxxx. 01 = Operated 01 = Force Operate
According to the Modbus protocol, in response to a 10 = Forced Released 10 = Force Release
request for register 4xxxx of a particular slave device 11 = Forced Operated
(3720), the Modbus master reads register xxxx-1 from the B) 00 = Relay is latched
slave. For example, register 40011 corresponds to 10 = Relay is pulsed inactive
register 10. 11 = Relay is pulsed active
The following sections will describe in detail the coded

values stored for various registers. The registers will be 5.2.2 Status Input Register
discussed in the order they appear on the 3720 ACM
Modbus Register Map (appendix B). The Status Input Register (40210) indicates the status of
the 3720 ACM Status Inputs (S1-S4).
5.1 Real Time Measurements Bits 15-6 5-4 3 2 1 0

0000000000 E D C B A
All real-time parameters return straight-forward
measurement units, except for one exception: the power A) Status Input #1: 0 = Normal, 1 = Active.
factor parameters are coded differently. B) Status Input #2: 0 = Normal, 1 = Active.
C) Status Input #3: 0 = Normal, 1 = Active.
D) Status Input #4: 0 = Normal, 1 = Active.
5.1.1 Power Factor Representation E) Logical Combination: Bit 6 = NAND, Bit 5 = OR
The 3720 ACM measures LEADING and LAGGING

5.2.3 Setpoint Status Registers
power factors for all phases. These are available via
Modbus as registers 40039-40042.
The Setpoint Status Registers (40211-40227) indicate
Power Factor measurements are represented as a value whether the setpoint is currently active.
from 0 to 200. The value is interpreted as follows:
Bits 15-8 7 6-0
PF Meaning 00000000 A 1111111
0-100 Power Factor = PF (lagging)
100-200 Power Factor = 200-PF (leading) A) Setpoint status: 0 = Inactive, 1 = Active
The setpoint key is defined in the setpoint configuration

section (registers 43301-43470).
5.2 Status Registers
The status registers indicate the state of the 3720 relays, 5.2.4 Status Input Counters
the four status inputs (S1-S4), and the internal setpoints.
When a Status Input on the 3720 ACM makes a transition
from Normal to Active, the counter associated with that
5.2.1 Relay Status Registers input will increment. Registers 40241-40244 indicate the
Status Input Counters.
The Relay Status Registers (40201-40203) indicate and
control the status of the 3720 ACM control relays. A The Status Input Counters are scaleable. Section 5.5.7 of
relay can be forced by writing a new status to the this document explains how to set the scale and roll-over
associated status register. The relay operation status can parameters on the Status Input Counters.
be in two states:
The Status Input Counter values are stored on the 3720
Released: Normally On position is OPEN. ACM as 32-bit values. These values are formatted as a
Operated: Normally On position is CLOSED. “scaled unsigned 30 bit integer”: the upper two bits of the
Bits 15-4 3-2 1-0 long word define a negative exponential multiplier.
12
5.4 Waveform Recorder

Bits 31-30 29-0
B A The 3720 ACM has a programmable Waveform Recorder
30
(WFR) feature, which records up to 36 cycles on 8
A) Integer component: range 0 to 2 -1 channels. Waveform recorder configuration and data
B) Multiplier: 00 = 1, 01 = 0.1, 10 = 0.01, 11 = 0.001 retrieval is available via the Modbus protocol.
The value stored is interpreted as: Since the size of the largest possible waveform recorder
log (36 cycles/channel x 8 channels x 16 samples/cycle =
value = A * 10-B 4608 samples) is prohibitive, a register re-use scheme has
been adopted for reading the waveform recorder logs via
Since this format uses the upper two bits of a 32-bit long Modbus.
word, it is recommended that the multiplier should
always be set to 1 when the device is configured for 16-
bit mode. The multiplier applies when presetting the 5.4.1 Waveform Recorder Reading Window
counter (section 5.5.4), and setting the scale and roll-over
parameters (section 5.5.7).
To read the waveform recorder log, a section of registers
(42100-42696) is considered a re-useable “reading
window”, into which one full channel of one log can be
5.3 High Speed Registers loaded at a time. Once the channel has been loaded, the
data for that channel of that log is treated as a contiguous
In 3720 ACM firmware releases V1500 or later, a set of group of holding registers.
high-speed registers have been added to the 3720 ACM
Modbus Register Map. These registers span the range of
40261-40287. 5.4.2 Loading the Waveform Reading Window
The first three registers of the waveform recorder reading

5.3.1 High Speed Polarity window (42100-42102) are the reading window setup
registers. To load the reading window with waveform
Four of the high speed measurements have associated recorder data, a Modbus master must perform a write to
polarities. For the phase kW measurements (40264- these registers.
40266), there is one contiguously located polarity register
(40267). For the total kW measurement (40275), there is 42100: WFR Channel Number
a single contiguously located polarity register (40276). 42101: Number of WFR logs to read
42102: WFR log index
High speed kW phase polarity:
Bit 15-3 2 1 0 The channel number (42100) can be one of the following
n/a C B A values:
A) Polarity for HS kW A: 0 = positive, 1 = negative Value (hex) Channel

B) Polarity for HS kW B: 0 = positive, 1 = negative A510 Va
C) Polarity for HS kW C: 0 = positive, 1 = negative A511 Ia
A512 Vb
High speed kW total polarity: A513 Ib
Bit 15-4 3 2-0 A514 Vc
n/a D n/a A515 Ic
A516 Vaux
D) Polarity for HS kW Total: 0 = positive, 1 = A517 Ineutral
negative
The number of logs to read (42101) must be set to value
1.
The WFR log index is a calculated value. This value must

index one of the currently stored WFR logs on the 3720
ACM. This can be calculated from the current WFR log
13
counters (43209, 43210). The next section describes the Record timestamp - same format as Trigger
calculation. timestamp.
If the values sent in the write request describe a non- The waveform data segment contains all the information
existant log, the 3720 ACM will generate an illegal value needed to reconstruct the sampled waveform. The first six
exception response. registers define 32-bit scaling values (multiplier: 42115/6,
divisor: 42117/8, and offset: 42119/20). The remaining
registers are the waveform samples. Each sample is one
5.4.3 WFR Log Counters: Calculating the WFR 16-bit register. The following formula applies:
Log Index
SAMPLERMS = (SAMPLEA/D+OFFSET) x MULTIPLIER
When a waveform recorder log is triggered, that log is DIVISOR
assigned a reference handle which identifies that log. The
reference handle is the WFR log index. This formula will scale each sample to its proper value.
At any time, the WFR data counter (43210) defines the

next log index to be used. This number is incremented 5.5 Setup Registers
after each trigger. The WFR size counter (43209)
indicates how many WFR logs are currently stored. The The 3720 ACM has an extensive set of Setup Registers
two numbers can be used to calculate the index for each (43002-43079, 43301-43470). These registers provide a
log that is currently stored on the 3720 ACM: means of programming the 3720 ACM from a remote
location. The following sections discuss the setup
index = WFR data counter - i, registers which contain an encoded value.
where: i defines how recent the log is,

and i <= WFR size counter 5.5.1 Relay Operation Setup
The following table shows the available WFR log indices:

The Relay Operation Setup register (43027-43032)
control the operation of the 3720 ACM relays. Each relay
WFR data ctr WFR size ctr Available can be assigned one of the following operation modes:
(43210) (43209) indices (42102)
d 0 n/a 0 Setpoint
d 1 d-1 1 kWh Pulse
d 2 d-2, d-1 2 kVARh Pulse
d 3 d-3, d-2, d-1 3 kVAh Pulse
4 kWh Import Pulse
5 kWh Export Pulse
5.4.4 Interpreting the WFR Data 6 kVARh Import Pulse
7 kVARh Export Pulse
Once the waveform recorder reading window has been set
up, the waveform recorder log is available to be read by a The relay operating value registers control the active time
Modbus master. (for setpoint mode operation), or the pulse interval (for
pulse mode operation).
The waveform recorder log can be considered as two
segments: the log information, and the waveform data.
The log information segment contains the following items:
Number of channels (1)

Samples per channel (16 x #cycles)
Sampling frequency
Trigger type (manual: low-order byte = 1, or setpoint:
high-order byte = setpoint #)
Trigger timestamp - contains two 32-bit numbers: the
meter time in UNIX time, and the number of
microseconds into the current UNIX second.
14
5.5.2 Log Status Input Transitions 3720 ACM Serial Communications Protocol document.
Consult section 2.3.3.1. of that document for more detail.
The Log Status Input Transitions Register (43033)
specifies whether changes to the status inputs (S1 - S4) are
logged in the Event Log. 5.5.6 Modbus Protocol Setup
Bits 15-12 11-8 7-4 3-0 Registers 43063-43067 of the 3720 ACM Modbus
D C B A register map define the operating parameters for the
Modbus protocol. See section 4 of this document for
A) Log S1 transitions: 0 = No, 1 = Yes more detail on these registers.
B) Log S2 transitions: 0 = No, 1 = Yes
C) Log S3 transitions: 0 = No, 1 = Yes
D) Log S4 transitions: 0 = No, 1 = Yes 5.5.7 Status Input Counter Setup
The 3720 ACM supports scaleable counters for the status

5.5.3 Trigger Waveform Capture inputs. For a full description of status input counters,
consult the 3720 ACM manual.
The Trigger Waveform Capture Register (43034) is used
to trigger or rearm the Waveform Capture Log on the Registers 43071-43074 define the number of counts that
3720 ACM. To trigger the Waveform Capture, write one the counter should increment for each input pulse.
of the following values:
Value (hex) Channel Register 43076-43079 define the roll-over points for the
0000 Va status input counters. When a counter reaches its roll-
0001 Ia over point, it resets to zero and continues to count up.
0002 Vb
0003 Ib Both of these parameter sets are of the same data format
0004 Vc as described in section 5.2.4 of this document.
0005 Ic
0006 Vaux
5.5.8 Waveform Recorder Depth
0007 Ineutral
Writing any other value will rearm the Waveform Capture The Waveform Recorder Depth register (43084) controls
Log. the number and size of waveform recorder logs on the
3720 ACM. The following values are allowed:
Note: After manually triggering a Waveform Capture, the 1: one recorder log of 36 cycles
Modbus master station should check the Waveform 2: two recorder logs of 18 cycles
Capture Log Counter (43208) to verify that the counter 3: three recorder logs of 12 cycles.
has incremented. If the log is read before the counter
increments, an improper waveform will be obtained. Changing the log depth will rearm the waveform recorder.
5.5.4 Preset Status Input Counters 5.5.9 Waveform Recorder Trigger/Rearm
The Status Input Counters can be preset to a known value, Register 43086 allows a manual trigger/rearm of the
by writing the value to the appropriate Preset Status Input waveform recorder on the 3720 ACM. Writing value 0 to
Counter register (43035-43038). The format of this this register will rearm the waveform recorder. Writing
register group matches that described in section 5.2.4 of any other value will trigger the waveform recorder.
this document.
5.5.10 Event Counters
5.5.5 Sliding Window Keys
Section 2.3.1.2 of the 3720 ACM Serial Communications
Registers 43052-43061 define the 10 programmable Protocol document describes a set of event counters, some
sliding window demand keys. The valid keys which can of which are duplicated in the Modbus protocol.
be programmed in these registers are defined in the Registers 43201-43260 in the 3720 ACM Modbus register
map cover the event counters.
15
The 3720 ACM Modbus protocol includes a special

section for the waveform capture log (43501-43600). The
5.5.11 Setpoint Registers waveform capture log can be retrieved in a single read
request.
The 3720 ACM setpoint control section spans registers
43301-43470.
5.6.1 Waveform Read Request
Each setpoint setup structure spans 10 Modbus registers.
For a description of the individual fields of the setup The 3720 ACM waveform capture log can be read only by
structure, consult the 3720 ACM Serial Communications a BLOCK READ command, requesting 100 registers,
Protocol document, section 2.3.6.1. starting at address 43501. An illegal address exception
response will be generated for any request to read
anything but 100 registers when the start address is 43501.
Figure 5-1 describes the packet format.
5.6 Waveform Capture
WAVEFORM CAPTURE BLOCK READ (16/32-BIT MODE)
WAVEFORM CAPTURE PACKET WAVEFORM CAPTURE RESPONSE PACKET


3500 (Start Register) (2 bytes) 200 (Byte Count) (1 byte)
100 (# of Registers) (2 bytes) Waveform Channel # (2 bytes)
CRC Checksum (2 bytes) Number of Sample Points (2 bytes)
Delay between each sample
(in microseconds) (2 bytes)
Trigger Type (2 bytes)
Compressed Samples (192 bytes)
Notes: 1) The Waveform Capture Packet format is identical in both 16 and 32 bit register size modes.
2) If the user requests a waveform register without following the above BLOCK READ format, an illegal address
exception will be generated.
______________
COMPRESSED SAMPLE FORMAT
The waveform samples are arranged in a packed format: two 12-bit samples are contained in three bytes (24-bits). Three
16-bit registers contain two three byte words:
Bits 15-12 11-8 7-4 3-0

Register 43505 A B C
Register 43506 D E
Register 43507 F G H
A) Second sample lower 8 bits E) Fourth sample lower 8 bits

B) First sample lower 4 bits F) Third sample lower 4 bits
C) Second sample upper 4 bits G) Fourth sample upper 4 bits
D) First sample upper 8 bits H) Third sample upper 8 bits
The pattern repeats for every three registers/four samples.
Figure 5-1: Waveform Capture Packet
16
5.6.2 Compressed Sample Format If a polarity bit is mapped for the register in question, that
bit would store value zero.
The waveform samples are arranged in a packed format.
In this format, two 12-bit samples are contained in three INVALID_MAX is defined as the most negative value.
bytes (24-bits). In 16-bit mode, INVALID_MAX is represented as FFFF
hex. In 32-bit mode, it is represented as FFFFFFFF hex.
Data is in unsigned 12-bit format with two samples in If a polarity bit is mapped for the register in question, that
every three-byte word. The three-byte word is ordered in bit would store value one.
the packet as low byte first, middle byte next, and high
byte last. The three-byte words are organized as follows: INVALID is defined as FFFF hex in 16-bit mode and
FFFFFFFF hex in 32-bit mode. If a polarity bit is mapped
Bit # 23-16 15-12 11-8 7-0 for the register in question, that bit would store value zero.
A B C D
A) Upper 8 bits of the first sample 5.8.2 Min/Max Registers

B) Lower 4 bits of the first sample
C) Upper 4 bits of the second sample When Min/Max registers are reset, they are initialized to a
D) Lower 8 bits of the second sample. default state. Min registers are reset to INVALID_MIN,
and Max registers are reset to INVALID_MAX.
Figure 5-1 shows how this format maps the first four
samples to the first three packed sample registers. For all Min/Max registers except for harmonics, the
associated polarity bit is used as described above. For
harmonic measurements, where all measurements are
5.7 Event Log positive, there are no polarity bits associated with the
Min/Max measurements.
The 3720 ACM device event log covers the Modbus
register range of 44001-45000. The most recent 100
5.8.3 Sliding Window and Predicted Demand
events are stored in this log.
Registers
Each device event spans 10 Modbus registers. That block
of 10 registers represents the event log structure described Any Sliding Window Demand which is unprogrammed
in the 3720 ACM Serial Communications Protocol will hold the INVALID value. This is true for the
document, section 2.3.7.1. corresponding Predicted Demand register as well.
When Sliding Window Demand is reset, all programmed

Sliding Windew registers are initialized to the value
5.8 Registers with Invalid Numbers INVALID_MIN, and will retain that value for the
duration of one SD sub-interval. The associated polarity
Certain registers in the 3720 ACM, under certain bits are cleared. The same is true for the corresponding
conditions, can hold invalid numbers. This is not to be Predicted Demand registers, except that these registers are
confused with invalid registers (described in section 3.7 updated every second.
of this document).
5.8.4 Time of Use Demand Registers

5.8.1 Representation of Invalid Numbers
When reset, the Time Of Use Demand registers are reset
Depending on the type of register, invalid numbers can to the INVALID_MAX value. There is no associated
mean different things. Therefore there are a few different polarity register for these registers.
representations of those invalid numbers.
• INVALID_MIN
• INVALID_MAX
• INVALID
INVALID_MIN is defined as the largest positive value.

In 16-bit mode, INVALID_MIN is represented as FFFF
hex. In 32-bit mode, it is represented as FFFFFFFF hex.
17
APPENDIX A: CRC-16 CALCULATION

This appendix describes the procedure for obtaining the CRC-16 error check field for a Modbus RTU frame.
PROCEDURE
A frame can be considered as a continuous, serial stream of binary data (ones and zeros). The 16-bit checksum is obtained by
multiplying the serial data stream by 216 (10000000000000000) and then dividing it by the generator polynomial
x16+x15+x2+1, which can be expressed as the 17-bit binary number 1100000000000101. The quotient is ignored and the 16-
bit remainder is the checksum, which is appended to the end of the frame.
In calculating the CRC, all arithmetic operations (additions and subtractions) are performed using MODULO TWO, or
EXCLUSIVE OR operation. A step-by-step example is provided to show how to obtain the checksum for a simple Modbus
RTU frame.
Steps for generating the CRC-16 checksum:
1) Form a new polynomial by dropping the MSB (Most Significant Bit) of the generator polynomial and reversing the
bit sequence. This yields the binary number 1010 0000 0000 0001, or A0 01 (hex).
2) Load a 16-bit register with initial value FF FF (hex).
3) Exclusive OR the first data byte with the low-order byte of the 16-bit register, storing the result in the 16-bit register.
4) Shift the 16-bit register one bit to the right.
5a) If the bit shifted out to the right is one, Exclusive OR the 16-bit register with the new generator polynomial, with the
result stored in the 16-bit registers. Return to step 4.
5b) If the bit shifted out to the right is zero, return to step 4.
6) Repeat steps 4 and 5 until 8 shifts have been performed.
7) Exclusive OR the next data byte with the 16-bit register.
8) Repeat steps 4 through 7 until all bytes of the frame have been Exclusive Ored with the 16-bit register and shifted 8
times.
9) The content of the 16-bit register is the checksum and is appended to the end of the frame.
Example:
A Modbus master node requests to read register 40011 from a Modbus slave with address 100 (64 hex). As per the
Modbus protocol, reading register 40011 means using the READ HOLDING REGISTERS function (03 hex) with start
register 10.
Initial frame:
Slave Function Start Register # of Registers Error Check (CRC-16)

Address
64 03 00 0A 00 01 To be calculated
Step Byte Bits Shifted Action 16-Bit Register Bit Shifted Out
2 Initial Value 1111 1111 1111 1111
1 Load First Data Byte 0000 0000 0110 0100
3 Exclusive OR 1111 1111 1001 1011
4 1 Shift 1 bit to the Right 0111 1111 1100 1101 1
Generator Polynomial 1010 0000 0000 0001
5a Exclusive OR 1101 1111 1100 1100
19
5a Exclusive OR 1011 1011 1111 1000
5a Exclusive OR 1010 1011 1011 1110
2 Load 2nd Data Byte 0000 0000 0000 0011
7 Exclusive OR 1010 1011 1011 1101
5a Exclusive OR 1111 0101 1101 1111
5a Exclusive OR 1101 1010 1110 1110
5a Exclusive OR 1001 0110 1011 1010
5a Exclusive OR 1000 0101 1010 1111
5a Exclusive OR 1110 0010 1101 0110
3 Load 3rd Data Byte 0000 0000 0000 0000
7 Exclusive OR 0111 0001 0110 1011
5a Exclusive OR 1001 1000 1011 0100
5a Exclusive OR 1011 0011 0001 0111
5a Exclusive OR 1111 1001 1000 1010
5a Exclusive OR 1001 1110 0110 0011
5a Exclusive OR 1110 1111 0011 0000
7 4 Load 4th Data Byte 0000 0000 0000 1010
Exclusive OR 1110 1111 0011 1010
5a Exclusive OR 1001 1011 1100 1111
20
5a Exclusive OR 1110 1101 1110 0110
5a Exclusive OR 1001 1011 0111 1000
7 5 Load 5th Data Byte 0000 0000 0000 0000
Exclusive OR 0001 0011 0110 1111
5a Exclusive OR 1010 1001 1011 0110
5a Exclusive OR 1000 1010 0110 1100
5a Exclusive OR 1011 0001 0100 1100
7 6 Load 6th Data Byte 0000 0000 0000 0001
Exclusive OR 0010 1100 0101 0010
5a Exclusive OR 1010 1011 0001 0101
5a Exclusive OR 1111 0101 1000 1011
5a Exclusive OR 1101 1010 1100 0100
5a Exclusive OR 1011 1011 0101 1001
5a Exclusive OR 1111 1101 1011 1100
RESULT Hex FD Hex AD
The frame completed with the CRC-16 checksum is as follows:
Slave Function Start Register # of Registers Error Check (CRC-16)

Address
21
64 03 00 0A 00 01 AD FD
PSEUDOCODE FOR CRC-16 GENERATION

For the users who are familiar with computer programming, the following is the pseudocode for calculating the 16-bit Cyclic
Redundancy Check.
Initialize a 16-bit register to FFFF Hex

Initialize the generator polynomial to A001 Hex
FOR n=1 to # of bytes in packet

BEGIN
XOR nth data byte with the 16-bit register
FOR bits_shifted = 1 to 8
BEGIN
SHIFT 1 bit to the right
IF (bit shifted out EQUAL 1)
XOR generator polynomial with the 16-bit register and store result in the 16-bit register
END
END
The resultant 16-bit register contains the CRC-16 checksum.
22
APPENDIX B: 3720 ACM REGISTER MAP
REAL TIME MEASUREMENTS..........................................................................................................................................25
THERMAL DEMAND MEASUREMENTS .........................................................................................................................25
STATUS REGISTERS ............................................................................................................................................................26
HIGH SPEED MEASUREMENTS........................................................................................................................................26
MINIMUM REAL TIME MEASUREMENTS.....................................................................................................................26
MINIMUM REAL TIME TIMESTAMPS............................................................................................................................26
SLIDING WINDOW DEMAND MEASUREMENTS..........................................................................................................27
MAXIMUM REAL TIME MEASUREMENTS ...................................................................................................................27
MAXIMUM REAL TIME TIMESTAMPS...........................................................................................................................27
MINIMUM THERMAL DEMAND MEASUREMENTS....................................................................................................28
MINIMUM THERMAL DEMAND TIMESTAMPS ...........................................................................................................29
MAXIMUM THERMAL DEMAND MEASUREMENTS ..................................................................................................29
MAXIMUM THERMAL DEMAND TIMESTAMPS..........................................................................................................29
MINIMUM SLIDING WINDOW MEASUREMENTS .......................................................................................................30
MINIMUM SLIDING WINDOW TIMESTAMPS...............................................................................................................30
MAXIMUM SLIDING WINDOW MEASUREMENTS ......................................................................................................30
MAXIMUM SLIDING WINDOW TIMESTAMPS .............................................................................................................31
PREDICTED DEMAND MEASUREMENTS ......................................................................................................................31
MINIMUM PREDICTED DMD MEASUREMENTS .........................................................................................................31
MINIMUM PREDICTED DMD TIMESTAMPS.................................................................................................................32
MAXIMUM PREDICTED DMD MEASUREMENTS ........................................................................................................32
MAXIMUM PREDICTED DMD TIMESTAMPS ...............................................................................................................32
WAVEFORM RECORDER WINDOW................................................................................................................................33
DEVICE CONFIGURATION PARAMETERS....................................................................................................................34
EVENT COUNTERS...............................................................................................................................................................35
SETPOINT SYSTEM CONFIGURATION...........................................................................................................................36
23
WAVEFORM CAPTURE LOG.............................................................................................................................................37
TIME OF USE INFORMATION ...........................................................................................................................................38
DEVICE EVENT LOG............................................................................................................................................................39
REAL TIME HARMONIC MEASUREMENTS..................................................................................................................41
MINIMUM REAL TIME HARMONIC MEASUREMENTS.............................................................................................42
MINIMUM REAL TIME HARMONIC TIMESTAMPS....................................................................................................43
MAXIMUM REAL TIME HARMONIC MEASUREMENTS ...........................................................................................44
MAXIMUM REAL TIME HARMONIC TIMESTAMPS...................................................................................................46
THERMAL DEMAND HARMONIC MEASUREMENTS .................................................................................................47
MINIMUM THERMAL DEMAND HARMONIC MEASUREMENTS............................................................................48
MINIMUM THERMAL DEMAND HARMONIC TIMESTAMPS ...................................................................................50
MAXIMUM THERMAL DEMAND HARMONIC MEASUREMENTS...........................................................................51
MAXIMUM THERMAL DEMAND HARMONIC TIMESTAMPS..................................................................................52
SLIDING DEMAND HARMONIC MEASUREMENTS.....................................................................................................53
MINIMUM SLIDING DEMAND HARMONIC MEASUREMENTS................................................................................55
MINIMUM SLIDING DEMAND HARMONIC TIMESTAMPS .......................................................................................56
MAXIMUM SLIDING DEMAND HARMONIC MEASUREMENTS ..............................................................................57
MAXIMUM SLIDING DEMAND HARMONIC TIMESTAMPS......................................................................................59
PREDICTED DEMAND HARMONIC MEASUREMENTS ..............................................................................................60
MINIMUM PREDICTED DEMAND HARMONIC MEASUREMENTS .........................................................................61
MINIMUM PREDICTED DEMAND HARMONIC TIMESTAMPS ................................................................................62
MAXIMUM PREDICTED DEMAND HARMONIC MEASUREMENTS........................................................................64
MAXIMUM PREDICTED DEMAND HARMONIC TIMESTAMPS ...............................................................................65
REGISTER MAP NOTES ......................................................................................................................................................67
24
Register Register
Address Type Description Units Notes Address Type Description Units Notes
40062 RO M/GVARh Import M/GVARh (c)
40063 RO kVARh Export kVARh
REAL TIME MEASUREMENTS 40064 RO M/GVARh Export M/GVARh (c)
40065 RO kVARh Total kVARh
40002 RW Year year - 1900 40066 RO M/GVARh Total M/GVARh (c)
40003 RW Month (1-12) 40067 RO kVARh Net kVARh
40004 RW Day (1-31) 40068 RO M/GVARh Net M/GVARh (c)
40005 RW Hour (0-23)
40006 RW Minute (0-59) 40071 RO kVAh Import kVAh
40007 RW Second (0-59) 40072 RO M/GVAh Import M/GVAh (c)
40008 RW UNIX Time seconds (d) 40073 RO kVAh Export kVAh
40074 RO M/GVAh Export M/GVAh (c)
40011 RO Van V rms (a) 40075 RO kVAh Total kVAh
40012 RO Vbn V rms (a) 40076 RO M/GVAh Total M/GVAh (c)
40013 RO Vcn V rms (a,b) 40077 RO kVAh Net kVAh
40014 RO Vln average V rms (a) 40078 RO M/GVAh Net M/GVAh (c)
40015 RO Vab V rms
40016 RO Vbc V rms (b)
40017 RO Vca V rms (b)
40018 RO Vll average V rms THERMAL DEMAND MEASUREMENTS
40020 RO Vaux V rms 40111 RO Van V rms (a)

40021 RO Ia A rms 40112 RO Vbn V rms (a)
40022 RO Ib A rms 40113 RO Vcn V rms (a,b)
40023 RO Ic A rms (b) 40114 RO Vln average V rms (a)
40024 RO I average A rms 40115 RO Vab V rms
40026 RO Neutral current (I4) A rms 40117 RO Vca V rms (b)
40118 RO Vll average V rms
40028 RO Voltage imbalance %
40029 RO Current imbalance % 40120 RO Vaux V rms
40121 RO Ia A rms
40031 RO kW Phase A kW rms (a) 40122 RO Ib A rms
40032 RO kW Phase B kW rms (a) 40123 RO Ic A rms (b)
40033 RO kW Phase C kW rms (a,b) 40124 RO I average A rms
40034 RO kW Total kW rms
40035 RO kVAR Phase A kVAR rms (a) 40126 RO Neutral current (I4) A rms
40036 RO kVAR Phase B kVAR rms (a)
40037 RO kVAR Phase C kVAR rms (a,b) 40128 RO Voltage imbalance %
40038 RO kVAR Total kVAR rms 40129 RO Current imbalance %
40039 RO Power Factor Phase A % (a)
40040 RO Power Factor Phase B % (a) 40131 RO kW Phase A kW rms (a)
40041 RO Power Factor Phase C % (a,b) 40132 RO kW Phase B kW rms (a)
40042 RO Power Factor Total % 40133 RO kW Phase C kW rms (a,b)
40043 RO kVA Phase A kVA (a) 40134 RO kW Total kW rms
40044 RO kVA Phase B kVA (a) 40135 RO kVAR Phase A kVAR rms (a)
40045 RO kVA Phase C kVA (a,b) 40136 RO kVAR Phase B kVAR rms (a)
40046 RO kVA Total kVA 40137 RO kVAR Phase C kVAR rms (a,b)
40138 RO kVAR Total kVAR rms
40048 RO Frequency on Va 0.01 Hz 40139 RO Power Factor Phase A % (a)
40049 RO Phase Reversal Logical 40140 RO Power Factor Phase B % (a)
40050 RO Real time polarity Bit mapped (d) 40141 RO Power Factor Phase C % (a,b)
40051 RO kWh Import kWh 40142 RO Power Factor Total %
40052 RO M/GWh Import M/GWh (c) 40143 RO kVA Phase A kVA (a)
40053 RO kWh Export kWh 40144 RO kVA Phase B kVA (a)
40054 RO M/GWh Export M/GWh (c) 40145 RO kVA Phase C kVA (a,b)
40055 RO kWh Total kWh 40146 RO kVA Total kVA
40056 RO M/GWh Total M/GWh (c)
40057 RO kWh Net kWh 40148 RO Frequency on Va 0.01 Hz
40058 RO M/GWh Net M/GWh (c)
40150 RO RT Thermal dmd polarity Bit mapped (d)
40061 RO kVARh Import kVARh
25
Register Register
STATUS REGISTERS 40287 RO S4 Counter Counts
40201 RW Relay #1
40202 RW Relay #2 MINIMUM REAL TIME MEASUREMENTS
40203 RW Relay #3
40311 RO Van V rms (a)
40210 RO Status inputs Bit mapped 40312 RO Vbn V rms (a)
40211 RO Setpoint #01 Bit mapped 40313 RO Vcn V rms (a,b)
40212 RO Setpoint #02 Bit mapped 40314 RO Vln average V rms (a)
40213 RO Setpoint #03 Bit mapped 40315 RO Vab V rms
40214 RO Setpoint #04 Bit mapped 40316 RO Vbc V rms (b)
40215 RO Setpoint #05 Bit mapped 40317 RO Vca V rms (b)
40216 RO Setpoint #06 Bit mapped 40318 RO Vll average V rms
40217 RO Setpoint #07 Bit mapped
40218 RO Setpoint #08 Bit mapped 40320 RO Vaux V rms
40219 RO Setpoint #09 Bit mapped 40321 RO Ia A rms
40220 RO Setpoint #10 Bit mapped 40322 RO Ib A rms
40221 RO Setpoint #11 Bit mapped 40323 RO Ic A rms (b)
40222 RO High speed setpoint #1 Bit mapped 40324 RO I average A rms
40223 RO High speed setpoint #2 Bit mapped
40224 RO High speed setpoint #3 Bit mapped 40326 RO Neutral current (I4) A rms
40225 RO High speed setpoint #4 Bit mapped
40226 RO High speed setpoint #5 Bit mapped 40328 RO Voltage imbalance %
40227 RO High speed setpoint #6 Bit mapped 40329 RO Current imbalance %
40241 RO Status #1 counter Counts (d) 40331 RO kW Phase A kW rms (a)

40242 RO Status #2 counter Counts (d) 40332 RO kW Phase B kW rms (a)
40243 RO Status #3 counter Counts (d) 40333 RO kW Phase C kW rms (a,b)
40244 RO Status #4 counter Counts (d) 40334 RO kW Total kW rms
40335 RO kVAR Phase A kVAR rms (a)
HIGH SPEED MEASUREMENTS 40337 RO kVAR Phase C kVAR rms (a,b)
40339 RO Power Factor Phase A % (a)
40261 RO HS kVA Phase A kVA 40340 RO Power Factor Phase B % (a)
40262 RO HS kVA Phase B kVA 40341 RO Power Factor Phase C % (a,b)
40263 RO HS kVA Phase C kVA 40342 RO Power Factor Total %
40264 RO HS kW Phase A kW 40343 RO kVA Phase A kVA (a)
40265 RO HS kW Phase B kW 40344 RO kVA Phase B kVA (a)
40266 RO HS kW Phase C kW 40345 RO kVA Phase C kVA (a,b)
40267 RO HS kW Phase Polarity Bit mapped 40346 RO kVA Total kVA
40268 RO HS Ia A rms
40269 RO HS Ib A rms 40348 RO Frequency on Va 0.01 Hz
40270 RO HS Ic A rms
40271 RO HS Va V rms 40350 RO RT minimum polarity Bit mapped (d)
40272 RO HS Vb V rms
40273 RO HS Vc V rms
40274 RO HS kVA Total kVA
40275 RO HS kW Total kW
MINIMUM REAL TIME TIMESTAMPS
40276 RO HS kW Total Polarity Bit mapped
40277 RO HS I average A rms 40411 RO Van Unix Time (a,d)
40278 RO HS V average V rms 40412 RO Vbn Unix Time (a,d)
40279 RO HS Neutral Current (I4) A rms 40413 RO Vcn Unix Time (a,b,d)
40280 RO HS Phase reversal Logical 40414 RO Vln average Unix Time (a,d)
40281 RO Status Inputs Bit mapped 40415 RO Vab Unix Time (d)
40282 RO HS Voltage imbalance % 40416 RO Vbc Unix Time (b,d)
40283 RO HS Frequency 0.01 Hz 40417 RO Vca Unix Time (b,d)
40284 RO S1 Counter Counts 40418 RO Vll average Unix Time (d)
40285 RO S2 Counter Counts
40286 RO S3 Counter Counts 40420 RO Vaux Unix Time (d)
26
Register Register
40421 RO Ia Unix Time (d) 40540 RO Power Factor Phase B % (a)
40422 RO Ib Unix Time (d) 40541 RO Power Factor Phase C % (a,b)
40423 RO Ic Unix Time (b,d) 40542 RO Power Factor Total %
40424 RO I average Unix Time (d) 40543 RO kVA Phase A kVA (a)
40544 RO kVA Phase B kVA (a)
40426 RO Neutral current (I4) Unix Time (d) 40545 RO kVA Phase C kVA (a,b)
40546 RO kVA Total kVA
40428 RO Voltage imbalance Unix Time (d) 40548 RO Frequency on Va 0.01 Hz
40429 RO Current imbalance Unix Time (d)
40550 RO Sliding demand polarity Bit mapped (d)
40431 RO kW Phase A Unix Time (a,d)
40432 RO kW Phase B Unix Time (a,d)
40433 RO kW Phase C Unix Time (a,b,d)
40434 RO kW Total Unix Time (d)
MAXIMUM REAL TIME MEASUREMENTS
40435 RO kVAR Phase A Unix Time (a,d)
40436 RO kVAR Phase B Unix Time (a,d) 40611 RO Van V rms (a)
40437 RO kVAR Phase C Unix Time (a,b,d) 40612 RO Vbn V rms (a)
40438 RO kVAR Total Unix Time (d) 40613 RO Vcn V rms (a,b)
40439 RO Power Factor Phase A Unix Time (a,d) 40614 RO Vln average V rms (a)
40440 RO Power Factor Phase B Unix Time (a,d) 40615 RO Vab V rms
40441 RO Power Factor Phase C Unix Time (a,b,d) 40616 RO Vbc V rms (b)
40442 RO Power Factor Total Unix Time (d) 40617 RO Vca V rms (b)
40443 RO kVA Phase A Unix Time (a,d) 40618 RO Vll average V rms
40444 RO kVA Phase B Unix Time (a,d)
40445 RO kVA Phase C Unix Time (a,b,d) 40620 RO Vaux V rms
40446 RO kVA Total Unix Time (d) 40621 RO Ia A rms
40622 RO Ib A rms
40448 RO Frequency on Va Unix Time (d) 40623 RO Ic A rms (b)
40624 RO I average A rms
40626 RO Neutral current (I4) A rms

SLIDING WINDOW DEMAND MEASUREMENTS
40511 RO Van V rms (a) 40629 RO Current imbalance %
40512 RO Vbn V rms (a)
40513 RO Vcn V rms (a,b) 40631 RO kW Phase A kW rms (a)
40514 RO Vln average V rms (a) 40632 RO kW Phase B kW rms (a)
40515 RO Vab V rms 40633 RO kW Phase C kW rms (a,b)
40516 RO Vbc V rms (b) 40634 RO kW Total kW rms
40517 RO Vca V rms (b) 40635 RO kVAR Phase A kVAR rms (a)
40518 RO Vll average V rms 40636 RO kVAR Phase B kVAR rms (a)
40637 RO kVAR Phase C kVAR rms (a,b)
40520 RO Vaux V rms 40638 RO kVAR Total kVAR rms
40521 RO Ia A rms 40639 RO Power Factor Phase A % (a)
40522 RO Ib A rms 40640 RO Power Factor Phase B % (a)
40523 RO Ic A rms (b) 40641 RO Power Factor Phase C % (a,b)
40524 RO I average A rms 40642 RO Power Factor Total %
40643 RO kVA Phase A kVA (a)
40526 RO Neutral current (I4) A rms 40644 RO kVA Phase B kVA (a)
40645 RO kVA Phase C kVA (a,b)
40528 RO Voltage imbalance % 40646 RO kVA Total kVA
40529 RO Current imbalance % 40648 RO Frequency on Va 0.01 Hz
40531 RO kW Phase A kW rms (a) 40650 RO RT maximum polarity Bit mapped (d)
40532 RO kW Phase B kW rms (a)
40533 RO kW Phase C kW rms (a,b)
40535 RO kVAR Phase A kVAR rms (a) MAXIMUM REAL TIME TIMESTAMPS
40537 RO kVAR Phase C kVAR rms (a,b) 40711 RO Van Unix Time (a,d)
40538 RO kVAR Total kVAR rms 40712 RO Vbn Unix Time (a,d)
40539 RO Power Factor Phase A % (a) 40713 RO Vcn Unix Time (a,b,d)
27
Register Register
40714 RO Vln average Unix Time (a,d) 40831 RO kW Phase A kW rms (a)
40715 RO Vab Unix Time (d) 40832 RO kW Phase B kW rms (a)
40716 RO Vbc Unix Time (b,d) 40833 RO kW Phase C kW rms (a,b)
40717 RO Vca Unix Time (b,d) 40834 RO kW Total kW rms
40718 RO Vll average Unix Time (d) 40835 RO kVAR Phase A kVAR rms (a)
40720 RO Vaux Unix Time (d) 40837 RO kVAR Phase C kVAR rms (a,b)
40721 RO Ia Unix Time (d) 40838 RO kVAR Total kVAR rms
40722 RO Ib Unix Time (d) 40839 RO Power Factor Phase A % (a)
40723 RO Ic Unix Time (b,d) 40840 RO Power Factor Phase B % (a)
40724 RO I average Unix Time (d) 40841 RO Power Factor Phase C % (a,b)
40842 RO Power Factor Total %
40726 RO Neutral current (I4) Unix Time (d) 40843 RO kVA Phase A kVA (a)
40728 RO Voltage imbalance Unix Time (d) 40845 RO kVA Phase C kVA (a,b)
40729 RO Current imbalance Unix Time (d) 40846 RO kVA Total kVA
40848 RO Frequency on Va 0.01 Hz
40732 RO kW Phase B Unix Time (a,d) 40850 RO Min. thermal dmd polarity Bit mapped (d)
40736 RO kVAR Phase B Unix Time (a,d)
40737 RO kVAR Phase C Unix Time (a,b,d)
40738 RO kVAR Total Unix Time (d)
40739 RO Power Factor Phase A Unix Time (a,d)
40740 RO Power Factor Phase B Unix Time (a,d)
40741 RO Power Factor Phase C Unix Time (a,b,d)
40742 RO Power Factor Total Unix Time (d)
40743 RO kVA Phase A Unix Time (a,d)
40745 RO kVA Phase C Unix Time (a,b,d)
40746 RO kVA Total Unix Time (d)
40748 RO Frequency on Va Unix Time (d)
MINIMUM THERMAL DEMAND

MEASUREMENTS
40811 RO Van V rms (a)

40813 RO Vcn V rms (a,b)
40814 RO Vln average V rms (a)
40815 RO Vab V rms
40817 RO Vca V rms (b)
40818 RO Vll average V rms
40820 RO Vaux V rms

40821 RO Ia A rms
40822 RO Ib A rms
40823 RO Ic A rms (b)

40829 RO Current imbalance %
28
Register Register
MINIMUM THERMAL DEMAND TIMESTAMPS 41026 RO Neutral current (I4) A rms

40911 RO Van Unix Time (a,d) 41029 RO Current imbalance %
40912 RO Vbn Unix Time (a,d)
40913 RO Vcn Unix Time (a,b,d) 41031 RO kW Phase A kW rms (a)
40914 RO Vln average Unix Time (a,d) 41032 RO kW Phase B kW rms (a)
40915 RO Vab Unix Time (d) 41033 RO kW Phase C kW rms (a,b)
40916 RO Vbc Unix Time (b,d) 41034 RO kW Total kW rms
40917 RO Vca Unix Time (b,d) 41035 RO kVAR Phase A kVAR rms (a)
40918 RO Vll average Unix Time (d) 41036 RO kVAR Phase B kVAR rms (a)
40920 RO Vaux Unix Time (d) 41038 RO kVAR Total kVAR rms
40921 RO Ia Unix Time (d) 41039 RO Power Factor Phase A % (a)
40922 RO Ib Unix Time (d) 41040 RO Power Factor Phase B % (a)
40923 RO Ic Unix Time (b,d) 41041 RO Power Factor Phase C % (a,b)
40924 RO I average Unix Time (d) 41042 RO Power Factor Total %
40926 RO Neutral current (I4) Unix Time (d) 41044 RO kVA Phase B kVA (a)
40928 RO Voltage imbalance Unix Time (d) 41046 RO kVA Total kVA
40929 RO Current imbalance Unix Time (d) 41048 RO Frequency on Va 0.01 Hz
40931 RO kW Phase A Unix Time (a,d) 41050 RO Max. thermal dmd polarity Bit mapped
40935 RO kVAR Phase A Unix Time (a,d) MAXIMUM THERMAL DEMAND TIMESTAMPS
40937 RO kVAR Phase C Unix Time (a,b,d) 41111 RO Van Unix Time (a,d)
40938 RO kVAR Total Unix Time (d) 41112 RO Vbn Unix Time (a,d)
40939 RO Power Factor Phase A Unix Time (a,d) 41113 RO Vcn Unix Time (a,b,d)
40940 RO Power Factor Phase B Unix Time (a,d) 41114 RO Vln average Unix Time (a,d)
40941 RO Power Factor Phase C Unix Time (a,b,d) 41115 RO Vab Unix Time (d)
40942 RO Power Factor Total Unix Time (d) 41116 RO Vbc Unix Time (b,d)
40943 RO kVA Phase A Unix Time (a,d) 41117 RO Vca Unix Time (b,d)
40944 RO kVA Phase B Unix Time (a,d) 41118 RO Vll average Unix Time (d)
40946 RO kVA Total Unix Time (d) 41120 RO Vaux Unix Time (d)
41121 RO Ia Unix Time (d)
40948 RO Frequency on Va Unix Time (d) 41122 RO Ib Unix Time (d)
41123 RO Ic Unix Time (b,d)
41124 RO I average Unix Time (d)
MAXIMUM THERMAL DEMAND
41126 RO Neutral current (I4) Unix Time (d)
MEASUREMENTS
41128 RO Voltage imbalance Unix Time (d)
41011 RO Van V rms (a) 41129 RO Current imbalance Unix Time (d)
41013 RO Vcn V rms (a,b) 41131 RO kW Phase A Unix Time (a,d)
41014 RO Vln average V rms (a) 41132 RO kW Phase B Unix Time (a,d)
41015 RO Vab V rms 41133 RO kW Phase C Unix Time (a,b,d)
41016 RO Vbc V rms (b) 41134 RO kW Total Unix Time (d)
41017 RO Vca V rms (b) 41135 RO kVAR Phase A Unix Time (a,d)
41018 RO Vll average V rms 41136 RO kVAR Phase B Unix Time (a,d)
41020 RO Vaux V rms 41138 RO kVAR Total Unix Time (d)
41021 RO Ia A rms 41139 RO Power Factor Phase A Unix Time (a,d)
41022 RO Ib A rms 41140 RO Power Factor Phase B Unix Time (a,d)
41023 RO Ic A rms (b) 41141 RO Power Factor Phase C Unix Time (a,b,d)
41024 RO I average A rms 41142 RO Power Factor Total Unix Time (d)
29
Register Register

41145 RO kVA Phase C Unix Time (a,b,d) 41320 RO Vaux Unix Time (d)
41146 RO kVA Total Unix Time (d) 41321 RO Ia Unix Time (d)
41322 RO Ib Unix Time (d)
41148 RO Frequency on Va Unix Time (d) 41323 RO Ic Unix Time (b,d)

MINIMUM SLIDING WINDOW MEASUREMENTS
41211 RO Van V rms (a) 41329 RO Current imbalance Unix Time (d)
41213 RO Vcn V rms (a,b) 41331 RO kW Phase A Unix Time (a,d)
41214 RO Vln average V rms (a) 41332 RO kW Phase B Unix Time (a,d)
41215 RO Vab V rms 41333 RO kW Phase C Unix Time (a,b,d)
41216 RO Vbc V rms (b) 41334 RO kW Total Unix Time (d)
41217 RO Vca V rms (b) 41335 RO kVAR Phase A Unix Time (a,d)
41218 RO Vll average V rms 41336 RO kVAR Phase B Unix Time (a,d)
41220 RO Vaux V rms 41338 RO kVAR Total Unix Time (d)
41221 RO Ia A rms 41339 RO Power Factor Phase A Unix Time (a,d)
41222 RO Ib A rms 41340 RO Power Factor Phase B Unix Time (a,d)
41223 RO Ic A rms (b) 41341 RO Power Factor Phase C Unix Time (a,b,d)
41224 RO I average A rms 41342 RO Power Factor Total Unix Time (d)
41226 RO Neutral current (I4) A rms 41344 RO kVA Phase B Unix Time (a,d)
41228 RO Voltage imbalance % 41346 RO kVA Total Unix Time (d)
41231 RO kW Phase A kW rms (a)
41234 RO kW Total kW rms MAXIMUM SLIDING WINDOW
41235 RO kVAR Phase A kVAR rms (a) MEASUREMENTS
41237 RO kVAR Phase C kVAR rms (a,b) 41411 RO Van V rms (a)
41238 RO kVAR Total kVAR rms 41412 RO Vbn V rms (a)
41239 RO Power Factor Phase A % (a) 41413 RO Vcn V rms (a,b)
41240 RO Power Factor Phase B % (a) 41414 RO Vln average V rms (a)
41241 RO Power Factor Phase C % (a,b) 41415 RO Vab V rms
41242 RO Power Factor Total % 41416 RO Vbc V rms (b)
41243 RO kVA Phase A kVA (a) 41417 RO Vca V rms (b)
41244 RO kVA Phase B kVA (a) 41418 RO Vll average V rms
41246 RO kVA Total kVA 41420 RO Vaux V rms
41248 RO Frequency on Va 0.01 Hz 41421 RO Ia A rms
41422 RO Ib A rms
41250 RO Min. sliding demand polarity Bit mapped (d) 41423 RO Ic A rms (b)
MINIMUM SLIDING WINDOW TIMESTAMPS 41426 RO Neutral current (I4) A rms

41311 RO Van Unix Time (a,d)
41313 RO Vcn Unix Time (a,b,d)
41431 RO kW Phase A kW rms (a)
41314 RO Vln average Unix Time (a,d)
41315 RO Vab Unix Time (d)
41316 RO Vbc Unix Time (b,d)
41317 RO Vca Unix Time (b,d)
41318 RO Vll average Unix Time (d)
30
Register Register
41436 RO kVAR Phase B kVAR rms (a) 41611 RO Van V rms (a)
41437 RO kVAR Phase C kVAR rms (a,b) 41612 RO Vbn V rms (a)
41438 RO kVAR Total kVAR rms 41613 RO Vcn V rms (a,b)
41439 RO Power Factor Phase A % (a) 41614 RO Vln average V rms (a)
41440 RO Power Factor Phase B % (a) 41615 RO Vab V rms
41441 RO Power Factor Phase C % (a,b) 41616 RO Vbc V rms (b)
41442 RO Power Factor Total % 41617 RO Vca V rms (b)
41443 RO kVA Phase A kVA (a) 41618 RO Vll average V rms
41445 RO kVA Phase C kVA (a,b) 41620 RO Vaux V rms
41446 RO kVA Total kVA 41621 RO Ia A rms
41448 RO Frequency on Va 0.01 Hz 41622 RO Ib A rms
41623 RO Ic A rms (b)
41450 RO Max. sliding demand polarity Bit mapped (d) 41624 RO I average A rms

MAXIMUM SLIDING WINDOW TIMESTAMPS 41628 RO Voltage imbalance %
41511 RO Van Unix Time (a,d)
41512 RO Vbn Unix Time (a,d) 41631 RO kW Phase A kW rms (a)
41513 RO Vcn Unix Time (a,b,d) 41632 RO kW Phase B kW rms (a)
41514 RO Vln average Unix Time (a,d) 41633 RO kW Phase C kW rms (a,b)
41515 RO Vab Unix Time (d) 41634 RO kW Total kW rms
41516 RO Vbc Unix Time (b,d) 41635 RO kVAR Phase A kVAR rms (a)
41517 RO Vca Unix Time (b,d) 41636 RO kVAR Phase B kVAR rms (a)
41518 RO Vll average Unix Time (d) 41637 RO kVAR Phase C kVAR rms (a,b)
41520 RO Vaux Unix Time (d) 41639 RO Power Factor Phase A % (a)
41521 RO Ia Unix Time (d) 41640 RO Power Factor Phase B % (a)
41522 RO Ib Unix Time (d) 41641 RO Power Factor Phase C % (a,b)
41523 RO Ic Unix Time (b,d) 41642 RO Power Factor Total %
41524 RO I average Unix Time (d) 41643 RO kVA Phase A kVA (a)
41526 RO Neutral current (I4) Unix Time (d) 41645 RO kVA Phase C kVA (a,b)
41646 RO kVA Total kVA
41528 RO Voltage imbalance Unix Time (d) 41648 RO Frequency on Va 0.01 Hz
41650 RO Predicted demand polarity Bit mapped (d)
41534 RO kW Total Unix Time (d) MINIMUM PREDICTED DMD MEASUREMENTS
41536 RO kVAR Phase B Unix Time (a,d) 41711 RO Van V rms (a)
41537 RO kVAR Phase C Unix Time (a,b,d) 41712 RO Vbn V rms (a)
41538 RO kVAR Total Unix Time (d) 41713 RO Vcn V rms (a,b)
41539 RO Power Factor Phase A Unix Time (a,d) 41714 RO Vln average V rms (a)
41540 RO Power Factor Phase B Unix Time (a,d) 41715 RO Vab V rms
41541 RO Power Factor Phase C Unix Time (a,b,d) 41716 RO Vbc V rms (b)
41542 RO Power Factor Total Unix Time (d) 41717 RO Vca V rms (b)
41543 RO kVA Phase A Unix Time (a,d) 41718 RO Vll average V rms
41545 RO kVA Phase C Unix Time (a,b,d) 41720 RO Vaux V rms
41546 RO kVA Total Unix Time (d) 41721 RO Ia A rms
41722 RO Ib A rms
41548 RO Frequency on Va Unix Time (d) 41723 RO Ic A rms (b)

PREDICTED DEMAND MEASUREMENTS
31
Register Register
41729 RO Current imbalance % 41846 RO kVA Total Unix Time (d)
41731 RO kW Phase A kW rms (a) 41848 RO Frequency on Va Unix Time (d)

MAXIMUM PREDICTED DMD MEASUREMENTS
41737 RO kVAR Phase C kVAR rms (a,b) 41911 RO Van V rms (a)
41738 RO kVAR Total kVAR rms 41912 RO Vbn V rms (a)
41739 RO Power Factor Phase A % (a) 41913 RO Vcn V rms (a,b)
41740 RO Power Factor Phase B % (a) 41914 RO Vln average V rms (a)
41741 RO Power Factor Phase C % (a,b) 41915 RO Vab V rms
41742 RO Power Factor Total % 41916 RO Vbc V rms (b)
41743 RO kVA Phase A kVA (a) 41917 RO Vca V rms (b)
41744 RO kVA Phase B kVA (a) 41918 RO Vll average V rms
41746 RO kVA Total kVA 41920 RO Vaux V rms
41748 RO Frequency on Va 0.01 Hz 41921 RO Ia A rms
41922 RO Ib A rms
41750 RO Min. predicted dmd polarity Bit mapped (d) 41923 RO Ic A rms (b)

MINIMUM PREDICTED DMD TIMESTAMPS
41811 RO Van Unix Time (a,d) 41929 RO Current imbalance %
41813 RO Vcn Unix Time (a,b,d) 41931 RO kW Phase A kW rms (a)
41814 RO Vln average Unix Time (a,d) 41932 RO kW Phase B kW rms (a)
41815 RO Vab Unix Time (d) 41933 RO kW Phase C kW rms (a,b)
41816 RO Vbc Unix Time (b,d) 41934 RO kW Total kW rms
41817 RO Vca Unix Time (b,d) 41935 RO kVAR Phase A kVAR rms (a)
41818 RO Vll average Unix Time (d) 41936 RO kVAR Phase B kVAR rms (a)
41820 RO Vaux Unix Time (d) 41938 RO kVAR Total kVAR rms
41821 RO Ia Unix Time (d) 41939 RO Power Factor Phase A % (a)
41822 RO Ib Unix Time (d) 41940 RO Power Factor Phase B % (a)
41823 RO Ic Unix Time (b,d) 41941 RO Power Factor Phase C % (a,b)
41824 RO I average Unix Time (d) 41942 RO Power Factor Total %
41826 RO Neutral current (I4) Unix Time (d) 41944 RO kVA Phase B kVA (a)
41828 RO Voltage imbalance Unix Time (d) 41946 RO kVA Total kVA
41829 RO Current imbalance Unix Time (d) 41948 RO Frequency on Va 0.01 Hz
41831 RO kW Phase A Unix Time (a,d) 41950 RO Max. predicted dmd polarity Bit mapped (d)
MAXIMUM PREDICTED DMD TIMESTAMPS
41837 RO kVAR Phase C Unix Time (a,b,d) 42011 RO Van Unix Time (a,d)
41838 RO kVAR Total Unix Time (d) 42012 RO Vbn Unix Time (a,d)
41839 RO Power Factor Phase A Unix Time (a,d) 42013 RO Vcn Unix Time (a,b,d)
41840 RO Power Factor Phase B Unix Time (a,d) 42014 RO Vln average Unix Time (a,d)
41841 RO Power Factor Phase C Unix Time (a,b,d) 42015 RO Vab Unix Time (d)
41842 RO Power Factor Total Unix Time (d) 42016 RO Vbc Unix Time (b,d)
41843 RO kVA Phase A Unix Time (a,d) 42017 RO Vca Unix Time (b,d)
41844 RO kVA Phase B Unix Time (a,d) 42018 RO Vll average Unix Time (d)
42020 RO Vaux Unix Time (d)
32
Register Register
42021 RO Ia Unix Time (d)
42022 RO Ib Unix Time (d)
42023 RO Ic Unix Time (b,d)


42038 RO kVAR Total Unix Time (d)
42039 RO Power Factor Phase A Unix Time (a,d)
42040 RO Power Factor Phase B Unix Time (a,d)
42041 RO Power Factor Phase C Unix Time (a,b,d)
42042 RO Power Factor Total Unix Time (d)
42046 RO kVA Total Unix Time (d)
WAVEFORM RECORDER WINDOW
42100 RW WFR Channel Number Channel (e)

42101 RW Number of logs to read (1) (e)
42102 RW WFR Log index counter (e)
42103 RO Number of channels (e)
42104 RO Samples per channel (e)
42105 RO Sampling Frequency samples/sec (e)
42106 RO Trigger Type (e)
42107 RO WFR trigger time, seconds MSW (e)
42108 RO WFR trigger time, seconds LSW (e)
42109 RO WFR trigger time, µseconds MSW (e)
42110 RO WFR trigger time, µseconds LSW (e)
42111 RO WFR record time, seconds MSW (e)
42112 RO WFR record time, seconds LSW (e)
42113 RO WFR record time, µseconds MSW (e)
42114 RO WFR record time, µseconds LSW (e)
42115 RO Multiplier MSW (e)
42116 RO Multiplier LSW (e)
42117 RO Divisor MSW (e)
42118 RO Divisor LSW (e)
42119 RO Offset MSW (e)
42120 RO Offset LSW (e)
42121 - 42696 WFR Samples 1-576 unscaled (e)
33
Register
Address Type Description Units Notes
DEVICE CONFIGURATION PARAMETERS
43002 RW Volts full scale (0 - 999999 V rms)

43003 RW V aux. full scale (0 - 999999 V rms)
43004 RW Current full scale (0 - 30000 A rms)
43005 RW Measurement mode (0=4W Wye, 1=Delta, 2=Single, 3=Demo, 4=3W Wye)
43006 RW Slave ID (1-247) (d)
43007 RW Baudrate (0=300, 1=1200, 2=2400, 3=4800, 4=9600, 5=19200, 6=38400,
7=57600, 8=115200)
43008 RW Sliding demand period (1 - 99 minutes, 0 = Off)
43009 RW Neutral current full scale (I4) (0 - 9999 A rms)
43010 WO Password (0 - 9999)
43011 WO Reset all min/max logs (1 = Reset all min/max parameters)
43012 WO Reset integrators (1 = Reset kWh, kVARh, kVAh integrators)
43013 RO Firmware revision (in hex. Ex Rev 1.5.0.2 = 1502h) (d)
43016 RO Device type (3720d)
43018 RW Number of sliding demand periods (0 -15)

43019 RW Sliding demand synchronisation (0 = Internal, 1 = External (status input #4)
43020 RW Thermal demand period (1 - 99 minutes, 0 = Off)
43021 RW Phase rotation (0 = Positive, 1 = Negative)
43022 RW Iout range (0 = 0-20 mA, 1 = 4-20 mA)
43023 RW Iout key
43024 RW Iout full scale (0 - 999999)
43025 RW Standard frequency (0 = 60 Hz, 1 = 50 Hz)
43026 RO Serial communication mode (0 = RS-232, 1 = RS-485)
43027 RW Relay #1 operating mode (d)
43028 RW Relay #1 operating value (d)
43033 RW Log status input transitions (d)
43034 WO Trigger waveform capture channel (d)
43035 RW Preset S1 counter Counts (d)
43041 RW RTS line mode (0 = Active Low, 1 = Active High)

43042 RW Display time-out (1-999 minutes, 0 = Remain on)
43043 RW Phase labels (0 = ABC, 1 = XYZ, 2 = RYB, 3 = RST)
43044 RW Numeric format (0 = 1,234.5 1 = 1234,5)
43045 RW Extended diagnostics (0 = No, 1 = Yes)
43046 RW V aux. zero scale (-999999 - 999999)
43047 RW Iout zero scale (-999999 - 999999)
43048 RW Prediction base (1 - 99 %, 0 = Off)
43051 WO Packet password (0-9999) (d)

43052 RW Sliding window #1 key Config key (d)
34
Register
43063 RW Active Protocol (0 = None, 1 = PML 3720, 2 = Modbus, 3 = PML3720AD,

4 = AB DF-1)
43064 RW Register Size (0 = 16 bits, 1 = 32 bits)
43065 RW Return Invalid Objects (0 = No, 1 = Yes)
43066 RW Password Protect (0 = No, 1 = Yes)
43067 RW Transmit Delay (0 - 999 ms)
43071 RW S1 Counter scale Counts/Pulse (d)

43076 RW S1 Counter roll-over Counts (d)

43084 RW Waveform Recorder Depth (1=1 x 36 cycles, 2=2 x 18 cycles, 3=3 x 12 cycles)
43086 WO Waveform Recorder Manual Trigger/Rearm (0 = rearm, nonzero = trigger) (d)
EVENT COUNTERS
43201 RO Setpoints changed state STCOUNT (d)
43204 RO Sliding demand config STCOUNT (d)

43205 RO Event log STCOUNT (d)
43207 RO Min/Max STCOUNT (d)

43208 RO Waveform capture STCOUNT (d)
43209 RO Waveform Recorder size counter Counts (d)
43210 RO Waveform Recorder data counter Counts (d)
43217 RO Integrator reset STCOUNT (d)

43218 RO All min/max log reset STCOUNT (d)
43219 RO Real-time min/max STCOUNT (d)
43220 RO Thermal dmd min/max STCOUNT (d)
43221 RO Sliding demand min/max STCOUNT (d)
43222 RO Harmonic Va min/max STCOUNT (d)
43223 RO Harmonic Vb min/max STCOUNT (d)
43224 RO Harmonic Vc min/max STCOUNT (d)
43225 RO Harmonic Vaux. min/max STCOUNT (d)
43226 RO Harm. Va dmd min/max STCOUNT (d)
43227 RO Harm. Vb dmd min/max STCOUNT (d)
43228 RO Harm. Vc dmd min/max STCOUNT (d)
43229 RO Harm Vaux dmd min/max STCOUNT (d)
43230 RO Harmonic Ia min/max STCOUNT (d)
43231 RO Harmonic Ib min/max STCOUNT (d)
43232 RO Harmonic Ic min/max STCOUNT (d)
43233 RO Harmonic I4 min/max STCOUNT (d)
43234 RO Harm. Ia dmd min/max STCOUNT (d)
43235 RO Harm. Ib dmd min/max STCOUNT (d)
43236 RO Harm. Ic dmd min/max STCOUNT (d)
43237 RO Harm. I4 dmd min/max STCOUNT (d)
43238 RO Predicted dmd min/max STCOUNT (d)
43241 RO Relay #1 Counts (d)

35
Register
43244 RO Setpoint #1 STCOUNT (d)

43255 RO High speed setpoint #1 STCOUNT (d)
SETPOINT SYSTEM CONFIGURATION
43301 - 43310 Setpoint #1

43311 - 43320 Setpoint #2 General Setpoint Format (d)
43321 - 43330 Setpoint #3
43331 - 43340 Setpoint #4
+0 RW Operation Flags
43341 - 43350 Setpoint #5
+1 RW Trigger Key
43351 - 43360 Setpoint #6
+2 RW High Limit - High order word
43361 - 43370 Setpoint #7
+3 RW High Limit - Low order word
43371 - 43380 Setpoint #8
+4 RW Low Limit - High order word
43381 - 43390 Setpoint #9
+5 RW Low Limit - Low order word
43391 - 43400 Setpoint #10
+6 RW Time delay to operate (STD = Seconds, HS = Cycles)
43401 - 43410 Setpoint #11
+7 RW Time delay to release (STD = Seconds, HS = Cycles)
+8 RW Action #1 Key
43411 - 43420 High speed setpoint #1
+9 RW Action #2 Key
36
Register
WAVEFORM CAPTURE LOG
43501 RO Waveform channel number channel

43502 RO Number of sample points (128)
43503 RO Sample point delay uS
43504 RO Trigger type 0=manual trigger, 1-17 = setpoint number
43505-43600 128 sample points packed
37
Register
43759 RO Peak Demand Register #3, Tariff #9 (d)
TIME OF USE INFORMATION 43761 RO Active Tariff (d)
43762 RO Energy Register #1 Configuration (d)
43701 RO Energy Register #1, Tariff #1 (d) 43763 RO Energy Register #2 Configuration (d)
43702 RO Energy Register #1, Tariff #2 (d) 43764 RO Energy Register #3 Configuration (d)
43703 RO Energy Register #1, Tariff #3 (d) 43765 RO Peak Demand Register #1 Configuration (d)
43706 RO Energy Register #1, Tariff #6 (d) 43768 RO Active Profile (d)
43707 RO Energy Register #1, Tariff #7 (d)
38
Register Register
Address Description Address Description
44431 - 44440 Event #44
44441 - 44450 Event #45
DEVICE EVENT LOG 44451 - 44460 Event #46
44461 - 44470 Event #47
44001 - 44010 Event #1 (Most Recent) 44471 - 44480 Event #48
44011 - 44020 Event #2 44481 - 44490 Event #49
44021 - 44030 Event #3 44491 - 44500 Event #50
General Event Format (d)
+0 RO Event Time - UNIX Time format - High order word

+1 RO Event Time - UNIX Time format - Low order word
+2 RO Event Time - microseconds - High order word
+3 RO Event Time - microseconds - Low order word
+4 RO Event Cause Key
+5 RO Event Cause Value - High order word
+6 RO Event Cause Value - Low order word
+7 RO Event Effect Key
+8 RO Event Effect Value - High order word
+9 RO Event Effect Value - Low order word
44031 - 44040 Event #4 44501 - 44510 Event #51

44041 - 44050 Event #5 44511 - 44520 Event #52
44051 - 44060 Event #6 44521 - 44530 Event #53
44061 - 44070 Event #7 44531 - 44540 Event #54
44071 - 44080 Event #8 44541 - 44550 Event #55
44081 - 44090 Event #9 44551 - 44560 Event #56
44091 - 44100 Event #10 44561 - 44570 Event #57
44101 - 44110 Event #11 44571 - 44580 Event #58
44111 - 44120 Event #12 44581 - 44590 Event #59
44121 - 44130 Event #13 44591 - 44600 Event #60
44131 - 44140 Event #14 44601 - 44610 Event #61
44141 - 44150 Event #15 44611 - 44620 Event #62
44151 - 44160 Event #16 44621 - 44630 Event #63
44161 - 44170 Event #17 44631 - 44640 Event #64
44171 - 44180 Event #18 44641 - 44650 Event #65
44181 - 44190 Event #19 44651 - 44660 Event #66
44191 - 44200 Event #20 44661 - 44670 Event #67
44201 - 44210 Event #21 44671 - 44680 Event #68
44211 - 44220 Event #22 44681 - 44690 Event #69
44221 - 44230 Event #23 44691 - 44700 Event #70
44231 - 44240 Event #24 44701 - 44710 Event #71
44241 - 44250 Event #25 44711 - 44720 Event #72
44251 - 44260 Event #26 44721 - 44730 Event #73
44261 - 44270 Event #27 44731 - 44740 Event #74
44271 - 44280 Event #28 44741 - 44750 Event #75
44281 - 44290 Event #29 44751 - 44760 Event #76
44291 - 44300 Event #30 44761 - 44770 Event #77
44301 - 44310 Event #31 44771 - 44780 Event #78
44311 - 44320 Event #32 44781 - 44790 Event #79
44321 - 44330 Event #33 44791 - 44800 Event #80
44331 - 44340 Event #34 44801 - 44810 Event #81
44341 - 44350 Event #35 44811 - 44820 Event #82
44351 - 44360 Event #36 44821 - 44830 Event #83
44361 - 44370 Event #37 44831 - 44840 Event #84
44371 - 44380 Event #38 44841 - 44850 Event #85
44381 - 44390 Event #39 44851 - 44860 Event #86
44391 - 44400 Event #40 44861 - 44870 Event #87
44401 - 44410 Event #41 44871 - 44880 Event #88
44411 - 44420 Event #42 44881 - 44890 Event #89
44421 - 44430 Event #43 44891 - 44900 Event #90
39
Register Register
Address Description Address Description
44901 - 44910 Event #91
44911 - 44920 Event #92
44921 - 44930 Event #93
44931 - 44940 Event #94
44941 - 44950 Event #95
44951 - 44960 Event #96
44961 - 44970 Event #97
44971 - 44980 Event #98
44981 - 44990 Event #99
44991 - 45000 Event #100 (Least Recent)
40
Register Register
45107 RO Vc Harmonic #4 Dist. 0.1 %
45108 RO V aux. Harmonic #4 Dist. 0.1 %
REAL TIME HARMONIC MEASUREMENTS 45109 RO Ia Harmonic #4 Dist. 0.1 %
45110 RO Ib Harmonic #4 Dist. 0.1 %
45049 RO Va K-Factor 0.1 45111 RO Ic Harmonic #4 Dist. 0.1 %
45050 RO Vb K-Factor 0.1 45112 RO I4 Harmonic #4 Dist. 0.1 %
45051 RO Vc K-Factor 0.1 45113 RO Va Harmonic #5 Dist. 0.1 %
45052 RO V aux. K-Factor 0.1 45114 RO Vb Harmonic #5 Dist. 0.1 %
45053 RO Ia K-Factor 0.1 45115 RO Vc Harmonic #5 Dist. 0.1 %
45054 RO Ib K-Factor 0.1 45116 RO V aux. Harmonic #5 Dist. 0.1 %
45055 RO Ic K-Factor 0.1 45117 RO Ia Harmonic #5 Dist. 0.1 %
45056 RO I4 (Neutral) K-Factor 0.1 45118 RO Ib Harmonic #5 Dist. 0.1 %
45057 RO Va Total Odd Harm. Dist. 0.1 % 45119 RO Ic Harmonic #5 Dist. 0.1 %
45058 RO Vb Total Odd Harm. Dist. 0.1 % 45120 RO I4 Harmonic #5 Dist. 0.1 %
45059 RO Vc Total Odd Harm. Dist. 0.1 % 45121 RO Va Harmonic #6 Dist. 0.1 %
45060 RO V aux. Total Odd Harm. Dist. 0.1 % 45122 RO Vb Harmonic #6 Dist. 0.1 %
45061 RO Ia Total Odd Harm. Dist. 0.1 % 45123 RO Vc Harmonic #6 Dist. 0.1 %
45062 RO Ib Total Odd Harm. Dist. 0.1 % 45124 RO V aux. Harmonic #6 Dist. 0.1 %
45063 RO Ic Total Odd Harm. Dist. 0.1 % 45125 RO Ia Harmonic #6 Dist. 0.1 %
45064 RO I4 Total Odd Harm. Dist. 0.1 % 45126 RO Ib Harmonic #6 Dist. 0.1 %
45065 RO Va Total Even Harm. Dist 0.1 % 45127 RO Ic Harmonic #6 Dist. 0.1 %
45066 RO Vb Total Even Harm. Dist. 0.1 % 45128 RO I4 Harmonic #6 Dist. 0.1 %
45067 RO Vc Total Even Harm. Dist. 0.1 % 45129 RO Va Harmonic #7 Dist. 0.1 %
45068 RO V aux. Total Even Harm. Dist. 0.1 % 45130 RO Vb Harmonic #7 Dist. 0.1 %
45069 RO Ia Total Even Harm. Dist. 0.1 % 45131 RO Vc Harmonic #7 Dist. 0.1 %
45070 RO Ib Total Even Harm. Dist. 0.1 % 45132 RO V aux. Harmonic #7 Dist. 0.1 %
45071 RO Ic Total Even Harm. Dist. 0.1 % 45133 RO Ia Harmonic #7 Dist. 0.1 %
45072 RO I4 Total Even Harm. Dist. 0.1 % 45134 RO Ib Harmonic #7 Dist. 0.1 %
45073 RO Va Total Harmonic Dist. 0.1 % 45135 RO Ic Harmonic #7 Dist. 0.1 %
45074 RO Vb Total Harmonic Dist. 0.1 % 45136 RO I4 Harmonic #7 Dist. 0.1 %
45075 RO Vc Total Harmonic Dist. 0.1 % 45137 RO Va Harmonic #8 Dist. 0.1 %
45076 RO V aux. Total Harmonic Dist. 0.1 % 45138 RO Vb Harmonic #8 Dist. 0.1 %
45077 RO Ia Total Harmonic Dist. 0.1 % 45139 RO Vc Harmonic #8 Dist. 0.1 %
45078 RO Ib Total Harmonic Dist. 0.1 % 45140 RO V aux. Harmonic #8 Dist. 0.1 %
45079 RO Ic Total Harmonic Dist. 0.1 % 45141 RO Ia Harmonic #8 Dist. 0.1 %
45080 RO I4 Total Harmonic Dist. 0.1 % 45142 RO Ib Harmonic #8 Dist. 0.1 %
45081 RO Va fundamental Dist. 0.1 % 45143 RO Ic Harmonic #8 Dist. 0.1 %
45082 RO Vb fundamental Dist. 0.1 % 45144 RO I4 Harmonic #8 Dist. 0.1 %
45083 RO Vc fundamental Dist. 0.1 % 45145 RO Va Harmonic #9 Dist. 0.1 %
45084 RO V aux. fundamental Dist. 0.1 % 45146 RO Vb Harmonic #9 Dist. 0.1 %
45085 RO Ia fundamental Dist. 0.1 % 45147 RO Vc Harmonic #9 Dist. 0.1 %
45086 RO Ib fundamental Dist. 0.1 % 45148 RO V aux. Harmonic #9 Dist. 0.1 %
45087 RO Ic fundamental Dist. 0.1 % 45149 RO Ia Harmonic #9 Dist. 0.1 %
45088 RO I4 fundamental Dist. 0.1 % 45150 RO Ib Harmonic #9 Dist. 0.1 %
45089 RO Va Harmonic #2 Dist. 0.1 % 45151 RO Ic Harmonic #9 Dist. 0.1 %
45090 RO Vb Harmonic #2 Dist. 0.1 % 45152 RO I4 Harmonic #9 Dist. 0.1 %
45091 RO Vc Harmonic #2 Dist. 0.1 % 45153 RO Va Harmonic #10 Dist. 0.1 %
45092 RO V aux. Harmonic #2 Dist. 0.1 % 45154 RO Vb Harmonic #10 Dist. 0.1 %
45093 RO Ia Harmonic #2 Dist. 0.1 % 45155 RO Vc Harmonic #10 Dist. 0.1 %
45094 RO Ib Harmonic #2 Dist. 0.1 % 45156 RO V aux. Harmonic #10 Dist. 0.1 %
45095 RO Ic Harmonic #2 Dist. 0.1 % 45157 RO Ia Harmonic #10 Dist. 0.1 %
45096 RO I4 Harmonic #2 Dist. 0.1 % 45158 RO Ib Harmonic #10 Dist. 0.1 %
41
45169 RO Va Harmonic #12 Dist. 0.1 % 45272 RO I4 Total Even Harm. Dist. 0.1 %
45170 RO Vb Harmonic #12 Dist. 0.1 % 45273 RO Va Total Harmonic Dist. 0.1 %
45171 RO Vc Harmonic #12 Dist. 0.1 % 45274 RO Vb Total Harmonic Dist. 0.1 %
45172 RO V aux. Harmonic #12 Dist. 0.1 % 45275 RO Vc Total Harmonic Dist. 0.1 %
45173 RO Ia Harmonic #12 Dist. 0.1 % 45276 RO V aux. Total Harmonic Dist. 0.1 %
45174 RO Ib Harmonic #12 Dist. 0.1 % 45277 RO Ia Total Harmonic Dist. 0.1 %
45175 RO Ic Harmonic #12 Dist. 0.1 % 45278 RO Ib Total Harmonic Dist. 0.1 %
45176 RO I4 Harmonic #12 Dist. 0.1 % 45279 RO Ic Total Harmonic Dist. 0.1 %
45177 RO Va Harmonic #13 Dist. 0.1 % 45280 RO I4 Total Harmonic Dist. 0.1 %
45178 RO Vb Harmonic #13 Dist. 0.1 % 45281 RO Va fundamental Dist. 0.1 %
45179 RO Vc Harmonic #13 Dist. 0.1 % 45282 RO Vb fundamental Dist. 0.1 %
45180 RO V aux. Harmonic #13 Dist. 0.1 % 45283 RO Vc fundamental Dist. 0.1 %
45181 RO Ia Harmonic #13 Dist. 0.1 % 45284 RO V aux. fundamental Dist. 0.1 %
45182 RO Ib Harmonic #13 Dist. 0.1 % 45285 RO Ia fundamental Dist. 0.1 %
45183 RO Ic Harmonic #13 Dist. 0.1 % 45286 RO Ib fundamental Dist. 0.1 %
45184 RO I4 Harmonic #13 Dist. 0.1 % 45287 RO Ic fundamental Dist. 0.1 %
45185 RO Va Harmonic #14 Dist. 0.1 % 45288 RO I4 fundamental Dist. 0.1 %
45186 RO Vb Harmonic #14 Dist. 0.1 % 45289 RO Va Harmonic #2 Dist. 0.1 %
45187 RO Vc Harmonic #14 Dist. 0.1 % 45290 RO Vb Harmonic #2 Dist. 0.1 %
45188 RO V aux. Harmonic #14 Dist. 0.1 % 45291 RO Vc Harmonic #2 Dist. 0.1 %
45189 RO Ia Harmonic #14 Dist. 0.1 % 45292 RO V aux. Harmonic #2 Dist. 0.1 %
45190 RO Ib Harmonic #14 Dist. 0.1 % 45293 RO Ia Harmonic #2 Dist. 0.1 %
45191 RO Ic Harmonic #14 Dist. 0.1 % 45294 RO Ib Harmonic #2 Dist. 0.1 %
45192 RO I4 Harmonic #14 Dist. 0.1 % 45295 RO Ic Harmonic #2 Dist. 0.1 %
45193 RO Va Harmonic #15 Dist. 0.1 % 45296 RO I4 Harmonic #2 Dist. 0.1 %
45304 RO I4 Harmonic #3 Dist. 0.1 %
45305 RO Va Harmonic #4 Dist. 0.1 %
45306 RO Vb Harmonic #4 Dist. 0.1 %
MINIMUM REAL TIME HARMONIC 45307 RO Vc Harmonic #4 Dist. 0.1 %
MEASUREMENTS 45308 RO V aux. Harmonic #4 Dist. 0.1 %
45309 RO Ia Harmonic #4 Dist. 0.1 %
45249 RO Va K-Factor 0.1 45310 RO Ib Harmonic #4 Dist. 0.1 %
45250 RO Vb K-Factor 0.1 45311 RO Ic Harmonic #4 Dist. 0.1 %
45251 RO Vc K-Factor 0.1 45312 RO I4 Harmonic #4 Dist. 0.1 %
45252 RO V aux. K-Factor 0.1 45313 RO Va Harmonic #5 Dist. 0.1 %
45253 RO Ia K-Factor 0.1 45314 RO Vb Harmonic #5 Dist. 0.1 %
45254 RO Ib K-Factor 0.1 45315 RO Vc Harmonic #5 Dist. 0.1 %
45255 RO Ic K-Factor 0.1 45316 RO V aux. Harmonic #5 Dist. 0.1 %
45256 RO I4 (Neutral) K-Factor 0.1 45317 RO Ia Harmonic #5 Dist. 0.1 %
45257 RO Va Total Odd Harm. Dist. 0.1 % 45318 RO Ib Harmonic #5 Dist. 0.1 %
45258 RO Vb Total Odd Harm. Dist. 0.1 % 45319 RO Ic Harmonic #5 Dist. 0.1 %
45259 RO Vc Total Odd Harm. Dist. 0.1 % 45320 RO I4 Harmonic #5 Dist. 0.1 %
45260 RO V aux. Total Odd Harm. Dist. 0.1 % 45321 RO Va Harmonic #6 Dist. 0.1 %
45261 RO Ia Total Odd Harm. Dist. 0.1 % 45322 RO Vb Harmonic #6 Dist. 0.1 %
45262 RO Ib Total Odd Harm. Dist. 0.1 % 45323 RO Vc Harmonic #6 Dist. 0.1 %
45263 RO Ic Total Odd Harm. Dist. 0.1 % 45324 RO V aux. Harmonic #6 Dist. 0.1 %
45264 RO I4 Total Odd Harm. Dist. 0.1 % 45325 RO Ia Harmonic #6 Dist. 0.1 %
45265 RO Va Total Even Harm. Dist 0.1 % 45326 RO Ib Harmonic #6 Dist. 0.1 %
45266 RO Vb Total Even Harm. Dist. 0.1 % 45327 RO Ic Harmonic #6 Dist. 0.1 %
45267 RO Vc Total Even Harm. Dist. 0.1 % 45328 RO I4 Harmonic #6 Dist. 0.1 %
45268 RO V aux. Total Even Harm. Dist. 0.1 % 45329 RO Va Harmonic #7 Dist. 0.1 %
45269 RO Ia Total Even Harm. Dist. 0.1 % 45330 RO Vb Harmonic #7 Dist. 0.1 %
45270 RO Ib Total Even Harm. Dist. 0.1 % 45331 RO Vc Harmonic #7 Dist. 0.1 %
45271 RO Ic Total Even Harm. Dist. 0.1 % 45332 RO V aux. Harmonic #7 Dist. 0.1 %
42
Register Register
MINIMUM REAL TIME HARMONIC
45343 RO Ic Harmonic #8 Dist. 0.1 % TIMESTAMPS
45345 RO Va Harmonic #9 Dist. 0.1 % 45449 RO Va K-Factor Unix Time (d)
45346 RO Vb Harmonic #9 Dist. 0.1 % 45450 RO Vb K-Factor Unix Time (d)
45347 RO Vc Harmonic #9 Dist. 0.1 % 45451 RO Vc K-Factor Unix Time (d)
45348 RO V aux. Harmonic #9 Dist. 0.1 % 45452 RO V aux. K-Factor Unix Time (d)
45349 RO Ia Harmonic #9 Dist. 0.1 % 45453 RO Ia K-Factor Unix Time (d)
45350 RO Ib Harmonic #9 Dist. 0.1 % 45454 RO Ib K-Factor Unix Time (d)
45351 RO Ic Harmonic #9 Dist. 0.1 % 45455 RO Ic K-Factor Unix Time (d)
45352 RO I4 Harmonic #9 Dist. 0.1 % 45456 RO I4 (Neutral) K-Factor Unix Time (d)
45353 RO Va Harmonic #10 Dist. 0.1 % 45457 RO Va Total Odd Harm. Dist. Unix Time (d)
45354 RO Vb Harmonic #10 Dist. 0.1 % 45458 RO Vb Total Odd Harm. Dist. Unix Time (d)
45355 RO Vc Harmonic #10 Dist. 0.1 % 45459 RO Vc Total Odd Harm. Dist. Unix Time (d)
45356 RO V aux. Harmonic #10 Dist. 0.1 % 45460 RO V aux. Total Odd Harm. Dist. Unix Time (d)
45357 RO Ia Harmonic #10 Dist. 0.1 % 45461 RO Ia Total Odd Harm. Dist. Unix Time (d)
45358 RO Ib Harmonic #10 Dist. 0.1 % 45462 RO Ib Total Odd Harm. Dist. Unix Time (d)
45359 RO Ic Harmonic #10 Dist. 0.1 % 45463 RO Ic Total Odd Harm. Dist. Unix Time (d)
45360 RO I4 Harmonic #10 Dist. 0.1 % 45464 RO I4 Total Odd Harm. Dist. Unix Time (d)
45361 RO Va Harmonic #11 Dist. 0.1 % 45465 RO Va Total Even Harm. Dist Unix Time (d)
45362 RO Vb Harmonic #11 Dist. 0.1 % 45466 RO Vb Total Even Harm. Dist. Unix Time (d)
45363 RO Vc Harmonic #11 Dist. 0.1 % 45467 RO Vc Total Even Harm. Dist. Unix Time (d)
45364 RO V aux. Harmonic #11 Dist. 0.1 % 45468 RO V aux. Total Even Harm. Dist. Unix Time (d)
45365 RO Ia Harmonic #11 Dist. 0.1 % 45469 RO Ia Total Even Harm. Dist. Unix Time (d)
45366 RO Ib Harmonic #11 Dist. 0.1 % 45470 RO Ib Total Even Harm. Dist. Unix Time (d)
45367 RO Ic Harmonic #11 Dist. 0.1 % 45471 RO Ic Total Even Harm. Dist. Unix Time (d)
45368 RO I4 Harmonic #11 Dist. 0.1 % 45472 RO I4 Total Even Harm. Dist. Unix Time (d)
45369 RO Va Harmonic #12 Dist. 0.1 % 45473 RO Va Total Harmonic Dist. Unix Time (d)
45370 RO Vb Harmonic #12 Dist. 0.1 % 45474 RO Vb Total Harmonic Dist. Unix Time (d)
45371 RO Vc Harmonic #12 Dist. 0.1 % 45475 RO Vc Total Harmonic Dist. Unix Time (d)
45372 RO V aux. Harmonic #12 Dist. 0.1 % 45476 RO V aux. Total Harmonic Dist. Unix Time (d)
45373 RO Ia Harmonic #12 Dist. 0.1 % 45477 RO Ia Total Harmonic Dist. Unix Time (d)
45374 RO Ib Harmonic #12 Dist. 0.1 % 45478 RO Ib Total Harmonic Dist. Unix Time (d)
45375 RO Ic Harmonic #12 Dist. 0.1 % 45479 RO Ic Total Harmonic Dist. Unix Time (d)
45376 RO I4 Harmonic #12 Dist. 0.1 % 45480 RO I4 Total Harmonic Dist. Unix Time (d)
45377 RO Va Harmonic #13 Dist. 0.1 % 45481 RO Va fundamental Dist. Unix Time (d)
45378 RO Vb Harmonic #13 Dist. 0.1 % 45482 RO Vb fundamental Dist. Unix Time (d)
45379 RO Vc Harmonic #13 Dist. 0.1 % 45483 RO Vc fundamental Dist. Unix Time (d)
45380 RO V aux. Harmonic #13 Dist. 0.1 % 45484 RO V aux. fundamental Dist. Unix Time (d)
45381 RO Ia Harmonic #13 Dist. 0.1 % 45485 RO Ia fundamental Dist. Unix Time (d)
45382 RO Ib Harmonic #13 Dist. 0.1 % 45486 RO Ib fundamental Dist. Unix Time (d)
45383 RO Ic Harmonic #13 Dist. 0.1 % 45487 RO Ic fundamental Dist. Unix Time (d)
45384 RO I4 Harmonic #13 Dist. 0.1 % 45488 RO I4 fundamental Dist. Unix Time (d)
45385 RO Va Harmonic #14 Dist. 0.1 % 45489 RO Va Harmonic #2 Dist. Unix Time (d)
45386 RO Vb Harmonic #14 Dist. 0.1 % 45490 RO Vb Harmonic #2 Dist. Unix Time (d)
45387 RO Vc Harmonic #14 Dist. 0.1 % 45491 RO Vc Harmonic #2 Dist. Unix Time (d)
45388 RO V aux. Harmonic #14 Dist. 0.1 % 45492 RO V aux. Harmonic #2 Dist. Unix Time (d)
45389 RO Ia Harmonic #14 Dist. 0.1 % 45493 RO Ia Harmonic #2 Dist. Unix Time (d)
45390 RO Ib Harmonic #14 Dist. 0.1 % 45494 RO Ib Harmonic #2 Dist. Unix Time (d)
45391 RO Ic Harmonic #14 Dist. 0.1 % 45495 RO Ic Harmonic #2 Dist. Unix Time (d)
45392 RO I4 Harmonic #14 Dist. 0.1 % 45496 RO I4 Harmonic #2 Dist. Unix Time (d)
43
45499 RO Vc Harmonic #3 Dist. Unix Time (d) 45561 RO Va Harmonic #11 Dist. Unix Time (d)
45500 RO V aux. Harmonic #3 Dist. Unix Time (d) 45562 RO Vb Harmonic #11 Dist. Unix Time (d)
45501 RO Ia Harmonic #3 Dist. Unix Time (d) 45563 RO Vc Harmonic #11 Dist. Unix Time (d)
45502 RO Ib Harmonic #3 Dist. Unix Time (d) 45564 RO V aux. Harmonic #11 Dist. Unix Time (d)
45503 RO Ic Harmonic #3 Dist. Unix Time (d) 45565 RO Ia Harmonic #11 Dist. Unix Time (d)
45504 RO I4 Harmonic #3 Dist. Unix Time (d) 45566 RO Ib Harmonic #11 Dist. Unix Time (d)
45505 RO Va Harmonic #4 Dist. Unix Time (d) 45567 RO Ic Harmonic #11 Dist. Unix Time (d)
45506 RO Vb Harmonic #4 Dist. Unix Time (d) 45568 RO I4 Harmonic #11 Dist. Unix Time (d)
45539 RO Vc Harmonic #8 Dist. Unix Time (d)
45540 RO V aux. Harmonic #8 Dist. Unix Time (d)
45541 RO Ia Harmonic #8 Dist. Unix Time (d)
45542 RO Ib Harmonic #8 Dist. Unix Time (d)
MAXIMUM REAL TIME HARMONIC
45543 RO Ic Harmonic #8 Dist. Unix Time (d) MEASUREMENTS
45544 RO I4 Harmonic #8 Dist. Unix Time (d)
45545 RO Va Harmonic #9 Dist. Unix Time (d) 45649 RO Va K-Factor 0.1
45546 RO Vb Harmonic #9 Dist. Unix Time (d) 45650 RO Vb K-Factor 0.1
45547 RO Vc Harmonic #9 Dist. Unix Time (d) 45651 RO Vc K-Factor 0.1
45548 RO V aux. Harmonic #9 Dist. Unix Time (d) 45652 RO V aux. K-Factor 0.1
45549 RO Ia Harmonic #9 Dist. Unix Time (d) 45653 RO Ia K-Factor 0.1
45550 RO Ib Harmonic #9 Dist. Unix Time (d) 45654 RO Ib K-Factor 0.1
45551 RO Ic Harmonic #9 Dist. Unix Time (d) 45655 RO Ic K-Factor 0.1
45552 RO I4 Harmonic #9 Dist. Unix Time (d) 45656 RO I4 (Neutral) K-Factor 0.1
45553 RO Va Harmonic #10 Dist. Unix Time (d) 45657 RO Va Total Odd Harm. Dist. 0.1 %
45554 RO Vb Harmonic #10 Dist. Unix Time (d) 45658 RO Vb Total Odd Harm. Dist. 0.1 %
45555 RO Vc Harmonic #10 Dist. Unix Time (d) 45659 RO Vc Total Odd Harm. Dist. 0.1 %
45556 RO V aux. Harmonic #10 Dist. Unix Time (d) 45660 RO V aux. Total Odd Harm. Dist. 0.1 %
45557 RO Ia Harmonic #10 Dist. Unix Time (d) 45661 RO Ia Total Odd Harm. Dist. 0.1 %
45558 RO Ib Harmonic #10 Dist. Unix Time (d) 45662 RO Ib Total Odd Harm. Dist. 0.1 %
45559 RO Ic Harmonic #10 Dist. Unix Time (d) 45663 RO Ic Total Odd Harm. Dist. 0.1 %
44
Register Register
45
45788 RO V aux. Harmonic #14 Dist. 0.1 % 45891 RO Vc Harmonic #2 Dist. Unix Time (d)
45789 RO Ia Harmonic #14 Dist. 0.1 % 45892 RO V aux. Harmonic #2 Dist. Unix Time (d)
45790 RO Ib Harmonic #14 Dist. 0.1 % 45893 RO Ia Harmonic #2 Dist. Unix Time (d)
45791 RO Ic Harmonic #14 Dist. 0.1 % 45894 RO Ib Harmonic #2 Dist. Unix Time (d)
45792 RO I4 Harmonic #14 Dist. 0.1 % 45895 RO Ic Harmonic #2 Dist. Unix Time (d)
45793 RO Va Harmonic #15 Dist. 0.1 % 45896 RO I4 Harmonic #2 Dist. Unix Time (d)
45794 RO Vb Harmonic #15 Dist. 0.1 % 45897 RO Va Harmonic #3 Dist. Unix Time (d)
45795 RO Vc Harmonic #15 Dist. 0.1 % 45898 RO Vb Harmonic #3 Dist. Unix Time (d)
45905 RO Va Harmonic #4 Dist. Unix Time (d)
45906 RO Vb Harmonic #4 Dist. Unix Time (d)
MAXIMUM REAL TIME HARMONIC 45907 RO Vc Harmonic #4 Dist. Unix Time (d)
TIMESTAMPS 45908 RO V aux. Harmonic #4 Dist. Unix Time (d)
45849 RO Va K-Factor Unix Time (d) 45910 RO Ib Harmonic #4 Dist. Unix Time (d)
45850 RO Vb K-Factor Unix Time (d) 45911 RO Ic Harmonic #4 Dist. Unix Time (d)
45851 RO Vc K-Factor Unix Time (d) 45912 RO I4 Harmonic #4 Dist. Unix Time (d)
45852 RO V aux. K-Factor Unix Time (d) 45913 RO Va Harmonic #5 Dist. Unix Time (d)
45853 RO Ia K-Factor Unix Time (d) 45914 RO Vb Harmonic #5 Dist. Unix Time (d)
45854 RO Ib K-Factor Unix Time (d) 45915 RO Vc Harmonic #5 Dist. Unix Time (d)
45855 RO Ic K-Factor Unix Time (d) 45916 RO V aux. Harmonic #5 Dist. Unix Time (d)
45856 RO I4 (Neutral) K-Factor Unix Time (d) 45917 RO Ia Harmonic #5 Dist. Unix Time (d)
45857 RO Va Total Odd Harm. Dist. Unix Time (d) 45918 RO Ib Harmonic #5 Dist. Unix Time (d)
45858 RO Vb Total Odd Harm. Dist. Unix Time (d) 45919 RO Ic Harmonic #5 Dist. Unix Time (d)
45859 RO Vc Total Odd Harm. Dist. Unix Time (d) 45920 RO I4 Harmonic #5 Dist. Unix Time (d)
45860 RO V aux. Total Odd Harm. Dist. Unix Time (d) 45921 RO Va Harmonic #6 Dist. Unix Time (d)
45861 RO Ia Total Odd Harm. Dist. Unix Time (d) 45922 RO Vb Harmonic #6 Dist. Unix Time (d)
45862 RO Ib Total Odd Harm. Dist. Unix Time (d) 45923 RO Vc Harmonic #6 Dist. Unix Time (d)
45863 RO Ic Total Odd Harm. Dist. Unix Time (d) 45924 RO V aux. Harmonic #6 Dist. Unix Time (d)
45864 RO I4 Total Odd Harm. Dist. Unix Time (d) 45925 RO Ia Harmonic #6 Dist. Unix Time (d)
45865 RO Va Total Even Harm. Dist Unix Time (d) 45926 RO Ib Harmonic #6 Dist. Unix Time (d)
45866 RO Vb Total Even Harm. Dist. Unix Time (d) 45927 RO Ic Harmonic #6 Dist. Unix Time (d)
45867 RO Vc Total Even Harm. Dist. Unix Time (d) 45928 RO I4 Harmonic #6 Dist. Unix Time (d)
45868 RO V aux. Total Even Harm. Dist. Unix Time (d) 45929 RO Va Harmonic #7 Dist. Unix Time (d)
45869 RO Ia Total Even Harm. Dist. Unix Time (d) 45930 RO Vb Harmonic #7 Dist. Unix Time (d)
45870 RO Ib Total Even Harm. Dist. Unix Time (d) 45931 RO Vc Harmonic #7 Dist. Unix Time (d)
45871 RO Ic Total Even Harm. Dist. Unix Time (d) 45932 RO V aux. Harmonic #7 Dist. Unix Time (d)
45872 RO I4 Total Even Harm. Dist. Unix Time (d) 45933 RO Ia Harmonic #7 Dist. Unix Time (d)
45873 RO Va Total Harmonic Dist. Unix Time (d) 45934 RO Ib Harmonic #7 Dist. Unix Time (d)
45874 RO Vb Total Harmonic Dist. Unix Time (d) 45935 RO Ic Harmonic #7 Dist. Unix Time (d)
45875 RO Vc Total Harmonic Dist. Unix Time (d) 45936 RO I4 Harmonic #7 Dist. Unix Time (d)
45876 RO V aux. Total Harmonic Dist. Unix Time (d) 45937 RO Va Harmonic #8 Dist. Unix Time (d)
45877 RO Ia Total Harmonic Dist. Unix Time (d) 45938 RO Vb Harmonic #8 Dist. Unix Time (d)
45878 RO Ib Total Harmonic Dist. Unix Time (d) 45939 RO Vc Harmonic #8 Dist. Unix Time (d)
45879 RO Ic Total Harmonic Dist. Unix Time (d) 45940 RO V aux. Harmonic #8 Dist. Unix Time (d)
45880 RO I4 Total Harmonic Dist. Unix Time (d) 45941 RO Ia Harmonic #8 Dist. Unix Time (d)
45881 RO Va fundamental Dist. Unix Time (d) 45942 RO Ib Harmonic #8 Dist. Unix Time (d)
45882 RO Vb fundamental Dist. Unix Time (d) 45943 RO Ic Harmonic #8 Dist. Unix Time (d)
45883 RO Vc fundamental Dist. Unix Time (d) 45944 RO I4 Harmonic #8 Dist. Unix Time (d)
45884 RO V aux. fundamental Dist. Unix Time (d) 45945 RO Va Harmonic #9 Dist. Unix Time (d)
45885 RO Ia fundamental Dist. Unix Time (d) 45946 RO Vb Harmonic #9 Dist. Unix Time (d)
45886 RO Ib fundamental Dist. Unix Time (d) 45947 RO Vc Harmonic #9 Dist. Unix Time (d)
45887 RO Ic fundamental Dist. Unix Time (d) 45948 RO V aux. Harmonic #9 Dist. Unix Time (d)
45888 RO I4 fundamental Dist. Unix Time (d) 45949 RO Ia Harmonic #9 Dist. Unix Time (d)
45889 RO Va Harmonic #2 Dist. Unix Time (d) 45950 RO Ib Harmonic #9 Dist. Unix Time (d)
45890 RO Vb Harmonic #2 Dist. Unix Time (d) 45951 RO Ic Harmonic #9 Dist. Unix Time (d)
46
Register Register
45953 RO Va Harmonic #10 Dist. Unix Time (d) 46056 RO I4 (Neutral) K-Factor 0.1
45954 RO Vb Harmonic #10 Dist. Unix Time (d) 46057 RO Va Total Odd Harm. Dist. 0.1 %
45955 RO Vc Harmonic #10 Dist. Unix Time (d) 46058 RO Vb Total Odd Harm. Dist. 0.1 %
45956 RO V aux. Harmonic #10 Dist. Unix Time (d) 46059 RO Vc Total Odd Harm. Dist. 0.1 %
45957 RO Ia Harmonic #10 Dist. Unix Time (d) 46060 RO V aux. Total Odd Harm. Dist. 0.1 %
45958 RO Ib Harmonic #10 Dist. Unix Time (d) 46061 RO Ia Total Odd Harm. Dist. 0.1 %
45959 RO Ic Harmonic #10 Dist. Unix Time (d) 46062 RO Ib Total Odd Harm. Dist. 0.1 %
45960 RO I4 Harmonic #10 Dist. Unix Time (d) 46063 RO Ic Total Odd Harm. Dist. 0.1 %
45961 RO Va Harmonic #11 Dist. Unix Time (d) 46064 RO I4 Total Odd Harm. Dist. 0.1 %
45962 RO Vb Harmonic #11 Dist. Unix Time (d) 46065 RO Va Total Even Harm. Dist 0.1 %
45963 RO Vc Harmonic #11 Dist. Unix Time (d) 46066 RO Vb Total Even Harm. Dist. 0.1 %
45964 RO V aux. Harmonic #11 Dist. Unix Time (d) 46067 RO Vc Total Even Harm. Dist. 0.1 %
45965 RO Ia Harmonic #11 Dist. Unix Time (d) 46068 RO V aux. Total Even Harm. Dist. 0.1 %
45966 RO Ib Harmonic #11 Dist. Unix Time (d) 46069 RO Ia Total Even Harm. Dist. 0.1 %
45967 RO Ic Harmonic #11 Dist. Unix Time (d) 46070 RO Ib Total Even Harm. Dist. 0.1 %
45968 RO I4 Harmonic #11 Dist. Unix Time (d) 46071 RO Ic Total Even Harm. Dist. 0.1 %
45969 RO Va Harmonic #12 Dist. Unix Time (d) 46072 RO I4 Total Even Harm. Dist. 0.1 %
45970 RO Vb Harmonic #12 Dist. Unix Time (d) 46073 RO Va Total Harmonic Dist. 0.1 %
45971 RO Vc Harmonic #12 Dist. Unix Time (d) 46074 RO Vb Total Harmonic Dist. 0.1 %
45972 RO V aux. Harmonic #12 Dist. Unix Time (d) 46075 RO Vc Total Harmonic Dist. 0.1 %
45973 RO Ia Harmonic #12 Dist. Unix Time (d) 46076 RO V aux. Total Harmonic Dist. 0.1 %
45974 RO Ib Harmonic #12 Dist. Unix Time (d) 46077 RO Ia Total Harmonic Dist. 0.1 %
45975 RO Ic Harmonic #12 Dist. Unix Time (d) 46078 RO Ib Total Harmonic Dist. 0.1 %
45976 RO I4 Harmonic #12 Dist. Unix Time (d) 46079 RO Ic Total Harmonic Dist. 0.1 %
45977 RO Va Harmonic #13 Dist. Unix Time (d) 46080 RO I4 Total Harmonic Dist. 0.1 %
45978 RO Vb Harmonic #13 Dist. Unix Time (d) 46081 RO Va fundamental Dist. 0.1 %
45979 RO Vc Harmonic #13 Dist. Unix Time (d) 46082 RO Vb fundamental Dist. 0.1 %
45980 RO V aux. Harmonic #13 Dist. Unix Time (d) 46083 RO Vc fundamental Dist. 0.1 %
45981 RO Ia Harmonic #13 Dist. Unix Time (d) 46084 RO V aux. fundamental Dist. 0.1 %
45982 RO Ib Harmonic #13 Dist. Unix Time (d) 46085 RO Ia fundamental Dist. 0.1 %
45983 RO Ic Harmonic #13 Dist. Unix Time (d) 46086 RO Ib fundamental Dist. 0.1 %
45984 RO I4 Harmonic #13 Dist. Unix Time (d) 46087 RO Ic fundamental Dist. 0.1 %
45985 RO Va Harmonic #14 Dist. Unix Time (d) 46088 RO I4 fundamental Dist. 0.1 %
45986 RO Vb Harmonic #14 Dist. Unix Time (d) 46089 RO Va Harmonic #2 Dist. 0.1 %
45987 RO Vc Harmonic #14 Dist. Unix Time (d) 46090 RO Vb Harmonic #2 Dist. 0.1 %
45988 RO V aux. Harmonic #14 Dist. Unix Time (d) 46091 RO Vc Harmonic #2 Dist. 0.1 %
45989 RO Ia Harmonic #14 Dist. Unix Time (d) 46092 RO V aux. Harmonic #2 Dist. 0.1 %
45990 RO Ib Harmonic #14 Dist. Unix Time (d) 46093 RO Ia Harmonic #2 Dist. 0.1 %
45991 RO Ic Harmonic #14 Dist. Unix Time (d) 46094 RO Ib Harmonic #2 Dist. 0.1 %
45992 RO I4 Harmonic #14 Dist. Unix Time (d) 46095 RO Ic Harmonic #2 Dist. 0.1 %
45993 RO Va Harmonic #15 Dist. Unix Time (d) 46096 RO I4 Harmonic #2 Dist. 0.1 %
THERMAL DEMAND HARMONIC 46107 RO Vc Harmonic #4 Dist. 0.1 %
47
MINIMUM THERMAL DEMAND HARMONIC
46143 RO Ic Harmonic #8 Dist. 0.1 % MEASUREMENTS
46145 RO Va Harmonic #9 Dist. 0.1 % 46249 RO Va K-Factor 0.1
46146 RO Vb Harmonic #9 Dist. 0.1 % 46250 RO Vb K-Factor 0.1
46147 RO Vc Harmonic #9 Dist. 0.1 % 46251 RO Vc K-Factor 0.1
46148 RO V aux. Harmonic #9 Dist. 0.1 % 46252 RO V aux. K-Factor 0.1
46149 RO Ia Harmonic #9 Dist. 0.1 % 46253 RO Ia K-Factor 0.1
46150 RO Ib Harmonic #9 Dist. 0.1 % 46254 RO Ib K-Factor 0.1
46151 RO Ic Harmonic #9 Dist. 0.1 % 46255 RO Ic K-Factor 0.1
46152 RO I4 Harmonic #9 Dist. 0.1 % 46256 RO I4 (Neutral) K-Factor 0.1
46153 RO Va Harmonic #10 Dist. 0.1 % 46257 RO Va Total Odd Harm. Dist. 0.1 %
46154 RO Vb Harmonic #10 Dist. 0.1 % 46258 RO Vb Total Odd Harm. Dist. 0.1 %
46155 RO Vc Harmonic #10 Dist. 0.1 % 46259 RO Vc Total Odd Harm. Dist. 0.1 %
46156 RO V aux. Harmonic #10 Dist. 0.1 % 46260 RO V aux. Total Odd Harm. Dist. 0.1 %
46157 RO Ia Harmonic #10 Dist. 0.1 % 46261 RO Ia Total Odd Harm. Dist. 0.1 %
46158 RO Ib Harmonic #10 Dist. 0.1 % 46262 RO Ib Total Odd Harm. Dist. 0.1 %
46159 RO Ic Harmonic #10 Dist. 0.1 % 46263 RO Ic Total Odd Harm. Dist. 0.1 %
46160 RO I4 Harmonic #10 Dist. 0.1 % 46264 RO I4 Total Odd Harm. Dist. 0.1 %
46161 RO Va Harmonic #11 Dist. 0.1 % 46265 RO Va Total Even Harm. Dist 0.1 %
46162 RO Vb Harmonic #11 Dist. 0.1 % 46266 RO Vb Total Even Harm. Dist. 0.1 %
46163 RO Vc Harmonic #11 Dist. 0.1 % 46267 RO Vc Total Even Harm. Dist. 0.1 %
46164 RO V aux. Harmonic #11 Dist. 0.1 % 46268 RO V aux. Total Even Harm. Dist. 0.1 %
46165 RO Ia Harmonic #11 Dist. 0.1 % 46269 RO Ia Total Even Harm. Dist. 0.1 %
46166 RO Ib Harmonic #11 Dist. 0.1 % 46270 RO Ib Total Even Harm. Dist. 0.1 %
46167 RO Ic Harmonic #11 Dist. 0.1 % 46271 RO Ic Total Even Harm. Dist. 0.1 %
46168 RO I4 Harmonic #11 Dist. 0.1 % 46272 RO I4 Total Even Harm. Dist. 0.1 %
46169 RO Va Harmonic #12 Dist. 0.1 % 46273 RO Va Total Harmonic Dist. 0.1 %
46170 RO Vb Harmonic #12 Dist. 0.1 % 46274 RO Vb Total Harmonic Dist. 0.1 %
46171 RO Vc Harmonic #12 Dist. 0.1 % 46275 RO Vc Total Harmonic Dist. 0.1 %
46172 RO V aux. Harmonic #12 Dist. 0.1 % 46276 RO V aux. Total Harmonic Dist. 0.1 %
46173 RO Ia Harmonic #12 Dist. 0.1 % 46277 RO Ia Total Harmonic Dist. 0.1 %
46174 RO Ib Harmonic #12 Dist. 0.1 % 46278 RO Ib Total Harmonic Dist. 0.1 %
46175 RO Ic Harmonic #12 Dist. 0.1 % 46279 RO Ic Total Harmonic Dist. 0.1 %
46176 RO I4 Harmonic #12 Dist. 0.1 % 46280 RO I4 Total Harmonic Dist. 0.1 %
46177 RO Va Harmonic #13 Dist. 0.1 % 46281 RO Va fundamental Dist. 0.1 %
46178 RO Vb Harmonic #13 Dist. 0.1 % 46282 RO Vb fundamental Dist. 0.1 %
48
Register Register
46343 RO Ic Harmonic #8 Dist. 0.1 %
49
MINIMUM THERMAL DEMAND HARMONIC 46507 RO Vc Harmonic #4 Dist. Unix Time (d)
TIMESTAMPS 46509 RO Ia Harmonic #4 Dist. Unix Time (d)
46449 RO Va K-Factor Unix Time (d) 46511 RO Ic Harmonic #4 Dist. Unix Time (d)
46450 RO Vb K-Factor Unix Time (d) 46512 RO I4 Harmonic #4 Dist. Unix Time (d)
46451 RO Vc K-Factor Unix Time (d) 46513 RO Va Harmonic #5 Dist. Unix Time (d)
46452 RO V aux. K-Factor Unix Time (d) 46514 RO Vb Harmonic #5 Dist. Unix Time (d)
46453 RO Ia K-Factor Unix Time (d) 46515 RO Vc Harmonic #5 Dist. Unix Time (d)
46454 RO Ib K-Factor Unix Time (d) 46516 RO V aux. Harmonic #5 Dist. Unix Time (d)
46455 RO Ic K-Factor Unix Time (d) 46517 RO Ia Harmonic #5 Dist. Unix Time (d)
46456 RO I4 (Neutral) K-Factor Unix Time (d) 46518 RO Ib Harmonic #5 Dist. Unix Time (d)
46457 RO Va Total Odd Harm. Dist. Unix Time (d) 46519 RO Ic Harmonic #5 Dist. Unix Time (d)
46458 RO Vb Total Odd Harm. Dist. Unix Time (d) 46520 RO I4 Harmonic #5 Dist. Unix Time (d)
46465 RO Vc Total Odd Harm. Dist. Unix Time (d) 46521 RO Va Harmonic #6 Dist. Unix Time (d)
46460 RO V aux. Total Odd Harm. Dist. Unix Time (d) 46522 RO Vb Harmonic #6 Dist. Unix Time (d)
46461 RO Ia Total Odd Harm. Dist. Unix Time (d) 46523 RO Vc Harmonic #6 Dist. Unix Time (d)
46462 RO Ib Total Odd Harm. Dist. Unix Time (d) 46524 RO V aux. Harmonic #6 Dist. Unix Time (d)
46463 RO Ic Total Odd Harm. Dist. Unix Time (d) 46525 RO Ia Harmonic #6 Dist. Unix Time (d)
46464 RO I4 Total Odd Harm. Dist. Unix Time (d) 46526 RO Ib Harmonic #6 Dist. Unix Time (d)
46465 RO Va Total Even Harm. Dist Unix Time (d) 46527 RO Ic Harmonic #6 Dist. Unix Time (d)
46466 RO Vb Total Even Harm. Dist. Unix Time (d) 46528 RO I4 Harmonic #6 Dist. Unix Time (d)
46467 RO Vc Total Even Harm. Dist. Unix Time (d) 46529 RO Va Harmonic #7 Dist. Unix Time (d)
46468 RO V aux. Total Even Harm. Dist. Unix Time (d) 46530 RO Vb Harmonic #7 Dist. Unix Time (d)
46469 RO Ia Total Even Harm. Dist. Unix Time (d) 46531 RO Vc Harmonic #7 Dist. Unix Time (d)
46470 RO Ib Total Even Harm. Dist. Unix Time (d) 46532 RO V aux. Harmonic #7 Dist. Unix Time (d)
46471 RO Ic Total Even Harm. Dist. Unix Time (d) 46533 RO Ia Harmonic #7 Dist. Unix Time (d)
46472 RO I4 Total Even Harm. Dist. Unix Time (d) 46534 RO Ib Harmonic #7 Dist. Unix Time (d)
46473 RO Va Total Harmonic Dist. Unix Time (d) 46535 RO Ic Harmonic #7 Dist. Unix Time (d)
46474 RO Vb Total Harmonic Dist. Unix Time (d) 46536 RO I4 Harmonic #7 Dist. Unix Time (d)
46475 RO Vc Total Harmonic Dist. Unix Time (d) 46537 RO Va Harmonic #8 Dist. Unix Time (d)
46476 RO V aux. Total Harmonic Dist. Unix Time (d) 46538 RO Vb Harmonic #8 Dist. Unix Time (d)
46477 RO Ia Total Harmonic Dist. Unix Time (d) 46539 RO Vc Harmonic #8 Dist. Unix Time (d)
46478 RO Ib Total Harmonic Dist. Unix Time (d) 46540 RO V aux. Harmonic #8 Dist. Unix Time (d)
46479 RO Ic Total Harmonic Dist. Unix Time (d) 46541 RO Ia Harmonic #8 Dist. Unix Time (d)
46480 RO I4 Total Harmonic Dist. Unix Time (d) 46542 RO Ib Harmonic #8 Dist. Unix Time (d)
46481 RO Va fundamental Dist. Unix Time (d) 46543 RO Ic Harmonic #8 Dist. Unix Time (d)
46482 RO Vb fundamental Dist. Unix Time (d) 46544 RO I4 Harmonic #8 Dist. Unix Time (d)
46483 RO Vc fundamental Dist. Unix Time (d) 46545 RO Va Harmonic #9 Dist. Unix Time (d)
46484 RO V aux. fundamental Dist. Unix Time (d) 46546 RO Vb Harmonic #9 Dist. Unix Time (d)
46485 RO Ia fundamental Dist. Unix Time (d) 46547 RO Vc Harmonic #9 Dist. Unix Time (d)
46486 RO Ib fundamental Dist. Unix Time (d) 46548 RO V aux. Harmonic #9 Dist. Unix Time (d)
46487 RO Ic fundamental Dist. Unix Time (d) 46549 RO Ia Harmonic #9 Dist. Unix Time (d)
46488 RO I4 fundamental Dist. Unix Time (d) 46550 RO Ib Harmonic #9 Dist. Unix Time (d)
50
Register Register
MAXIMUM THERMAL DEMAND HARMONIC 46707 RO Vc Harmonic #4 Dist. 0.1 %
\46649 RO Va K-Factor 0.1 46710 RO Ib Harmonic #4 Dist. 0.1 %
51
MAXIMUM THERMAL DEMAND HARMONIC
46760 RO I4 Harmonic #10 Dist. 0.1 % 46864 RO I4 Total Odd Harm. Dist. Unix Time (d)
46761 RO Va Harmonic #11 Dist. 0.1 % 46865 RO Va Total Even Harm. Dist Unix Time (d)
46762 RO Vb Harmonic #11 Dist. 0.1 % 46866 RO Vb Total Even Harm. Dist. Unix Time (d)
46763 RO Vc Harmonic #11 Dist. 0.1 % 46867 RO Vc Total Even Harm. Dist. Unix Time (d)
46764 RO V aux. Harmonic #11 Dist. 0.1 % 46868 RO V aux. Total Even Harm. Dist. Unix Time (d)
46765 RO Ia Harmonic #11 Dist. 0.1 % 46869 RO Ia Total Even Harm. Dist. Unix Time (d)
46766 RO Ib Harmonic #11 Dist. 0.1 % 46870 RO Ib Total Even Harm. Dist. Unix Time (d)
46767 RO Ic Harmonic #11 Dist. 0.1 % 46871 RO Ic Total Even Harm. Dist. Unix Time (d)
46768 RO I4 Harmonic #11 Dist. 0.1 % 46872 RO I4 Total Even Harm. Dist. Unix Time (d)
46769 RO Va Harmonic #12 Dist. 0.1 % 46873 RO Va Total Harmonic Dist. Unix Time (d)
46770 RO Vb Harmonic #12 Dist. 0.1 % 46874 RO Vb Total Harmonic Dist. Unix Time (d)
46771 RO Vc Harmonic #12 Dist. 0.1 % 46875 RO Vc Total Harmonic Dist. Unix Time (d)
46772 RO V aux. Harmonic #12 Dist. 0.1 % 46876 RO V aux. Total Harmonic Dist. Unix Time (d)
46773 RO Ia Harmonic #12 Dist. 0.1 % 46877 RO Ia Total Harmonic Dist. Unix Time (d)
46774 RO Ib Harmonic #12 Dist. 0.1 % 46878 RO Ib Total Harmonic Dist. Unix Time (d)
46775 RO Ic Harmonic #12 Dist. 0.1 % 46879 RO Ic Total Harmonic Dist. Unix Time (d)
46776 RO I4 Harmonic #12 Dist. 0.1 % 46880 RO I4 Total Harmonic Dist. Unix Time (d)
46777 RO Va Harmonic #13 Dist. 0.1 % 46881 RO Va fundamental Dist. Unix Time (d)
46778 RO Vb Harmonic #13 Dist. 0.1 % 46882 RO Vb fundamental Dist. Unix Time (d)
46779 RO Vc Harmonic #13 Dist. 0.1 % 46883 RO Vc fundamental Dist. Unix Time (d)
46780 RO V aux. Harmonic #13 Dist. 0.1 % 46884 RO V aux. fundamental Dist. Unix Time (d)
46781 RO Ia Harmonic #13 Dist. 0.1 % 46885 RO Ia fundamental Dist. Unix Time (d)
46782 RO Ib Harmonic #13 Dist. 0.1 % 46886 RO Ib fundamental Dist. Unix Time (d)
46783 RO Ic Harmonic #13 Dist. 0.1 % 46887 RO Ic fundamental Dist. Unix Time (d)
46784 RO I4 Harmonic #13 Dist. 0.1 % 46888 RO I4 fundamental Dist. Unix Time (d)
46787 RO Vc Harmonic #14 Dist. 0.1 % 46891 RO Vc Harmonic #2 Dist. Unix Time (d)
46788 RO V aux. Harmonic #14 Dist. 0.1 % 46892 RO V aux. Harmonic #2 Dist. Unix Time (d)
46789 RO Ia Harmonic #14 Dist. 0.1 % 46893 RO Ia Harmonic #2 Dist. Unix Time (d)
46790 RO Ib Harmonic #14 Dist. 0.1 % 46894 RO Ib Harmonic #2 Dist. Unix Time (d)
46791 RO Ic Harmonic #14 Dist. 0.1 % 46895 RO Ic Harmonic #2 Dist. Unix Time (d)
46792 RO I4 Harmonic #14 Dist. 0.1 % 46896 RO I4 Harmonic #2 Dist. Unix Time (d)
52
Register Register
SLIDING DEMAND HARMONIC
53
54
Register Register
47193 RO Va Harmonic #15 Dist. 0.1 % 47296 RO I4 Harmonic #2 Dist. 0.1 %
MINIMUM SLIDING DEMAND HARMONIC 47307 RO Vc Harmonic #4 Dist. 0.1 %
47272 RO I4 Total Even Harm. Dist. 0.1 % 47333 RO Ia Harmonic #7 Dist. 0.1 %
47273 RO Va Total Harmonic Dist. 0.1 % 47334 RO Ib Harmonic #7 Dist. 0.1 %
47274 RO Vb Total Harmonic Dist. 0.1 % 47335 RO Ic Harmonic #7 Dist. 0.1 %
47275 RO Vc Total Harmonic Dist. 0.1 % 47336 RO I4 Harmonic #7 Dist. 0.1 %
47276 RO V aux. Total Harmonic Dist. 0.1 % 47337 RO Va Harmonic #8 Dist. 0.1 %
47277 RO Ia Total Harmonic Dist. 0.1 % 47338 RO Vb Harmonic #8 Dist. 0.1 %
47278 RO Ib Total Harmonic Dist. 0.1 % 47339 RO Vc Harmonic #8 Dist. 0.1 %
47279 RO Ic Total Harmonic Dist. 0.1 % 47340 RO V aux. Harmonic #8 Dist. 0.1 %
47280 RO I4 Total Harmonic Dist. 0.1 % 47341 RO Ia Harmonic #8 Dist. 0.1 %
47281 RO Va fundamental Dist. 0.1 % 47342 RO Ib Harmonic #8 Dist. 0.1 %
47282 RO Vb fundamental Dist. 0.1 % 47343 RO Ic Harmonic #8 Dist. 0.1 %
47283 RO Vc fundamental Dist. 0.1 % 47344 RO I4 Harmonic #8 Dist. 0.1 %
47284 RO V aux. fundamental Dist. 0.1 % 47345 RO Va Harmonic #9 Dist. 0.1 %
47285 RO Ia fundamental Dist. 0.1 % 47346 RO Vb Harmonic #9 Dist. 0.1 %
47286 RO Ib fundamental Dist. 0.1 % 47347 RO Vc Harmonic #9 Dist. 0.1 %
47287 RO Ic fundamental Dist. 0.1 % 47348 RO V aux. Harmonic #9 Dist. 0.1 %
47288 RO I4 fundamental Dist. 0.1 % 47349 RO Ia Harmonic #9 Dist. 0.1 %
47289 RO Va Harmonic #2 Dist. 0.1 % 47350 RO Ib Harmonic #9 Dist. 0.1 %
47290 RO Vb Harmonic #2 Dist. 0.1 % 47351 RO Ic Harmonic #9 Dist. 0.1 %
55
47353 RO Va Harmonic #10 Dist. 0.1 % 47456 RO I4 (Neutral) K-Factor Unix Time (d)
47354 RO Vb Harmonic #10 Dist. 0.1 % 47457 RO Va Total Odd Harm. Dist. Unix Time (d)
47355 RO Vc Harmonic #10 Dist. 0.1 % 47458 RO Vb Total Odd Harm. Dist. Unix Time (d)
47356 RO V aux. Harmonic #10 Dist. 0.1 % 47465 RO Vc Total Odd Harm. Dist. Unix Time (d)
47357 RO Ia Harmonic #10 Dist. 0.1 % 47460 RO V aux. Total Odd Harm. Dist. Unix Time (d)
47358 RO Ib Harmonic #10 Dist. 0.1 % 47461 RO Ia Total Odd Harm. Dist. Unix Time (d)
47359 RO Ic Harmonic #10 Dist. 0.1 % 47466 RO Ib Total Odd Harm. Dist. Unix Time (d)
47360 RO I4 Harmonic #10 Dist. 0.1 % 47467 RO Ic Total Odd Harm. Dist. Unix Time (d)
47361 RO Va Harmonic #11 Dist. 0.1 % 47464 RO I4 Total Odd Harm. Dist. Unix Time (d)
47362 RO Vb Harmonic #11 Dist. 0.1 % 47465 RO Va Total Even Harm. Dist Unix Time (d)
47363 RO Vc Harmonic #11 Dist. 0.1 % 47466 RO Vb Total Even Harm. Dist. Unix Time (d)
47364 RO V aux. Harmonic #11 Dist. 0.1 % 47467 RO Vc Total Even Harm. Dist. Unix Time (d)
47365 RO Ia Harmonic #11 Dist. 0.1 % 47468 RO V aux. Total Even Harm. Dist. Unix Time (d)
47366 RO Ib Harmonic #11 Dist. 0.1 % 47475 RO Ia Total Even Harm. Dist. Unix Time (d)
47367 RO Ic Harmonic #11 Dist. 0.1 % 47470 RO Ib Total Even Harm. Dist. Unix Time (d)
47368 RO I4 Harmonic #11 Dist. 0.1 % 47471 RO Ic Total Even Harm. Dist. Unix Time (d)
47369 RO Va Harmonic #12 Dist. 0.1 % 47472 RO I4 Total Even Harm. Dist. Unix Time (d)
47370 RO Vb Harmonic #12 Dist. 0.1 % 47473 RO Va Total Harmonic Dist. Unix Time (d)
47371 RO Vc Harmonic #12 Dist. 0.1 % 47474 RO Vb Total Harmonic Dist. Unix Time (d)
47372 RO V aux. Harmonic #12 Dist. 0.1 % 47475 RO Vc Total Harmonic Dist. Unix Time (d)
47373 RO Ia Harmonic #12 Dist. 0.1 % 47476 RO V aux. Total Harmonic Dist. Unix Time (d)
47374 RO Ib Harmonic #12 Dist. 0.1 % 47477 RO Ia Total Harmonic Dist. Unix Time (d)
47375 RO Ic Harmonic #12 Dist. 0.1 % 47478 RO Ib Total Harmonic Dist. Unix Time (d)
47376 RO I4 Harmonic #12 Dist. 0.1 % 47479 RO Ic Total Harmonic Dist. Unix Time (d)
47377 RO Va Harmonic #13 Dist. 0.1 % 47480 RO I4 Total Harmonic Dist. Unix Time (d)
47378 RO Vb Harmonic #13 Dist. 0.1 % 47481 RO Va fundamental Dist. Unix Time (d)
47379 RO Vc Harmonic #13 Dist. 0.1 % 47482 RO Vb fundamental Dist. Unix Time (d)
47380 RO V aux. Harmonic #13 Dist. 0.1 % 47483 RO Vc fundamental Dist. Unix Time (d)
47381 RO Ia Harmonic #13 Dist. 0.1 % 47484 RO V aux. fundamental Dist. Unix Time (d)
47382 RO Ib Harmonic #13 Dist. 0.1 % 47485 RO Ia fundamental Dist. Unix Time (d)
47383 RO Ic Harmonic #13 Dist. 0.1 % 47486 RO Ib fundamental Dist. Unix Time (d)
47384 RO I4 Harmonic #13 Dist. 0.1 % 47487 RO Ic fundamental Dist. Unix Time (d)
47385 RO Va Harmonic #14 Dist. 0.1 % 47488 RO I4 fundamental Dist. Unix Time (d)
MINIMUM SLIDING DEMAND HARMONIC 47507 RO Vc Harmonic #4 Dist. Unix Time (d)
56
Register Register
MAXIMUM SLIDING DEMAND HARMONIC
47560 RO I4 Harmonic #10 Dist. Unix Time (d) 47664 RO I4 Total Odd Harm. Dist. 0.1 %
47561 RO Va Harmonic #11 Dist. Unix Time (d) 47665 RO Va Total Even Harm. Dist 0.1 %
47562 RO Vb Harmonic #11 Dist. Unix Time (d) 47666 RO Vb Total Even Harm. Dist. 0.1 %
47563 RO Vc Harmonic #11 Dist. Unix Time (d) 47667 RO Vc Total Even Harm. Dist. 0.1 %
47564 RO V aux. Harmonic #11 Dist. Unix Time (d) 47668 RO V aux. Total Even Harm. Dist. 0.1 %
47565 RO Ia Harmonic #11 Dist. Unix Time (d) 47669 RO Ia Total Even Harm. Dist. 0.1 %
47566 RO Ib Harmonic #11 Dist. Unix Time (d) 47670 RO Ib Total Even Harm. Dist. 0.1 %
47567 RO Ic Harmonic #11 Dist. Unix Time (d) 47671 RO Ic Total Even Harm. Dist. 0.1 %
47568 RO I4 Harmonic #11 Dist. Unix Time (d) 47672 RO I4 Total Even Harm. Dist. 0.1 %
47569 RO Va Harmonic #12 Dist. Unix Time (d) 47673 RO Va Total Harmonic Dist. 0.1 %
47570 RO Vb Harmonic #12 Dist. Unix Time (d) 47674 RO Vb Total Harmonic Dist. 0.1 %
47571 RO Vc Harmonic #12 Dist. Unix Time (d) 47675 RO Vc Total Harmonic Dist. 0.1 %
47572 RO V aux. Harmonic #12 Dist. Unix Time (d) 47676 RO V aux. Total Harmonic Dist. 0.1 %
47573 RO Ia Harmonic #12 Dist. Unix Time (d) 47677 RO Ia Total Harmonic Dist. 0.1 %
47574 RO Ib Harmonic #12 Dist. Unix Time (d) 47678 RO Ib Total Harmonic Dist. 0.1 %
47575 RO Ic Harmonic #12 Dist. Unix Time (d) 47679 RO Ic Total Harmonic Dist. 0.1 %
47576 RO I4 Harmonic #12 Dist. Unix Time (d) 47680 RO I4 Total Harmonic Dist. 0.1 %
47577 RO Va Harmonic #13 Dist. Unix Time (d) 47681 RO Va fundamental Dist. 0.1 %
47578 RO Vb Harmonic #13 Dist. Unix Time (d) 47682 RO Vb fundamental Dist. 0.1 %
57

47743 RO Ic Harmonic #8 Dist. 0.1 %
58
Register Register
MAXIMUM SLIDING DEMAND HARMONIC 47907 RO Vc Harmonic #4 Dist. Unix Time (d)
TIMESTAMPS 47909 RO Ia Harmonic #4 Dist. Unix Time (d)
47849 RO Va K-Factor Unix Time (d) 47911 RO Ic Harmonic #4 Dist. Unix Time (d)
47850 RO Vb K-Factor Unix Time (d) 47912 RO I4 Harmonic #4 Dist. Unix Time (d)
47851 RO Vc K-Factor Unix Time (d) 47913 RO Va Harmonic #5 Dist. Unix Time (d)
47852 RO V aux. K-Factor Unix Time (d) 47914 RO Vb Harmonic #5 Dist. Unix Time (d)
47853 RO Ia K-Factor Unix Time (d) 47915 RO Vc Harmonic #5 Dist. Unix Time (d)
47854 RO Ib K-Factor Unix Time (d) 47916 RO V aux. Harmonic #5 Dist. Unix Time (d)
47855 RO Ic K-Factor Unix Time (d) 47917 RO Ia Harmonic #5 Dist. Unix Time (d)
47856 RO I4 (Neutral) K-Factor Unix Time (d) 47918 RO Ib Harmonic #5 Dist. Unix Time (d)
47857 RO Va Total Odd Harm. Dist. Unix Time (d) 47919 RO Ic Harmonic #5 Dist. Unix Time (d)
47858 RO Vb Total Odd Harm. Dist. Unix Time (d) 47920 RO I4 Harmonic #5 Dist. Unix Time (d)
47865 RO Vc Total Odd Harm. Dist. Unix Time (d) 47921 RO Va Harmonic #6 Dist. Unix Time (d)
47860 RO V aux. Total Odd Harm. Dist. Unix Time (d) 47922 RO Vb Harmonic #6 Dist. Unix Time (d)
47861 RO Ia Total Odd Harm. Dist. Unix Time (d) 47923 RO Vc Harmonic #6 Dist. Unix Time (d)
47866 RO Ib Total Odd Harm. Dist. Unix Time (d) 47924 RO V aux. Harmonic #6 Dist. Unix Time (d)
47867 RO Ic Total Odd Harm. Dist. Unix Time (d) 47925 RO Ia Harmonic #6 Dist. Unix Time (d)
59
PREDICTED DEMAND HARMONIC 48107 RO Vc Harmonic #4 Dist. 0.1 %
60
Register Register
MINIMUM PREDICTED DEMAND HARMONIC
48143 RO Ic Harmonic #8 Dist. 0.1 % MEASUREMENTS
48145 RO Va Harmonic #9 Dist. 0.1 % 48249 RO Va K-Factor 0.1
48146 RO Vb Harmonic #9 Dist. 0.1 % 48250 RO Vb K-Factor 0.1
48147 RO Vc Harmonic #9 Dist. 0.1 % 48251 RO Vc K-Factor 0.1
48148 RO V aux. Harmonic #9 Dist. 0.1 % 48252 RO V aux. K-Factor 0.1
48149 RO Ia Harmonic #9 Dist. 0.1 % 48253 RO Ia K-Factor 0.1
48150 RO Ib Harmonic #9 Dist. 0.1 % 48254 RO Ib K-Factor 0.1
48151 RO Ic Harmonic #9 Dist. 0.1 % 48255 RO Ic K-Factor 0.1
48152 RO I4 Harmonic #9 Dist. 0.1 % 48256 RO I4 (Neutral) K-Factor 0.1
48153 RO Va Harmonic #10 Dist. 0.1 % 48257 RO Va Total Odd Harm. Dist. 0.1 %
48154 RO Vb Harmonic #10 Dist. 0.1 % 48258 RO Vb Total Odd Harm. Dist. 0.1 %
48155 RO Vc Harmonic #10 Dist. 0.1 % 48259 RO Vc Total Odd Harm. Dist. 0.1 %
48156 RO V aux. Harmonic #10 Dist. 0.1 % 48260 RO V aux. Total Odd Harm. Dist. 0.1 %
48157 RO Ia Harmonic #10 Dist. 0.1 % 48261 RO Ia Total Odd Harm. Dist. 0.1 %
48158 RO Ib Harmonic #10 Dist. 0.1 % 48262 RO Ib Total Odd Harm. Dist. 0.1 %
48159 RO Ic Harmonic #10 Dist. 0.1 % 48263 RO Ic Total Odd Harm. Dist. 0.1 %
48160 RO I4 Harmonic #10 Dist. 0.1 % 48264 RO I4 Total Odd Harm. Dist. 0.1 %
48161 RO Va Harmonic #11 Dist. 0.1 % 48265 RO Va Total Even Harm. Dist 0.1 %
48162 RO Vb Harmonic #11 Dist. 0.1 % 48266 RO Vb Total Even Harm. Dist. 0.1 %
48163 RO Vc Harmonic #11 Dist. 0.1 % 48267 RO Vc Total Even Harm. Dist. 0.1 %
48164 RO V aux. Harmonic #11 Dist. 0.1 % 48268 RO V aux. Total Even Harm. Dist. 0.1 %
48165 RO Ia Harmonic #11 Dist. 0.1 % 48269 RO Ia Total Even Harm. Dist. 0.1 %
48166 RO Ib Harmonic #11 Dist. 0.1 % 48270 RO Ib Total Even Harm. Dist. 0.1 %
48167 RO Ic Harmonic #11 Dist. 0.1 % 48271 RO Ic Total Even Harm. Dist. 0.1 %
48168 RO I4 Harmonic #11 Dist. 0.1 % 48272 RO I4 Total Even Harm. Dist. 0.1 %
48169 RO Va Harmonic #12 Dist. 0.1 % 48273 RO Va Total Harmonic Dist. 0.1 %
48170 RO Vb Harmonic #12 Dist. 0.1 % 48274 RO Vb Total Harmonic Dist. 0.1 %
48171 RO Vc Harmonic #12 Dist. 0.1 % 48275 RO Vc Total Harmonic Dist. 0.1 %
48172 RO V aux. Harmonic #12 Dist. 0.1 % 48276 RO V aux. Total Harmonic Dist. 0.1 %
48173 RO Ia Harmonic #12 Dist. 0.1 % 48277 RO Ia Total Harmonic Dist. 0.1 %
48174 RO Ib Harmonic #12 Dist. 0.1 % 48278 RO Ib Total Harmonic Dist. 0.1 %
48175 RO Ic Harmonic #12 Dist. 0.1 % 48279 RO Ic Total Harmonic Dist. 0.1 %
48176 RO I4 Harmonic #12 Dist. 0.1 % 48280 RO I4 Total Harmonic Dist. 0.1 %
48177 RO Va Harmonic #13 Dist. 0.1 % 48281 RO Va fundamental Dist. 0.1 %
48178 RO Vb Harmonic #13 Dist. 0.1 % 48282 RO Vb fundamental Dist. 0.1 %
48179 RO Vc Harmonic #13 Dist. 0.1 % 48283 RO Vc fundamental Dist. 0.1 %
48180 RO V aux. Harmonic #13 Dist. 0.1 % 48284 RO V aux. fundamental Dist. 0.1 %
48181 RO Ia Harmonic #13 Dist. 0.1 % 48285 RO Ia fundamental Dist. 0.1 %
48182 RO Ib Harmonic #13 Dist. 0.1 % 48286 RO Ib fundamental Dist. 0.1 %
48183 RO Ic Harmonic #13 Dist. 0.1 % 48287 RO Ic fundamental Dist. 0.1 %
48184 RO I4 Harmonic #13 Dist. 0.1 % 48288 RO I4 fundamental Dist. 0.1 %
48185 RO Va Harmonic #14 Dist. 0.1 % 48289 RO Va Harmonic #2 Dist. 0.1 %
48186 RO Vb Harmonic #14 Dist. 0.1 % 48290 RO Vb Harmonic #2 Dist. 0.1 %
48187 RO Vc Harmonic #14 Dist. 0.1 % 48291 RO Vc Harmonic #2 Dist. 0.1 %
48188 RO V aux. Harmonic #14 Dist. 0.1 % 48292 RO V aux. Harmonic #2 Dist. 0.1 %
48189 RO Ia Harmonic #14 Dist. 0.1 % 48293 RO Ia Harmonic #2 Dist. 0.1 %
48190 RO Ib Harmonic #14 Dist. 0.1 % 48294 RO Ib Harmonic #2 Dist. 0.1 %
48191 RO Ic Harmonic #14 Dist. 0.1 % 48295 RO Ic Harmonic #2 Dist. 0.1 %
48192 RO I4 Harmonic #14 Dist. 0.1 % 48296 RO I4 Harmonic #2 Dist. 0.1 %
48193 RO Va Harmonic #15 Dist. 0.1 % 48297 RO Va Harmonic #3 Dist. 0.1 %
48194 RO Vb Harmonic #15 Dist. 0.1 % 48298 RO Vb Harmonic #3 Dist. 0.1 %
61

MINIMUM PREDICTED DEMAND HARMONIC
62
Register Register
63
MAXIMUM PREDICTED DEMAND HARMONIC 48707 RO Vc Harmonic #4 Dist. 0.1 %
48672 RO I4 Total Even Harm. Dist. 0.1 % 48733 RO Ia Harmonic #7 Dist. 0.1 %
48673 RO Va Total Harmonic Dist. 0.1 % 48734 RO Ib Harmonic #7 Dist. 0.1 %
48674 RO Vb Total Harmonic Dist. 0.1 % 48735 RO Ic Harmonic #7 Dist. 0.1 %
48675 RO Vc Total Harmonic Dist. 0.1 % 48736 RO I4 Harmonic #7 Dist. 0.1 %
48676 RO V aux. Total Harmonic Dist. 0.1 % 48737 RO Va Harmonic #8 Dist. 0.1 %
48677 RO Ia Total Harmonic Dist. 0.1 % 48738 RO Vb Harmonic #8 Dist. 0.1 %
48678 RO Ib Total Harmonic Dist. 0.1 % 48739 RO Vc Harmonic #8 Dist. 0.1 %
48679 RO Ic Total Harmonic Dist. 0.1 % 48740 RO V aux. Harmonic #8 Dist. 0.1 %
48680 RO I4 Total Harmonic Dist. 0.1 % 48741 RO Ia Harmonic #8 Dist. 0.1 %
48681 RO Va fundamental Dist. 0.1 % 48742 RO Ib Harmonic #8 Dist. 0.1 %
48682 RO Vb fundamental Dist. 0.1 % 48743 RO Ic Harmonic #8 Dist. 0.1 %
48683 RO Vc fundamental Dist. 0.1 % 48744 RO I4 Harmonic #8 Dist. 0.1 %
48684 RO V aux. fundamental Dist. 0.1 % 48745 RO Va Harmonic #9 Dist. 0.1 %
48685 RO Ia fundamental Dist. 0.1 % 48746 RO Vb Harmonic #9 Dist. 0.1 %
48686 RO Ib fundamental Dist. 0.1 % 48747 RO Vc Harmonic #9 Dist. 0.1 %
48687 RO Ic fundamental Dist. 0.1 % 48748 RO V aux. Harmonic #9 Dist. 0.1 %
48688 RO I4 fundamental Dist. 0.1 % 48749 RO Ia Harmonic #9 Dist. 0.1 %
48689 RO Va Harmonic #2 Dist. 0.1 % 48750 RO Ib Harmonic #9 Dist. 0.1 %
48690 RO Vb Harmonic #2 Dist. 0.1 % 48751 RO Ic Harmonic #9 Dist. 0.1 %
64
Register Register
48753 RO Va Harmonic #10 Dist. 0.1 % 48856 RO I4 (Neutral) K-Factor Unix Time (d)
48754 RO Vb Harmonic #10 Dist. 0.1 % 48857 RO Va Total Odd Harm. Dist. Unix Time (d)
48755 RO Vc Harmonic #10 Dist. 0.1 % 48858 RO Vb Total Odd Harm. Dist. Unix Time (d)
48756 RO V aux. Harmonic #10 Dist. 0.1 % 48865 RO Vc Total Odd Harm. Dist. Unix Time (d)
48757 RO Ia Harmonic #10 Dist. 0.1 % 48860 RO V aux. Total Odd Harm. Dist. Unix Time (d)
48758 RO Ib Harmonic #10 Dist. 0.1 % 48861 RO Ia Total Odd Harm. Dist. Unix Time (d)
48759 RO Ic Harmonic #10 Dist. 0.1 % 48866 RO Ib Total Odd Harm. Dist. Unix Time (d)
48760 RO I4 Harmonic #10 Dist. 0.1 % 48867 RO Ic Total Odd Harm. Dist. Unix Time (d)
48761 RO Va Harmonic #11 Dist. 0.1 % 48864 RO I4 Total Odd Harm. Dist. Unix Time (d)
48762 RO Vb Harmonic #11 Dist. 0.1 % 48865 RO Va Total Even Harm. Dist Unix Time (d)
48763 RO Vc Harmonic #11 Dist. 0.1 % 48866 RO Vb Total Even Harm. Dist. Unix Time (d)
48764 RO V aux. Harmonic #11 Dist. 0.1 % 48867 RO Vc Total Even Harm. Dist. Unix Time (d)
48765 RO Ia Harmonic #11 Dist. 0.1 % 48868 RO V aux. Total Even Harm. Dist. Unix Time (d)
48766 RO Ib Harmonic #11 Dist. 0.1 % 48875 RO Ia Total Even Harm. Dist. Unix Time (d)
48767 RO Ic Harmonic #11 Dist. 0.1 % 48870 RO Ib Total Even Harm. Dist. Unix Time (d)
48768 RO I4 Harmonic #11 Dist. 0.1 % 48871 RO Ic Total Even Harm. Dist. Unix Time (d)
48769 RO Va Harmonic #12 Dist. 0.1 % 48876 RO I4 Total Even Harm. Dist. Unix Time (d)
48770 RO Vb Harmonic #12 Dist. 0.1 % 48877 RO Va Total Harmonic Dist. Unix Time (d)
48771 RO Vc Harmonic #12 Dist. 0.1 % 48874 RO Vb Total Harmonic Dist. Unix Time (d)
48772 RO V aux. Harmonic #12 Dist. 0.1 % 48875 RO Vc Total Harmonic Dist. Unix Time (d)
48773 RO Ia Harmonic #12 Dist. 0.1 % 48876 RO V aux. Total Harmonic Dist. Unix Time (d)
48774 RO Ib Harmonic #12 Dist. 0.1 % 48877 RO Ia Total Harmonic Dist. Unix Time (d)
48775 RO Ic Harmonic #12 Dist. 0.1 % 48878 RO Ib Total Harmonic Dist. Unix Time (d)
48776 RO I4 Harmonic #12 Dist. 0.1 % 48885 RO Ic Total Harmonic Dist. Unix Time (d)
48777 RO Va Harmonic #13 Dist. 0.1 % 48880 RO I4 Total Harmonic Dist. Unix Time (d)
48778 RO Vb Harmonic #13 Dist. 0.1 % 48881 RO Va fundamental Dist. Unix Time (d)
48779 RO Vc Harmonic #13 Dist. 0.1 % 48886 RO Vb fundamental Dist. Unix Time (d)
48780 RO V aux. Harmonic #13 Dist. 0.1 % 48887 RO Vc fundamental Dist. Unix Time (d)
48781 RO Ia Harmonic #13 Dist. 0.1 % 48884 RO V aux. fundamental Dist. Unix Time (d)
48782 RO Ib Harmonic #13 Dist. 0.1 % 48885 RO Ia fundamental Dist. Unix Time (d)
48783 RO Ic Harmonic #13 Dist. 0.1 % 48886 RO Ib fundamental Dist. Unix Time (d)
48784 RO I4 Harmonic #13 Dist. 0.1 % 48887 RO Ic fundamental Dist. Unix Time (d)
48785 RO Va Harmonic #14 Dist. 0.1 % 48888 RO I4 fundamental Dist. Unix Time (d)
MAXIMUM PREDICTED DEMAND HARMONIC 48907 RO Vc Harmonic #4 Dist. Unix Time (d)
65
48943 RO Ic Harmonic #8 Dist. Unix Time (d)
66
Register Register
REGISTER MAP NOTES
Register Types: RO = Read Only

RW = Read/Write
WO = Write Only
(a) Register not valid in DELTA mode.
(b) Register not valid in SINGLE PHASE mode.
(c) Register size dependent: 16 BIT = MWH/MVARH/MVAH

32 BIT = GWH/GVARH/GVAH
(d) In 32-bit mode, register is expressed in LONG WORD format.

Any registers not annotated with “(d)” are expressed in MOD-10000 format when in 32-bit mode.
(e) Waveform Recorder registers are available only in 16-bit mode.
67
POLARITY REGISTERS
Real Thermal Minimum Sliding Maximum Minimum Maximum Minimum Maximum Predicted Minimum Maximum
Time demand real time window real time thermal thermal sliding sliding demand predicted predicted
demand demand demand window window demand demand
demand demand
BIT 40050 40150 40350 40550 40650 40850 41050 41250 41450 41650 41750 41950
0 40031 40131 40331 40531 40631 40831 41031 41231 41431 41631 41731 41931
1 40032 40132 40332 40532 40632 40832 41032 41232 41432 41632 41732 41932 D
2 40033 40133 40333 40533 40633 40833 41033 41233 41433 41633 41733 41933 A
3 40034 40134 40334 40534 40634 40834 41034 41234 41434 41634 41734 41934 T
4 40035 40135 40335 40535 40635 40835 41035 41235 41435 41635 41735 41935 A
5 40036 40136 40336 40536 40636 40836 41036 41236 41436 41636 41736 41936
6 40037 40137 40337 40537 40637 40837 41037 41237 41437 41637 41737 41937 R
7 40038 40138 40338 40538 40638 40838 41038 41238 41438 41638 41738 41938 E
8 40042 40142 40342 40542 40642 40842 41042 41242 41442 41642 41742 41942 G
9 40039 40139 40339 40539 40639 40839 41039 41239 41439 41639 41739 41939 I
10 40040 40140 40340 40540 40640 40840 41040 41240 41440 41640 41740 41940 S
11 40041 40141 40341 40541 40641 40841 41041 41241 41441 41641 41741 41941 T
12 40020 40120 40320 40520 40620 40820 41020 41220 41420 41620 41720 41920 E
13 RESERVED FOR FUTURE USE R
14 40057/8 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A S
15 40067/8 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
68
|70020-0016-00P~
Revision date: May 1998

Modbus 3720

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Modbus 3720

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3720 ACM

Advanced Digital Power

3720 ACM / Modicon Modbus

Revision Date: May 1998

The following versions of this document have been released:

- Revision 1.0 March 5, 1996: Initial Release

- Revision 1.1 May 5, 1997: Minor errors corrected

- Revision 1.2 August 14, 1997: Added waveform recorder, MPCC/MPE

- Revision 1.3 May, 1998: Minor corrections

5.5.3 Trigger Waveform Capture ................................................................................................................................15

APPENDIX B: 3720 ACM REGISTER MAP.......................................................................................................................23

LIST OF TABLES AND FIGURES

TABLE 2-1: MODBUS FUNCTION SUPPORTED BY THE 3720 ACM.................................................................................................2

FIGURE 3-1: READ HOLDING REGISTERS (16-BIT MODE) .............................................................................................................4

5) Allowing the interrogation of the event log.

The Modbus protocol uses ASCII and RTU modes of

2.3 Description of the Modbus packet Example 2.1:

A 32-bit register contains the value 0A1B2C3D Hex.

2.3.4 Error Check Field (Checksum)

FUNCTION MEANING ACTION

2.4 Exception Responses 2.5 Broadcast Packets

CODE NAME MEANING

READ HOLDING REGISTERS (16-BIT MODE)

READ REGISTERS REQUEST PACKET READ REGISTERS RESPONSE PACKET

Unit ID/Slave Address (1 byte) Unit ID/Slave Address (1 byte)

Slave address: 100 = 64 (Hex) Start register: 10 = 000A (Hex)

Slave Function Start Register (40011) # of Registers (3) CRC Checksum

Slave Function Byte Count Register 1 Register 2

The Master station retrieves the data from the response:

Figure 3-1: Read Holding Registers (16-Bit Mode)

PRESET MULTIPLE REGISTERS (16-BIT MODE)

PRESET REGISTERS REQUEST PACKET PRESET REGISTERS RESPONSE PACKET

Unit ID/Slave Address (1 byte) Unit ID/Slave Address (1 byte)

Slave address: 200 = C8 (Hex) Start register: 3001 = 0BB9 (Hex)

Slave Function Start Register (43002) # of Registers (2) Byte Count

Slave Function Start Register (43002) # of Registers (2) CRC Checksum

Figure 3-2: Preset Multiple Registers (16-Bit Mode)

3.3 Extended (32-bit) Mode Packet High-Order Register = value

Value 12345678 is passed in special 32-bit format:

12345678 = 00BC614E Hex

READ HOLDING REGISTERS (32-BIT MODE)

READ REGISTERS REQUEST PACKET READ REGISTERS RESPONSE PACKET

Unit ID/Slave Address (1 byte) Unit ID/Slave Address (1 byte)

Example 3.5: (32-bit version of example 3.1)

Slave address: 100 = 64 (Hex)

Slave Function Start Register (40011) # of Registers (2 x 3 = 6) CRC Checksum

Slave Function Byte Count Register 1high Register 1low

The Master station retrieves the data from the response:

Figure 3-3: Read Holding Registers (32-Bit Mode)

PRESET MULTIPLE REGISTERS (32-BIT MODE)

PRESET REGISTERS REQUEST PACKET PRESET REGISTERS RESPONSE PACKET

Unit ID/Slave Address (1 byte) Unit ID/Slave Address (1 byte)

Example 3.6: (32-bit version of example 3.2)

Slave address: 200 = C8 (Hex) Start register: 3001 = 0BB9 (Hex)

Figure 3-4: Preset Multiple Registers (32-Bit Mode)

3.5 Energy Hour Value Formats 3.6 Password Protection

kWh Import is reading 123456.

A request is made to read 6 registers, starting at 40026.

i Skip Invalids Return Invalids

This feature of the 3720 ACM Modbus protocol is

3.8 16-/32-bit Mode Mismatch

If the 3720 ACM is configured to 16-bit mode, and a 32-

If the 3720 ACM is configured to 32-bit mode, and a 16-