YOGESH VERMA E-mail: yogeshverma021@gmail.

com
Phone no. : +917697678531
OBJECTIVE

To associate with an organization which provides me the opportunity to improve my skills and knowledge, to grow along
with the organizational objectives.

ACADEMIC RECORD
Year Degree Institution(Board) CPI/%
2016-2018 M.Tech (Signal Processing and communication) Indian Institute of Technology, Kanpur 8.25
2012-2016 B.Tech (Electronics & Communication Engg.) National Institute of Technology, Bhopal 7.97
2012 XII School for Excellence, Dewas (MP Board) 89
2010 X School for Excellence, Dewas (MP Board) 87

OCCUPATION June2018-Present
Digital Back-end Design Engineer at INTEL INDIA.
• Working on a high speed and power efficient memory execution unit of BIG CORE.
• Responsible for synthesizing the physical layout from RTL.
• Experience of working on 14 and 10 nm process.
• Working on Dc and icc2 tool of Synopsys.

MTECH THESIS Dr. A. Jagannatham

Title: Optimal power allocation and Robust precoder design for MAC based wireless sensor networks.
• Linear precoder designs for the estimation of an unknown vector parameter in a coherent multiple access channel
(MAC)-based multiple-input multiple-output (MIMO) wireless sensor network (WSN) .Considering both perfect as well as
imperfect CSI at the fusion center. The proposed designs minimize the mean squared error (MSE)
• The proposed schemes are computationally faster and more accurate compared to the existing iterative schemes.

B.TECH. PROJECTS Dr. J.S. Yadav

Title: 3 dimensional Food printer
• A simple device to decorate cakes. 3Dprinting of food allows enormous freedom to design most complex design.

TRAINING Sci. Vivek Dadu

Title: NvRam Interfacing with ADSP Microprocessor
• Interfacing ADSP microprocessor running at 5 volts with 128 Kbyte Non-Volatile RAM running at 3.3 volts using Buffers.
This module might be used in the indigenous design of AHRS UNIT
Organization: HINDUSTAN AERONAUTICS LIMITED (Avionics division Korwa U.P.)

RELEVENT COURSEWORK
• Analog Electronics
• Digital Electronics
• Electronic Devices and Circuits
• VLSI Design
• Convex optimization
• Statistical signal processing

TECHNICAL PROFICIENCY
Programming Languages : C, C++, perl, python, basics of HTML and LaTeX.
Concepts : Convex optimization, Data Structure, STA.
Tools : DC, ICC2, Matlab, LabVIEW, CADSTAR, Xilinx.
SCHOLASTIC ACHIEVEMENTS
• Achieved AIR 691 rank in GATE 2016.
• Achieved AIR 82nd in ASIAN MATHEMATICS OLYMPIAD in 2012 with 99.51 Percentile.
• Awarded scholarship under MEDHAVI KHATRA PROTSAHAN YOJANA by honorable CM Mr. Shivraj Singh Chouhan.

EXTRA-CURRICULAR ACTIVITIES
• Member of EE Web-Team IITK since July 2016.
• Participated in 3 days workshop on “Ultra Low Power RISC Microcontrollers & its Application” held at NIT Bhopal.
• Participated in 3 days workshop on “Autonomous Robotics” held at NIT Bhopal.
• Participated in Manthan National competition and shortlisted for final Held at Delhi.
• Participated in one-month summer camp organized by INSPIRE for all-round Development.
• Regular Participation in blood Donation.

HOBBIES
Yoga Swimming Badminton.