CMOS Fabrication Process

Semiconductor Physics Course
Final Presentation
“CMOS Fabrication”
by Özgür Çobanoğlu
(Turin, 2006)
1
Outline
Sections and Contents of the Presentation
➢ What is MOS ?
➢ The structure of simplest device
Final Presentation on “CMOS Fabrication” by Özgür Çobanoğlu
➢ How does MOS behave in low level ?

➢ MOS capacitor under external bias
Can we produce something useful out of it ?

Semiconductor Physics Course (2006)
➢ Diode, transistor etc.
➢ How to build an actual MOSFET ?

➢ A useful device
➢ Fabrication Process Steps

➢ Crystal growth, substrate formation
➢ Lithography (Photo resist, Exposure, Development, etching)
➢ Ion implantation, passivation, protective layer formation
➢ Example “beasts” we develop

➢ Read-out & communication chips for High Energy Physics (HEP) experiments
➢ General purpose processors
2
MOS Structure
Metal, Oxide and Semiconductor Capacitor Structure
Formation : ● In the p-silicon we have positively

● Acceptor dep. charged mobile holes, and negatively
● Heat treatment charged fixed acceptors.
● Polysilicon dep.
● Ef goes down with the effect of
impurities (e.g. Boron as acceptor)
● [0] np = ni 2 1
ni 2
npo ≃ 2
NA
p po≃N A 3
kT n
Fp = ln  i  4 [8]
q NA
kT ND
Fp= ln   5 Ef Intrinsic
q ni
Fermi
level
➢ Mass Action Law (1)
➢ Electron (2) & hole (3) concentrations
➢ Fermi potentials for p-type (4) & n-type (5)
3
MOS Biasing
The MOS Capacitor System under External Bias
An electric field develops The positive charge pushes the holes

between the positive holes and the away from the region under the gate and
negative gate charge. Note that the uncovers some of the negative charged
gate and the substrate form a kind of fixed acceptors. Now the electric field points
parallel plate capacitor, with the the other way, and goes from the positive
oxide acting as the insulating layer in- gate charge, terminating on the negative
between them (Accumulation). acceptor charge within the silicon.
[8]
Ef
Ef
4
MOS Biasing (Cont'd)
The MOS Capacitor System under External Bias
If the bending increases, Ec the conduction

band edge, and Ef the Fermi level start to get
closer which means that n the electron
concentration, should soon start to become

significant. In the situation represented by the
first figure, we say we are at the threshold, and
the gate voltage Vg at this point is called the
threshold voltage Vt.
Even though, we have increased Vg beyond the

threshold voltage Vt, and more positive charge
appeared on the gate, the depletion region no
longer moves back into the substrate. Instead
electrons start to appear under the gate region,
and the additional electric field lines
terminate on these new electrons, instead
of on additional acceptors. We have created
[8] an inversion layer of electrons under the
gate, and it is this layer of electrons which we
can use to connect the two n-type regions in a
MOS transistor..
5
MOS Biasing Summary
The MOS Field Effect Transistor - Structure
[8]
Accumulation occurs typically for negative voltages where the negative charge on
the gate attracts holes from the substrate to the oxide-semiconductor interface.
Depletion occurs for positive voltages; the positive charge on the gate pushes the
mobile holes into the substrate, thereby depleting the semiconductor of the mobile
carriers. The voltage separating the accumulation and depletion regime is referred to as
the flat-band voltage.
Inversion occurs at more positive voltages which are larger than the threshold
voltage. In addition to the depletion layer charge, a negatively charged inversion layer
forms at the oxide-semiconductor interface.
6
MOSFET
The MOS Field Effect Transistor
➢ What is MOS ?



➢ A useful device


7
MOSFET - Structure
The MOS Field Effect Transistor - Structure
● [0] Principle :
Control the current flowing through

Drain-Source terminals by adjusting the
electric field the Gate potential creates.
As the Vgs increases, first the

depletion region (Vgs<Vth) and then

the inversion layer (Vgs>Vth) are
formed. [8] W
L
[3]
8
MOSFET - Operation
The MOS Field Effect Transistor - Operation
[6]
.....................
V TH =V THN , THP  N  ∣2 F V SB∣−∣2F∣
I DS , TRI =±N / P C OX
W
L [ 1
V DS V GS−V THN ,THP − V 2DS
2 ]
1 W 2
[6] [5] I DS , SAT =± 2  N / P C OX L V GS−V THN , THP 
[3]
.....................
9
Non-Idealities
The MOSFET “Channel Length Modulation” Effect
One of several short channel effects in CMOS scaling, Channel Length

Modulation (CLM) is the effect of a pinch-off region forming before the drain under
large drain bias. This shortens the channel region, and leaves a gap of un-inverted
silicon between the end of the formed inversion layer. [3]
Id expression is valid until the pinch-off point; the additional term comes due to
the region between pinch-off point and the drain.
ro
T
GCA is (Gradual Channel Approximation)

Together with the effect of Channel Length Modulation
1 W 2
[6] I DS , SAT =±  N / P C OX V GS−V THN , THP 
2 L
1 W 2
I DS , SAT =±  N / P C OX V GS −V THN , THP  1 V DS 
2 L
10
Non-Idealities (Cont'd)
The MOSFET “Bulk Effect”
V TH =V THN , THP  N  ∣2 F V SB∣−∣2  F∣

[6]
11
Down-Scaling Effects
Small Geometry Effects
➔ Constant-Field Scaling Effect

● Tries to preserve the magnitude of internal electric fields; dimensions are
scaled down and supply voltage is reduced accordingly.
➔ Constant Voltage Scaling Effect

● Dimensions are reduced and the supply voltages remain unchanged; doping
concentrations are increased.
➔ Narrow-Channel Effects
● The most significant one is that the threshold voltage of such a device is
larger than the calculated one.
➔ Short-Channel Effects
● the limitations imposed on electron drift characteristics in the channel
● modification of threshold voltage due to shortening channel length
➔ Other Limitations Imposed by Small-Device Geometries ● [0]

● Sub-threshold conduction (Drain Induced Barrier Lowering DIBL)
● Punch-through (Depletion regions of D & S merge, FET melts locally)
● Everything can NOT be scaled down arbitrarily like tox (pinholes on the oxide
can short an active area to gate, oxide breakdown
● Hot carriers can be injected to gate oxide degrading the device
characteristics, injection occurs in the vicinity of drain junction.
● Interconnect damage due to electro-migration
● Electrostatic discharge (ESD)
● Electrical over-stress (EOS)
12
Parasitic Devices
Small Geometry Effects
➢ At least, two arbitrarily

selected layer form a
“parasitic device”
➢ Parasitic capacitance is
inevitable.
M1
M2
[6]
Capacitance
13
CMOS Fabrication
Actual Implementation
➢ What is MOS ?



➢ A useful device


14
Process Cycle
Actual Fabrication via Lithographic Layout Formation Processes
The following section will deal with the CMOS fabrication technology which requires
both n & p-channel transistors to be built on the same substrate.[0]
The simplified process sequence for the fabrication of CMOS integrated circuits on
a p- type silicon substrate is shown.

.
The lithographic sequence is
repeated for each physical layer
used to construct IC. Sequence is

always the same: [2]
● Photoresist application
● Printing (exposure)
● Development
● Etching
Finalize
A grown ingot to
be sliced into
“wafers”.
.
[8] 15
MOS Layout
To accommodate both nMOS and pMOS devices, special

regions must be created in which the semiconductor type is
opposite to the substrate type. These regions are called wells or
tubs. [0]
A p-well is created in an n-type substrate or, alternatively,
an n- well is created in a p-type substrate. In the simple n-well
CMOS fabrication technology, the nMOS transistor is created in
the p-type substrate, and the pMOS transistor is created in the

n-well, which is built-in into the p-type substrate.
[8]
Metal
FOX
Active Area
Polysilicon
Substrate 16
One Lithography Cycle
[0]
Each processing step requires that
certain areas are defined on chip by
appropriate masks. Consequently, the
integrated circuit may be viewed as a set
of patterned layers of doped silicon,

polysilicon, metal and insulating silicon
dioxide. In general, a layer must be
patterned before the next layer of
material is applied on chip. The process
used to transfer a pattern to a layer on

the chip is called lithography. [0]
The sequence starts with the

thermal oxidation of the silicon
surface, by which an oxide layer of about
1 micrometer is created on the substrate,
see (b).
The entire oxide surface is covered

with a layer of photoresist, which is a
light-sensitive, acid-resistant organic
polymer, initially insoluble in the
developing solution (c).
The photoresist material is exposed

to ultraviolet (UV) light, the exposed
areas become soluble so that they are no
longer resistant to etching solvents (d).
17
One Lithography Cycle (Cont'ed)
After hardening the remaining

photoresist covered area; a solvent
removes (etching) the soluble parts of
the applied photresist (e). During this
process, oxide layer is also etched down

till the substrate layer (f).
After that, photoresist can be

removed by another solvent (f) which
does not attack the substrate, so that the

silicon layer is left patterned as required.
[0]
Above is what we achieved

during this 7-step process. 18
Summary
[8]
Grow crystalline silicon (1); make a wafer (2–3); grow a silicon dioxide
(oxide) layer in a furnace (4); apply liquid photoresist (resist) (5); mask
exposure (6); a cross-section through a wafer showing the developed
resist (7); etch the oxide layer (8); ion implantation (9–10); strip the resist
(11); strip the oxide (12).
Steps similar to 4–12 are repeated for each layer (typically 12–20 times
for a CMOS process).
19
Forming an nMOS Transistor
[0]
[7]
● Nitride defines the

active areas
● FOX is developed
● Nitride is removed
by a solvent
● Polysilicon is
deposited
20
Forming an nMOS Transistor (Cont'd)
● Spacer & active

field formation
● Dep. of SiO2 [0]

● Etching contact
holes
● Metal dep.
21
Forming an Inverter - 1st Step
● To be able to place nMOS & pMOS devices on the same

substrate, so called N-Well process has been developed.
[4]
22
Forming an Inverter - 2nd Step
[4]
Defining
active
areas
Stress-relief oxide Silicon Nitride
n-well
p-type [2]
[7]
23
Forming an Inverter - 3rd Step
[4]
24
Forming an Inverter - 4th Step
● All the MOSFET

gates are defined in a
single step
[4] ● The polysilicon gate

can be doped (n+)
while is being
deposited to lower its
parasitic resistance
(important in high
speed fine line
processes)
Polysilicon mask
Polysilicon gate
n-well
[2] p-type
[7] 25
[4]
The process is self-aligned
26
[4]
Annealing [2]
● After the implants are completed a thermal annealing cycle is executed
● This allows the impurities to diffuse further into the bulk
● After thermal annealing, it is important to keep the remaining process
steps at as low temperature as possible
27
● The surface of the IC is covered by a layer of CVD oxide [2]

– The oxide is deposited at low temperature (LTO) to avoid that
underlying doped regions will undergo diffusive spreading
● Contact cuts are

defined by etching
SiO2 down to the

surface to be
contacted
[4] ● These allow metal
to contact diffusion
and/or polysilicon
regions
Mask for contacts
28
[4]
Final form
• Metals may react with nearby materials, and may [7]

have to be encapsulated using nitrides (e.g. Si3N4
or TiN) to prevent unwanted reactions, or partial
erosion in subsequent etching procedures. [2]
29
[4]
30
Forming an Inverter - Summary
[0]
Create N-Well S/D implantation SiO2 dep. & via etch

Define actives & FOX SiO2 dep. & contact etch M2 deposition
Polysilicon dep.2 M1 dep. Final w/o oxide layers
31
Finalization
Over glass and pad openings
Over glass and pad openings [2]

● A protective layer is added over the surface:
● The protective layer consists of:

– A layer of SiO2
– Followed by a layer of silicon nitride

● The SiN layer acts as a diffusion barrier

against contaminants (passivation)
● Finally, contact cuts are etched, over metal
2, on the passivation to allow for wire
bonding.
32
Design Rules
Important Link in the Lithography Chain
[6] [8]
Designer :
● Designing the circuit in

building block and
schematic levels
● Drawing the "layer"
patterns on a layout editor
Silicon Foundry :
● Mask generation from the
layer patterns in the design
data base
● Printing: transfer the mask
pattern to the wafer
surface
● Process the wafer to
physically pattern each
layer of the IC [2]
Reasons :
● Rules originating from the
reliability of the materials
and the system they form
33
Design Rules (Cont'd)
● Interface between the circuit

designer and process
engineer [2]
● Guidelines for constructing
process masks
● Unit dimension: minimum
line width
➢ scalable design rules:

lambda parameter
➢ Absolute dimensions:
micron rules
● Rules constructed to ensure
that design works even
when small fab. errors
(within some tolerance)
occur
● A complete set includes
➢ set of layers [0]
➢ intra-layer:relations
between objects in the
same layer
➢ inter-layer:relations
between objects on
different layers
34
[0]
35
[8]
A Couple of Design Tabus
● Never put transistors in mixed directions (put all of them preferably vertical)
● Substrate is tilted to prevent channeling of dopant ions
● Shadowed areas would differ leading to matching problems; even to chip failure
● Never pass-over one of the two transistors with a wire whereas matching is
important
● Capacitive transistor model changes leading to e.g. different speed characteristics
● Psychology of the devices must be identical

● Dummy elements must be used to create the same environment for every
corresponding device; devices are NOT isolated perfectly
Implant
36
A Couple of Design Tabus
● Never put long wires; switch between different layers via “via”s.
● Never connect a long M1 wire to a gate polysilicon (unless gate is connected to an

active)
● Etching in the next step can load gate excessively; leading to oxide bread-down
● Put short M1 then a long M2; this would prevent gate loading during processing
37
What We Have
State of Art
– Up to eight metal levels in modern processes [2] Transceiver Chip

Copper for metal levels 2 and higher
– Stacked contacts and vias

– ChemicalMetal Polishing for technologies with several metal levels
For analogue applications some processes offer:
● capacitors
● resistors
● bipolar transistors (BiCMOS)
● etc.
– Shallow
Bit Slicetrench isolation [2]
– n+ and p+-doped polysilicon gates (low threshold)
– source-drain extensions LDD10-Bits D/A Converter
(hot-electron Core
effects)
– Self-aligned silicide (spacers)
– Non-uniform channel doping (short-channel effects)
● Tools for “real simulations” :

● Cadence (commercial, for real-world production)
● Elektrik (open source, schematic, layout, analog, digital)
● Qucs (open source, schematic, limited layout, analog, digital)
38
What We Have
State of Art
Transceiver Chip
– Up to eight metal levels in modern processes
– Copper for metal levels 2 and higher

– Stacked contacts and vias
– ChemicalMetal Polishing for technologies with several metal levels
– For analogue applications some processes offer:

● capacitors
● resistors
● bipolar transistors (BiCMOS)
Bit Slice
– Shallow trench isolation
– n+ and p+-doped polysilicon gates (low threshold)
10-Bits D/A Converter Core
– source-drain extensions LDD (hot-electron effects)
– Self-aligned silicide (spacers)
– Non-uniform channel doping (short-channel effects)
[6]
39
Fabrication Details
Alternative and/or Advanced Fabrication Steps
➢ What is MOS ?
Etching types
●
How doesWet
MOSchemical,
behave dry (plasma
in lowassisted),
level ? ion
●
➢

Lithography types
●
Optic, electron
Can we produce
● beam, x-ray,
something ion beam
useful out of it ?

Deposition types
●
➢ Ion, CVD,
How to build an PVD
●
actual MOSFET ?
➢ A useful device
XXXresist details
●
➢ Positive,
Fabrication negative,
Process
●
Stepspolymers as electron resists
● Advanced Processes
➢ Ion implantation, passivation,CMOS
● Twin-Tub(Well) Process
protective layer formation
● Silicon on insulator (SOI) CMOS Process
40
Photoresist
Howto
• Photoresist normally comes in powder form, which is insensitive to light. It is

reconstituted into liquid form by adding a solvent, typically alcohol.
•
• The wafer is mounted on a turntable, spinning slowly, and the photoresist is discharged
into its center. Centrifugal force spreads the resist outward across the wafer. The
thickness that remains on the wafer is a function of the rate of wafer spin and the
viscosity of the photoresist. The thickness is monitored by light diffraction, which is

used to adjust the spin rate to reach the correct PR thickness.
Pha se Inter fer ence g iv es
Pho tor esist Thick ness
• After the PR is applied, the wafer is heated (~160C) to evaporate the solvent, leaving
a smooth solid coating.
– The wafer is heated to harden the patterned resist so that it will withstand immersion
into acids. A typical hardening bake is ~300C.
– In rare cases, the photoresist is not adequate as a mask itself, and the patterns are
processed to make a more robust mask, e.g. of thick SiO2 (for very high energy
implants) or Si3N4 for solvent etches which also attack PR.
[1]
41
Lithography Types
Optic
The name optical lithography comes from the early application where the exposing
energy was visible light. While those wavelengths can still be used, the push to reduce
the size of feature sizes has lead to the use of shorter wavelengths to increase
resolution. Ultraviolet (UV) and deep ultraviolet (DUV) sources are now used. Such
sources include excimer lasers which operate at wavelengths of 248 nm, 193 nm, and
less. Visible wavelengths end in the red at about 400 nm. At these shorter wavelengths,
particularly 193 nm, optical materials and even air absorb the energy very well and
there are still many problems to be overcome when using this wavelength.
42
Lithography Types (Cont'd)
X-Ray
Collimated x-rays as the exposing

energy
Lower in wavelength; better

resolution
Allows micro structures with great

height to be fabricated, relative to

optical lithography
Lithography process uses different

materials (e.g. gold as absorber)
Mask substrate is normally a low

atomic number material such as
diamond, beryllium, or
polyimide, or a thin membrane of
a higher atomic number material
such as silicon or silicon carbide.
The substrate is, again, any
structural material which fits the
particular application and the
photoresist of choice is polymethyl
methacrylate (PMMA)
43
Lithography Types (Cont'd)
X-Ray
(There are also ion & electron beam

lithographies other than mentioned here) 44
Etching
Howto
anisotropic etch (ideal)

resist
● Etching :
– Process of removing unprotected layer 1

material
– Etching occurs in all directions
layer 2
– Horizontal etching causes an
under cut
– “preferential” etching can be isotropic etch
used to minimize the undercut
undercut resist
● Etching techniques :
– Wet etching : uses chemicals to layer 1 [2]
remove the unprotected
materials layer 2
– Dry or plasma etching : uses
ionized gases rendered
chemically active by an rf-
generated plasma [1] preferential etch
undercut resist
layer 1
layer 2
45
Chemical Vapor Deposition
Howto
• SiH4(gas) + O2(gas) -> SiO2(solid) + 2H2 (gas) [1]

• SiH4(gas) + H2(gas) +SiH2(gas) -> 2H2(gas) + PolySilicon (solid)
[8]
46
Twin-Tub CMOS Process
Howto
For inexpensive and low-performance chips, one may use a heavily doped
substrate and omit one well. The substrate should be doped to about 1016/cm3, with a
resistivity of about 1 Ω-cm. This allows simpler construction, with good “Ground
Potential” distribution, but the devices are not optimal and there is a chance of
latch-up if the voltages are pushed hard.
For high-performance chips, one uses a low doped substrate, 1015/cm3, 10 Ω-cm,
and then constructs Two Wells at optimum doping levels (called Tubs in the
diagram). Since the substrate is lightly doped, there is less chance for latch-up
because of the high resistivity. [1]
[8]
47
Twin-Tub CMOS Process (Cont'd)
Howto
● This technology provides the basis for separate optimization of the nMOS and pMOS
transistors, thus making it possible for threshold voltage, body effect and the
channel transconductance of both types of transistors to be tuned independently.
● Generally, the starting material is a n+ or p+ substrate, with a lightly doped

epitaxial layer (~1015/cm3) on top. This epitaxial layer provides the actual substrate
on which the n-well and the p-well are formed.
● Since two independent doping steps are performed for the creation of the well
regions, the dopant concentrations can be carefully optimized to produce the
desired device characteristics.

• In the conventional n-well CMOS process, the doping of the well region is typically
about one order of magnitude higher than the substrate, which, among other effects,
results in unbalanced drain parasitics (possible latch-up). The twin-tub process, below,
avoids this problem.
[8]
48
Silicon On Inculator CMOS Process
Howto
● Rather than using silicon as the substrate material, an insulating substrate will
improve process characteristics such as speed and latch-up susceptibility. [1]
● The SOI CMOS technology allows the creation of independent, completely

isolated nMOS and pMOS transistors virtually side-by-side on an insulating
substrate.
● The main advantages of this technology are
– the higher integration density (because of the absence of well regions)

– complete avoidance of the latch-up problem
– lower parasitic capacitances compared to the conventional n-well or
twin-tub CMOS processes.
● A cross-section of nMOS and pMOS devices in created using SOI process is
shown below.
49
References
Throughout the presentation
● [0] CMOS Digital Integrated Circuit Design - Analysis and Design by S.M.
Kang and Yusuf Leblebici
[1] S.M. Sze, VLSI Technology, New York, NY: McGraw-Hill, 1983.
● [2] Paulo Moreira, “ELEC-2002_11Apr02_3.ppt”

● [3] Design of Analog CMOS Integrated Circuits by Behzad Razavi, McGraw-
Hill Higher Education; ISBN: 0072380322
● [4] CSE/EE 462: VLSI Design Fall 2004, The CMOS Fabrication Process and
Design Rules by Jay Brockman
● [5] CMOS Circuit Design, Layout, and Simulation by R. Jacob Baker, Harry
W. Li, David E. Boyce, IEEE Press Series on Microelectronic Systems; IEEE;
ISBN: 0780334167
● [6] Web resources, http://www.ph.unito.it/~cobanogl
● [7] Bell-Labs, web resources
● [8] Anonymous web resources
50

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Semiconductor Physics Course

➢ How does MOS behave in low level ?

Can we produce something useful out of it ?

➢ Diode, transistor etc.

➢ How to build an actual MOSFET ?

➢ Fabrication Process Steps

➢ Example “beasts” we develop

Formation : ● In the p-silicon we have positively

An electric field develops The positive charge pushes the holes

If the bending increases, Ec the conduction

concentration, should soon start to become

threshold voltage Vt.

Even though, we have increased Vg beyond the

➢ How does MOS behave in low level ?

Can we produce something useful out of it ?

➢ Diode, transistor etc.

➢ How to build an actual MOSFET ?

➢ Fabrication Process Steps

➢ Example “beasts” we develop

Control the current flowing through

As the Vgs increases, first the

depletion region (Vgs<Vth) and then

V TH =V THN , THP  N  ∣2 F V SB∣−∣2F∣

One of several short channel effects in CMOS scaling, Channel Length

silicon between the end of the formed inversion layer. [3]

GCA is (Gradual Channel Approximation)

V TH =V THN , THP  N  ∣2 F V SB∣−∣2  F∣

➔ Constant-Field Scaling Effect

➔ Constant Voltage Scaling Effect

➔ Other Limitations Imposed by Small-Device Geometries ● [0]

➢ At least, two arbitrarily

➢ How does MOS behave in low level ?

Can we produce something useful out of it ?

➢ Diode, transistor etc.

➢ How to build an actual MOSFET ?

➢ Fabrication Process Steps

➢ Example “beasts” we develop

a p- type silicon substrate is shown.

used to construct IC. Sequence is

To accommodate both nMOS and pMOS devices, special

the p-type substrate, and the pMOS transistor is created in the

of patterned layers of doped silicon,

used to transfer a pattern to a layer on

The sequence starts with the

The entire oxide surface is covered

The photoresist material is exposed

After hardening the remaining

process, oxide layer is also etched down

After that, photoresist can be

does not attack the substrate, so that the

Above is what we achieved

● Nitride defines the

● Spacer & active

● Dep. of SiO2 [0]

● To be able to place nMOS & pMOS devices on the same

Stress-relief oxide Silicon Nitride

● All the MOSFET

[4] ● The polysilicon gate

The process is self-aligned

● The surface of the IC is covered by a layer of CVD oxide [2]

● Contact cuts are

SiO2 down to the

Mask for contacts