EE272 Final study guide V 0.2 1.3. How can the AXI bus improve performance?

● Because there are independent read and write channels, read and
1. AXI bus write can happen at the same time
1.1. What are the basic concepts of the AXI bus? ● AXI Protocol:
● Instead of one bus for data transaction, there are five channels. ○ Permits address info to be issued ahead of actual data
● These 5 channels are: ○ Supports multiple transactions
○ Write address ○ Supports out-or-order completion of transactions
○ Write data
○ Read address 1.4. How many sub busses does the AXI bus contain? What function does
○ Read data each perform?
○ Write response ● There are five sub busses
● Key features of AXI Protocol: ● See P1.2 for their function
○ Separate address/control and data phases
○ Support unaligned data transfers
○ Uses burst-based transactions with only start address issued 2. PCI-E
○ Separate read and write data channels 2.1. What are the layers of PCI-E?
○ Support for issuing multiple outstanding address
○ Support for out-of-order transaction completion
○ Permits easy addition of register stages to provide timing closure

1.2. How are the different portions of the AXI bus used?
● AXI is burst-based and has five independent transaction channels.
● Address channels carries control information that describes nature of
data to be transferred.
● Data channels transfer data between the master and slave by:
○ Write data channel
■ Master to slave
■ Carries write data
■ This channel is always treated as buffered, so master can
perform write transaction without slave ack of previous write
transaction
■ Slave uses write response channel to signal completion of
transfer to master
● PCI-E uses packets to communicate information between components
○ Read data channel
● Packets are formed in TL and DLL to carry information from TX to RX
■ Slave to master
● As transmitted packets flows through other layers, they are extended
■ Carries both read data and read response
with additional info necessary to handle packets at those layers
■ Read response indicates completion status of read transaction
● At RX, the reverse process occurs, and packets gets transformed from
● Write response channel responds to write transaction
PL representation to DLL representation to TLP so TL from receiving
● Each channel has a set of information signals and VALID and READY
device can process it
signals to provide a two-way handshake
○ VALID
■ From source
■ show when valid address/data/control info is available
○ READY
■ From destination
■ Show when it can accept info
○ LAST
■ Both read and write data channel have this
■ Indicate transfer of final data in transaction

2.2. What does the TLP layer perform?

● Upper layer of architecture
● Primary responsibility is assembly and disassembly of Transaction
Layer Packets (TLPs)
● TLPs are used to communicate transaction
● TL also responsible for managing credit-based flow control of TLPs
● Key aspects
○ Pipelined full split-transaction protocol
○ Mechanisms for differentiating ordering and processing
requirements of TLPs
○ Credit-based flow control
○ Optional support for data poisoning and end-to-end data integrity
detection
● Request packet that requires response packet
○ Implemented as split transaction
○ Each packet has unique identifier that enables response packets
to be directed to correct originator
○ Packet format for addressing depends on type of transaction
(Memory, I/O, Configuration, Message)
○ Packets may have attributes (No Snoop, Relaxed Ordering,
ID-Based Ordering (IDO))
 ● Supports four address spaces (first three are PCI address spaces) 2.4. What is the DLP?
○ Memory ● Middle layer
○ I/O ● Serves as intermediate stage between TL and PL
○ Configuration ● Primary responsibilities:
○ Message Space ○ Link management
○ Data integrity
■ Error detection
■ Error correction
● TX side
○ Accepts TLPs from TL
○ Calculates and applies data protection code and TLP sequence #
○ Submits to PL for transmission across Link
● RX side
○ Checks integrity of received TLPs
○ Submit packets to TL for further processing
○ If TLP error detected, DL is responsible for requesting
● Transaction Layer packet (TLP) format overview retransmission of TLPs until correctly received, or Link is
○ Transaction consist of Requests and Completions, which are determined to have failed
communicated using packets ● DLL also generates and consumes packets (DLLP) for Link management

2.5. Why are buffers placed in the TLP and DLP?

● For retires

2.6. How does PCI-E handle priority traffic?

● In the TLP header, there is a Transaction Descriptor that describes the
properties of the Transaction
● Traffic class field handles priority traffic
● Note:​ these fields are not contiguous in packet header

● It has three fields

○ Transaction ID – identifies outstanding Transactions
● All TLP prefixes and headers contains the following fields
○ Fmt[2:0] = format of TLP
○ Type[4:0] = type of TLP

○ Attributes – specifies characteristics of Transaction

● TLP Header
○ Fmt and Type provide information required to determine size of
remaining part of TLP Header
○ Traffic Class (TC) – associates Transaction with type of required
service
■ Allows differentiation of transaction into eight traffic classes
■ As packet traverses across fabric, this info is used at every
Link and within each Switch to make decisions with regards to
proper servicing of traffic
2.3. Where does input for the TLP come from? Why is it not in the spec?
● Root Complex
○ Denotes root of an I/O hierarchy that connects CPU/Memory
subsystem to I/O
● Intel did not want to get into trivia hence it is not placed above TL
2.7. Can PCI-E be handled with routers? How?
● Yes. Since the messages are sent through transactions which contains
the information of the source and destination, these packets can be
routed
2.8. What actions does the physical layer perform?
● Takes packets, adds 3​rd​ header, checks it, recode and sends to DL/Link
● Contains all circuitry for interface operations, initialization, and
maintenance
● PL exchanges info with DLL in implementation-specific format
● Is responsible for converting info received from DLL into an
appropriate serialized format and transmitting across PCI Link
● Isolates TL and DL from signaling technology used for Link data
interchange
● Is divided into two sub-blocks
○ Logical Sub-block
■ Directs control and management functions of PL
■ Has two main sections
● Transmit
○ Prepares outgoing info passed from DLL for
transmission by electrical sub-block
● Receiver
○ Identifies and prepares received info before passing
to DLL
○ Electrical Sub-block
2.11. How many packet wrappings happen in PCI-E?
● Three, once at each layer
2.12. Can the input and output busses work at the same time?
● Yes, since they are independent from each other. Only Ack and Nak
cross overs
2.13. How does the PCI-E bus achieve high data rates?
● By having extremely high clocks
● PL isolates TL and DLL from signaling technology used for Link data
interchange
● Logical sub-block and electrical sub-block in PL coordinate state of
each Transceiver through status and control register interface or
functional equivalent
● PCI-E used 8b/10b encoding when data rate is 2.5 GT/s or 5.0 GT/s
○ 8-bit data characters are treated as 3 bits and 5 bits mapped onto
a 4-bit code group and a 6-bit code group, respectively
○ Control bit with data character is used to identify when to encode
one of the 12 special symbols included in 8b/10b transmission
code
○ They are concatenated to form a 10-bit symbol
○ Bits are placed on a Lane

2.9. How are errors handled in PCI-E?

● Simply retried at DLP
● DLL apply these to TLP for error detection
○ TLP Sequence Number
○ Link CRC (LCRC)
● DLL Retry is used for recovery
● TLP transmission through DLL prepares each TLP by applying sequence
number, then calculating and appending LCRC (used to ensure
integrity of TLPs during transmission across Link from one component
to another)
● TLPs are stored in retry buffer, and are re-sent unless +ACK is received
● If repeated attempts to transmit TLP are unsuccessful, the TX will
determine Link not operating correctly, and instruct PL to retrain Link ● For data rates ≥ 8.0 GT/s, it uses per-lane code along with PL
● If retraining Link fails, PL will indicate Link is no longer up, causing encapsulation
DLCMSM to move to DL_Inactive state ○ Uses 128b/130b encoding

2.14. As an external bus how does PCI-E deal with low cost devices?
● If PL indicates Receiver Error ● Run at slower clock rates 2.5 GT/s or 5.0 GT/s
○ Discard any DLLP currently being received
○ Free any storage allocated for DLLP
○ Reporting such errors to software is done by PL
3. Ring busses
3.1. How does a ring bus work?
● Data is passed in a ring
2.10. How is retry enabled in the DLP?
● Each device has an in and out
● Nak DLLP
● If message is not for the device, it is passed to next device
○ TLP sequence number negative acknowledgement
○ Used to initiate a DLL Retry
● DLLP has Ack/Nak (0000_0000/0001_0000) DLLP Type Encodings for
successful/unsuccessful receipt of TLP
● Copies of transmitted TLPs must be stored in DLL Retry Buffer in the
order of their arrival, except for nullified TLPs
● Replay initiated by reception of Nak or REPLAY_TIMER expiration
3.2. How is arbitration handled on a ring bus? ■ Unidirectional 8-bit
● There is no master and slave ● Ultra Fast-mode 5MB/s
● A token is passed around the ring ○ On-chip filtering rejects spikes on bus data line to preserve data
● Whichever device requests and is granted bus ownership can start integrity
data transfer ○ Number of ICs that can be connected to same bus is limited only
by max bus capacitance
3.3. What is a token passing arbitration method?
● A token is passed among all devices on the bus ● Benefits of SPI:
● If device wishes for bus ownership, it must assert want token signal ○ Master mode and slave mode
● When request is granted, device assert have token signal until transfer ○ Bi-directional mode
is complete ○ Slave select output
● Else device passes token if no transfer or transaction is complete ○ Mode fault error flag with CPU interrupt capability
○ Double-buffered data register
○ Serial clock with programmable polarity and phase
3.4. How can high performance be obtained with a ring bus? ○ Control of SPI operation during wait mode
● Multiple rings
● Small ring size (less devices in ring, reduces latency) 4.2. Why are I2C and SPI found on most SOC designs?
● High clock rates ● Both are serial buses
● No central arbitration to avoid long wires ● Very cheap to implement in terms of pin count
● Passing continuously in large burst size ● Stable communication protocol
● Multiple messages ● Smaller printed circuit boards
● Simplified design
3.5. Why do ring busses tend to have large latency? ● Typically, lower power consumption
● Data packet has to pass all devices between sender and receiver
● This causes latency, especially if the number of devices increases 4.3. How is the protocol performed in I2C and SPI?
● Max latency occurs when sender is first node and receiver is the very ● I2C
last node 1. Send START bit (S)
2. Send slave address
3.6. What is the benefit of implementing a ring bus? 3. Send R/W bit
● Simple 4. Wait for or send Ack
● Easy to reuse because everything is built into the nodes 5. Send/receive data byte (8-bits)
● Short wires between nodes 6. Expect/send Ack bit
7. Send STOP bit (P)
3.7. Why are bi-directional busses a benefit?
● Uses less pins since transmitting (TX and RX) happens on same pin
● Complexity increases linearly with addition of devices
● If long latency in one direction, the other direction has short latency

3.8. How can a router be used to create a cluster of rings?

● A router in a ring can connect to another ring
● These can also be connected to other rings through a router, creating
a cluster of rings

3.9. Can a ring bus be hierarchical? How?

● Yes, a ring may have a router and be further connected to more rings,
creating a hierarchy
○ All transaction begins with START (S) and terminated by a STOP (P)
(only by bus master)
4. I2C and SPI
4.1. What is the most important benefit of I2C and SPI?
● Supports multi-masters
● Off chip bus
● Enables rapid system deployment
● Integrated addressing and data-transfer protocol so devices can be
added/removed easily without affecting remaining system
● Less number of pins ○ After START, slave address is sent contain 7-bits of slave address
○ I2C requires two pins and eight bit for data direction (R/W)
■ Serial data line (SDA) ■ 0 = write
■ Serial clock line (SCL) ■ 1 = read
○ SPI requires two control lines and two data lines
■ Chip-Select (CS) or Slave Select ( SS )
■ Clock (SCLK)
■ Serial Data In (SDI) or Master Out-Slave In (MOSI)
■ Serial Data Out (SDO) or Master In-Slave Out (MISO)
● Benefits of I2C:
○ Supports multi masters
○ Uses only two lines SDA and SCLK
○ Each device connected to bus is addressable by a unique address
○ Transfers can be
■ Bi-directional 8-bit
● Standard-mode 100 kB/s
● Fast-mode 400 kB/s
● Fast-mode plus 1 MB/s
● High-speed mode 3.4 MB/s
 ○ Acknowledge (ACK) takes place after every byte
■ ACK signal is defined by
● Transmitter releases SDA during Ack clock pulse so
receiver pull SDA low
● remains LOW during HIGH period of this clock pulse
■ ACK bit allows receiver to signal transmitter that byte was
successfully received and another byte may be sent
■ If SDA remains high during 9​th​ clock, then it is NACK
■ Master can STOP to abort transfer or repeat START to start
new transfer
■ ACK from slave: master writing to slave (W)
■ ACK from master: master receiving data from slave (R)
4.6. What are the benefits of SPI over I2C?
4.5. How are errors detected in I2C?
● ACK bit
● Since an ACK is after each byte of data sent, can see check for NACK
● Five conditions for generating NACK
1. No receiver present on bus with transmitted address so there is
no device to respond with ACK
2. Receiver is unable (not ready) to receive or transmitted
3. During transfer, receiver gets data/commands that it does not
understand
4. During transfer, receiver cannot receive any more data bytes
5. A master-receiver must signal end of transfer to slave-transmitter
● SPI is faster
● SPI requires less power
● SPI is duplex, while I2C is half-duplex
● SPI does not define any speed limit, while I2C is limited to 1 MB/s in
Fast Mode+ and 3.4 MB/s in High Speed Mode

5. General bus concepts

● SPI 5.1. Contrast all the busses studied for bandwidth, handling of interrupts
and other messages, costs, if on chip, or off chip as the primary target.
On chip Off chip
● Long wires ● Electrical issues
● Arbiter needs big muxes ● Turn around time
to select master ● Missing device detection
● Memory only interactions ● Configuration space
● Erros? ● Multiple buses can connect to
● Less latency this device
● Broad speed range
● Multiple data sizes
● Pins is an issue to keep number
○ Is a single-master communication protocol of wires
■ One central device initiates all communication with slaves ● Message based
■ When SPI master wishes to send/request data to slave, it
selects slave by pulling SS low 5.2. What are the issues with arbitration on high performance busses?
■ Clock activated at clock freq usable by master and slave ● As arbitration gets more complex, there may be additional cycles for
■ Master generates information onto MOSI (W) while it samples arbitration delays, hence even if the bus is fast and losing a couple of
MISO (R) cycles just for arbitration, there is no benefit if arbitration is done
○ Master or Slave mode (SPI Control Register 1) after every sing transfer
■ Master mode when MSTR is set ● Extra time
■ Slave mode when MSTR is clear ● Long wires
○ SPI functions in three modes ● More waiting time
■ Run mode = Basic mode of operation
■ Wait mode = Low power mode (if SPISWAI = 0, runs line Run
6. SV rand and rand/randc
but goes to power conservative state if set)
6.1. Where are rand and randc placed in SV code?
■ Stop mode = Inactive mode for reduced power consumption
● In classes
● rand
4.4. Draw the I2C and SPI waveforms
○ a standard random variables
● I2C
○ they are uniformly distributed
○ Example: 8-bit unsigned integer with range of 0 to 255
rand bit​ [7:0] y;
● randc
○ variables declared with ​randc​ keyword are random-cyclic
variables that cycle through all values in random permutation of
declared range
○ Example: 2-bit random variable ​y ​where it can be 0, 1, 2, or 3
randc bit​ [1:0] y;

● SPI

○ randomize()​ computes an initial random permutation of

range values of the variable and then returns those values in
order on successive calls
○ After it returns the last element of permutation, it repeats the
process by computing a new random permutation
○ Basic idea: randomly iterates over all values in range where no
value is repeated within an iteration
■ When iteration finishes, new iteration automatically starts
 ○ Permutation is recomputed whenever Array Reduction
■ Constraints changes on that variable
■ None of remaining values can satisfy constraints byte​ b[] = {1, 2, 3, 4};
int​ y; y = b.sum;
○ Permutation sequence contains only 2-state values // y becomes 10 => 1 + 2 + 3 + 4
y = b.product ;
6.2. What does declaring a variable rand perform? // y becomes 24 => 1 * 2 * 3 * 4
● See 6.1 y = b.xor ​with ​(item + 4);
// y becomes 12 => 5 ^ 6 ^ 7 ^ 8
6.3. Provide examples using the randomize function?
● randomize() logic​ [7:0] m [2][2] = '{'{5, 10},'{15, 20}};
int​ y;
○ temporarily control set of random and state variables within class
instance or object y = m.sum ​with ​(item.sum with (item));
○ with no arguments, it assigns new values to all random variables // y becomes 50 => 5+10+15+20
in an object (those declared as ​rand​ or ​randc​)
○ with arguments, those arguments designate the complete set of logic bit​_arr [1024];
int​ y;
random variables within the object; all other variables in object
y = bit_arr.sum ​with​ (int'(item));
are state variables // forces result to be 32-bit
○ Example: ● In randomize
class​ CA; ○ Accepts a set of constraints enclosed in braces
rand byte​ x, y;
byte​ v, w
○ Using ​randomize()​ ​with​ construct, users can declare in-line
constraints at the point where ​randomize()​ method is called
constraint​ c1 (x < v && y > w); ○ additional constraints are applied along with object constraints
endclass ○ Example: additional constraint of ​x < y
class ​SimpleSum;
CA a = ​new​;
​rand bit ​[7:0] x, y, z;
​constraint​ c {z == x + y;}
a.randomize(); //rand: x, y state: v, w
endclass
a.randomize(x); //rand: x state:
y, v, w
task ​InlineConstraintDemo(SimpleSum p);
a.randomize(v, w); //rand: v, w state: x, y
​int​ success;
a.randomize(w, x); //rand: w, x state: y, v
success = p.randomize() ​with ​{x < y;};
endtask
6.4. Provide examples of the SV rand distribution functions
● See 6.1
6.7. How is a range of values specified in a rand and randc usage?
6.5. Provide examples and explanations of the SV rand conditions ● The range of values is specified by the size of the variable
● See 6.1 ● Example: see 6.1 where 8-bit variable ​y​ has a range of 0 to 255

6.6. What is the use of the with keyword? What is the with syntax? 6.8. What other functions and variables may be placed in a class with rand
● In arrays and randc variables?
○ Accepts expression enclosed in parentheses ● Variables – integer, reg, enum, bit, array
Array Locator ● Functions
string​ SA[10], qs[$];
○ $urandom_range
int​ IA[​int​], qi[$]; ■ returns unsigned integer with specified range
■ Example: returns a value between 0 to 7
SA[1:5] = {“Bob”,”Abc”,”Bob”,”Henry”,”John”}; val = $urandom range(7, 0);
IA[2] = 3;
IA[3] = 13; ○ $urandom
IA[5] = 43; ■ returns 32-bit random number (seed optional)
IA[8] = 36; ■ will produce same numbers if same seed is used
IA[55] = 4; ■ Example: using ​$urandom
IA[28] = 1;
bit [64:0] addr;
bit [3:0] number;
//Find all items greater than 5
qi = IA.find(x ) ​with​ (x > 5); // 13,43,36
addr[32:0] = $urandom(254); // Initialize generator,
qi = IA.find(x ); // error
addr = {$urandom, $urandom}; // 64-bit random number
// Find indices of all items equal to 3
number = $urandom & 15;​ ​// 4-bit random number
qi = IA.find_index ​with​ (item == 3); // 2
○ $srandom​ – Allows manually seeding RNG of objects/threads
// Find first item equal to Bob ○ $set_randstate​ – Sets state of an object’s RNG
qs = SA.find first ​with​ (item == "Bob"); // Bob ○ $get_randstate​ – Retrieves current state of object’s RNG

Array Ordering 6.9. Create test cases using constraints to meet a testing requirement?
● Constraint block
string s[] = {"hello", "sad", "world"}; ○ Values of random variables are determined using constraint
s.reverse; // s = {"world", "sad", "hello"};
expression declared in constraint blocks
int q[$] = {4, 5, 3, 1}; ○ They are class members just like variables, functions, and tasks
q.sort; // q = {1, 3, 4, 5} ○ Example: ensures “​mode​” is between 2 and 6
class​ C;
struct {byte red, green, blue;} c [512]; rand bit​ [3:0] mode;
c.sort with (item.red); // sort red field only ​constraint​ c_mode { mode > 2;
c.rsort(x) with ({x.blue, x.green}); // green, blue mode <= 6;
};
endclass
6.10. How can pre and post functions be used to further modify a test case? ○ Example: interface using named bundle
● Every class contains ​pre_randomize()​ and interface ​simple_bus;
post_randomize() ​methods, which are automatically called by ​logic​ req, gnt;
randomize()​ before and after computing new random values ​logic​ [7:0] addr, data;
● Can be used to manipulate constraints ​logic​ [1:0] mode;
● pre_randomize() ​logic​ start, rdy;
endinterface​ : simple_bus
○ perform initialization and set preconditions before object is
randomized module​ memMod(simple_bus a, ​input logic c ​ lk);
● post_randomize() ​logic​ avail;
○ perform cleanup, print diagnostics, and check post-conditions ​always​ @(​posedge​ clk) a.gnt <= a.req & avail;
after object is randomized endmodule

module​ cpuMod(simple_bus b, ​input​ ​logic​ clk);

6.11. What is the difference between rand and randc? ...
● Rand generates random numbers between the specified range while endmodule
randc will generate random-cyclic numbers that will go throughout
the permutation module​ top;
​logic​ clk = 0;
simple_bus sb_intf(); // instantiate interface
6.12. Write a test case for an adder that will generate a carry out 80% of the
time // connect interface to module instance by position or
class ​adder; // by name
​randc bit​ [6:0] x, y; memMod mem(sb_intf, clk);
​bit​ [7:0] temp; cpuMod cpu(.b(sb_intf), .clk(clk));
constraint eighty {x > ; endmodule
x < ;
○ Example: if same identifier (​sb_intf​) had been used to name
}; simple_bus​ in ​memMod​ and ​cpuMod​ module headers, then
implicit port connections could have been used to instantiate
temp = x + y; memMod​ and ​cpuMod​ modules into top module
sum = temp[6:0];
carry = temp[7]; module​ memMod(simple_bus sb_intf, ​input​ ​logic​ clk);
endclass ...
endmodule
6.13. Why is the repeat statement commonly used with the randomize
statement? module cpuMod(simple_bus sb_intf, ​input​ ​logic​ clk);
● repeat​ statement is commonly used with ​randomize()​ so that it ...
endmodule
will generate a value within the given constraints
module​ top;
7. Interfaces ​logic​ clk = 0;
7.1. What is an interface? simple_bus sb_intf(); // instantiate interface
memMod mem(.*); // implicit port connection
● Interface construct in SV was created to encapsulate communication cpuMod cpu(.*); // implicit port connection
(also functionality as well as connectivity) between blocks endmodule
● Interface construct provides a new hierarchical structure that can
contain smaller interfaces and can be passed through ports ● Interface using generic bundle “Generic interface reference”
● allows smooth migration from abstract system-level design through ○ Module header can be created with unspecified interface
successive refinement down to lower level register-transfer and reference as placeholder when module itself is instantiated
structural views of the design ○ Example: an interface using generic bundle
● By encapsulating communication gives design reuse interface ​simple_bus;
● Lowest level: named bundle of nets and variables ​logic​ req, gnt;
● Instantiated in design and access through a port as single item, then ​logic​ [7:0] addr, data;
components nets/variables referenced where needed ​logic​ [1:0] mode;
● Ability to replace group of names by single name reduce size of ​logic​ start, rdy;
endinterface​ : simple_bus
description and improve maintainability
● Can contain module​ memMod(​interface​ a, ​input logic ​clk);
○ Parameters ​...
○ Constants endmodule
○ Variables
module​ cpuMod(​interface​ b, ​input​ ​logic​ clk);
○ Subroutines (functions or tasks)
...
○ Processes (​initial​ or ​always​) endmodule
○ Continuous assignments
○ Member variables and functions are referenced relative to instance module​ top;
name of interface as instance member ​logic​ clk = 0;
● To provide direction for module ports and control the use of tasks and simple_bus sb_intf(); // instantiate interface
functions within particular modules, use ​modport​ construct // reference sb_intf instance of simple_bus interface
● Interfaces can be declared and instantiated in modules, but modules // from generic interface of memMod and cpuMod modules
can neither be declared nor instantiated in interfaces memMod mem(.a(sb_intf), .clk(clk));
● Interface using named bundles cpuMod cpu(.b(sb_intf), .clk(clk));
○ When referencing through a port, variables and nets in interface endmodule
assumed to have ​ref​ and ​inout​ access, respectively
 ○ Implicit port cannot be used to reference a generic interface ● changes to underlying design do not require code using virtual
■ A named port is used to reference a generic interface interfaces to be rewritten
■ Example: implicit port reference ● allowed operations on virtual interface variables
module​ memMod(​interface​ a, ​input logic ​clk); ○ assignment (​=​) to following
​... ■ another virtual interface of same type
endmodule ■ an interface of same type
module​ cpuMod(​interface​ b, ​input​ ​logic​ clk);
■ special constant ​null
... ○ equality (​==​) and inequality (​!=​) with following
endmodule ■ same as above ^^^
● cannot be used as ports, interface items, or members of unions
module​ top; ● can be declared as class properties, which can be initialized
​logic​ clk = 0;
procedurally or by ​new()
simple_bus sb_intf(); ○ cannot reference in a class an actual interface, hence a virtual
interface is used to point to the actual interface in a class
memMod mem(.*, .a(sb_intf)); ○ Example: transaction class SbusTrans is a simple reusable
cpuMod cpu(.*, .b(sb_intf)); component
endmodule ■ It is written without any global or hierarchical references and
● Ports in Interfaces is unaware of the particular device with which it will interact
○ Limitation: nets and variables declared within interface are only ■ Nevertheless, the class can interact with any number of
used to connect to a port with same nets and variables devices (4 in example) that adhere to interface’s protocol
○ To share an external net/variable, one that makes a connection interface​ SBus; // A Simple bus interface
from outside interface as well as forming common connection to ​logic​ req, grant;
all module ports that instantiate the interface, an interface port ​logic​ [7:0] addr, data;
declaration is required endinterface
○ Only nets and variables in interface port list can be connected
class​ SBusTrans; // SBus transactor class
externally by name or position when interface is instantiated ​virtual​ SBus bus; // virtual interface of type SBus
○ Example: wires a, b, c can be individually connected to interface
and shared with other interfaces ​function​ ​new​( virtual SBus s );
interface​ i1 (​input​ a, ​output​ b, ​inout​ c); bus = s; // initialize virtual interface
​wire​ d; ​endfunction
endinterface
​task​ request(); // request the bus
○ Example: shows how to specify an interface with inputs, allowing bus.req <= 1'b1;
a wire to be shared between two instances of the interface ​endtask
interface​ simple_bus (​input​ logic clk);
​logic​ req, gnt; ​task​ wait_for_bus(); // wait for the bus to be granted
logic ​[7:0] addr, data; @(​posedge​ bus.grant);
logic ​[1:0] mode; ​endtask
logic ​start, rdy; endclass
endinterface ​simple_bus
module​ devA( SBus s ) ... endmodule // devices using SBus
module​ memMod(simple_bus a); module​ devB( SBus s ) ... endmodule
...
endmodule module​ top;
SBus s[1:4] (); // instantiate 4 interfaces
module​ cpuMod(simple_bus b);
... devA a1( s[1] ); // instantiate 4 devices
endmodule devB b1( s[2] );
devA a2( s[3] ); d
module​ top; evB b2( s[4] );
​logic​ clk = 0;
​initial​ ​begin
simple_bus sb_intf1(clk); // create 4 bus-transactors and bind
simple_bus sb_intf2(clk); SBusTrans t[1:4];
t[1] = ​new​( s[1] );
memMod mem1(.a(sb_intf1)); t[2] = ​new​( s[2] );
cpuMod cpu1(.b(sb_intf1)); t[3] = ​new​( s[3] );
memMod mem2(.a(sb_intf2)); t[4] = ​new​( s[4] );
cpuMod cpu2(.b(sb_intf2)); // test t[1:4]
endmodule ​end
endmodule

7.2. How are interfaces used?

● The interface is used to encapsulate communication between blocks

7.3. Can interfaces be used on modules? How?

● Yes, with modports.
● By instantiating the interface in the module and referencing the
interface’s member variables and functions through a hierarchy
● See 7.1

7.4. What is a virtual interface? How is it used?

● provide a mechanism for separating abstract models and test
programs from the actual signals that make up the design
● allows same subprogram to operate on different portion of design and
dynamically control set of signals associated with subprogram
● instead of referring to actual signals directly, users can manipulate
virtual signals
 ● Example: interface instance, or virtual interface, with no modport module ​m(i2 i);
selected may be assigned to virtual interface with modport selected ...
interface​ PBus #(​parameter​ WIDTH = 8); endmodule
​logic​ req, grant;
​logic​ [WIDTH:0] addr, data; module ​s(i2 i);
​modport​ phy(​input​ addr, ref data); ...
endinterface endmodule

module​ top; module

PBus #(16) p16(); i2 i();
m u1(.i(i.master)); // same as modport master
// legal declaration, but no legal assignments s u2(.i(i.slave)); // same as modport slave
​virtual​ PBus v8; endmodule
// legal declaration, but no legal assignments ○ Constraints:
​virtual​ PBus #(35) v35; ■ All names used in ​modport​ declarations must be declared
​virtual​ PBus #(16) v16; by the same interface as the modport itself
​virtual​ PBus #(16).phy v16_phy;
■ Names used must not be those declared by another enclosing
​virtual​ PBus #(32) v32;
​virtual​ PBus #(32).phy v32_phy; interface
​initial​ ​begin ■ modport​ declaration must not implicitly declare new ports
v16 = p16; // legal – parameter values match ■ Example: the following declaration would be illegal
v32 = p32; // legal – parameter values match interface​ i;
v16 = p32; // illegal – parameter values don't match ​wire​ x, y;
v16 = v32; // illegal – parameter values don't match
v16_phy = v16; // legal assignment from no selected ​interface​ illegal_i;
// modport to selected modport ​wire​ a, b, c, d;
v16 = v16_phy; // illegal assignment from selected // x, y not declared by this interface
// modport to no selected modport ​modport​ master(​input​ a, b, x, ​output​ c, d, y);
v32_phy = p32; // legal assignment from no selected ​modport​ slave(​output​ a, b, x, ​input​ c, d, y);
// modport to selected modport ​endinterface​ : illegal_i
v32 = p32.phy; // illegal assignment from selected endinterface​ : i
// modport to no selected modport
​end interface​ illegal_i; ​input
endmodule // a, b, c, d not declared by this interface
​modport​ master(​input​ a, b, ​output​ c, d);
7.5. How is an interface modport used? ​modport​ slave(​output​ a, b, c, d);
● Modports endinterface​ : illegal i
○ A list to restrict access within a module ● Example: control signal directions as in port declarations by using
○ modport​ indicates directions as if declared inside a module modport name in module definition
○ Example: interface with ​modport interface​ simple_bus (​input​ ​logic​ clk);
​logic​ req, gnt;
interface ​i2;
​logic​ [7:0] addr, data;
​wire​ a, b, c, d;
​logic​ [1:0] mode;
​logic​ start, rdy;
​modport​ master(​input​ a, b, ​output​ c, d);
​modport​ slave (​input​ req, addr, mode, start, clk,
​modport​ slave(​output​ a, b, i
​ nput​ c, d);
​output​ gnt, rdy,
endinterface​ : simple bus
​ref​ data);
○ Example: the ​modport​ list name (​master​ or ​slave​) can be ​modport​ master(​input​ gnt, rdy, clk,
specified in module header, where interface name selects an ​output​ req, addr, mode, start,
interface and ​modport​ name selects appropriate directional ​ref​ data);
endinterface ​: simple_bus
information for interface signals accessed in module header
module ​m(i2.master i); // interface name and modport name
... module​ memMod (simple_bus.slave a);
endmodule ​logic​ avail;
​always​ @(​posedge​ a.clk) // clk from interface
module ​s(i2.slave i); a.gnt <= a.req & avail; // gnt & req in interface
... endmodule
endmodule
module​ cpuMod (simple_bus.master b);
module ...
i2 i(); endmodule
m u1(.i(i));
s u2(.i(i)); module​ top;
endmodule ​logic​ clk = 0;
○ Syntax of a local name for hierarchical reference simple_bus sb_intf(clk); // Instantiate the interface
interface_name.modport_name reference_name ​initial​ ​repeat​(10) #10 clk++;
○ For generalized hierarchical reference use
interface​.modport_name reference_name // Connect interface to module instance
memMod mem(.a(sb_intf));
○ if port connection specifies a ​modport​ list name in both the cpuMod cpu(.b(sb_intf));
module instance and module header declaration, then the two endmodule
modport​ list names are identical
○ Example: modport list name is specified in module instance and
module header in following example and previous example
 ● Example: restrict interface signal access and control their direction by ● Example: using tasks in modports
using modport name in module instantiation interface​ transfer (​input​ clk); // define interface
interface​ simple_bus (​input​ ​logic​ clk); ​logic​ RW;
​logic​ v1, v2, v3; ​logic​ [7:0] data;
​modport​ slave (​input​ v1, ​output​ v2, ​ref​ v3);
​modport​ master(​input​ v2, ​output​ v1, ​ref​ v3); ​modport​ readwrite(​input​ rw,
endinterface ​: simple_bus ​output​ data,
​import​ read, write);
// interface name and modport name
module​ memMod (simple_bus.slave a); ​task​ read(​input​ ​logic​ [7:0] raddr);
​logic​ num; ...
​always​ @(​posedge​ a.clk) // clk from interface ​endtask​ : read
a.v2 <= a.v1 + num; // v2 & v1 in interface
endmodule ​task​ write(​input​ ​logic​ [7:0] waddr);
...
module​ cpuMod (simple_bus.master b); ​endtask​ : write
... endinterface​ : ReadWrite
endmodule
module​ save(​interface​ a);
module​ top; ​logic​ [7:0] addr = $random();
​logic​ clk = 0; ​if​(a.RW == 0)
simple_bus sb_intf(clk); // Instantiate the interface a.read(addr);
​initial​ ​repeat​(10) #10 clk++; else
a.write(addr);
// Connect interface to module instance endmodule
memMod mem(sb_intf.slave);
cpuMod cpu(sb_intf.master); module​ top;
endmodule ​logic​ clk = 0;
transfer rw(clk);
save s(rw.readwrite);
7.6 Why can interfaces contain initial and always blocks? Provide examples endmodule
of use. ● Example: exporting tasks and functions
● Useful for system-level modeling and testbench applications interface​ transfer (​input​ clk); // define interface
● Not synthesizable ​logic​ RW;
​logic​ [7:0] data;
7.7. What is the purpose and function of interface import and export?
● Subroutines (tasks and functions) can be defined within an interface, ​modport​ readwrite(​input​ rw,
​output​ data,
allowing more abstract level of modeling
ex​port​ read, write);
● In ​modport​, these tasks are declared as ​import​ tasks endinterface​ : ReadWrite
● A function prototype specifies types and direction of arguments and
the return value of the function is defined elsewhere module​ save(​interface​ a);
● A task prototype specifies type and direction of arguments of a ​task​ a.read;
function that is defined elsewhere ...
​endtask
● In a modport, ​import​ and ​export​ constructs can either use
subroutine prototypes or use just the identifiers ​task​ a.write;
● Exceptions ...
○ When modport is used to import subroutine from another module ​endtask
○ When default argument values or argument binding by name is endmodule
used, in which full prototype is used
module​ top;
● If subroutines are defined in module using hierarchical name, they are ​logic​ clk = 0;
declared as transfer rw(clk);
○ extern​ in interface save s(rw.readwrite);
○ export​ in modport endmodule
● Example: using tasks in interface 7.8. Can interfaces be nested? How and why?
interface​ transfer (​input​ clk); // define interface ● Yes
​logic​ RW;
​logic​ [7:0] data; 7.9. What is the purpose of the interface clocking block? How is it used?
Provide examples.
​task​ read(​input​ ​logic​ [7:0] raddr);
...
● to establish a clock for everything in the interface
​endtask​ : read ● the ​modport​ construct can be used to specify the direction of
clocking​ blocks declared within the interface
​task​ write(​input​ ​logic​ [7:0] waddr); interface​ A_Bus( ​input​ ​logic​ clk );
... ​wire​ req, gnt;
​endtask​ : write ​wire​ [7:0] addr, data;
endinterface​ : ReadWrite
​clocking​ sb @(​posedge​ clk);
module​ top; ​input​ gnt;
​logic​ clk = 0; ​output​ req, addr;
transfer rw(clk); ​inout​ data;
endmodule
​property​ p1; req ##[1:3] gnt; ​endproperty
​endclocking

​modport​ DUT (​input​ clk, req, addr, // DUT modport

​output​ gnt,
​inout​ data);
​modport​ STB (​clocking​ sb); // synchronous TB modport
​modport​ TB (​input​ gnt, // asynchronous TB modport
​output​ req, addr,
​inout​ data);
endinterface
7.10. Provide examples of an interface specify block and indicate why it ● two kinds of assertion
would be used. ○ concurrent
● Used to describe various paths across a module and perform timing ■ based on clock semantics
checks to verify that events occurring at module inputs satisfy timing ■ use sampled values of their expressions
constraints of device described by module ○ immediate
● Module paths are from module input ports to output ports ■ follow simulation event semantics for execution
● Timing checks relative to module inputs (timing constraints) ■ primarily intended to use with simulation
interface​ itf; ■ test of an expression when statement is executed in
​logic​ c, q, d; procedural code
​modport​ flop(​input​ c, d, ​output​ q); ■ interpreted the same way as ​if​ statement
endinterface
● false if evaluates to X, Z, or 0 (assertion fails)
module​ dtype(itf.flop ch); ● otherwise, true (assertion passes)
​always​_ff @(​posedge​ ch.c) ch.q <= ch.d;
8.2. What is the purpose of the 'iff' element? How can it aid an assertion?
​specify ● the event expression only triggers if the expression after iff is true
(​posedge​ ch.c => (ch.q+:ch.d)) = (5,6);
● state machine will only start if it sees this condition
$setup(ch.d, ​posedge​ ch.c, 1);
​endspecify
endmodule 8.3. How is the ### used in assertions?
● A ## followed by a number or range specifies the delay from current
7.11. What is the benefit of placing a specify block in an interface instead of clock tick to beginning of sequence that follows
the design module? ● when used as a concatenation between two sequences, the delay is
● sometimes you do no want to change the design from end of first sequence to beginning of second sequence
● interface is usually simpler than the design ● in assertions, this is used to describe a sequence
● Example: the sequence is given for the specified wave
7.12. What are the uses of ‘with’ req ##2 gnt
● says which clock we’re specifying

7.13. How is the ## statement used?

● cycle delay
● delay execution by specified number of clocking events or clock cycles
##5; // wait 5 cycles
● cycle delays of ​##0
○ if clocking event has not occurred in the current time step, it 8.4. What are sequences and properties? How are they used with
suspends calling process until clocking even occurs assertions?
○ if clock vent has occurred, the process continues execution ● sequence​ feature provides the capability to build and manipulate
without suspension sequential behaviour
○ when used on RHS of synchronous drive, has no effect ○ a named ​sequence​ may be declared in
7.14. What is required for the ## statement use? ■ module ■ package
● a cycle is determined by default clocking ■ interface ■ compilation-unit scope
● clocking block can be specified as default for all cycle delay operations ■ program ■ checker
● Example: declaring a clocking as default ■ clocking block ■ generate block
program​ test(​input​ l​ ogic​ clk, ​input​ ​logic​ [15:0] data); ● properties are constructed out of sequential behaviors
​default​ ​clocking​ bus @(​posedge​ clk);
​inout​ data;
○ may involve checking of one or more sequential behavior
​endclocking beginning at various times
● Example: a sequence is used in the assert property
​initial​ ​begin sequence​ delay_ex(x, y, min, max, delay1);
## 5; x ##delay1 y[*min:max];
​if​ (bus.data == 10) endsequence
## 1;
​else // Legal
... assert​ ​property​ (@(​posedge​ clk) delay_ex(x, y, 3, $, 2));
​end
endprogram int​ z, d;
● Example: assigning an existing clocking to be default
module​ processor ... // Illegal: z and d are not elaboration-time constants
​clocking​ busA @(​posedge​ clk1); ... ​endclocking assert​ ​property​ (@(​posedge​ clk) delay ex(x, y, z, $, d));
​clocking​ busB @(​negedge​ clk2); ... ​endclocking
​module​ cpu( ​interface​ y ); 8.5. Write code to detect errors in an example.
​default​ clocking busA ;
● See Morris assertion cheat sheet
​initial​ ​begin
## 5; // use busA => (​posedge​ clk1)
... 9. Covergroups
​end 9.1. What is a covergroup? How are they used?
​endmodule
● a covergroup construct (user-defined) encapsulates the specification
endmodule
of a coverage mode
● each covergroup specification can include
8. Assertions ○ clocking event that synchronizes the sampling of coverage points
8.1. What are assertions? ○ a set of coverage points
● shorthand language for set of state machines that will check whether ○ cross coverage between coverage points
or not a condition is made ○ optional formal arguments
● an assertion specifies a behavior of the system ○ coverage options
● primarily used to validate the behaviour of a design ● like a class, a covergroup instance can be created via new()
● other functions
covergroup​ cg; … endgroup
○ provide functional coverage cg cg inst = ​new​;
○ flag input stimulus for validation
 ● Coverpoint ● Example: goto repetition followed by additional value
○ can contain one or more coverage point, covering a variable or 1 => 3 [-> 3] => 5 // 1...=>3...=>3...=>3=>5
expression ● Example: nonconsecutive repetition (transition following
○ each coverage point includes a set of bins associated with its nonconsecutive repetition may occur after any number of sample
sampled values or its value transitions points so long as repetition value does not occur again)
■ state bins = bins associated with value sets
3 [= 2] // ...=>3...=>3
■ transition bins = bins associated with value transitions
○ Example: coverage group ​g1​ with single coverage point ● Example: nonconsecutive rep. followed by additional value
associated with variable color 1 => 3 [= 2] => 6 // 1...=>3...=>3=>6
■ sampled at indicated clocking event (posedge of ​clk​) ○ if any of the sequence of value transitions of coverage pont
■ because coverage point does not explicitly define any bins, it matches any complete sequence, the coverage count of the
automatically creates three bins for each possible value of corresponding bin in incremented
enum type ● Example: the coverage for the sequence of value transitions with
enum​ {red, green, blue} color; the following sequence of sampled values:
4 5 7 11 8 12 2 2 3
covergroup​ g1 @(​posedge​ clk);
c: ​coverpoint​ color; bit ​[4:1] v_a;
endgroup
covergroup ​cg @(​posedge​ clk);
○ a coverpoint coverage point creates a hierarchical scope and can ​coverpoint ​v_a
be optionally labeled {
9.2. How is coverage of a variable specified? ​bins ​sa =(4 => 5 => 6), ([7:9],10=>11,12);
● through a ​coverpoint​ in a covergroup block ​bins ​sb[] = (4=> 5 => 6), ([7:9],10=>11,12);
​bins ​sc = (12 => 3 [-> 1]);
​bins ​allother = ​default ​sequence ;
9.3. What are coverage bins? Why are they used? }
● when a coveropint is specified, SV creates a number of bins to record endgroup
how many times each value has been seen
● these bins are basic units of measurement of functional coverage
● bins for coverage point can be automatically created by SV or
explicitly defined using ​bins​ construct
● specifying bins for values
○ allows creating bins for
■ separate bins for each value (array of bins)
● bin_name[]
■ fixed number of bins for set of values
● bin_name[fixed_num]
○ Example: associates bins to variable ​v_a
■ bin ​a​: one bin for values 0 to 63, and value 65
■ bin ​b​: set of 65 bins ​b[127]​, ​b[128]​, …, ​b[191]
■ bin ​c​: 3 bins ​c[200]​, ​c[201]​, ​c[202]
■ bin ​d​: one bin for values 1000 to 1023 (max)
■ bin ​others​: other values not in any of the above has its own
distinct bin
bit​ [9:0] v_a;
covergroup​ cg @(​posedge​ clk);

​coverpoint​ v_a
{
​bins​ a = { [0:63],65 };
​bins​ b[] = { [127:150],[148:191] }; // overlapping
​bins​ c[] = { 200,201,202 }; 9.4. What is cross coverage? How is it used?
​bins​ d = { [1000:$] }; // “$” max value of v_a ● cross coverage between two or more coverage points or variables
​bins​ others[] = default; ● specified using ​cross​ construct
} ● Example: cross coverage of two 4-bit variables (​a​ and ​b​)
endgroup
○ coverpoint is created for each variable
● specifying bins for transitions ○ each variable has 16 bins (4-bits = 0 to 15)
○ accepts a subset of sequence ○ cross of ​a​ and ​b​ has 256 cross products, thus 256 bins
○ Example: a single value transition
bit​ [3:0] a, b;
value1 => value 2 covergroup​ cov @(​posedge​ clk);
○ Example: sequence of transitions aXb : ​cross​ a, b;
endgroup
value1 => value3 => value4 => value5
○ Example: specifies the four transitions
9.5. What is the purpose of the 'iff' element in coverage?
range_list1 => range-list2
1,5 => 6,7 // (1=>6), (1=>7), (5=>6), (5=>7)
● the expression within the ​iff​ construct specifies an optional
condition that disables coverage for that ​coverpoint
○ Example: repetitions of transitions
● expressions cannot be used directly in cross; a coverage point must be
trans_item [* repeat_range]
3 [* 5] // ​3=>3=>3=>3=>3
explicitly defined first
○ Example: range of repetitions
9.6. How is the coverage checking started?
3 [* 3:5]
// (3=>3=>3), (3=>3=>3=>3), (3=>3=>3=>3=>3) ● coverage starts and ends when simulation ends
○ Example: goto repetition where any number of sample points can ● declaring covergroup doesn’t start coverage collection
occur before the first occurrence of the specified value and also ● covergroup is instantiated with ​new ​operator
between each occurance (transition must immediately follow last ● In a class, instance name not required and new operator is called on
occurrence of repetition) covergroups instead of class constructor
● see 9.1
3 [-> 4] // ...=>3...=>3...=>3...=>3
9.7. How is a covergroup used? ○ have lifetime of the call or block and are initialized on each entry
● can be defined in a package, module, program, interface, or class to the call of block
● encapsulates the following information 10.4. What can be placed in a class?
○ set of coverpoints ● everything (except modules) such as
○ cross coverage between coverpoints ○ variables
○ an event that defined when a covergroup sampled ○ functions and tasks
○ other options to configure overage object ○ covergroups
○ classes
9.8. How many items may a covergroup contain?
● no limitations 10.5. What restrictions exist on class usage?
● in order to use class object, it must be instantiated
9.9. How is the data for a covergroup saved? ● classes can only see variables they created in the scope they are in
● using​ $coverage_save ● cannot have assertions
● saves current state of coverage to tool’s cover database ● is dynamic by nature, thus not synthesizable
$coverage_save(coverage_type, "name")
10.6. Can a class be synthesized?
● if no type specified, then all types are saved into database ● No, automatic functions are not synthesizable

9.10. Where is a good place to place a covergroup? 10.7. Why are classes a good way to write reusable code?
● outside the DUT ● a class can be extended into class and inherit another class
● classes are used to model data
9.11. Provide code to detect coverage for a given situation ● Example: a packet might be an object
● see 9.1 ○ may contain command field, address, sequence number, time
stamp, and payload
9.12. Why are post processing routines used after simulation? ○ things can be done to packet such as initializing packet, set
● for processing database of covergroups which is not in simulation commands, read packet’s status, or check sequence
● coverage tools gather information during simulation and then does
post-processing into coverage report 10.8. Provide examples of a class to perform a desired function/task with
● report is used to look for coverage holes and modify existing tests or local variables.
creating new ones to fill holes
class btclass; // Binary Tree Homework
● once coverage database is formed, you can analyze coverage data, do btclass lpt;
some post-simulation procedures, or merge data after multiple btclass gpt;
simulation runs real value;

function automatic void add(input btclass nn);

10. Classes begin
10.1. What is an object? if(nn.value < value) begin
● a class defines a data type if(lpt) lpt.add(nn); else lpt=nn;
● an object is an instance of that class end else begin
● class if(gpt) gpt.add(nn); else gpt=nn;
end
○ class is a type that includes data and subroutines that operator on return;
those data end
○ class’s data are referred as ​class properties endfunction
○ subroutines are called ​methods
○ both ^^ are members of the class function automatic void printascending;
if(lpt) lpt.printascending;
○ new ​function is class constructor
$display(value);
■ defined as a nonblocking function with no return type if(gpt) gpt.printascending;
■ if an explicit user-defined new method is not provided, an return;
implicit new method is provided automatically endfunction

10.2. How are objects used? function automatic void printdescending;

if(gpt) gpt.printdescending;
1. declare a variable of that class type $display(value);
2. creating an object of that class using ​new ​function by assigning it if(lpt) lpt.printdescending;
to a variable return;
endfunction
Packet p; // declare a variable of class
Packet p = ​new​; // initialize variable to a new allocated function new(input real vl);
// object of the class Packet begin
value=vl;
lpt=null;
10.3. What is an automatic function and variable? Why are they required? gpt=null;
● automatic variable and function only exists for a limited lifetime end
● used in recursive calling endfunction
● automatic function endclass
○ functions declared in a class are always automatic
○ allocated dynamically for each function call 10.9. How is a class created in SV?
○ items cannot be accessed by hearchical references ● defined in a class block
○ the function can be invoked through hierarchical name
○ lifetime class ​class_name
● automatic variable // list of class properties and methods
endclass
○ are created the moment the program execution comes to scope
of variable
○ any variable that is declared inside a task or function without
specifying type will be considered automatic
 ● Example: accessing the members of the packet class ○ value coverage
■ monitors what values signals, and expressions take on during
class ​Packet;
​bit ​[3:0] command;
simulation
​bit ​[40:0] address; ■ toggle coverage
​integer ​status; ● monitors value changes on signal bits in design
● if 100%, means that every bit of every monitored signal
​function new​(); has changed its value from 0 to 1 and from 1 to 0
command = 4’b0;
● VCS generates metrics for total coverage of nets and
address = 41’b’0;
​endfunction registers which tells how much activity is occurring on all
elements, thus giving clear indication of how much testing
​task ​clean; is actually being performed at gate level
command = 0; ● missing transitions shows inactive elements and
address = 0; unexercised portions of design which helps you to write
​endtask
tests to address missing activity
​function integer ​current_status(); ■ FSM coverage
current_status = status; ● a Finite State Machine (FSM) is a sequential logic that
​endfunction outputs a current state and a combinational logic that
enclass outputs the next state
● FSM coverage keep tracks of states and transitions in
// instantiating the class and accessing its
// properties and methods design that occur in FSM during simulation
Packet p = ​new​;
p.command = INIT; 11.4. What is function coverage?
status = p.current_state(); ● provides information of testbench variables and signal values and
their state transition
10.10. How is a class destroyed in SV? ● functional coverage metrics is gathered during simulation runs
● garbage collection is implicit and automatic ● if assertions and covergroups are defined in design, VCS collects
coverage data and generates coverage database in simv.vdb where
10.11. Need a class be destroyed in SV? the URG generate text or HTML reports
● No, there are no destructors in SV ● database is saved in a directory will URG will know how to retrieve
● garbage collection is automatic ● to generate coverage database, perform the following in VCS
○ compile the design
10.12. Are classes used more in synthesizable code, or test benches? ○ run simulation
● testbenches since classes are not synthesizable
● classes are used to model data, whose values can be created as part of 11.5. What metrics are used to determine if the tests are robust?
the constrained random methodology
11.6. What metrics are used to determine if the design is robust?
11. Test philosophy
11.1. Why shouldn't the module designer write the tests?
● the design engineer knows how the code works and will fall into the 11.7. What is a corner case?
habit of testing their code according to this knowledge ● corner case in verification normally refers to a scenario that is very
hard to be simulated/tested
11.2. Why are tests developed from the specifications?
● want to separate the design and the tests 11.8. Why is directed random testing often preferred?
● in verification, an engineer will not be able to think of all possible
11.3. What is code coverage? scenarios/conditions to be tested and systems are usually large, hence
● measures how much the design code is exercised a directed random testing is preferred
● two types of code coverage information ● though this does not guarantee 100% cases are covered, a random
○ control-flow coverage stimulus gives more confidence
■ tracks which lines and branches have taken flow of execution
■ line coverage 11.9. Why is the separation of test cases from interface details desired in
● shows which lines of code are exercised (and which ones test development?
are not)) by testbench during simulation run
● zero execution count pin-points a line of code that has
not been exercised which could be a potential source of 11.10. How are differences in the specification resolved?
design error
● VCS generates metrics for total coverage of lines, blocks,
and branches that tell how much of code actually 11.11. Why are the test case generation typically separated from the test
executed by tests case checking?
● keeps track of
○ individual procedural statements
○ procedural statement blocks 11.12. Why is the checker not part of the monitor?
○ procedural statement block type
○ missing (implied) conditional statements
● identifies unexercised statements, giving information for 11.13. How are all tests started? From what code?
additional test to complete coverage
■ branch coverage
● analyzes how ​if​ and ​else​ statements and how ternary 11.14. Why are functions divided up in UVM/OVM?
operator (​?:​) establish branches of execution in design
● shows possible branches and if it ever occurred during
simulation 11.15. What is a monitor and checker? What functions do they perform?
■ conditional coverage
● monitors certain expressions in your code that evaluate
to true or false (not all will result in condition coverage)