CENG355-Advanced Digital Logic Design

SPRING 2020

HW 1

Question 1 : True & False and Multiple-Choice Questions

PART 1 Indicate if the below statements are T(True) or F(False)

# Statement T/F
Synthesis is the process of generating a logic circuit from schematics or
1
code written in HDL
2 A full-adder is used to add 2 bits while a half-adder is used to add 3 bits

3 In VHDL, the inputs and outputs are declared in the Entity

4 Functional Simulation and Timing Simulation refer to the same design step

5 CPLD can implement larger circuits than FPGA

6 PLA and PAL are useful to implement relatively small digital circuits

7 In FPGA chips, a five-input LUT requires 16 storage cells

8 The word Behavior is a VHDL syntax keyword

PART2
Each of the following may have only one correct answer. Indicate the correct answers. Your answer should
be clear otherwise no grade will be granted. Put your answers in the corresponding table on the next page.

1. In VHDL, the circuit functionalities:

a) must be specified in Architecture
b) must be specified in Entity
c) can be specified in both
d) none of the above

2. The propagation delay occurs due to

a) the time needed by the logic elements to generate a valid output signal
b) the signals that must propagate through wires that connect other logic elements
c) both a and b
d) none of the above

3. In VHDL, the data type that can hold 0, 1, Z, ‘-‘, L, H, and W

a) BIT
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 b) STD_LOGIC
c) SIGNAL
d) Both a and b

4. A CPLD is based on
a) PLA blocks with interconnections
b) PAL blocks with interconnections
c) LUTs with interconnections
d) None of the above

5. The following LUT realizes the

Question # Answer
1
2
3
a) 𝑓1 = 𝑥1 𝑥2 + ̅̅̅𝑥
𝑥1 2 4
b) 𝑓1 = 𝑥1 𝑥2 + 𝑥1 𝑥2 5
c) 𝑓1 = ̅̅̅
𝑥1 ̅̅̅
𝑥2 + 𝑥1 𝑥2 6
d) None of the above
7
6. A 6-input LUT requires 8
a) 16 storage cells
b) 32 storage cells
9
c) 64 storage cells
d) 128 storage cells

7. In VHDL, the following statement defines:

a) 4-bit STD_LOGIC_VECTOR X(3) is the MSB and X(0) is LSB

b) 4-bit STD_LOGIC_VECTOR X(0) is the MSB and X(3) is LSB
c) 3-bit STD_LOGIC_VECTOR X(3) is the MSB and X(0) is LSB
d) 3-bit STD_LOGIC_VECTOR X(0) is the MSB and X(3) is LSB

8. Which of the following languages can describe the hardware of logic circuits?
a) C
b) C++
c) JAVA
d) VERILOG

9. A _____________ adder has the highest complexity but is the fastest among all adders
a) Hierarchical Carry-Lookahead
b) Carry-Lookahead

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 c) Ripple-Carry
d) All of the above give the same gate delay

Question 2: Implementation of logic functions on LUTs

Consider the function 𝒇 = 𝒘𝟏 . 𝒘𝟐 . 𝒘𝟑 + ̅̅̅̅.

𝒘𝟏 ̅̅̅̅
𝒘𝟐 + ̅̅̅̅.
𝒘𝟐 ̅̅̅̅
𝒘𝟑

1. Implement f using one 3-input LUT. Show the truth table implemented inside each LUT
2. Implement f using one 4-input LUT. Show the truth table implemented inside each LUT
3. Implement 𝒇 using only five two-input LUTs. Factorize in terms of w2. Show the truth table
implemented inside each LUT.

4. Redraw this circuit using only two two-input LUTs. Show the truth table implemented inside each
LUT.

Question 3: PLDs & Gate Delay

1. Consider the below PAL. Find the logic expression of the outputs W, X and Y. Do not simplify.

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2. Consider the following circuit. Find its gate delay assuming the delay of each gate type as stated in
following table.

Gate Type Gate Delay

AND Gate 2 ∆t
Z NAND Gate ∆t
OR Gate ∆t
NOT Gate ∆t

3. Consider the below FPGA on the next page to which we connect 4 inputs A, B, C and D and 2
outputs F and G. Show on this FPGA diagram the cells values of the different LUTs and the
different connections needed to build F and G where
a. F = F1 AND F2
b. G = F1 OR F2
c. F1 = A XOR C
d. F2 = B NAND D

G F

F1

F2

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Question 4: Combinational circuits and VHDL

1. Consider the following VHDL code representing a digital circuit named mylogicfunc. Draw the
corresponding logic circuit.
LIBRARY ieee ;
USE ieee.STD_LOGIC_1164.all ;
ENTITY mylogicfunc IS
PORT ( A, B, C, D, E : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mylogicfunc;

ARCHITECTURE Behavior OF mylogicfunc IS

SIGNAL x, y : STD_LOGIC;
BEGIN
x<= (C AND D) OR NOT (E);
y<= A AND B
f<=NOT(x AND y) OR E;
END Behavior ;

2. Consider two Boolean functions F and G as below. Write the behavioral VHDL code that
implements both functions in the same entity. The entity name should be myfunctions.

𝐹 (𝐴, 𝐵, 𝐶, 𝐷) = (A + B)⨁𝐶 + (𝐴𝐵⨁𝐶𝐷)

𝐺 (𝐴, 𝐵, 𝐶, 𝐷) = ̅̅̅̅̅̅̅̅̅̅̅̅̅
A+B ̅ + D + (𝐴⨁𝐶 ) + 𝐴𝐶̅ 𝐷

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