IET Power Electronics

Research Article

Single-phase common-grounded transformer- ISSN 1755-4535

Received on 23rd March 2019
Revised 23rd September 2019
less grid-tied inverter for PV application Accepted on 10th October 2019
doi: 10.1049/iet-pel.2019.0364
www.ietdl.org

Naser Vosoughi1 , Seyed Hossein Hosseini1,2, Mehran Sabahi1

1Faculty of Electrical and Computer Engineering, University of Tabriz, 29th Bahman Blvd, Tabriz, Iran
2Engineering Faculty, Near East University, 99138 Nicosia, North Cyprus, Mersin 10, Turkey
E-mail: naser.vosoughi@yahoo.com

Abstract: In this study, a novel topology for the single-phase transformerless grid-connected inverters family is proposed. By
using the series–parallel switching conversion of the integrated switched-capacitor module in a packed unit, several merits can
be added to the proposed inverter, such as higher efficiency, boosting ability within a single-stage operation, and removing the
leakage current problem by using the common grounding technique. In this study, a peak current controller strategy is
implemented in order to generate the gate pulses of semiconductor switches. Moreover, this strategy is used to control both the
active and reactive powers. Therefore, a thoroughly controlled current with a proper quality can be supplied to the grid from a
single source renewable energy resource. The operating procedure, design consideration, comparison study, and the
experimental results for a 510 W prototype are presented in order to validate the correctness and feasibility of the proposed
topology.

1 Introduction
The use of the transformerless inverters as an interface for
renewable energy resources like photovoltaic (PV) panels in
commercial and domestic grid-connected distributed generation
(DG) systems has been increased in recent years. The main
advantages of these inverters in comparison to the transformer-
based systems are higher efficiency, proper power density, and
lower cost. However, some extra steps shall be taken in order to
meet the requirements of the grid code [1–4].
The most important parameter in supplying current to the grid is
its noisy dc offset, which should be eliminated by controlling the
leakage current. This undesirable leakage current is a consequence
of variable high frequency common-mode voltage (CMV) of the
inverter, which circulates between the neutral point of the ac grid
and the parasitic capacitor of the negative terminal of the PV array,
for which the parasitic capacitance value is around 100 nF per 1  Karschny [21] inverters are other case studies to maintain the CMV
kW [5, 6]. Consequently, a resonant path between the output
inductor-based filter and the parasitic capacitor is formed, in which
not only can decrease the quality of the supplied current to the grid,
but also makes additional power losses and might saturate the core
of the other energised distributed transformers of the ac grid.
According to VDE 0126-1-1 IEEE standard, the value of leakage
current for any type of transformerless grid-connected inverters
should not exceed 100 mA [7].
Due to the aforementioned code, many approaches have been
put forward in the literature for eliminating this leakage current.
The simplest method for overcoming the leakage current issue is to
use the bi-polar PWM strategy as well as half-bridge (HB) inverter
instead of full-bridge (FB) one [8, 9]. Here, the CMV is almost
constant; however, due to the presence of the output or filter's
inductor, the current ripple losses degrade the injected power
quality, which can violate the grid code requirements of the grid-
connected interfaces. Nevertheless, the output voltage of the HB
inverter must have complied with the grid voltage amplitude
requirement, which results in another stage to increase the input
voltage; therefore, it leads to extra costs and higher losses for the
interface system [9].
Another method for providing a constant CMV across the
parasitic capacitors can be done by implementing neutral point
clamp (NPC) or active NPC inverter [10, 11]. Here, the midpoint of
the dc source connecting to the dc-link capacitors is directly
connected to the neutral point of the grid, where the value of CMV
is almost constant with respect to the variation of time. In this case,
to improve the power quality supplied to the grid a unipolar PWM
scheme can be used; however extra DC–DC converters at the input
side are needed to increase the inverter's output voltage to a proper
level in compliance with the ac grid [10].
In order to solve the voltage level problem in grid-connected
systems, many studies have been done in recent years. The variable
high-frequency CMV in unipolar PWM method appears by
generating zero voltage level at the inverter's output voltage.
Therefore, in order to eliminate the leakage current caused by the
variable CMV, the PV module should be separated from the ac grid
during the freewheeling mode. To achieve this aim, H5 [12],
Optimised H5 [13], different family of H6 [14–16], HERIC [17,
18] and HB-ZVRB [19] have modified the FB inverter by adding
extra switches and decoupling the PV source from the grid in dc or
ac side during the freewheeling period. Paralleled buck [20] and
at the relatively constant value. Nevertheless, apart from using the
extra elements in the forward current flowing path, the operation of
such circuit architectures are not workable for a wide range of
demanded power factor and in some cases like the Karschny and
HERIC-based inverters, the reactive current injection cannot be
theoretically supported. Here, in all the above-mentioned circuits,
the leakage current problem can be mitigated but never is
suppressed. Also, meeting the grid's voltage amplitude requirement
is again a challenging issue since another dc–dc power processing
stage is required to recruit a much lower scaled PV panel at the
input side of the converter.
For preserving the system against the leakage current problem,
the use of common-grounded type inverters can have an
appropriate performance. In such types of inverters, the negative
terminal of the PV panel is directly connected to the neutral point
of the grid; therefore the overall CMV can be properly bypassed
[22]. From this viewpoint, a virtual dc link method with five active
power switches is introduced in [22]. Here, the dc link is realised
by the auxiliary capacitor. During the positive half-cycle of the
grid, this capacitor charges, whereas during the negative cycle one,
the voltage across the capacitor is converted to the inverter's output
voltage. The same approach is used in [23], where the virtual dc-
link capacitor is charged indirectly by a charge-pumped circuit and
a few excess diodes. In following three different common-
grounded circuit architectures were presented in [24], where the dc
to ac energy conversion can be obtainable through four power

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Fig. 1  Proposed grid-connected inverter topology

switches. The maximum value of the output voltage in these three

cases has complete compliance with the grid side. Therefore, there
is no need for an extra step-up stage unless a low voltage PV is
utilised. Such extra step-up stage, apart from requiring additional
passive and active power components, causes more power losses
since the platform of energy conversion cannot be possible within a
single-stage operation. Due to the use of common-grounded
approach, two different bipolar PWM-based transformerless
inverters were also introduced in [25, 26], in which by
implementing the extra inductors, a buck and a buck–boost
converter can be acquired, respectively. In [27], the bipolar buck-
based performance of the topology presented in [26] was improved
through a unipolar-based buck–boost inverter, however, with the
cost of extra elements and power losses.
In this paper, a new type of transformerless inverters is
proposed, which is classified in the common ground types. Using
the inherent boosting capability and unipolar PWM method, the
proposed structure improves the performance of the conventional
grid-tied system. In the proposed topology, by using switched-
capacitor (SC) module and also the virtual dc-link concept, a two
times boost factor can be obtained within a single-stage operation
without using any auxiliary inductors. In addition, in order to
thoroughly control the supplied current to the grid, a peak current
controller (PCC) strategy is implemented. In the proposed
structure, the supplied active and reactive powers to the grid can be
controlled with a fast and robust dynamic response. The complete
analyses of the structure in different operating modes are presented
in Section 2. The detailed explanation of the operation of the
proposed grid-tied topology under the PCC strategy is presented in
Section 3. The design consideration, current stress, and conduction
loss analyses of the semiconductor switches are analysed in Section
4. The comparison results between the proposed inverter and the
conventional ones are summarised in Section 5. Finally, in order to
validate the analyses as well as the robustness and accurate
performance of the proposed system, the experimental results of a
510 W built prototype inverter are presented in Section 6.

2 Proposed common ground type inverter

The equivalent circuit of the proposed structure is shown in Fig. 1.
In this figure, the topology consists of six semiconductor switches,
Fig. 2  Operating modes of the proposed grid-tied inverter
two diodes, two capacitors, and an inductor as a filter. Due to the
(a) In the first operating mode,
use of integrated SC module, the proposed system can boost the
(b) In the second operating mode,
output voltage of the PV during a single stage. In this operating
(c) In the third operating mode,
mode, the capacitor C2 acts a virtual dc link similar to the
(d) In the fourth operating mode
conventional methods. The negative terminal of the PV source is
directly connected to the neutral point of the grid, which provides
the common ground feature of the proposed system. The polarity of the grid voltage and the direction of the current supplied
semiconductor switches are unidirectional ones with anti-parallel to the grid, four operating modes can be defined, which are
diodes. The switching frequency of the four power switches is high depicted in Figs. 2a–d.
and the capacitors C1 and C2 will be charged in both negative and In the first operating mode (see Fig. 2a), the grid voltage is
positive and the switches S1, S3, and S4 are ON. Therefore, C1 is in
positive half-cycles of the switching period, thus, it is possible to
series with the input voltage and the inductor current rises. Hence,
use metalised polyester film capacitors or MKT capacitors instead
the output voltage will be 2 V PV and C2 is in a charging state. The
of electrolyte capacitors. These capacitors can operate under high
temperatures and have suitably high efficiency. According to the diode D2 is in forwarding bias.

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Fig. 3  Control block diagram of the proposed system
Fig. 4  Reference and inductor current waveforms with switching pulses of
switches based on the PCC technique
During the second operating mode (see Fig. 2b), the grid
voltage is still positive and the switch S4 and diode D1 are
conducting. In order to decrease the current through the inductor,
based on the volt-second balance principle, and also in order to
charge the capacitor C1, the switches S2 and S5 are turned ON. In
this operating mode, the current through the capacitor C2 is zero.
The freewheeling circuit consists only S4 and S5. In order to
generate the zero level at the output voltage, the inductor current
must be decreased, which realises the operation of the unipolar
PWM method.
When the polarity of the grid voltage becomes negative, the
third operating mode starts. In this operating mode, S2, S5, S6, and
D1 are ON (see Fig. 2c). The power is supplied to the grid through
C2, and the voltage across C1 is charged to PV voltage. The
inductor current is linearly increased in negative polarity.
In the fourth operating mode, the voltage across C2 is 2 V PV. In
this operating mode, S1, S3, S6 and D2 are ON, where S6 and D2
provide the freewheeling path. The current through inductor
decreases, while the energy stored in C1 as well as the energy from
the PV source charge into C2 (see Fig. 2d). Thus, during the
negative half-cycle of the grid voltage, the zero-level can also be
obtained.
According to the operation of the proposed inverter in a
switching period, by series–parallel conversion of SC module
switches, C1 can be charged in both half-cycles, whereas C2 is
charged from the supply in the positive half-cycle and will be
charged and discharged in the negative half-cycle. Thus, the
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voltage across C1 and C2 will be fixed on V PV and 2V PV,
respectively.
Therefore, a three-level unipolar based boosted voltage is
generated at the output terminals. According to the proposed
structure, the voltage rating of the PV panels can be half of the
conventional grid-connected inverters. Thus, there is no need to use
another boosting stage based on the inductor, which results in the
reduction of losses and costs. In order to control the supplied active
and reactive currents to the grid, the use of the PCC method on the
proposed modulation approach is introduced in the next section.
3 PCC operation of the proposed system
In this paper, a PPC-based approach is used to generate the gate
pulses of the switches in the proposed inverter in order to control
the active and reactive power flow to the grid. This control method
is shown in Fig. 3. As the input source is a PV panel, the maximum
power point tracker (MPPT) system, as well as the current
controller block, are two considered the main elements of the
proposed structure. A phase-locked loop (PLL) system is also
implemented in order to synchronise the inverter with the grid.
In this proposed system, in order to have a fast and robust
dynamic feature for the injected current, the implementation of a
filter based PLL systems such as enhanced PLL (E-PLL) [27] or
second-order generalised integrator (SOGI) [28] is recommended.
By measuring the output voltage and current of the PV panel and
applying the common perturb and observation (P&O) technique,
the maximum power of the PV source can be tracked. Then,
according to the reference values of the active and reactive power,
the required amplitude and phase angle of the reference current
(iref ) can be calculated. This reference current is considered to be
the input parameter of the current controller block, which allows
the PCC to be applied.
According to the diagram representing the current controller,
the instantaneous slope of the current through the inductor Lf ,
which is called an L-type filter, is being measured. By comparing
the reference waveform with the measured value of the inductor
current (ig), the switching patterns are formed. The related
waveforms and the resulting gate pulses of the switches are
illustrated in Fig. 4. According to this figure, the polarity of the
voltage at the grid side (vg) determines the performance of the
system. The sampling time (T SA) is set to have a specific value that
is related to the switching frequency by 1/(2 f S). During this
sampling time, the MPPT and PLL units generate the reference
current, which is to be compared with the measured grid current or
the current through the inductor. During the positive half-cycle of
the voltage waveform at the grid side, the switches S1, S3, and S4
will be turned ON if the measured current value is lower than the
generated reference current. Therefore, the current through the
inductor linearly rises. This happens in the first operating mode.
During the positive half-cycle of the voltage waveform at the grid
side for the next sampling time, the switches S2, S4, and S5 will be
turned ON if the measured current value is higher than the
generated reference current.
Therefore, the current through the inductor decreases. This
happens in the second operating mode. For the negative half-cycle
of the voltage at the grid side, a similar approach for controlling the
switching transitions will be applied. The flowchart for PCC and
the corresponding logical circuit topology for the proposed
structure is depicted in Figs. 5a and b. According to the controlling
method, the output current of the inverter that is going to be
injected into the grid can fit thoroughly over the sinusoidal
reference current. Due to the absence of any conventional
proportional–resonant (PR) or proportional–integrator (PI)
controllers in the proposed controlling approach, the supplied
current to the grid is very robust for the dynamic violations of the
voltage and frequency at the grid side. According to the
relationship between the voltage and current of an inductor in the
first and second operating modes, the following equations can be
written for the switching duty cycle and the voltage gain of the
proposed inverter:
3
 ∫
DT S TS t
∫ 0
(V out − vg)dt + ∫
DT S
( − vg) dt = 0 (1) iLf(t) =
1
Lf 0
V L(t)dt + iLf(0) (4)

vg According to (1) and the above equation, the ripple of the current
D= (2) through the inductor can be calculated as the following:
2V PV

vg (V out − vg)D
G= = 2D (3) ΔILf = (5)
V PV f sLf

where V out is the inverter output voltage. By replacing (3) into (5), we can also write

2V PV ⋅ vg − vg2
4 Design guidelines and loss analysis ΔILf = (6)
2 f s ⋅ Lf ⋅ V PV
In this section, the design considerations for selecting proper
values for the inductance of the L-type filter and the required value As the maximum value of the current ripple occurs at the instance
of the capacitors are presented. Moreover, based on the switching corresponds to the peak value of the grid voltage (V m, g), the
duty cycle of the proposed system, current stress analysis of the formulations for the value of Lf can be restated as follows:
switches as well as their power losses calculations, are given in the
following. 2
2V PV ⋅ V m, g − V m ,g
Lf = (7)
2 f s ⋅ V PV ⋅ ΔILf, max
4.1 Determination of inductor (L f )
The relationship between the voltage and current of an inductor is Considering 180 V as the fixed value of the PV voltage
formulated as the following [27]: (V PV = 180) and 220 2 as the V m, g along with regarding 25 kHz as
the switching frequency and 0.56 as the maximum current ripple
across the inductor, the value of Lf will be around 3 mH.

4.2 Determination of capacitance

During the first operating mode (see Fig. 2a), the current through a
capacitor C1 (iC1) is equal to the current of the inductor. The
relationship between the voltage and current of a capacitor is
formulated as the following equation [22]:

∫
t
1
V C1(t) = iC1(t)dt + vC1(0) (8)
C1 0

Therefore, the ripple of the voltage across C1 can be calculated as

the following:

iL ⋅ vg
ΔV C1 = (9)
2 f s ⋅ C1 ⋅ V PV

The maximum value of voltage ripple of C1 occurs when the grid

voltage and the inductor current reach their peak values. Thus, the
capacitance C1 can be written as (10). Since the discharging
process of C1 is in the positive half-cycle of the grid voltage, by
considering the average value of grid voltage and inductor current,
the accurate value of C1 can be formulated as (11)

Im, g × V m, g
C1 = (10)
2ΔV C1, max × f s × V PV

4Im, g × V m, g
C1 = (11)
2ΔV C1 × π 2 × f s × V PV

Fig. 5  switching frequency used in the proposed PCC strategy, the
(a) Applied PCC operation and the switching pulses flowchart,
Q6 (b) Logic-based diagram of switching pulses
where V m, g and Im, g are the maximum values of the grid voltage
and grid or inductor current, respectively. From the proposed
current control-based strategy and Fig. 3, it is obvious that Im, g is
related to the MPPT block and the required value of active and
reactive powers injecting to the grid. According to (10) and (11),
the same procedure and result can be obtained for the C2 being
considered in the negative half-cycle of the grid voltage. Having
considered the same parameters for the V PV and V m, g as discussed
in the inductor design guideline and taken a 3.3 A maximum
current injection to the grid with the 25 kHz as the maximum
required capacitance will be around 120 μF.

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 ton toff
∫ ∫
4.3 Current stress and loss analysis of the power switches 1 Im, gD 1 Im, gD
PS1, N , SW = f S ⋅ V dt + V dt
In this section, in order to calculate the conduction and switching 0
6 PV π 0
6 PV π
losses, the current stress is analysed. For the first step, the average f S ⋅ V PV ⋅ Im, gD(ton + toff )
value of the inductor or injected grid current at unity power factor =
6π
(PF) is formulated as the following [22]:
(22)
T
1
∫ I m, g Hence, considering (16), (17), (21), and (22), the total value of
2
IL = Im, gsin ωtdt = (12)
T 0
π conduction and switching losses of S1 within a full cycle of the grid
frequency can be expressed by (23) and (24), respectively,
By considering the same internal ON-state resistance of switches
2 2 2
(rDS1 = ⋯ = rDS6), the current through S1 in the positive half-cycle rDS1Im , gD rDS1Im , gD
PS1, Con = 2 + 2 (23)
is written as π π (1 − D)

Im, g f S ⋅ V PV ⋅ Im, gD(ton + toff )

, 0 < t ≤ DT S PS1, SW = (24)
iS1, P = π (13) 3π
0, DT S < t ≤ T S
The current of the C1 capacitor can be expressed as follows:
According to (13), the average and RMS value of current stress of
S1 in the positive half-cycle will be calculated as follows: ΔV C1
iS2 = iC1 = C1 (25)
τ1
DT S
IS1, P, ave =
1
TS ∫ 0
Im, g
π
dt =
Im, gD
π
(14) In (25), τ1 is the charging time constant of capacitor C1 and is
defined as follows:
1
DT S
∫ I m, g 2 I m, g τ1 = Req1 ⋅ C1
2
1 (15) (26)
IS1, P, rms = dt = D
TS 0
π π
Req1 is charging path resistance of the capacitor C1 and is
Therefore, according to the value of switch internal resistance, the expressed as follows:
conduction loss of S1 in the positive half-cycle is obtained as
Req1 = rDS1 + rD1 + rESR, C1 (27)
2
rDS1Im , gD
PS1, P, Con = rDS1IS2 1, P, rms = (16) In relation (27), rDS1 is the internal resistance of the switch S1, rD1
π2
is the internal resistance of the diode D1 and rESR,C1 is the
The voltage across S1 during the positive half-cycle is V PV, resistance of the capacitor C1. By placing (9) and (27) into (25), the
therefore the switching losses of S1 in this period can be formulated iC1 is expressed as follows:
as follows:
iL ⋅ vg
iC1 = (28)
ton toff 2 ⋅ f s ⋅ V PV ⋅ τ1
PS1, P, SW = f S ⋅ ∫0
1
V
Im, gD
6 PV π
dt + ∫ 0
1
V
I m, g D
6 PV π
dt
iL = Im, gsin ωt (29)
f S ⋅ V PV ⋅ Im, gD(ton + toff )
=
6π vg = V m, gsin ωt (30)
(17)
By considering (26)–(30), the current passing through C1 and S2
During the negative half-cycle of the grid voltage, the equation for are expressed as follows:
the current passing through S1 is as follows:
Im, g ⋅ V m, g ⋅ sin2ω t
0, 0 < t ≤ DT S iS2 = iC1 =
2 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1
iS1, N = DIm, g (18)
, DT S < t ≤ T S Im, g ⋅ V m, g Im, g ⋅ V m, g
(1 − D)π = − cos(2ωt)
4 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1 4 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1
Consequently, its average and RMS value in the negative half- (31)
cycle can be expressed as (19) and (20), respectively,
Since the charging time of the C1 is faster than the DTS time, so the
TS current of S2 is zero at the turning-off time and causes the zero
IS1, N , ave =
1
TS ∫ DT S
DIm, g
(1 − D)π
dt =
I m, g D
π
(19) losses of this switch at this time. Switching losses of the S2 is
calculated as follows:
1 (see (32)) . The RMS current value of the S2 is obtained as
TS
∫ DIm, g 2 D ⋅ I m, g
2
1 (20) follows:
IS1, N , rms = dt =
TS DT S π(1 − D) π 1−D (see (33)) . Therefore, the conduction losses of the S2 are
calculated from the following relation:
Similar to the positive half-cycle calculations, the conduction and
2
switching losses of S1 in the negative half-cycle can be calculated 3
I m, g ⋅ V m, g ⋅
as (21) and (22), respectively, 2 2 (34)
PCon_S2 = rDS2 ⋅ IS2, RMS = rDS2 ⋅
4 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1
2 2
rDS1Im, gD
PS1, N , Con = rDS1IS2 1, N , rms = (21)
π 2(1 − D)

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Table 1 Current stress and loss equations of the involved switches
Related Passing current in a Average RMS value of the Conduction loss in a Switching loss in a positive
switch positive half cycle value of current positive half positive half cycle half cycle
current in a cycle
positive half
cycle
Passing current in a Average RMS value of Conduction loss in the Switching loss in the
negative half cycle value of current in a negative negative half cycle negative half cycle
current in half cycle
the negative
half cycle
S2 Im, g ⋅ V m, g ⋅ sin2ω t — 3 3
2 Im, g ⋅ V m, g 1
Im, g ⋅ V m, g ⋅ Im, g ⋅ V m, g ⋅ t − sin(2ωton)
2 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1 2 2 4 ⋅ Req1 ⋅ C1 on 2ω
4 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1 rDS1 ⋅
4 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1

S3 Im, g Im, gD Im, g 2

rDS3Im , gD
f S ⋅ V PV ⋅ Im, gD(ton + tof f )
; 0 < t ≤ DT S D
π π π π2 6π
DIm, g Im, gD D ⋅ I m, g 2
rDS3Im , gD
2 f S ⋅ V PV ⋅ Im, gD(ton + toff )
; DT S < t ≤ T S
(1 − D)π π π 1−D 2
π (1 − D) 6π
S4 Im, g I m, g I m, g rDS4Im2
,g
≃0
; 0 < t ≤ TS
π π π π 2

0 0 0 0 0
S5 DIm, g Im, gD D ⋅ Im, g 2
rDS5Im , gD
2 f S ⋅ V PV ⋅ Im, gD(ton + toff )
; DT S < t ≤ T S
(1 − D)π π π 1−D 2
π (1 − D) 3π
I m, g Im, gD Im, g 2
rDS5Im , gD
f S ⋅ V PV ⋅ Im, gD(ton + toff )
; 0 < t ≤ DT S D
π π π π2 3π
S6 0 0 0 0 0
I m, g Im, g Im, g rDS6Im2
,g
≈0
; 0 < t ≤ DT S
π π π π 2

The equations of the current stress and power losses of the other
involved switches have the same principle as mentioned for S1.
Such calculations have been summarised in Table 1 for the other
involved switches.
According to the proposed PCC method, S4 and S6 are turned
ON during positive and negative half-cycles, respectively, while S1,
S2, S3, and S5 are switched in both half-cycles. Thus, the power loss
of OFF switches considered to be zero, which is accordingly stated
in Table 1. The switching frequency of S4 and S6 is equal to the grid
frequency; therefore the corresponding switching loss of them can
be neglected. Regarding Table 1 and the presented procedure for
calculating the switching and conduction losses of S1, the details of
losses for the other involved switches can be derived.
5 Comparison study
In order to highlight the advantages of the proposed topology, a
comparison is conducted between the proposed inverter and the
conventional ones. The results of this comparison are summarised
in Table 2. In this study, the comparative criteria can be expressed
as the number of active and passive components, the value of
passive elements, the number of ON-state switches at each
switching instance, the required value of input voltage for grid-
connected applications, boosting feature, output voltage type of the
inverter, the leakage current elimination capability, the maximum
average current stresses of switches and the weighted overall
system efficiency. According to Table 2, excluding the presented
structure in [27], all the mentioned topologies offer a buck-based
characteristic without any boosting ability; therefore, in order to
meet the grid's amplitude requirement, another power processing
energy conversion stage should be added to the input dc side of
such inverters. Such extra dc–dc stage affects the overall system
efficiency since the efficiency of each stage should be multiplied to

ton
PS2, SW = ∫0
f S ⋅ V DS1 ⋅ iS2 dt

ton
= ∫0
f S ⋅ V PV ⋅
Im, g ⋅ V m, g
−
Im, g ⋅ V m, g
4 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1 4 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1
cos(2ωt) dt (32)

Im, g ⋅ V m, g 1
= t − sin(2ωton)
4 ⋅ Req1 ⋅ C1 on 2ω

1
2

∫
π
1 Im, g ⋅ V m, g ⋅ sin2ω t 2

IS2, RMS = dωt

π 0
2 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1
1

∫
π
Im, g ⋅ V m, g 1 2
2
= 1 − 2cos(2ωt) + cos (2ωt) dωt (33)
2 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1 4π 0

3
Im, g ⋅ V m, g ⋅
2
=
4 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1
6 IET Power Electron.
© The Institution of Engineering and Technology 2019
Table 2 Comparative study
Type of Total no. No. of on Output filter Vin, Boosting Type of Leakage Max. Overallb
converter components state V feature PWM current average system
S D Ca L switches Lf1 Lf2 Cf current efficiency %
stresses of
switches
H5 5 0 1 0 3 3 mH 3 mH 0.47 μF 400 no unipolar 89 mA 0.32 × Im, g 0.95 × 0.985
= 93.5%
common- 7 2 3 1 3 2.8 mH — — 400 no unipolar 10 mA 0.16 × Im, g 95.31%
ground-type [4]
NPC [10] 6 0 2 2 4 4 mH — 2 μF 100 yes unipolar NA 0.34 × Im, g 96.33%
OH5 [13] 6 0 2 0 3 4 mH 4 mH 6.6 μF 400 no unipolar 44 mA 0.32 × Im, g 0.95 × 0.972
= 92.3%
H6 [14, 15] 6 2 2 0 3 3 mH 3 mH 0.47 μF 400 no unipolar 45 mA 0.32 × Im, g 0.95 × 0.974
= 92.5%
HERIC 6 2 1 0 2 3 mH 3 mH 2.2 μF 400 no unipolar 84 mA 0.16 × Im, g 0.95 × 0.97
= 92.1%
ActiveNPC [11] 6 0 2 0 2 NA NA NA 800 no unipolar NA 0.32 × Im, g 0.95 × 0.973
= 92.4%
Modified H6 7 0 2 0 3 3 mH 3 mH 6 μF 400 no unipolar 9 mA 0.32 × Im, g 0.95 × 0.97
[16] = 92.18%
HB-ZVR [19] 5 5 2 0 2 1.8 mH 1.8 mH 2 μF 400 no unipolar 27 mA 0.16 × Im, g 0.95 × 0.948
= %90.13
non common- 4 4 1 - 2 3 mH 3 mH 3.3 μF 400 no unipolar NA 0.32 × Im, g 0.95 × 0.987
ground-type = 93.76%
[20]
Karschny [21] 5 2 1 1 3 NA NA NA 400 no unipolar < 5 mA 0.33 × Im, g NA
virtual DC bus 5 0 2 0 2 8 mH 0.8 mH 0.34 μF 400 no unipolar ≃0 0.32 × Im, g 0.95 × 0.95
type [22] = 90.25%
common- 4 2 2 0 2 4 mH 2 mH 2.2 μF 400 no unipolar ≃0 0.32 × Im, g 0.95 × 0.975
ground-type = 92.62%
[23]
common-ground-type [24]
 type I 4 1 2 0 2 3 mH — 2.2 μF 400 no unipolar ≃0 0.32 × Im, g 0.95 × 0.992
= 94.24%
 type II 4 1 2 0 2 3.5 mH — 2.2 μF 400 no unipolar ≃0 0.32 × Im, g 0.95 × 0.992
= 94.28%
 type III 4 0 2 0 1 3 mH — 10 μF 400 no unipolar ≃0 0.16 × Im, g 0.95 × 0.978
= 92.91%
common- 2 0 2 1 1 1 mH 1 mH 2.2 μF 400 no bipolar ≃0 0.34 × Im, g 0.95 × 0.96
ground-type = %91.2
[26]
common- 5 0 2 1 2 3.5 mH — 3.3 μF 100 yes unipolar ≃0 0.34 × Im, g 92.50%
ground-type
[27]
NIIFBC [29] 6 4 2 - 4 3 mH 3 mH 2 μF 400 no unipolar 7.6 mA 0.32 × Im, g 0.95 × 0.977
= 92.81%
proposed 6 1 3 0 2 or 3 3 mH — — 200 yes unipolar ≃0 0.32 × Im, g 98.1%
Where Vin = input voltage (for 220 V grid voltage), S = switch, D = diode, C = capacitor, L = inductor, NA = not available in the publication,
aIncluding the input capacitor.
bIt shows the total system efficiency with the front-end boost stage dc-dc converter.

each other as mentioned in Table 2. Herein, it is assumed that the
weighted efficiency of the dc–dc stage for boosting the value of the
input voltage is to be 95%. Regarding these descriptions, the
required source for the active NPC structure presented in [11]
exceeds 750 V and the one required for the structure presented in
the other references is 400 V. The common-grounded type inverters
presented in [22–27] can eliminate the undesired leakage current,
while the other ones can only reduce this current. If the grid
demands reactive power supplied by the inverter, the value of the
leakage current will be high due to some restrictions posed by the
modulation, although the HERIC and Karschny topologies
basically are not able to pass the reverse current as for the reactive
power support operation.
In following, in order to reflect the performance of the proposed
topology over the others from current stress viewpoint and
regarding Table 1, an average value over a full cycle of the grid's
frequency for the switching duty cycle has been considered as (35)
which is derived on the basis of (2). Hereby, it is assumed to
modulate all the involved switches of other mentioned structures
by the use of the proposed PCC-based technique. Having taken the
same parameters like the same type of switches and the same value
of the local grid voltage and considered 25 kHz switching
frequency used in the proposed PCC technique, the average value
of the switching duty cycle will be around 0.55. As it is shown in
Table 2, the proposed topology possesses a suitable condition from
the maximum average value of the current stress on the switches

IET Power Electron. 7

© The Institution of Engineering and Technology 2019
Table 3 List of used components and required descriptions
of an experimental prototype
Element Type Description
S1, S2, S3, S4, S5 and S6 47N60C 650 V/47A
gate driver TLP 250 IC
power diode RURP3060 600 V/30 A
current transducer LA55P hall effect
microcontroller beagle bone black ARM
local grid's frequency 50 Hz —
sampling frequency 50 kHz —
C1 and C2 MKT 6 × 20 μF
magnetising inductor ferrite core 3 mH

Fig. 7 
(a) Voltage across C1 (100 V/div),
(b) Voltage across C2 (200 V/div)

case, although the number of active switches of [27] is lower than

the proposed topology, its weighted efficiency is much lower than
the proposed one since it has used the capability of the inductor to
convert the energy in both half cycle.

Fig. 6  Obtained experimental results
(a) Inverter output voltage waveforms (200 V/div) and the injected current (4 A/div),
(b) Inverter output voltage waveforms (200 V/div) and the local grids voltage (200 V/
div),
(c) Reference current (up-side) (4 A/div) and the injected current (down-side) (4 A/
div) waveforms
aspect. Here, the maximum value of the average current stress
among different involved switches has been considered.
V m, g 1
Davg = × (35)
V PV π
According to this table, the proposed structure, which consists of
six semiconductor switches and a reduced number of passive
elements, has the capability to eliminate the leakage current, while
it possesses two times boosting feature. Due to the step-up
capability of the proposed structure, the required dc power source
or the PV panel value is 200 V, which results in lower costs, power
losses, and system size. Moreover, the conduction loss of the
proposed structure is quite compatible with the other conventional
topologies, since the number of conducting switches in the first
three operating modes and in the fourth one is two or three. The
structures presented in [26, 27] have fewer switches, however,
some extra passive elements are added to their topologies. In this
6 Experimental results
In order to revalidate the analyses and proper operation of the
proposed inverter, the experimental results of a 510 W built
prototype inverter are presented in this section. Regarding the
control block diagram of the proposed system shown in Fig. 3 and
considering the proposed PCC procedure implied in Fig. 4, the dc
voltage source has been assumed to be fixed at 180 V. In this case,
the details of the MPPT process of the proposed system are beyond
the scope of the paper, a PV simulator as the dc source and the
Beagle Bone Black (Texas instrument) as the microprocessor have
been used to implement the proposed PCC method. The circuit
elements used in the prototype inverter and their description are
summarised in Table 3. Here the peak and frequency of the local
grid's voltage are respectively 311 V and 50 Hz.
As explained in Fig. 3, a hardware-based PLL procedure has
been used to detect the zero-crossing point of the local grid
voltage. Such detection is used to find out the phase of the
reference current used in the proposed PCC. Considering such PLL
and 3.3 A as the amplitude obtained by the PV simulator, a proper
reference current is made. Such a peak value of the reference
current has been obtained by the P&O MPPT technique, like what
has been using in the conventional approach.
Regarding the working principle of the proposed topology
Fig. 6a shows the inverter output voltage with the peak of the 360 
V besides the injected grid current waveform with the peak value
of 3.3 A. As it is clear, through a 180 V input dc voltage, a two
times voltage boosting feature has been obtained which results in
360 V as the peak voltage value of the proposed inverter. The
unipolar boosted three-level output voltage of the proposed inverter
and the local grid's voltage have also been depicted in Fig. 6b,
while the reference current and the injected grid current waveform
generated by the proposed current-controlled technique have been
shown in Fig. 6c. Considering such taken results, the realisation of
the PCC method and fine tracking capability of the proposed
method can be confirmed. Here, the total harmonic distortion of the
current supplied to the grid is <2.1%.
Additionally, the balanced voltage waveforms across C1 and C2
as well as the injected current are presented in Figs. 7a and b,
respectively. According to Fig. 7, the voltages across C1 and C2
have satisfactory ripples through the explained self-voltage
balancing and they could be fixed at 180 and 360 V, respectively.

8 IET Power Electron.

© The Institution of Engineering and Technology 2019
Fig. 8  Efficiency curve of the proposed inverter for different output powers

Table 4 Details of switching and conduction losses of different involved power switches and diodes in the proposed topology
Pout, W S1 S2 S3 S4 S5 S6 D1 D2 Tot. loss, W
PCon
P 100 0.0014 0.0724 0.0014 0.0026 0.0017 0 0.091 0 0.773
N 0.0017 0.0017 0 0.0014 0.0026 0.0908 0.1838
PSw
P 0.015 0.1378 0.015 0 0.031 0 0.0101 0
N 0.015 0.015 0 0.031 0 0.0101 0.0405
Tot., W 0.0331 0.2102 0.0331 0.0026 0.0651 0.0026 0.202 0.2243
PCon
P 300 0.0127 0.6522 0.0127 0.023 0.0155 0 0.2786 0 2.869
N 0.0155 0.0155 0 0.0127 0.023 0.2771 0.5739
PSw
P 0.0451 0.4134 0.0451 0 0.0902 0 0.0304 0
N 0.0451 0.0451 0 0.0902 0 0.0304 0.1216
Tot., W 0.1184 1.0656 0.1184 0.023 0.2086 0.023 0.6165 0.6955
PCon
P 500 0.0351 1.8118 0.0351 0.0639 0.043 0 0.4736 0 5.7053
N 0.043 0.043 0 0.0351 0.0639 0.4694 0.9936
PSw
P 0.0752 0.6891 0.0752 0 0.1504 0 0.0507 0
N 0.0752 0.0752 0 0.1504 0 0.0507 0.2027
Tot., W 0.2285 2.5009 0.2285 0.0639 0.3789 0.0639 1.0444 1.1963
PCon
P 700 0.0689 3.5512 0.0689 0.1252 0.0842 0 0.676 0 9.2795
N 0.0842 0.0842 0 0.0689 0.1252 0.6677 1.4431
PSw
P 0.1052 0.9647 0.1052 0 0.2104 0 0.0709 0
N 0.1052 0.1052 0 0.2104 0 0.0709 0.2837
Tot., W 0.3635 4.5159 0.3635 0.1252 0.5739 0.1252 1.4855 1.7268
In order to calculate the losses in this table, the following values are used: P = positive half cycle, N = negative half cycle, PCon  = conduction loss, PSw  = switching loss.

By measuring the input and output powers, the efficiency of the vg V m, gsin(ω t)
D= = ⇒ Dave = 0.55 (37)
proposed structure is captured, which is around 98%. Fig. 8 shows 2V PV 2V PV
the efficiency curve of the proposed inverter for different output
powers. rDS = 0.061 Ω , ton, S = 35 ns , toff , S = 143 ns (38)
As it is obvious, the proposed topology with its PCC technique
possesses around 98.1% as the overall efficiency for a wide range rD = 0.033 Ω , V γ = 0.8 V, ton, D = 60 ns, toff , D = 60 ns (39)
of output power. Herein, to consider the details of switching and
conduction losses of different power switches and diodes used in
where the maximum value of the grid current to the grid and the
the proposed structure. Table 4 can be taken into account.
maximum grid voltage are expressed by (36), while considering
Regarding the internal resistance of the power switches and diodes
(2), the average value of the switching duty cycle is denoted by
derived from datasheet thereof and considering the procedure
(37). Also, the information about the internal resistance of the
presented for switching and conduction loss calculation in Section
switches and diodes are also shown in (38) and (39), respectively.
4.3 and Table 1, the details of losses for different active and passive
In this case, regarding (31), the maximum value of the current
devices can be realised here. In this case, the following parameters
passing through the S2 which occurs at ω t = π/2 can be
have been used for a proper loss calculation:
expressed by the following equation: (see (40)) .
2Pout To confirm this derived value for the current stress of S2, Fig. 9
I m, g = , V m, g = 220 2 (36) can be considered. As shown here, the peak current of this switch
V m, g
is about 8.8 A, which is accorded by the relation expressed as (40).
From Table 4, it is also found that the highest value of total
power losses for different value of output power belongs to S2,
IET Power Electron. 9
© The Institution of Engineering and Technology 2019
 Im, g ⋅ V m, g
IS2, max =
2. f s ⋅ V PV ⋅ Req1 ⋅ C1
(40)
3.2 × 220 2
= = 8.8 A
2 × 25 × 103 × 180 × (0.061 + 0.033 + 0.01) × 120 × 10−6

Fig. 9  Current stress of S2 (4 A/div)

Fig. 10  Grids voltage (100 V/div) and the injected current (5 A/div)
waveforms under
(a) Leading PF,
(b) Lagging PF

while two low-frequency switches (S4 and S6) possess the minimal
ones.
To confirm the accurate performance of the proposed controlled
system under the non-unity PF value, the voltage and current of the
grid for leading and lagging power factors are shown in Figs. 10a
and b. According to the experimental results, the output current of
the proposed structure controlled by the PCC method generates a
sinusoidal waveform for any needed PF.
In the following of the dynamic results clarification, the overall
performance of the proposed inverter under the input power
changes can be observed in Fig. 11. In this case, since the
performance of the MPPT block may affect the dynamic result of
the proposed current-controlled technique, so the MPPT block has
been excluded, and only the peak value of reference current
changes has been applied. Regarding this, once the input voltage
possesses an upward trend, the input power will be increased. So,
through increasing the range of input voltage, the active power has
changed from 510 to 620 W. Therefore, the injected current to the
grid has changed from a peak value of 3.2 to 4 A, as shown in
Fig. 11a. Figs. 11b and c also show the capacitors voltage
variations along with the variations in the injected current to the
grid. It can be seen that when the output power is increased, the
voltage of the capacitor is slightly increased. Fig. 11d also shows
the output voltage of the inverter along with the injected current to
the grid. As can be concluded from these results, the performance
of the control system and the inverter are desirable in response to
the power changes.
Fig. 11  Experimental results of the proposed topology in a dynamic state
(a) Grid voltage(100 V/div) and the injected current to the grid (5 A/div),
(b) Voltage of capacitor C1 (100 V/div) and the injected current to the grid (5 A/div),
(c) Voltage of capacitor C2 (200 V/div) and the injected current to the grid (5 A/div),
(d) Output voltage of inverter (400 V/div) and the injected current to the grid (5 A/div)
7 Conclusion
A new topology of single-phase grid-tied inverters was proposed in
this paper. In the proposed structure, in order to provide a boost
feature, the SC technique was used as well as the provision of the
common ground feature. The capacitors used in the SC module of
the proposed inverter are balanced by series–parallel switching
conversion and can handle the power-boosting single-stage process
in the positive and negative half-cycle of the grid frequency.
According to the introduced PCC method, by using a small-sized
inductor-based filter the injected current can be thoroughly
controlled for any desired value of power factor. The leakage
current issue is solved by common grounding the neutral point the
grid and the negative terminal of the PV panel. In this paper, the
design considerations for the proposed structure were presented as
well as the power loss analyses for the switches. Moreover, in
order to highlight the advantages and disadvantages of the

10 IET Power Electron.

© The Institution of Engineering and Technology 2019
 proposed structure, it was compared with the conventional grid-tied
topologies. Finally, the correctness of the analyses was revalidated
by the experimental results.
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11
IET-PEL20190364
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Q2 Please check your references thoroughly as we have updated them according to Crossref, and not all information may be correct.
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