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Communication System Design for Super-Wifi

(802.11af)
A Hardware platform to utilize TVWS using Wi-Fi Radio

Asif Ahmad A S, Bharat Keshavamurthy, Abhay Narasimha K S, Mahesh N, Suma M N


Electronics and Communication Engineering
BMS College of Engineering
Bengaluru, India
{asif949, bharathkeshavamurthy.811, abhaynarasimha1, mahilion01}@gmail.com, suma.ece@bmsce.ac.in

Abstract— “4.4 billion people around the globe still aren’t considerably, the Internet will be more accessible than ever to
connected to the Internet!” There is a tremendous technological the common man in India.
gap between the country‘s urban and rural areas. While, people
in the metropolitan areas enjoy seamless connectivity, people in Reach: The second most powerful argument in favor of
the villages and suburbs lack basic infrastructure to facilitate TVWS deployment in India is the reach. Wireless broadband
fundamental connectivity. A key to this is to use long-range provided over the TV White Space spectrum (UHF band) has
broadband service to utilize TVWS to provide Wi-Fi in long better propagation characteristics and hence will travel long
range distant communications. A key to design hardware distances, through solid objects and foliage. The proposed
effectively is described in this paper. The Hardware discussed TVWS systems can be employed in these
consists of UHF translator to down convert 2.4 GHz Wi-Fi band scenarios/environments aimed at providing cost-effective
to the appropriate unused TV Band in the UHF spectrum. We Internet access to the nation‘s off-the-grid villages through
operate in the UHF Band-IV which extends from 470-582 MHz remote deployment.
and comprises 14 channels. In the first section a brief description
of the project is described. In the second, the UHF translator
design is outlined. In the third section, the Raised Cosine Filter II. BLOCK DIAGRAM AND HARDWARE DESCRIPTION
and the roll of factor is described which contributes to the
efficiency to validate our design compliance with IEEE 802.11af
standards. In the fourth section, the UHF translator ADRF 6655
is described and in the further sections the drive to TVWS is
described.

Keywords—TVWS; UHF translator, raised cosine filter;


dynamic spectrum allocation; ADRF 6655; frequency phase
detector;

I. INTRODUCTION
White Spaces are portions of licensed spectrum for which
licensees do not use them all the time. The UHF TV spectrum
in India (Our Band of Interest: 470-582MHz) has incredible
scope for cheap, long-range connectivity because of its lower Fig. 1 Block Diagram for Hardware Setup
frequency and hence better penetration and range compared to
the other unlicensed services operating in the ISM (2.4GHz
band) and the UNII (5GHz band) are provided. Recent studies A. UHF Scanner
performed by CARE at IIT-Delhi suggest that nearly 85% of From Fig.1, to scan the TV band of 470-582MHz we
the TV band in the 470-698MHz range are not used in urban employ a commercially available spectrum analyzer and its
Delhi while almost 95% of the TV band is not utilized in the related software. The spectrum analyzer would be set to scan
rural areas surrounding the NCR (National Capital Region). the spectrum in between the 470-582MHz range and beyond
These statistics clearly suggest a tremendous scope for a primary focus on the power-levels in each band. The spectrum
system that facilitates the use of these TV White Spaces to is repeatedly scanned for a certain period within our campus
provide affordable rural connectivity. The usage here is limited (BMSCE, Bangalore) to establish a Geo-Location Data Base.
to UHF Band-IV extending from 470-582 MHz comprising of The spectrum analyzer will be equipped with automation
14 channels. algorithms to scan the desired range of 470-582MHz consisting
of 14 channels of 8MHz bandwidth. The spectrum will be
Affordability: Connectivity to India‘s 1.2 billion population scanned from 470MHz in bands of 20MHz (steps). Each band
is a herculean task. By bringing down the affordability of data is scanned 20-30 times after which the tool shifts to the next
20MHz band. After scanning, graphs are plotted denoting the amplified and filtered. Then the signal is passed to mixer
frequency band and its associated power levels to analyze the which has multiplier, oscillator and specific filter. Then the
under-utilized or free bands in the frequency range which is of signal is sent for bandwidth compression.
interest to our project, as seen in Fig.2.
III. UHF TRANSLATOR

Fig. 3 Internals of UHF Translator

The Wi-Fi signal is received by the antenna as shown in


Fig. 3. The mixer has a signal multiplier, oscillator and a filter.
Fig. 2 The snapshot of UHF spectrum (470 – 582MHz) in Spectrum
The frequency of oscillator is set to 4885 MHz (473 MHz +
analyser 1939 MHz = 4885 MHZ). The filter will have Fc = 473 MHz
The signal at 473 MHz will have a Bandwidth of 20 MHZ.
B. Wi-Fi Device this signal has to be converted to a signal of 5 MHz
bandwidth. Therefore Bandwidth Compressor is used. It
contains Raised-Cosine filters. The resulting is a signal at 473
According to [2], research specifies that ―the peak signal MHz with bandwidth of 5 MHz. When the licensed signal is
across +/- 11 MHz of the Wi-Fi signal to be attenuated by 30 occupied at 473 MHz, the carrier frequency is changed to 478
dB from the centre frequency. If this signal is transmitted MHz, this is achieved by changing the frequency of oscillator
without modifications on the TV band, where a channel width to 1933 MHz and this continues till a free channel is found.
is 6 MHz (in the US), and the transmission will interfere with Thus Dynamic Spectrum Allocation (DSA) is used to allocate
TV signals in the neighboring bands. The design has several the next available unused spectrum to TVWS. The DSA is
advantages. Firstly, we do not require any changes to the Wi- through by p-persistent Carrier Sense Multiple Access
Fi radio. Secondly, our system is sensitive to changes in the (CSMA) as shown in Fig. 4.
TV bands. When there is a transmission in the TV band by a
licensed operator, our scanner routines detect this
transmission, and shift the signals from the Wi-Fi radio to a
different TV band. Through this system we show that it is
possible to perform opportunistic data communication in the
TV white spaces without interfering with a TV receiver.

TABLE I. WI-FI MODULE SPECIFICATIONS


Specifications Wi-Fi Module
Sl. no
Unit Value
1 TX Power 18.000dBm at 1DSSS

2 RX Sensitivity -95.7dBm at 1DSSS

3 802.11 b/g/n Radio

4 ARM Cortex M4 4 DMA’s, 80 MHz.


Fig. 4 p-persistent CSMA
5 Ambient Temperature Range: –40°C to 85°C
The following system (UHF Scanner) waits for a
C. UHF Translator predefined timeslot even if the channel is free before
transmitting. This helps in establishing a collision free
environment with other licensed signals in the same spectrum.
The UHF Translator converts the Wi-Fi 2.4 GHz signals to Thus this avoids violation of the TRAI rules and regulations for
the appropriate TV band and vice-versa. In other words, the interference of spectrum bandwidths.
UHF translator converts the S-band 2.4 GHz Wi-Fi signals
from the Wi-Fi radio to the UHF TVWS band (470-585MHz)
and the UHF TVWS band back to the 2.4GHz ISM Wi-Fi
signal band. The Wi-Fi signal received by the antenna is
A

  1
H ( )   A (1 cos( )) 
rc rc
2
0
 (1)
sin   1  r    4r cos    1  r  
   0
 
H Tc
i
 1  4r 2
 
(2)

According to (2) and Fig. 5, the impulse response of the


Raised Cosine Filter (RCF) consists of unity gain at low
frequencies, a raised cosine at zero frequencies and is
attenuated at high frequencies.
The reason for using a raised cosine filter is that it rolls off
very quickly as opposed to raised cosine filter as shown in the
(6),(7),(8). The  chosen in our case is 0.2. The roll off Fig. 5 Raised Cosine Filter (RRC) Impulse Response
determines the factor necessary to reduce Inter Symbol 
 1 
Interference (ISI). h (t )   (1    4 ), t  0
 TS
 
A pulse of duration  requires twice its Bandwidth, 2  for (6),(7),(8)
reliable transmission. For a bandlimited system, the data rate 
  2  2  T
can be increased if there is an increase in the number of pulses h(t )   (1  ) sin( )  (1  ) cos( ), t   s
 4  4 4
transmitted per second. The symbol duration of the signal   2TS

1 sin[
t t t
(1   )]  4  cos[ (1   )]
 1 Ts Ts Ts
has to be decreased, indicates an increase in the frequency  . h(t )  
t t 2
, otherwise
This means an increase in Bandwidth, overlapping with the  Ts  [1  (4  ) ]
neighboring channels leading to a condition called as Inter Ts Ts
Symbol Interference (ISI).
Therefore, to reduce ISI, the minimum bandwidth (BW)
S
needed to transmit B symbols per second is,
S
BW  B
2 Hz. (3)

For zero ISI,


p  t   1, t  0
(4)
p (t )  0, t  Tb , 2Tb , 3Tb .....  nTb (5) Fig. 6 UHF TV Spectrum signals in TV Band output from UHF translator

1. The pulse p (t ) should be one at sampling instant zero (4)


2. The pulse should be zero for all other integral multiples for
bit period
Tb (5)
From (4), (5), a RRC filter impulse response is found out
with better roll off factor  =0.2 with a BW=5 MHz. An RCF
satisfies both these conditions for providing zero ISI. This
ensures undisturbed transmission of pulses in the channel. Fig. 7 Raised Cosine Filter frequency response

TABLE II. MULTI SOURCE PROPERTIES: 13 CHANNELS ROW SAMPLE


SIGNALS
Centre Frequency 2412 MHz
Bandwidth 20 MHz
Power -50 dBm for better IP3 performance at the rate of high current. The
mixer gives an input IP3 exceeding 25 dBm with 12 dB single
No of carriers 13 sideband under practical conditions. The IP3 could be boosted
Carrier Offset 5 MHz to 29 dBm with roughly 20 mA of additional current. The
mixer provides a conversion gain of 6 dB with a 200 Ω IF
TABLE III. FILTER PROPERTIES I
output impedance. The IF output can be externally matched to
support up conversion over a limited frequency range.
Insertion Loss 2.2 dB
Order (N) 7
The device is programmed by a 3-wire SPI. The eight
F low 2402 MHz programmable units of registers, each with 24 bits, which
F high 2422 MHz controls the operation of ADRF 6655. The device is
programmed by a 3-wire SPI. The eight programmable units
Apass 0.01 dB of registers, each with 24 bits, which controls the operation of
Amax ADRF 6655.To ensure power-up of the chip, it is important to
100 dB
reset the PLL circuitry after the supply rail (VCC1, VCCLO
Type 1 and VCC2 , VCCV2I, VCCMIX) has settled 5 V ± 0.26V.
The power of the signal is about - 90dBm. The signal is
filtered using a Chebyshev filter. F low = 2402 MHz, F high =
2422 MHz and Fc = 2412 MHz (BW = 20 MHz). Next the Resetting the PLL ensures the internal bias cells to be
signal is passed onto a mixer. properly configured even under poor start-up conditions. To
ensure that PLL is reset after power-up, the PLEN bit (DB6) in
TABLE IV. FILTER PROPERTIES II REG 5 should be programmed to disable the PLL (PLEN = 0).
After a delay of >100 ms, REG 5 should be programmed to
Gain 35 dB enable the PLL (PLEN = 1). The registers should be
Noise Factor 2.5 programmed as shown in Fig.8
The following tables indicate the characteristics of the
signal and the Chebyshev’s Filter. The integer divide ratio is used to set the integer value in
the INTEGER, FRACTIONAL, and ABSOLUTE parameters
IV. ADRF 6655 AND ITS OPERATION make it possible to output frequencies that are spaced by
fractions of the PFD frequency. The VCO frequency (FVCO)
is calculated by (9),

FRAC
f vco  2  f PFD  ( INT  ( ))
MOD (9)

f vco : Output frequency of the internal Voltage Controlled


Oscillator (VCO)
Fig. 8 ADRF 6655 Functional Internal Block Diagram

f PFD : The frequency of operation of the phase-frequency


detector. INT is integer divide ratio value (24 to 119 in FRAC
mode). MOD is the preset fractional modulus (1 to 2047).
ADRF6655 as in Fig.7 is a high dynamic active mixer with FRAC is the fractional divider ratio value (0 to MOD − 1).
dual PLL and VCO. The synthesizer makes use of a
programmable integer-N or fractional-N PLL to generate a LO
input to the mixer. The PLL reference input being 20 MHz is
divided or multiplied by and then given to the PLL phase
detector. The PLL supports input reference frequency from 10
MHz to 160 MHz. The phase detector output controls a charge
pump output of which is integrated in an off-chip loop filter.
The loop filter output is then transmitted to an integrated
VCO. The output 2 × fLO of VCO is then given to a local
oscillator (LO) divider as well as to a programmable PLL
divider. The broadband, mixer uses a bias adjustment to allow
V. INTERRUPT DRIVEN APPROACH

Real time designs require an extra interrupt driven


approach simply because many systems will have a number of
inputs that will at times require better processing. Inputs from
these devices are generally asynchronous to the process and
the task currently executing, so you cannot always predict
when the event will occur. Using these interrupts enables to
continue processing until an event admits, during which the
processor can address the event. The interrupt driven approach
enables a faster response to events than a polled one, in which
a program actively samples the status of an external device in
a synchronous manner.
Fig. 9 Register R0 for Integer Divide Control

Divide mode determines the switch between fractional As processors get more advanced, there is a large number
mode and integer mode. In integer mode, the RF VCO output of sources interrupts can come from. The Zynq FPGA
frequency (fVCO) is calculated by (10), architectures a Generic Interrupt Controller (GIC), as shown in
Fig. 11, to process interrupts. The GIC handles interrupts from
the following:
f vco  2  f PFD  ( INT ) (10)
Software-generated interrupt – There are 16 interrupts for
each processor. They can interrupt one or both of the Zynq
R5 [2:0] is set to 101, the LO path, mixer REG as in Fig 9. SoC‘s ARM® Cortex™-A9 processor cores.

The LO output driver is to be enabled to allow the user to Shared peripheral interrupts – 60 in total, these interrupt
review the performance of the internal applied LO through the come from the I/O peripherals, and from the programmable
input LOP and output LON local oscillator pins. The LO logic (PL) side of the device. They are shared between the two
input/output control allows them to disconnect the internal LO CPUs of Zynq SoC.
signal and apply an external LO signal to the input and output
local oscillator input/output pins. A divide-by-2 or divide-by-3
prescaler can be selected to divide the frequency of the Private peripheral interrupts – The five interrupts in this
external or internal applied oscillator signal just before the category are private to each CPU for such as CPU timer,
mixer. When using an external frequency, and the stable watchdog timer and dedicated PL-to-CPU interrupt. The
oscillator signal to commutate mixer core, it is possible to shut shared peripheral interrupts are very interesting and flexible.
down the PLL circuitry through the PLL enable address (DB6) They can be routed to CPU from the I/O peripherals (44
of REG 5. The internal mixer can be disabled using the mixer interrupts in total) and from the FPGA PL (16 interrupts).
bias enable address (DB7) of REG 5. REG 5 also provides However, it is possible to route interrupts from the I/O
access to the CDAC Distortion Compensation Setting peripherals to the programmable logic of the device.
(DB11:DB8). CDAC control can allow to optimize internal
linear circuit to enhance IP3 performance for high frequency
RF input signals.

Fig. 11 The Generic Interrupt Controller is circled in Red

Fig. 10 REG 5 FOR LO Path and Mixer Control Register


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