Department: Electronic Engineering

Assignment 3 – Complex Engineering Problems

EE—423 Embedded System Design and Application, Spring 2020

Announced Date: 28-03-20 Due Date: 5-04-20 Total Marks = 5 Marks

Marks Obtained = __________
Teacher Name: Engr. Shiraz Afzal
CLO_3: (Cognitive Level C6 (Creating), PLO_3: Design and development of solution.

Complex Engineering Problem

Sr. Course Learning Blooms PLOs Knowledge Complex Problem Solving
No Outcomes in CEP Taxonomy Profile

Design an WP1
CLO_ embedded system C6 (Creating) PLO3 WK5 (Depth of Knowledge
3 based solution for the (WA3) Engineering required)
engineering problem. Design and Design WP3
developmen (Depth of Analysis required)
t of Solution WP7
(Interdependence)

Q# 01

Consider a vending machine used to sell coffee cup that costs 2$ each. Design an engineering solution
using a state machine that determines when to dispense a cup and how to return the change. Students are
required to choose 3 types of coins by themselves at first.
Note: in this design student should ignore the capacity of the stock, which means that there are always be
sufficient number of cups and all ingredient of the coffee in the vending machine. Also, assume that only
one action could be made in every clock cycle or state.

RULES:
first give back the change then dispense the coffee cup

Submit the solution (with tips and tricks) and design in the form of report (5-8) pages that must include

1. Introduction
2. Literature review (FSM based vending machine design controller)
3. State diagram
4. VHDL code
5. Result

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 Department: Electronic Engineering
Complex Engineering Problem/Activity:

Complex Engineering Problem Details Included: Yes

Nature and details of Complex Engineering Problem (CEP): It
will be given in Assignment # 03.

CEP will be based on CLO 3 “Design an embedded system

based solution for the engineering problem.”. To solve the
problem, students have to use in-depth knowledge related to
the following concepts: Finite state machine, moore machine
FSM, mealy machine FSM, state diagram and VHDL
language

Attributes could be: WP1, WP3, WP7, WK5, WK8, WA4

WP1: Depth of knowledge required
WP3: Depth of analysis required
WP7: Interdependence
WK5: Engineering Design
WA3: Design and development of solution
Assessment in: Assignment # 03

Complex Engineering Activity Details Included: No

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