STP9NB50

STP9NB50FP
N-CHANNEL 500V - 0.75 Ω - 8.6 A TO-220/TO-220FP
PowerMesh™ MOSFET
TYPE VDSS RDS(on) ID

STP9NB50 500 V < 0.85 Ω 8.6 A

STP9NB50FP 500 V < 0.85 Ω 4.9 A
■ TYPICAL RDS(on) = 0.75 Ω
■ EXTREMELY HIGH dv/dt CAPABILITY
■ 100% AVALANCHE TESTED 3 3
■ VERY LOW INTRINSIC CAPACITANCES 2 2
1 1
■ GATE CHARGE MINIMIZED
TO-220 TO-220FP
DESCRIPTION
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Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an ad-
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vanced family of power MOSFETs with outstanding
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performances. The new patent pending strip layout
coupled with the Company’s proprieraty edge termi- INTERNAL SCHEMATIC DIAGRAM
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nation structure, gives the lowest R DS(on) per area,
exceptional avalanche and dv/dt capabilities and
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unrivalled gate charge and switching characteris-
tics.
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APPLICATIONS
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■ HIGH CURRENT, HIGH SPEED SWITCHING

■ SWITH MODE POWER SUPPLIES (SMPS)

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■ DC-AC CONVERTERS FOR WELDING

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EQUIPMENT AND UNINTERRUPTIBLE
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POWER SUPPLIES AND MOTOR DRIVE

ABSOLUTE MAXIMUM RATINGS

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Symbol
r o Parameter Value Unit

VDS
e P
Drain-source Voltage (VGS = 0)
STP9NB50
500
STP9NB50FP
V
VDGR
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Drain-gate Voltage (RGS = 20 kΩ) 500 V

s
VGS
o Gate- source Voltage ±30 V

O b ID
ID
Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C
8.6
5.4
4.9
3.1
A
A
IDM (●) Drain Current (pulsed) 34.4 34.4 A
PTOT Total Dissipation at TC = 25°C 125 40 W
Derating Factor 1 0.32 W/°C
dv/dt (1) Peak Diode Recovery voltage slope 4.5 4.5 V/ns
VISO Insulation Withstand Voltage (DC) - 2000 V
Tstg Storage Temperature –65 to 150 °C
Tj Max. Operating Junction Temperature 150 °C
(•)Pulse width limited by safe operating area (1)ISD<9A, di/dt<200A/µ, VDD<V(BR)DSS,TJ<TJMAX
May 2000 1/9
 STP9NB50/FP

THERMAL DATA
TO-220 TO-220FP
Rthj-case Thermal Resistance Junction-case Max 1 3.13 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
Rthc-sink Thermal Resistance Case-sink Typ 0.5 °C/W
Tl Maximum Lead Temperature For Soldering Purpose 300 °C

AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
Avalanche Current, Repetitive or Not-Repetitive
IAR 8.6 A
(pulse width limited by Tj max)
Single Pulse Avalanche Energy
EAS 520 mJ
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)

OFF
Symbol Parameter Test Conditions Min. Typ. Max.

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Unit

V(BR)DSS
Drain-source
Breakdown Voltage
ID = 250 µA, VGS = 0 500
c t( V

IDSS
Zero Gate Voltage VDS = Max Rating
d u 1 µA

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Drain Current (VGS = 0) VDS = Max Rating, TC = 125 °C 50 µA

IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ±30V

e P ±100 nA

ON (1)
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Symbol
VGS(th)
Parameter
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Test Conditions
VDS = VGS, ID = 250 µA
Min. Typ. Max. Unit

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Gate Threshold Voltage 3 4 5 V

RDS(on)
Static Drain-source On
Resistance
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VGS = 10V, ID = 4.3 A 0.75 0.85 Ω

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ct
VDS > ID(on) x RDS(on)max,
ID(on) On State Drain Current 8.6 A
VGS = 10V

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DYNAMIC
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Symbol

e P Parameter Test Conditions Min. Typ. Max. Unit

gfs (1)

l et
Forward Transconductance
VDS > ID(on) x RDS(on)max,
ID = 4.3 A
5.7 S

s
Ciss
o Input Capacitance 1250 pF

O b Coss

Crss
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25V, f = 1 MHz, VGS = 0 175

20
pF

pF

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 STP9NB50/FP

ELECTRICAL CHARACTERISTICS (CONTINUED)

SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on) VDD = 250 V, ID = 4.3 A 19 ns
Turn-on Delay Time
RG = 4.7Ω VGS = 10 V
tr Rise Time 11 ns
(see test circuit, Figure 3)
Qg Total Gate Charge 32 45 nC
VDD = 400V, ID = 8.6 A,
Qgs Gate-Source Charge 10.6 nC
VGS = 10V
Qgd Gate-Drain Charge 13.7 nC

SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
tr(Voff) Off-voltage Rise Time 11.5 ns
VDD = 400V, ID = 8.6 A,
tf Fall Time RG = 4.7Ω, VGS = 10V 11 ns
(see test circuit, Figure 5)
tc Cross-over Time 20

s)
ns

SOURCE DRAIN DIODE

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Symbol Parameter Test Conditions Min. Typ.
d u
Max. Unit

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ISD Source-drain Current 8.6 A
ISDM (2)
VSD (1)
Source-drain Current (pulsed)
Forward On Voltage ISD = 8.6 A, VGS = 0
e P 34.4
1.6
A
V

let
trr Reverse Recovery Time 420 ns
ISD = 8.6 A, di/dt = 100A/µs,

so
Qrr Reverse Recovery Charge VDD = 100V, Tj = 150°C 3.5 µC
(see test circuit, Figure 5)
IRRM Reverse Recovery Current
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
Ob 16.5 A

2. Pulse width limited by safe operating area.

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Safe Operating Area Safe Operating Area for TO-220FP

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 STP9NB50/FP

Thermal Impedence for TO-220 Thermal Impedence for TO-220FP

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Output Characteristics Transfer Characteristics

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P r
te
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Transconductance

Pr Static Drain-source On Resistance

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b s
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4/9
 STP9NB50/FP

Gate Charge vs Gate-source Voltage Capacitance Variations

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Normalized Gate Threshold Voltage vs Temp.
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Normalized On Resistance vs Temperature

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r
Source-drain Diode Forward Characteristics

P
et e
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5/9
 STP9NB50/FP

Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform

Fig. 3: Switching Times Test Circuit For Fig. 4: Gate Charge test Circuit
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Resistive Load
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Fig. 5: Test Circuit For Inductive Load Switching
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And Diode Recovery Times
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6/9
 STP9NB50/FP

TO-220 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
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H2
L2
10.0
16.4
10.40 0.393
0.645
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0.409

L4 13.0 14.0 0.511

d u 0.551
L5
L6
2.65
15.25
2.95
15.75
0.104
0.600
r o 0.116
0.620
L7 6.2 6.6 0.244

e P 0.260
L9
DIA.
3.5
3.75
3.93
3.85
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0.137
0.147
0.154
0.151

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A

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D

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C

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D1

( s
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d
F1

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G1

t
H2
G

o l e Dia.
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F

b
F2

O L5
L7
L9

L6 L4
P011C

7/9
 STP9NB50/FP

TO-220FP MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.7 0.045 0.067
F2 1.15 1.7 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106

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H
L2
10
16
10.4 0.393
0.630 t(
0.409

c
L3 28.6 30.6 1.126

d u 1.204

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L4 9.8 10.6 0.385 0.417

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L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366

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let
Ø 3 3.2 0.118 0.126

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A

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D

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B

ct ( L3

d u L6

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P
F1

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G1

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G
H

b s
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F2

1 2 3
L2 L4

8/9
 STP9NB50/FP

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

b s
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products

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are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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© 2000 STMicroelectronics – Printed in Italy – All Rights Reserved

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