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ISSN: 2455-5703
Abstract
Radix-2 FFT algorithm is the simplest and most common form of the Cooley-Tukey algorithm. This considers radix-2 FFT
processors and realization of butterfly operations. The properties, e.g., area and power consumption, of the FFT processor
depend mainly on implementation of butterfly operations. These algorithms have been developed using verilog hardware
descriptive language. Butterfly unit method reduces the number of multiplications and additions compared to formula method.
Keywords- Cooley Tukey, DFT, Decimation, FFT, Twiddle Factor
I. INTRODUCTION
Discrete Fourier Transform (DFT) is one of the most important tools in the field of DSP. Due to its computational complexity,
several fast fourier transform algorithms have been developed over the years.
The most popular FFT algorithm is the Cooley-Tukey algorithm. It has been shown that the decimation in time
algorithm provides better signal to noise ratio than the decimation in frequency algorithms when finite word length is used. The
basic computation performed at every stage is to take two complex numbers say (a, b), multiply b by WNr and then add and the
product from a to form two new complex numbers (A, B).
This basic computation is called a butterfly because the flowgraph resembles a butterfly. In general, each butterfly
involves one complexmultipliction and two complex additions.
For N=2^n,there are N/2 butterflies per stage of the computation process and log2N stages.
Therefore the total number of complex multiplications is (N/2)log2N and complex additions is Nlog2N.
The basic need for implementation of butterfly structure in VHDL is to prevent arithmetic flow. It plays an important
role in operation of digital signal processor.
Before addition takes place with the first input, the second input is multiplied with the twiddle factor. A code has been
specifically written for the twiddle factor multiplication. Once Multiplication takes place, the addition with the first term must
also take place. For doing this step, a series of CARRY LOOK AHEAD ADDERS (CLA) are used.
The Carry Look Ahead Adder works as a simple adder whose sum is produced along with a carry, where, the carry acts
as an input for the next adder block.
The first output results A1, is obtained by adding the multiplied result with the first term. The second output result, A2
is obtained by subtracting the multiplied result with the first term.
This can be mathematically written as:
A1r+jA1i = [(x1+jx2) *(Wr+jWi)] + (b1+jb2)
A2r+jA2i = [(x1+jx2) *(Wr+jWi)] – (b1+jb2)
Where Wr and jWi are taken as the twiddle factor
From this, it is found out that there are 2 complex numbers that contains 4 normal multiplications and the process also
requires 4 carry look ahead adder units to perform addition. The booth multiplier module that is specified reads the 2 complex
numbers and the twiddle factors mentioned. Multiplication now takes place for the 2 numbers along with the twiddle factors.
The product obtained in the booth multiplier module must be added with the 1st term to produce the first output. Hence,
the Carry Look Ahead Adder for 32-bit and 4-bit is instantiated into the main butterfly module. Each Carry Look Ahead Adder
has sub-modules that perform logical AND, logical OR and logical XOR.
The modules declared as „and21‟ shows that logical AND has been done for 2 inputs, module „and31‟ shows that logical
AND has been done for 3 inputs and module „and41‟ shows that logical AND has been done for 4 inputs.
Similarly, module „or21‟ shows that logical OR has been done for 2 inputs, module „or31‟ shows that logical OR has been
done for 3 inputs and module „or41‟ shows that logical OR has been done for 4 inputs.
In the same manner, module „xor21‟ shows that logical XOR has been done for 2 inputs, module „xor31‟ shows that logic
XOR has been done for 3 inputs and module „xor41‟ shows that logical XOR has been done for 4 inputs.
The same is used for finding the next output. The product that was produced in the booth multiplier module must be
subtracted with the 1st term to produce the first output for the same. For this too, the Carry Look Ahead Adder is used.
V. SIMULATION RESULT
REFERENCES
[1] J.G.Proakis and D.G.Manolakis, "Digital signal processing, principles, Algorithms and applications."3rdEdition,1998, Prentice Hall India Publications,
[2] Digital signal processing, Dr J S Chitode
[3] Charles wu, “implementation of radix-4 decimation in frequency(DIF)fast fourier transform algorithm using TMS320C80 DSP”