L T P C

EC8661 VLSI DESIGN LABORATORY

0 0 4 2
OBJECTIVES:
The student should be made:
 To learn Hardware Descriptive Language(Verilog/VHDL)
 To learn the fundamental principles of VLSI circuit design in digital and analog
domain
 To familiarize fusing of logical modules on FPGAs
 To provide hands on design experience with professional design (EDA) platforms

LIST OF EXPERIMENTS:
Part I: Digital System Design using HDL & FPGA (24 Periods)
Design an Adder (Min 8 Bit) using HDL. Simulate it using Xilinx/Altera Software and
1.
implement by Xilinx/Altera FPGA
Design a Multiplier (4 Bit Min) using HDL. Simulate it using Xilinx/Altera Software and
2.
implement by Xilinx/Altera FPGA
Design an ALU using HDL. Simulate it using Xilinx/Altera Software and implement by
3.
Xilinx/Altera FPGA
Design a Universal Shift Register using HDL. Simulate it using Xilinx/Altera Software
4.
and implement by Xilinx/Altera FPGA
Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera
5.
Software and implement by Xilinx/Altera FPGA
Design Memories using HDL. Simulate it using Xilinx/Altera Software and implement
6. by Xilinx/Altera FPGA

Compare pre synthesis and post synthesis simulation for experiments 1 to 6.

Requirements: Xilinx ISE/Altera Quartus/ equivalent EDA Tools along with
Xilinx/Altera/equivalent FPGA Boards

Part-II Digital Circuit Design (24 Periods)

7. Design and simulate a CMOS inverter using digital flow
8. Design and simulate a CMOS Basic Gates & Flip-Flops
9. Design and simulate a 4-bit synchronous counter using a Flip-Flops
Manual/Automatic Layout Generation and Post Layout Extraction for experiments 7
to 9
Analyze the power, area and timing for experiments 7 to 9 by performing Pre Layout
and Post Layout Simulations.
Part-III Analog Circuit Design (12 Periods)

10. Design and Simulate a CMOS Inverting Amplifier.

Design and Simulate basic Common Source, Common Gate and Common Drain
11.
Amplifiers.
Analyze the input impedance, output impedance, gain and bandwidth for
experiments 10 and 11 by performing Schematic Simulations.
Design and simulate simple 5 transistor differential amplifier. Analyze Gain,
12.
Bandwidth and CMRR by performing Schematic Simulations.

Requirements: Cadence/Synopsis/ Mentor Graphics/Tanner/equivalent EDA Tools

TOTAL :60 PERIODS

Exp: 1 Design entry simulation and implementation of 8 bit adder

Aim:

To design simulate and implement 8 bit adder in cyclone II FPGA

Apparatus Required:

Altera Quartus software, cyclone II FPGA, Personal computer

Procedure:

1. Double click on Quartus II 8.1 icon on desktop or start ->Altera quartus II 8.1. A new window
opens go to file New project wizard Give project name and directory
2. Give the device family package and package as Cyclone II, EP2C70F896C6
3. Select new file and select verilog HDL and choose ok.
4. Type the program and save this file under project directory folder.
5. Choose the compiler tool from Processing tab and give start to compile it and check the errors
6. Select the new file and choose Vector Waveform file to provide the inputs and save it
7. Choose the Simulator tool through the processing tab. Select simulation mode as functional and
choose the saved vwf file as simulation input file the click start to initiate the simulation. Finally
check the function of the program through the obtained outputs.

Program:

8 BIT ADDER

module adder(s,cout,a,b,cin);
output[7:0]s;
output cout;
input[7:0]a,b;
input cin;
wire c1,c2,c3,c4,c5,c6,c7;
fulladd fa0(s[0],c1,a[0],b[0],cin);
fulladd fa1(s[1],c2,a[1],b[1],c1);
fulladd fa2(s[2],c3,a[2],b[2],c2);
fulladd fa3(s[3],c4,a[3],b[3],c3);
fulladd fa4(s[4],c5,a[4],b[4],c4);
fulladd fa5(s[5],c6,a[5],b[5],c5);
fulladd fa6(s[6],c7,a[6],b[6],c6);
fulladd fa7(s[7],cout,a[7],b[7],c7);
endmodule
 module fulladd(s,cout,a,b,cin);
output s,cout;
input a,b,cin; xor
(s,a,b,cin);
assign cout = ((a & b )|(b& cin)|( a & cin)) ;
endmodule
Output:

Result:

Thus the 8 bit adder was successfully designed using verilog HDL and implemented in cyclone II FPGA.
Exp: 2 Design entry simulation and implementation of 4 bit multiplier

Aim:

To design simulate and implement 4 bit multiplier in cyclone II FPGA

Apparatus Required:

Altera Quartus software, cyclone II FPGA, Personal computer

Procedure:

1. Double click on Quartus II 8.1 icon on desktop or start ->Altera quartus II 8.1. A new window
opens go to file New project wizard Give project name and directory
2. Give the device family package and package as Cyclone II, EP2C70F896C6
3. Select new file and select verilog HDL and choose ok.
4. Type the program and save this file under project directory folder.
5. Choose the compiler tool from Processing tab and give start to compile it and check the errors
6. Select the new file and choose Vector Waveform file to provide the inputs and save it
7. Choose the Simulator tool through the processing tab. Select simulation mode as functional and
choose the saved vwf file as simulation input file the click start to initiate the simulation. Finally
check the function of the program through the obtained outputs.
Program:

module fourbitmulti(m,a,b);
input[3:0]a;
input[3:0]b;
output[7:0]m;
wire[15:0]p;
wire[12:1]s;
wire[12:1]c;

and(p[0],a[0],b[0]);
and(p[1],a[1],b[0]);
and(p[2],a[0],b[1]);
and(p[3],a[2],b[0]);
and(p[4],a[1],b[1]);
and(p[5],a[0],b[2]);
and(p[6],a[3],b[0]);
and(p[7],a[2],b[1]);
and(p[8],a[1],b[2]);
and(p[9],a[0],b[3]);
and(p[10],a[3],b[1]);
and(p[11],a[2],b[2]);
and(p[12],a[1],b[3]);
and(p[13],a[3],b[2]);
and(p[14],a[2],b[3]);
and(p[15],a[3],b[3]);

half ha1(s[1],c[1],p[1],p[2]);
half ha2(s[2],c[2],p[4],p[3]);
half ha3(s[3],c[3],p[7],p[6]);
full fa4(s[4],c[4],p[11],p[10],c[3]);
full fa5(s[5],c[5],p[14],p[13],c[4]);
full fa6(s[6],c[6],p[5],s[2],c[1]);
full fa7(s[7],c[7],p[8],s[3],c[2]);
full fa8(s[8],c[8],p[12],s[4],c[7]);
full fa9(s[9],c[9],p[9],s[7],c[6]);
half ha10(s[10],c[10],s[8],c[9]);
full fa11(s[11],c[11],s[5],c[8],c[10]);
full fa12(s[12],c[12],p[15],s[5],c[11]);

buf (m[0],p[0]);
buf (m[1],s[1]);
buf (m[2],s[6]);
buf (m[3],s[9]);
buf (m[4],s[10]);
buf (m[5],s[11]);
buf (m[6],s[12]);
buf (m[7],c[12]);
endmodule

module half (s,c0,x,y);

input x,y;
output s,c0;
xor(s,x,y);
and(c0,x,y);
endmodule

module full(s,c0,x,y,cin);
input x,y,cin;
output s,c0;
wire s1,d1,d2;
half ha_1(s1,d1,x,y);
half ha_2(s,d2,s1,cin);
or or_gate(c0,d2,d1);
endmodule

Output:

Result:

Thus the 4 bit multiplier was successfully designed using verilog HDL and implemented in cyclone II
FPGA.
Exp: 3 Design entry simulation and implementation of Arithmetic Logic Unit (ALU)

Aim:

To design simulate and implement an arithmetic logic unit in cyclone II FPGA

Apparatus Required:

Altera Quartus software, cyclone II FPGA, Personal computer

Procedure:

1. Double click on Quartus II 8.1 icon on desktop or start ->Altera quartus II 8.1. A new window
opens go to file New project wizard Give project name and directory
2. Give the device family package and package as Cyclone II, EP2C70F896C6
3. Select new file and select verilog HDL and choose ok.
4. Type the program and save this file under project directory folder.
5. Choose the compiler tool from Processing tab and give start to compile it and check the errors
6. Select the new file and choose Vector Waveform file to provide the inputs and save it
7. Choose the Simulator tool through the processing tab. Select simulation mode as functional and
choose the saved vwf file as simulation input file the click start to initiate the simulation. Finally
check the function of the program through the obtained outputs.

Program:

module alu(s,a,b,f);
input[2:0]s;
input[3:0]a,b;
output[3:0]f;
reg[3:0]f;
always@(s or a or b)
begin
case(s)
3'b000:f<=4'b0000;
3'b001:f<=a-b;
3'b010:f<=a+b;
3'b011:f<=b-a;
3'b100:f<=a&b;
3'b101:f<=a|b;
3'b110:f<=~a;
default:f<=4'b1111;
endcase
end
endmodule
Output:

Result:

Thus the Arithmetic Logic Unit was successfully designed using verilog HDL and implemented in cyclone
II FPGA.
Exp: 4 Design entry simulation and implementation of memories

Aim:

To design simulate and implement a Read only Memory (ROM) in cyclone II FPGA

Apparatus Required:

Altera Quartus software, cyclone II FPGA, PC

Procedure:

1. Double click on Quartus II 8.1 icon on desktop or start ->Altera quartus II 8.1. A new window
opens go to file New project wizard Give project name and directory
2. Give the device family package and package as Cyclone II, EP2C70F896C6
3. Select new file and select verilog HDL and choose ok.
4. Type the program and save this file under project directory folder.
5. Choose the compiler tool from Processing tab and give start to compile it and check the errors
6. Select the new file and choose Vector Waveform file to provide the inputs and save it
7. Choose the Simulator tool through the processing tab. Select simulation mode as functional and
choose the saved vwf file as simulation input file the click start to initiate the simulation. Finally
check the function of the program through the obtained outputs.

Theory:

Read only memory (ROM) is a type of memory that usually holds the application program or fixed user
data. ROM is nonvolatile. If power is removed from ROM and then reapplied, the original data will still
be there. ROMs are programmed at the factory during the manufacturing process and their content
cannot be changed by the user. Programmable read only memory (PROM) is a type of ROM that can be
programmed in the field, often by the end user, using a device called a PROM programmer. PROM is
used to store an application program or constant data. Once a PROM has been programmed, its
contents cannot be changed again. PROMs are usually used in low production applications where only
several such memories are required. EPROMs have a small clear glass window on top of the chip where
the data can be erased under strong ultraviolet light. Once the memory is programmed, the window
should be covered with dark tape to prevent accidental erasure of the data. An EPROM must be erased
before it can be reprogrammed.

Program:

module rom(addr,data,rd_en,cs);
input[2:0]addr;
input rd_en,cs;
output reg[7:0]data;
always@(addr or rd_en or cs)
case(addr)
0:data=12;
1:data=14;
2:data=16;
3:data=18;
4:data=20;
5:data=22;
6:data=24;
7:data=26;
endcase
endmodule

Output:
Result:

Thus the ROM based memory was successfully designed using verilog HDLand implemented in cyclone II
FPGA
Exp: 5 Design entry simulation and implementation of Finite State Machine

Aim:

To design simulate and implement a finite state machine in cyclone II FPGA

Apparatus Required:

Altera Quartus software, cyclone II FPGA, PC

Theory:

The finite state machine is a mathematical model of computation. It is an abstract machine that can be
in exactly one of a finite number of states at any given time. The finite state machine can change from
one state to another in response to some inputs. The change from one state to another is called a
transition. There are two types of finite state machines that generate output. They are Mealy state and
Moore state machine. In Moore state machine the output depends only on the current state. The
advantages of the Moore model are a simplification of the behavior. In Mealy state machine, the output
depends on both current state and input.

Procedure:

1. Double click on Quartus II 8.1 icon on desktop or start ->Altera quartus II 8.1. A new window
opens go to file New project wizard Give project name and directory
2. Give the device family package and package as Cyclone II, EP2C70F896C6
3. Select new file and select verilog HDL and choose ok.
4. Type the program and save this file under project directory folder.
5. Choose the compiler tool from Processing tab and give start to compile it and check the errors
6. Select the new file and choose Vector Waveform file to provide the inputs and save it
7. Choose the Simulator tool through the processing tab. Select simulation mode as functional and
choose the saved vwf file as simulation input file the click start to initiate the simulation. Finally
check the function of the program through the obtained outputs.

Program:

module seqckt(y,x,clk,rst);
input x,clk,rst;
output y;
reg y;
reg[2:0]state;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
state<=3'b000;
y<=0;
end
else
begin
case(state)
3'b000:begin
if(x)
begin
state<=3'b001;
y<=0;
end
end
3'b001:
begin
if(x)
begin
state<=3'b001;
y<=0;
end
else
begin
state<=3'b010;
y<=0;
end
end
3'b010:
begin
if(x)
begin
state<=3'b001;
y<=0;
end
else
begin
state<=3'b011;
y<=0;
end
end
3'b011:
begin
if(x)
begin
state<=3'b100;
y<=1;
end
else
begin
state<=3'b000;
y<=0;
end
end
3'b100:
begin
if(x)
begin
state<=3'b001;
y<=0;
end
else
begin
state<=3'b000;
y<=0;
end
end
endcase
end
end
endmodule
Output:

Result

Thus the sequence detector using Moore state machine for the sequence 1001 was successfully
designed using verilog HDL and implemented in cyclone II FPGA
Exp: 6 Design entry simulation and implementation of Universal Shift Register

Aim:

To design simulate and implement a Universal Shift Register in cyclone II FPGA

Apparatus Required:

Altera Quartus software, cyclone II FPGA, PC

Theory:

Universal Shift register is a register which has both the right shift and left shift with parallel load
capabilities. It is used as memory elements in computers. A unidirectional shift registers is capable of
shifting in only one direction and at the same time bidirectional shift registers performed shifting in both
the directions. The universal shift register is a combination design of bidirectional and unidirectional
shift registers with parallel load provision. An n bit universal shift register consists of n-flipflops and n-
multiplexer. All the multipliers share the same select lines (S1 and S0) to select the mode in which the
shift register operates. The select lines choose the suitable input for flipflops.

Procedure:

1. Double click on Quartus II 8.1 icon on desktop or start ->Altera quartus II 8.1. A new window
opens go to file New project wizard Give project name and directory
2. Give the device family package and package as Cyclone II, EP2C70F896C6
3. Select new file and select verilog HDL and choose ok.
4. Type the program and save this file under project directory folder.
5. Choose the compiler tool from Processing tab and give start to compile it and check the errors
6. Select the new file and choose Vector Waveform file to provide the inputs and save it
7. Choose the Simulator tool through the processing tab. Select simulation mode as functional and
choose the saved vwf file as simulation input file the click start to initiate the simulation. Finally
check the function of the program through the obtained outputs.
Diagram:

Mode control Register Operation

S1 S0
0 0 No operation
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load

Program:

module USR(A,g,clk,SLin,SRin,mode);
wire[3:0]w;
input[3:0]g;
input[1:0]mode;
input clk;
input SLin,SRin;
output [3:0]A;
mux4_1 M0(w[0],A[0],A[1],SLin,g[0],mode);
mux4_1 M1(w[1],A[1],A[2],A[0],g[1],mode);
mux4_1 M2(w[2],A[2],A[3],A[1],g[2],mode);
mux4_1 M3(w[3],A[3],SRin,A[2],g[3],mode);

dfff D0(A[0],w[0],clk);
dfff D1(A[1],w[1],clk);
dfff D2(A[2],w[2],clk);
dfff D3(A[3],w[3],clk);
endmodule

module mux4_1(y,i0,i1,i2,i3,mode);
input i0,i1,i2,i3;
input [1:0]mode;
output reg y;
always@(mode,i3,i2,i1,i0)
begin
case(mode)
2'b00:y=i0;
2'b01:y=i1;
2'b10:y=i2;
2'b11:y=i3;
endcase
end
endmodule

module dfff(q,d,clk);
input d,clk;
output reg q;
always@(posedge clk)
q<=d;
endmodule

Output:

Input : g=1010 (Decimal Value:10) sLin=1, sRin=1

Operation Mode (S1,S0) Output

S1 S0
No operation 0 0 0000
Shift Right 0 1 1000
Shift Left 1 0 0001
Parallel Load 1 1 1010
Result:

Thus the 4 bit universal shift register was successfully designed and implemented in FPGA
Exp: 7 Design and simulate a CMOS inverter circuit

AIM:

To design and simulate a CMOS inverter using Dsch2 and Microwind tools and perform the prelayout
and post layout simulations

Apparatus Required:

Dsch2 and microwind, Personal Computer

Theory:

NOT gate: The CMOS NOT design is detailed in the following figure. Here one p-channel MOS and one n-
channel MOS transistors are used as switches. The channel width for pMOS devices is set to twice the
channel width for nMOS devices. When the input signal is logic 0, the nMOS is switched off while the
PMOS passes VDD through the output, which turns to 1. When the input signal is logic 1.the pMOS is
switched off while the nMOS passes VSS to the output, which goes back to 0. In that simulation, the
MOS is considered as a simple switch. The n channel MOS symbol is a device that allows the current to
flow between the source and the drain when the gate voltage is "1".

Procedure:

Opening Dsch3 file.

Selecting the nNMOS transistor from Symbol Library on top right and dragging it to the main screen.

Selecting the nNMOS transistor from Symbol Library on top right and dragging it to the main screen.

Similarly selecting supply and ground symbols from Symbol Library and dragging them to the main
screen.

Connecting all symbols as shown in the figure.

Use add a line command to connect different nodes of these symbols

Adding a Button Symbol to the input and Light symbol to the output of the circuit from Symbols library
and completes the schematic diagram. Then save as the file using a particular name.

Then go to simulate tab and click start simulation. After few seconds stop the simulation and click on
timing diagram to view the outputs.

Go to file and click on make verilog file and save it

Open the microwind file. Choose Compile verilog file option and select the respective file from dsch2
folder. Compile it and back to editor to view the automatic generated layout.

Finally simulate the file and get the final output.

RESULT:

Thus the CMOS inverter was designed and simulated successfully using microwind and dsch2
tools.
Exp. No.8 Design and simulate CMOS Basic gates and Flipflops

AIM:

To design and simulate a CMOS basic logic gates (NAND and NOR) and flipflops (D,T, JK flipflops) using
Dsch2 and microwind tools and perform the prelayout and post layout simulations.

Apparatus Required:

Dsch2 and microwind

Theory:

NAND gate: A NAND gate can be implemented using four MOS transistors i.e. two pmos and two nmos
as the inputs of the gate is two. pmos are connected in parallel while nmos are connected in series, Vdd
is supplied to the parallel combination of pmos while the series combination of nmos is grounded.
Inputs a & b are applied to the gate terminals of all FETs, and the output f is obtained from the common
junction of these series and parallel combinations as illustrated in NAND circuit.

NOR gate: The two-input NOR gate shown on the left is built from four transistors. The parallel
connection of the two n-channel transistors between GND and the gate-output ensures that the
gateoutput is driven low (logical 0) when either gate input A or B is high (logical 1). The complementary
series-connection of the two transistors between VCC and gate-output means that the gate-output is
driven high (logical 1) when both gate inputs are low (logical 0).

Procedure:

Opening Dsch3 file.

Selecting the nNMOS transistor from Symbol Library on top right and dragging it to the main screen.

Selecting the nNMOS transistor from Symbol Library on top right and dragging it to the main screen.

Similarly selecting supply and ground symbols from Symbol Library and dragging them to the main
screen.

Connecting all symbols as shown in the figure.

Use add a line command to connect different nodes of these symbols

Adding a Button Symbol to the input and Light symbol to the output of the circuit from Symbols library
and completes the schematic diagram. Then save as the file using a particular name.

Then go to simulate tab and click start simulation. After few seconds stop the simulation and click on
timing diagram to view the outputs.

Go to file and click on make verilog file and save it

Open the microwind file. Choose Compile verilog file option and select the respective file from dsch2
folder. Compile it and back to editor to view the automatic genrated layout.
Finally simulate the file and get the final output
FLIPFLOPS:

D FLIP FLOP
D Flip flop Schematic
Layout of D flip flop

RESULT:

Thus the CMOS basic gates and flipflops were designed and simulated successfully.
Exp: 9 Design and simulate a 4 bit synchronous counter using Flip flops

AIM:

To design and simulate a 4 bit synchronous counter using flip flop with the tools Dsch2 and microwind.

Theory:

In this circuit, the single clock signal is directly connected to all flipflops, so that all flipflops change state
at the same time. The result of this synchronization is that all the individual output bits changing state at
exactly the same time in response to the common clock signal with no ripple effect and therefore, no
propagation delay. Obviously, this counter consists of four identical stages with a D-type flipflop, an
XOR-gate, and a two-input AND-gate each. The XOR-gate in front of the D input of the flipflop basically
converts the D-type flipflop into a toggle (T-type) flipflop. Synchronous counters are sometimes called
parallel counters as the clock is fed in parallel to all flip-flops. The inherent memory circuit keeps track of
the counters present state. The count sequence is controlled using logic gates. Overall faster operation
may be achieved compared to Asynchronous counters.

Procedure:

Opening Dsch3 file.

Selecting the D flipflop from Symbol Library on top right and dragging it to the main screen.

Selecting the XOR, AND gate from Symbol Library on top right and dragging it to the main screen.

Similarly selecting supply and ground symbols from Symbol Library and dragging them to the main
screen. Select the digit symbol to display the output.

Connecting all the symbols as shown in the figure.

Use add a line command to connect different nodes of these symbols

Adding a Button Symbol to the input and Light symbol to the output of the circuit from Symbols library
and completes the schematic diagram. Then save as the file using a particular name.

Then go to simulate tab and click start simulation. After few seconds stop the simulation and click on
timing diagram to view the outputs.

Go to file and click on make verilog file and save it

Open the microwind file. Choose Compile verilog file option and select the respective file from dsch2
folder. Compile it and back to editor to view the automatic generated layout.

Finally simulate the file and get the final output.

Schematic of 4 bit synchronous counter
Layout:

Layout of 4 bit synchronous counter

RESULT:

Thus the 4 bit synchronous counter using flipflop was designed and simulated successfully.
Exp: 10 Design a CMOS inverting amplifier circuit

Aim:

To design and simulate the simple five transistor differential amplifier circuit and measure
the parameters using Tanner EDA tools.

Apparatus Required:

PC with windows, Tanner EDA tools v13.0

Procedure:

1. Click on the S-Edit 13.0. In the window select the file

2. Create new design by Click file  New  New Design
3. Enter the design name and select the path to save the design.
4. Create new cell view  Cell  new view  Select the parameters and give ok.
5. Click add available in library window and select the library file.
6. Select devices in the library drag required PMOS and NMOS components from
the symbol browser and design five transistor differential amplifier circuit.
7. Common mode Inputs are applied to the circuit.
8. To open T spice window click Tools  T- Spice.
9. Insert technology file and required comments using insert comment option in
T- Spice.
10. Run the simulation by clicking simulation  Run simulation.
11. Output waveform is viewed in the waveform viewer (W-edit) now verify the result.
12. Input and output voltages are measured and tabulated for common mode.
13. Step 7 to step 12 is repeated for the differential mode.
14. Now calculate the gain, ICMR, and CMRR.
Theory:

CMOS inverter act as an inverting linear amplifier with a characteristics of Vout =-AVin where A is
the stage gain. Near the input threshold voltage the, the CMOS inverter acts as an inverting
linear amplifier. It should be noted that the CMOS inverter when used as a logic element is in
reality an analog amplifier operated under saturating condition. It can also be viewed as an
nMOS common source amplifier driving a pMOS common source amplifier.. For amplifiers
operating at very low supply voltages, the inverting amplifier stages should be applied. This
circuits display an output voltage range that is nearly equal to the supply voltage and can
operate on supply voltages.
Result:

Thus the CMOS inverting amplifier circuit was designed and simulated successfully using Tanner
EDA tool.
Exp: 11 Design a CMOS Common Source, Common Drain and Common Gate Amplifier circuits

Aim:

To design and simulate the Common source, drain and common gate amplifier circuit
using Tanner EDA tools.

Apparatus Required:

PC with windows, Tanner EDA tools v13.0

Procedure:

1. Click on the S-Edit 13.0. In the window select the file

2. Create new design by Click file  New  New Design
3. Enter the design name and select the path to save the design.
4. Create new cell view  Cell  new view  Select the parameters and give ok.
5. Click add available in library window and select the library file.
6. Select devices in the library drag required PMOS and NMOS components from
the symbol browser and design five transistor differential amplifier circuit.
7. Common mode Inputs are applied to the circuit.
8. To open T spice window click Tools  T- Spice.
9. Insert technology file and required comments using insert comment option in
T- Spice.
10. Run the simulation by clicking simulation  Run simulation.
11. Output waveform is viewed in the waveform viewer (W-edit) now verify the result.
12. Input and output voltages are measured and tabulated for common mode.

Theory:

Common Drain Amplifier (Source Follower):

The common drain amplifier figure shows the source follower circuit in which drain terminal of
the device is common. In this circuit the drain terminal is directly connected to V DD. In CS
amplifier analysis we have seen that in order to achieve the high voltage gain the load
impedance should be as high as possible. Therefore for low impedance load the buffer must be
placed after the amplifier to drive the load with negligible loss of the signal level. The source
follower thus worked as a buffer stage. The source follower is also called as the common drain
amplifier. In this circuit, the signal at the gate is sensed and drives the load at the source which
allows the source potential to follow the gate voltage. The drawback of source follower is
nonlinearity due to body effect and poor driving capability of the input signal.

Common Source Amplifier:

In this circuit the MOSFET converts variations in the gate-source voltage into a small signal drain
current which passes through a resistive load and generates the amplified voltage across the
load resistor. the voltage gain of CS amplifier is depends upon the transconductance g m, the
linear resistor ro and load. In order to increase the gain we have to increase the g m. Inturn we
have to increase the ratio.

Common Gate amplifier:

In common source amplifier and source follower circuits, the input signal are applied to the
gate of a MOSFET. It is also possible to apply the input signal to the source terminal by keeping
common gate terminal. This type of amplifier is called as common gate amplifier. The CG
amplifier in which the input signal is sensed at the source terminal and the output is produced
at the drain terminal. The gate terminal is connected to V B i.e. dc potential which will maintain
the proper operating conditions.

Circuit Diagram:

Common Source:
Output:

Common Gate:
Common Source:
Result:

Thus the common source, drain and gate amplifier circuit was design and simulated successfully using
tanner EDA tool.
Exp:12 Design a 5 transistor differential amplifier circuit

Aim:

To design and simulate the simple five transistor differential amplifier circuit and measure
the parameters using Tanner EDA tools.

Apparatus Required:

PC with windows, Tanner EDA tools v13.0

Procedure:

1. Click on the S-Edit 13.0. In the window select the file

2. Create new design by Click file  New  New Design
3. Enter the design name and select the path to save the design.
4. Create new cell view  Cell  new view  Select the parameters and give ok.
5. Click add available in library window and select the library file.
6. Select devices in the library drag required PMOS and NMOS components from
the symbol browser and design five transistor differential amplifier circuit.
7. Common mode Inputs are applied to the circuit.
8. To open T spice window click Tools  T- Spice.
9. Insert technology file and required comments using insert comment option in
T- Spice.
10. Run the simulation by clicking simulation  Run simulation.
11. Output waveform is viewed in the waveform viewer (W-edit) now verify the result.
12. Input and output voltages are measured and tabulated for common mode.
13. Step 7 to step 12 is repeated for the differential mode.
14. Now calculate the gain, ICMR, and CMRR.

Theory:

The differential amplifier is a form of amplifier that strengthens the difference between two voltages in
a circuit. In electronic designs, we use a differential amplifier to produce high voltage gain and high
CMRR. Its main characteristics include very low bias current input, very high impedance input, and very
low offset voltage. The essential benefit of differential mode from common mode is its higher immunity
to noise. Also, differential amplifiers provide better immunity to environmental noise, improve linearity,
and more upper signal swing. It may operate in two modes: common mode and differential mode. The
common method produces a zero voltage output result while the differential mode produces a high
voltage output result. Given this, the differential amplifier generally has high CMRR. If the two input
voltages are of similar value, the amp provides an output voltage value that is almost zero. When the
two input voltages are unequal, the amplifier produces a high voltage output. The remarkable
advantage of differential operation over common mode operation is its higher immunity to noise.
Circuit Diagram:

Differential Mode

Common mode:
Outputs:

Result:

Thus the simple five transistor differential amplifier was simulated and gain, ICMR, and
CMRR are calculated using Tanner EDA tools.