UVM Cookbook

Recipe of the Month:

Introduction to UVM
Registers
Tom Fitzpatrick
Verification Evangelist
DVT

October 2011
 The Idea Behind The Methodology

 OVM & UVM underpin best

practices
— It's all about people...
— Team Development
 Peopleware is most important
— Develop Skill Set
— Common language
— Strategy and cohesion
— Clarity and transparency
 A Guiding Methodology
— Provides Freedom From Choice
— Avoids Chaos and Repetition
— Ease of Use APIs

— Not just for Super-heroes!

© 2011 Mentor Graphics Corp. Company Confidential
2 TF - UVM Recipe of the Month 10/11 www.mentor.com
 UVM Foundations
Objective
 Separation of stimulus
generation from delivery
 Raise the abstraction level of
stimulus and checking
 Test bench configuration
 Interoperability
— Standard class library & API
 Reuse
— VIP
— Testbench components
— Stimulus
3 TF - UVM Recipe of the Month 10/11
Justification
 Several people can develop
stimulus
 Increase productivity
 Avoid expensive recompilation
 Important for intra and inter
company development
 Key to productivity
© 2011 Mentor Graphics Corp. Company Confidential
www.mentor.com
 UVM Testbench - Architectural Design
For Each Interface:
• How does the interface work?
• What information is transferred?
• Transaction variants?
• Uni/bidirectional? Pipelined?
DUT
APB

SPI
I/F
For the Design: IRQ
• What does it do?
• What are the use cases?
• Which test cases are required?
• What type of stimulus scenarios are required?
• What represents correct behavior?
• What kind of functional coverage do I need?
© 2011 Mentor Graphics Corp. Company Confidential
4 TF - UVM Recipe of the Month 10/11 www.mentor.com
 UVC Structural Building Block
Analysis port: Send Detects transactions
transactions for checking on the interface

- Contains virtual UVC(agent)

interface handle
- Pass information Configuration One per
on how agent Object Monitor interface
should behave

Sequencer
DUT
seq_item
Driver
Sends stimulus
to Driver

Stimulus Converts seq_item

to pin wiggles
© 2011 Mentor Graphics Corp. Company Confidential
5 TF - UVM Recipe of the Month 10/11 www.mentor.com
 UVM Registers are Layered

 UVM Register Layer provides

protocol-independent
register-based layering

UVM Reg Layer UVC(agent)

Configuration
Predict Object Monitor

RegSeq Sequencer
DUT
Driver

Device specific Bus specific

cfg.write(0xDE); wr(0xAF, 0xDE);
© 2011 Mentor Graphics Corp. Company Confidential
6 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Registers, Blocks & Maps

31:14 13 12 11 10 9 8 7 6:0
Registers contain R R/W R/W R/W R/W R/W R/W R R/W

bits & fields

Reserved ASS IE LSB TxNeg RxNeg GoBsy Rsrv Char_Len

Register Map
contains Registers

Register Block
contains Maps

One Map per

physical interface

Blocks are
hierarchical
© 2011 Mentor Graphics Corp. Company Confidential
7 TF - UVM Recipe of the Month 10/11 www.mentor.com
 The Register Map – uvm_reg_map

 Contains offsets for:

— Registers and Memories
— (Hierachical blocks)
— (Sub-maps) SQR

 Also provides means to access registers

— Handle for target sequencer
— Handle for register layer adapter
A block can have > 1 map
SQR

— AXI Master1, AXI Master2 (Fabric)
UVC(agent)

Monitor

Sequencer
DUT
Driver

© 2011 Mentor Graphics Corp. Company Confidential

8 TF - UVM Recipe of the Month 10/11 www.mentor.com
 UVM Register Use Models

 Stimulus Generation
— Abstraction of stimulus:
– i.e. Set this bit in this register rather than write x to address y
— Stimulus reuse
– If the bus agent changes, the stimulus still works
— Front and Back Door access:
– Front door is via an agent
– Back door is directly to the hardware via the simulator database

 Configuration
— Register model reflects hardware programmable registers
— Set up desired configuration in register model then dump to DUT
– Randomization with configuration constraints

 Analysis ‘Mirror’
— Current state of the register model matches the DUT hardware
— Useful for scoreboards and functional coverage monitors
© 2011 Mentor Graphics Corp. Company Confidential
9 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Model Code Example (Only 1 Reg)
Register class with one field
Block containing Register
class spi_reg_block extends uvm_reg_block;
`uvm_object_utils(spi_reg_block)
rand divider divider_reg;
uvm_reg_map APB_map; // Block map
class divider extends uvm_reg;
`uvm_object_utils(divider)
uvm_reg_field reserved;
rand uvm_reg_field ratio;
function new(string name = "divider");
super.new(name, 16, UVM_NO_COVERAGE);
endfunction
virtual function void build();
ratio = uvm_reg_field::type_id::create("ratio");
ratio.configure(this, 16, 0, "RW", 0, 16'hffff, 1, 1, 1);
endfunction
endclass

function new(string name = "spi_reg_block");

super.new(name, build_coverage(UVM_CVR_ADDR_MAP));
endfunction
Build is not the component build
virtual function void build();

divider_reg = divider::type_id::create("divider");
divider_reg.build();
divider_reg.configure(this, null, "");
divider_reg.add_hdl_path_slice("divider", 0, 16); A map is a component of a block
APB_map = create_map("APB_map", 'h800, 4, UVM_LITTLE_ENDIAN);
APB_map.add_reg(divider_reg, 32'h00000014, "RW");

add_hdl_path("DUT", "RTL");
lock_model();
endfunction: build

endclass: spi_reg_block
© 2011 Mentor Graphics Corp. Company Confidential
10 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Assistant* Overview
Register/Memory Definition & Management for the Entire Design Process

 Central, Scalable & Extensible Register/Memory

Datamodel
— Enables easy specification of registers
— Manages register changes
— Eliminates hand coding & resultant mistakes
— Completely customizable
 Automatically Generates
Register Outputs
— OVM/UVM Register Package
— Synthesizable RTL
— Documentation
— Extensive roadmap

Supports the entire design team

* Included with Certe Testbench Studio
© 2011 Mentor Graphics Corp. Company Confidential
11 www.mentor.com
 Common Register Path

 Generate the UVM/OVM register model

 Generate the DUT registers
 Use Certe templates to generate Register Assistant
-Generation
UVM sequences, adaptor class
& the bus agent
Template
Generated
SQR

UVC(agent)

Template-Generated Monitor
RegSeq

Sequencer
DUT
Driver

© 2011 Mentor Graphics Corp. Company Confidential

12 www.mentor.com
 UVM Register Package Generation

Optional Blocks & Block Maps

Customer Example
Register Definitions Early in project:
335 Registers  11,500 lines

Final project:
1,000 Registers  35,000+ lines
of Register Package code
© 2011 Mentor Graphics Corp. Company Confidential
13 www.mentor.com
 Register Documentation Generation
 Communicate the
register layer to all
team members
 Final documents
auto-generated
 Customizable
content & style

© 2011 Mentor Graphics Corp. Company Confidential

14 www.mentor.com
 The Architecture – Open & Extensible

Spreadsheet (CSV) Control File

IP-XACT
API calls

Reg. Definitions Documentation

A A
Blocks Readers P Datamodel P Writers RTL
I I

Block Map
OVM/UVM Pkg.

Checks

© 2011 Mentor Graphics Corp. Company Confidential

15 www.mentor.com
 UVM Coverage

 You can specify the coverage model you wish to generate

for instances in a block
 Simply add a column to your spreadsheet

© 2011 Mentor Graphics Corp. Company Confidential

16 www.mentor.com
 UVM Register Class Access API
 Direct access methods
 reg.read() and reg.write()
— Access the hardware register and update the register database
— Can specify front or back door access
– Front door access takes time and may create side effects
– Uses bus agent and consumes clock cycles
– Back door access is instant and does not cause side effects
– Uses simulation database and access API (VPI)
— Not used for individual fields
 reg.peek() and reg.poke()
— For back door accesses, register model updated with result
— Can be used for individual fields
 The register model has two register variables:
— Desired value
– For when a field has been updated, but not the hardware
— Mirrored value
– Containing the latest known value

© 2011 Mentor Graphics Corp. Company Confidential

17 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Access Method Fields
Type Name Purpose
uvm_status_e status Indicates Access completed OK
uvm_reg_data_t value Data value transfered
uvm_path_e path Front or back door access
uvm_reg_map map Map to use for access
uvm_sequence_base parent Parent sequence
int prior Sequence priority on sequencer
uvm_object extension Transfer extension object
string fname Filename (For reporting)
int lineno Line number (For reporting)

 Good news – most of these fields have defaults!

 A typical register access only needs a few of these:
spi_rm.ctrl.write(status, wdata, .parent(this));
© 2011 Mentor Graphics Corp. Company Confidential
18 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Stimulus Examples – Base Class
class spi_bus_base_seq extends uvm_sequence #(uvm_sequence_item);

`uvm_object_utils(spi_bus_base_seq) Sequence base class contains variables

common to all register sequences:
// SPI Register model: • data, status
spi_reg_block spi_rm; • register model handle
// SPI env config object (contains register model handle)
spi_env_config m_cfg;

// Properties used by the various register access methods:

rand uvm_reg_data_t data; // For passing data
uvm_status_e status; // Returning access status

// Common functionality:
// Getting a handle to the register model
task body;
m_cfg = spi_env_config::get_config(m_sequencer);
spi_rm = m_cfg.spi_rm;
endtask: body

endclass: spi_bus_base_seq

© 2011 Mentor Graphics Corp. Company Confidential

19 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Stimulus Example: Set Divider Value
class div_load_seq extends spi_bus_base_seq;
Extends base sequence
`uvm_object_utils(div_load_seq) Randomizes data value with specific constraint
Writes data to divider register
// Interesting divisor values:
constraint div_values {data[15:0] inside {16'h0, 16'h1, 16'h2,
16'h4, 16'h8, 16'h10,
16'h20, 16'h40, 16'h80};}

task body;
super.body;
// Randomize the local data value
assert(this.randomize());
// Write to the divider register
spi_rm.divider_reg.write(status, data, .parent(this));
endtask: body

endclass: div_load_seq

© 2011 Mentor Graphics Corp. Company Confidential

20 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Sequence Example – TX Data Load
class data_load_seq extends spi_bus_base_seq;

`uvm_object_utils(data_load_seq) Extends the base class

Gets an array of register handles
uvm_reg data_regs[]; // Array of registers Randomizes the array index order
Foreach reg in the array:
task body; Randomize the content
super.body; Updates the register
// Set up the data register handle array
data_regs = '{spi_rm.rxtx0_reg, spi_rm.rxtx1_reg,
spi_rm.rxtx2_reg, spi_rm.rxtx3_reg};
// Randomize order
data_regs.shuffle();
foreach(data_regs[i]) begin
// Randomize register content and then update
assert(data_regs[i].randomize());
data_regs[i].update(status, .path(UVM_FRONTDOOR), .parent(this));
end

endtask: body

endclass: data_load_seq

© 2011 Mentor Graphics Corp. Company Confidential

21 TF - UVM Recipe of the Month 10/11 www.mentor.com
 How Do Front Door Register Accesses Work?

 When an explicit register access method is called

— The register access method forms a generic register
command:
– Address, Data, Read or Write
— This is then sent through a layering to the target bus agent
 The layering has to convert:
— Generic register requests to
target bus sequence items B

 This conversion takes place SQR

in the adapter
— Extended from uvm_reg_adapter
UVC(agent)

Monitor
RegSeq

Sequencer
DUT
Reg Driver

© 2011 Mentor Graphics Corp. Company Confidential

22 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Adapter Class Example
class reg2ahb_adapter extends uvm_reg_adapter;
`uvm_object_utils(reg2ahb_adapter)

function new(string name = "reg2ahb_adapter");

super.new(name); reg2bus() converts register item
endfunction to bus item – note single access only

virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);

ahb_seq_item ahb = ahb_seq_item::type_id::create("ahb");
ahb.HWRITE = (rw.kind == UVM_READ) ? AHB_READ : AHB_WRITE;
ahb.HADDR = rw.addr;
ahb.DATA = rw.data; bus2reg() converts bus item
return ahb; to reg item
endfunction

virtual function void bus2reg(uvm_sequence_item bus_item,

ref uvm_reg_bus_op rw);
ahb_seq_item ahb;
if (!$cast(ahb, bus_item)) begin
`uvm_fatal("NOT_AHB_TYPE","Provided bus_item is not of the correct type")
return;
end
rw.kind = (ahb.HWRITE == AHB_READ) ? UVM_READ : UVM_WRITE;
rw.addr = ahb.HADDR;
rw.data = ahb.DATA;
rw.status = UVM_IS_OK;
endfunction

endclass: reg2ahb_adapter
© 2011 Mentor Graphics Corp. Company Confidential
23 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Keeping The Register Model Up To Date

 Need to update register model with results of hardware

access
— This is referred to as prediction
 Two ways:
— Auto prediction
– Register model updates based on value written or read back
– OK in simple situations where only one way to access the DUT
registers
– Requires no additional components

— Explicit prediction (UVM Default)

– A predictor component:
– Observes bus analysis transactions
– Updates the register model on what it observes
– Works for normal to complex scenarios
– Supports hierarchical reuse

© 2011 Mentor Graphics Corp. Company Confidential

24 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Auto Prediction

 For ‘simple’ scenarios:

— Only sequences accessing the bus agent are register sequences
— Register can only be accessed via one bus
 The register model updates itself
— Based on value read or written to the register
 Has to be enabled – reg_model.set_auto_predict(1);
Breq
SQR

UVC(agent)

Monitor

RegSeq
Sequencer
Driver reg
Reg

© 2011 Mentor Graphics Corp. Company Confidential

25 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Explicit Prediction - Recommended

 Supports arbitrary complexity

 Predictor component updates register model
— Based on any detected bus transaction
— Regardless of origin
 Supports vertical reuse

Reg
Breq
SQR

UVC(agent)
Predictor
Monitor

RegSeq
Sequencer
Breq Driver Breq reg
Reg

© 2011 Mentor Graphics Corp. Company Confidential

26 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Explicit Prediction - Recommended
UVC(agent)
Predictor
Monitor

RegSeq
Sequencer
Driver

reg
SQR

UVC(agent)
Predictor
Monitor

RegSeq
Sequencer
Driver reg

© 2011 Mentor Graphics Corp. Company Confidential

27 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Model Testbench Integration
class spi_env extends uvm_env;
Register adapter specific to
apb_agent m_apb_agent; bus agent
spi_env_config m_cfg;
// Register layering adapter:
Predictor is a parameterised
reg2apb_adapter reg2apb;
uvm base class
// Register predictor:
uvm_reg_predictor #(apb_seq_item) apb2reg_predictor;

function void spi_env::connect_phase(uvm_phase phase);

if(m_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) begin
reg2apb = reg2apb_adapter::type_id::create("reg2apb");
// Register sequencer layering part:
m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb);
// Set the predictor map:
apb2reg_predictor.map = m_cfg.ss_rm.TOP_map; Predictor is integrated during
// Set the predictor adapter: the connect phase
apb2reg_predictor.adapter = reg2apb;
// Connect the predictor to the bus agent monitor analysis port
m_apb_agent.ap.connect(apb2reg_predictor.bus_in);
end
endfunction: connect

© 2011 Mentor Graphics Corp. Company Confidential

28 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Read And The Register Mirror

Before After  Read cycle results in the

mirrored mirrored
register model being
value value updated

desired desired
value value

hardware hardware
value value

Mirrored and desired Mirrored and desired

value out of step with value updated at the
hardware value end of the bus read cycle

© 2011 Mentor Graphics Corp. Company Confidential

29 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Write And The Register Mirror

Before During After

mirrored mirrored mirrored
value value value

desired desired desired

value value value

hardware hardware hardware

value value value

Initial state, hardware Hardware value Mirrored and desired

and reg model in sync changed by bus value updated at the
write cycle end of the write cycle

© 2011 Mentor Graphics Corp. Company Confidential

30 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Model Internal Access And Update()

 Indirect methods:
— Only access the register database
 reg.get(), reg.set(),
— Can be used on registers and fields
 reg.reset(), reg.get_reset()
— set/get the register or field reset value

 reg.update()
— Cause the hardware to be updated if register model content has
changed via reg.set(), reg.reset() or reg.randomize()
— Can specify front or back door access

 These methods set the desired value

© 2011 Mentor Graphics Corp. Company Confidential
31 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Write And The Register Mirror

Before set() update() After

mirrored mirrored mirrored mirrored
value value value value

desired desired desired desired

value value value value

hardware hardware hardware hardware

value value value value

Initial state, hardware Desired value changed Update() transfers Mirrored value updated
and reg model in sync by indirect access desired value to HW at the end of the
method (e.g. set()) via a write bus cycle write cycle

© 2011 Mentor Graphics Corp. Company Confidential

32 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Built-In Sequences

 Sequences are automatic

— Low overhead to use
— Useful for initial sanity checks on bus connectivity

 Access modes are respected

— e.g. Read only registers are not bit bashed
— Read only memories are not tested

 Memories, Registers or Fields can be opted out of a test

— e.g. Clock enable bit
— Mechanism is to use the uvm_resource_db to set an attribute for
the register

© 2011 Mentor Graphics Corp. Company Confidential

33 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Built-In Sequences
Sequence Name
uvm_reg_hw_reset_seq
uvm_reg_single_bit_bash_seq
uvm_reg_bit_bash_seq
uvm_reg_single_access_seq
uvm_reg_access_seq
uvm_reg_shared_access_seq
34 TF - UVM Recipe of the Month 10/11
Description
Checks register reset values
Checks R/W path to each register bit in a register
Runs single_bit_bash_seq on a register block
Checks that both front and back door accesses work
correctly for a register
Runs single_access_seq on a register block
If a register is in multiple maps, checks that accesses
can be made from each map
© 2011 Mentor Graphics Corp. Company Confidential
www.mentor.com
 Stimulus Reuse (Bridge Example)

 SPI master is integrated inside an AHB peripheral block

 Host bus sequences can reused as is
 Testbench structure changes

AHB to APB
Bridge
SPI Master
SPI Host Bus
Sequence AHB
APB
Bus Agent
APB SPI

Another DUT
Another DUT
APB ANI
Another DUT
APB ANI
APB ANI

© 2011 Mentor Graphics Corp. Company Confidential

35 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Stimulus Reuse Code Example
class spi_env extends uvm_env;

apb_agent m_apb_agent;
spi_env_config m_cfg;
// Register layering adapter:
reg2apb_adapter reg2apb;
// Register predictor:
uvm_reg_predictor #(apb_seq_item) apb2reg_predictor;

function void spi_env::connect_phase(uvm_phase phase);

if(m_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) begin
reg2apb = reg2apb_adapter::type_id::create("reg2apb");
// Register sequencer layering part:
m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb);
// Set the predictor map:
apb2reg_predictor.map = m_cfg.ss_rm.TOP_map;
// Set the predictor adapter:
apb2reg_predictor.adapter = reg2apb;
// Connect the predictor to the bus agent monitor analysis port
m_apb_agent.ap.connect(apb2reg_predictor.bus_in);
end
endfunction: connect

© 2011 Mentor Graphics Corp. Company Confidential

36 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Stimulus Reuse Code Example
class spi_env
io_ss_env
extends
extends
uvm_env;
uvm_env;

apb_agent
ahb_agent m_apb_agent;
m_ahb_agent;
spi_env_config
io_ss_env_configm_cfg;
m_cfg;
// Register layering adapter:
reg2apb_adapter
reg2ahb_adapter reg2apb;
reg2ahb;
// Register predictor:
uvm_reg_predictor #(apb_seq_item)
#(ahb_seq_item) apb2reg_predictor;
ahb2reg_predictor;

function void spi_env::connect_phase(uvm_phase phase);

if(m_cfg.m_apb_agent_cfg.active
if(m_cfg.m_ahb_agent_cfg.active == UVM_ACTIVE) begin
reg2apb
reg2ahb = reg2apb_adapter::type_id::create("reg2apb");
reg2ahb_adapter::type_id::create("reg2ahb");
// Register sequencer layering part:
m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer,
m_cfg.io_ss_rm.TOP_map.set_sequencer(m_ahb_agent.m_sequencer,
reg2apb);
reg2ahb);
// Set the predictor map:
apb2reg_predictor.map
ahb2reg_predictor.map = m_cfg.ss_rm.TOP_map;
m_cfg.io_ss_rm.TOP_map;
// Set the predictor adapter:
apb2reg_predictor.adapter
ahb2reg_predictor.adapter = reg2apb;
reg2ahb;
// Connect the predictor to the bus agent monitor analysis port
m_apb_agent.ap.connect(apb2reg_predictor.bus_in);
m_ahb_agent.ap.connect(ahb2reg_predictor.bus_in);
end
endfunction: connect

© 2011 Mentor Graphics Corp. Company Confidential

37 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Register Stimulus Reuse: Set Divider Value

class div_load_seq extends spi_bus_base_seq;

`uvm_object_utils(div_load_seq)

// Interesting divisor values:

constraint div_values {data[15:0] inside {16'h0, 16'h1, 16'h2,
16'h4, 16'h8, 16'h10,
16'h20, 16'h40, 16'h80};}

task body; Extends base sequence which gets register

super.body; model handle from config object.
// Randomize the local data value Sequence works as before but via the AHB agent
assert(this.randomize());
// Write to the divider register
spi_rm.divider_reg.write(status, data, .parent(this));
endtask: body

endclass: div_load_seq

© 2011 Mentor Graphics Corp. Company Confidential

38 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Stimulus Reuse Layer II – Across Fabric

SPI Host Bus

Sequence

AHB to APB
Bridge
AXI SPI Master
Bus
Fabric APB SPI
AXI AXI
Bus Agent 2
AHB
Bridge

© 2011 Mentor Graphics Corp. Company Confidential

39 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Relevant Parts Of Top Level Environment

class sys_env extends uvm_env;

axi_agent m_axi_agent;
sys_env_config m_cfg;
// Register layering adapter:
reg2ahb_adapter reg2axi;
// Register predictor:
uvm_reg_predictor #(axi_seq_item) axi2reg_predictor;

function void spi_env::connect_phase(uvm_phase phase);

if(m_cfg.m_axi_agent_cfg.active == UVM_ACTIVE) begin
reg2axi = reg2axi_adapter::type_id::create("reg2axi");
// Register sequencer layering part:
m_cfg.sys_rm.TOP_map.set_sequencer(m_axi_agent.m_sequencer, reg2axi);
// Set the predictor map:
axi2reg_predictor.map = m_cfg.sys_rm.TOP_map;
// Set the predictor adapter:
axi2reg_predictor.adapter = reg2axi;
// Connect the predictor to the bus agent monitor analysis port
m_axi_agent.ap.connect(axi2reg_predictor.bus_in);
end
endfunction: connect
© 2011 Mentor Graphics Corp. Company Confidential
40 TF - UVM Recipe of the Month 10/11 www.mentor.com
 UVM Register Package Works with OVM
`include “ovm_macros.svh”
`include “uvm_reg_macros.svh”
import ovm_pkg::*;
import uvm_reg_pkg::*;

class sys_env extends ovm_env;

axi_agent m_axi_agent;
sys_env_config m_cfg;
// Register layering adapter:
reg2ahb_adapter reg2axi;
// Register predictor:
uvm_reg_predictor #(axi_seq_item) axi2reg_predictor;

function void spi_env::connect();

if(m_cfg.m_axi_agent_cfg.active == UVM_ACTIVE) begin
reg2axi = reg2axi_adapter::type_id::create("reg2axi");
// Register sequencer layering part:
m_cfg.sys_rm.TOP_map.set_sequencer(m_axi_agent.m_sequencer, reg2axi);
// Set the predictor map:
axi2reg_predictor.map = m_cfg.sys_rm.TOP_map;
// Set the predictor adapter:
axi2reg_predictor.adapter = reg2axi;
// Connect the predictor to the bus agent monitor analysis port
m_axi_agent.ap.connect(axi2reg_predictor.bus_in);
end
endfunction: connect

© 2011 Mentor Graphics Corp. Company Confidential

41 TF - UVM Recipe of the Month 10/11 www.mentor.com
 UVM Register Summary
 Register model follows hardware structure
— Fields, Registers, Blocks, Maps
 Register model generator available:
— Certe Register Assistant
 Register access API:
— Internal access – get(), set() etc
– Sets up desired value
— External access – Front and Backdoor
 Access layered via model
— Generic sequences adapted to target bus sequences
— Sequence reuse straight-forward
 Use explicit prediction
 Built in sequences available for initial testing
 Works with OVM
© 2011 Mentor Graphics Corp. Company Confidential
42 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Verification Academy—Provide the necessary skills that enable
you to take advantage of today’s latest, advanced functional
verification techniques.

Wide Variety of Topics

•Verification Planning
•ABV •CDC •FPGA Verification
•Basic and Advanced UVM/OVM
•Intelligent Testbench Automation
•SystemVerilog Testbench Acceleration

New UVM/OVM Online Methodology Cookbook Available too!

© 2011 Mentor Graphics Corp. Company Confidential

43 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Online Documentation - UVM/OVM Cookbook
 UVM/OVM docs
 Comment-able
 PDF printed
books
 Real code
examples

© 2011 Mentor Graphics Corp. Company Confidential

44 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Three Industry Leading Platforms
 Vista
— Architectural Design, Analysis, Transactions Transistors
Verification, and Virtual
Prototyping

 Questa
— Highest Performance with Questa
Support for TLM through
Transistor
— Unique Technologies
Combined for 100X in
Verification Per Cycle
— Unified Coverage Tracking and
Verification Process
Management
Vista Veloce
 Veloce
— Hardware Assisted Verification
Platform for Both Acceleration
and Emulation UVM / OVM

ESL Em ulation
© 2011 Mentor Graphics Corp. Company Confidential
45 TF - UVM Recipe of the Month 10/11 www.mentor.com
 Future Recipe of the Month Webinars

 More UVM Registers: November, 2011

— How to write scoreboards and functional coverage at the register
level
— Implementing “Quirky” Registers
— Register-layer coverage model
— Implementing “back-door” register accesses
— Scoreboarding at the register layer
 Configuring your UVM Testbench: December, 2011
— UVM Configuration Database Overview
— Desiginging Configuration Objects
— Configuration Reuse

Register at http://www.mentor.com/products/fv/series/uvm-ovm-series
© 2011 Mentor Graphics Corp. Company Confidential
46 TF - UVM Recipe of the Month 10/11 www.mentor.com
© 2011 Mentor Graphics Corp. Company Confidential
www.mentor.com