5 4 3 2 1

NOTES: REV DATE PAGES DESCRIPTION

1. Project Drawing Numbers: A1 Jun 19 2015 All Initial Revision A Release.
Raw PCB 100-0321404-A1.1 A1.1 Sep 15 2015 1 Update block diagram.
Gerber Files 110-0321404-A1.1 2 Update power tree.
PCB Design Files 120-0321404-A1.1 10 Delete C12.
Assembly Drawing 130-0321404-A1.1 18 Add note for SW2.4 MAX10_BYPASSn.
Fab Drawing 140-0321404-A1.1
Schematic Drawing 22 Change the value of C219 from DNI to 47uF.
150-0321404-A1.1
PCB Film 160-0321404-A1.1 23 Add R315 to 1.2V_VCCIO.
25 Change the value of C232 from 100uF to DNI.
D Bill of Materials
Schematic Design Files
170-0321404-A1.1
180-0321404-A1.2 A1.2 Dec 23 2015 10 Change LPDDR2_IS43LD16640A-3BL(333MHz part) to IS43LD16640A-25BL (400MHz part) D
Functional Specification 210-0321404-A1.1 due to Altera IP recommendation.
PCB Layout Guidelines 220-0321404-A1.1
Assembly Rework 320-0321404-A1.1

MAX 10 FPGA 10M50 Evaluation Kit Board

HDMI CONN PAGE DESCRIPTION
1 Title, Notes, Block Diagram, Rev. History
2 Power Tree
3 Clock Tree
C 512Mb QSPI C
PMOD x 2 ADV7513 User GPIO 4 MAX10 Banks 1 & 2
Flash
5 MAX10 Banks 3 & 4
6 MAX10 Banks 5 & 6

x31
x7 x10

x16
7 MAX10 Banks 7 & 8
8 MAX10 Clocks
9 MAX10 Configuration
Mini-USB 10 LPDDR2 SDRAM
On-Board x19 USB Interface
2.0 USB BlasterTM II 11 MIPI CSI-2 Tx D-PHY LI-USB3
& USB Interface
12 MIPI CSI-2 Rx D-PHY OV10640
13 MIPI CSI-2 Rx D-PHY OV5640
JTAG x5 JTAG x36 1Gb LPDDR2 14 HDMI (VIDEO ONLY)
Header (x16)
15 On-Board USB Blaster II -1
B B
16 On-Board USB Blaster II -2
17 PMOD, GPIO, LVDS UserIO
MIPI CSI-2 TX D-PHY 18 Pushbutton, Switch, LED
x31 x4
(interface LI-MIPI-USB3- Buttons 19 Clocking
x6
TESTER module) 10M50 F484 Package Switches 20 QSPI Flash
x5
LEDs 21 Hot Swap and Power 3.3 V
x5 22 Power 2.5 V & 1.8V
Oscillators
23 Power 1.2V
(50M + programmable)
24 MAX 10 Power & Ground
x22 x16
x29

25 Decoupling

A User LVDS I/O Array MIPI CSI-2 RX D-PHY
(interface OV10640 module)
MIPI CSI-2 RX D-PHY A
(interface OV5640 module)
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

B <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 1 of 25

5 4 3 2 1
 5 4 3 2 1

POWER TREE
5.0V  @  55m A
D C_IN 5V_H D M I @  55m A

D             ( 5V@  10W  ) 3.3V_O V 5640 @  182m A D

3.3V_O V 10640 @  145m A
3.3V  @  820m A 3.3V_PM O D @  200m A
E N 5329Q I
3 3.3V_AD V7513@  0.5m A
2A
3.3V_CY7C68013A @  85m A
55 m m 2 3.3V_VCCIO _M AXII @  9m A
3.3V_VCCIO _M AX10 @  16.5m A
3.3V_Si510 @  26 m A
3.3V_Si5338_VD D  @ 60 m A
3.3V_Si5338_VD D O  @  96 m A

2.5V_VCCA @  61m A
Pow er U P SequencIng 2.5V  @  221m A
E P 5348U I 2.5V_VCCIO _M AX10 @  71m A
‐ 5V available to all regulators through D C plug or U SB cable 4
C   
0.4A C
        1.8V
1 2.5V_VCCIN T_M AXII @  84m A
14 m m 2
        1.2V_VCCIO
2 _M AX10, 1.2V_LPD DR2_VD D 2.5V_VCCIO _M AXII @  4.41m A

        3.3V
3

        2.5V 
4 1.8V_VCCIO _M AX10 @  2.81m A
        1.2V_VCC_M AX10, 1.2V_VCCD _PLL_M AX10,  
E P 5358 H U I 1.8V  @  192m A
5 1 0.6A
        1.2V_VCCIN T_M AX10 1.8V_O V 10640 @ 40m A

14 m m 2 1.8V_AD V7513 @  143m A

1.8V_LPDD R2_VD D @  6m A

B B

E N 5339Q I 1.2V  @  1557m A 1.2V_VCC_M AX10 @  1511m A

5
3A

55 m m 2
1.2V_VCCD_PLL_M AX10 @  45m A

1.2V_VCCIN T_M AX10 @  0.02m A

E P 5348U I 1.2V @  243m A 1.2V_VCCIO _M AX10 @  32.5m A

2
0.4A
A 1.2V_LPDD R2_VD D @  210m A A
14 m m 2

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 2 of 25

 5 4 3 2 1

CLOCK TREE

2
D Cypress
Cypress D
USB_CLK CLK50M_MAXII
CY7C68013A
CY7C68013A
USB Controller
USB Controller

3
On-Board Si510
FA‐128 USB BlasterTM II
24MHz XTAL 50MHz Osc
4
CLK50M_MAX10

               Default  LVCMOS 100MHz CLK3
             Default  LVCMOS 125MHz CLK2
Si5338
8 7
8Y‐25MHz         Default LVCMOS 24MHz CLK1
C XTAL C
Default  LVCMOS24MHz CLK0

 1A
CLK125M

6
CLK100M_LPDDR2

1B
CLK24M

5
MIPI_TX_CLKP
MIPI_TX_CLK24MHz *
B MIPI LI‐USB3.0 Tester MIPI_TX_CLKN B

3 4

OV10640_HS_CLKN
OV10640_HS_CLKP
OV5640_HS_CLKP
OV5640_HS_CLKN
CLKOUT_LVDS_P
Note *: Not included, purchase  CLKOUT_LVDS_N User LVDS I/O
and assembly required

OV5640_CLK24MHz MIPI CSI‐2 Camera Module MIPI CSI‐2 Camera Module

A OV5640 * OV10640 * A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 3 of 25

 5 4 3 2 1

MAX10 BANKS 1 & 2

MAX10 USB Interface

D USB_DATA[7:0] 16 D
USB_ADDR[1:0] 16
USB_FULL 16
USB_EMPTY 16
USB_SCL 16
USB_SDA 16
USB_RESETn 15
U1A USB_OEn 16

MAX 10 LEFT BANKS USB_RDn 16

USB_WRn 15
BANK-1A ( VCCIO = 3.3V ) BANK-2 ( VCCIO = 1.8V )
USER_DIPSW5 F5 P4 OV10640_CMOS_RST
USB_FULL F4 DIFFIO_RX_L1N/ADC1IN1 DIFFIO_RX_L29N P5 OV10640_CMOS_SCLK
USB_DATA2 E4 DIFFIO_RX_L1P/ADC1IN2 DIFFIO_RX_L29P N3 MIPI_TX_CMOS_SCLK_1V8
OV5640 CSI-2 RX Interface
USB_DATA3 E3 DIFFIO_RX_L2N/ADC2IN1 DIFFIO_RX_L37N N2 MIPI_TX_CMOS_SDATA_1V8
J8 DIFFIO_RX_L2P/ADC2IN8 DIFFIO_RX_L37P R4 OV10640_G_RDY OV5640_CAM_PWRON
DIFFIO_RX_L3N/ADC1IN3 DIFFIO_RX_L39N 13
J9 R5 OV10640_XM_INT2
USER_DIPSW4 G4 DIFFIO_RX_L3P/ADC1IN4 DIFFIO_RX_L39P T1 MIPI_TX_DATA_HS_N2 OV5640_SDC
DIFFIO_RX_L4N/ADC2IN3 DIFFIO_RX_L40N 13
USB_EMPTY F3 T2 MIPI_TX_DATA_HS_P2
USB_DATA6 H3 DIFFIO_RX_L4P/ADC2IN4 DIFFIO_RX_L40P N8 OV10640_CMOS_SDATA OV5640_SDA
DIFFIO_RX_L5P/ADC1IN6 DIFFIO_RX_L41N 13
USB_RDn J4 N9 OV10640_GYRO_INT
C USB_DATA0 H4 DIFFIO_RX_L5N/ADC1IN5 DIFFIO_RX_L41P P1 MIPI_TX_DATA_HS_N1 OV5640_CAM_RESETB 13
C
USB_ADDR1 G3 DIFFIO_RX_L6N/ADC2IN5 DIFFIO_RX_L42N N1 MIPI_TX_DATA_HS_P1
K5 DIFFIO_RX_L6P/ADC2IN6 DIFFIO_RX_L42P T3 MIPI_TX_CMOS_RST_1V8
K6 DIFFIO_RX_L7N/ADC1IN7 DIFFIO_RX_L43N U2 MIPI_TX_GPIO2
USB_DATA7 J3 DIFFIO_RX_L7P/ADC1IN8 DIFFIO_RX_L43P U1 MIPI_TX_DATA_HS_N3
K4 DIFFIO_RX_L8P/ADC2IN2 DIFFIO_RX_L44N V1 MIPI_TX_DATA_HS_P3
DIFFIO_RX_L8N/ADC2IN7 DIFFIO_RX_L44P U4 MIPI_TX_GPIO3
OV10640 CSI-2 RX Interface
DIFFIO_RX_L45N U5 MIPI_TX_GPIO4 1.8V
( VCCIO = 3.3V ) DIFFIO_RX_L45P U3 MIPI_TX_GPIO1 OV10640_CMOS_RST
BANK-1B DIFFIO_RX_L46N 12
K8 V3 MIPI_TX_GPIO5
USB_SDA D3 DIFFIO_RX_L15N DIFFIO_RX_L46P P8 OV10640_FSIN OV10640_CMOS_SCLK
DIFFIO_RX_L16N DIFFIO_RX_L47N 12
USB_SCL D2 R7 OV10640_XM_INT1
USB_RESETn K2 DIFFIO_RX_L16P DIFFIO_RX_L47P W1 MIPI_TX_DATA_HS_N4 VREF_1V8HSTL R1 OV10640_CMOS_SDATA
DIFFIO_RX_L19N DIFFIO_RX_L48N 12
OV5640_CAM_PWRON L2 W2 MIPI_TX_DATA_HS_P4 VREF_1V8HSTL
L8 DIFFIO_RX_L19P DIFFIO_RX_L48P R1 MIPI_TX_CLK_HS_N 1.00k OV10640_GYRO_INT
DIFFIO_RX_L20N DIFFIO_RX_L60N 12
L9 R2 MIPI_TX_CLK_HS_P
USB_ADDR0 E1 DIFFIO_RX_L20P DIFFIO_RX_L60P M2 OV10640_G_RDY
DIFFIO_RX_L21N VREFB2N0 12
USB_OEn F2 M1
USB_DATA5 H1 DIFFIO_RX_L21P TBD2 OV10640_XM_INT2
DIFFIO_RX_L22N 12
USB_WRn J1 C1 C3 R2
USB_DATA4 G1 DIFFIO_RX_L22P 0.1uF OV10640_XM_INT1
DIFFIO_RX_L23N 12
USB_DATA1 F1 0.1uF 1.00k
OV5640_CAM_RESETB M4 DIFFIO_RX_L23P OV10640_FSIN
DIFFIO_RX_L24N 12
OV5640_SDC M3
JTAG_SAFE K1 DIFFIO_RX_L24P
OV5640_SDA L1 DIFFIO_RX_L25N
C1 DIFFIO_RX_L25P
D1 VREFB1N0 LI-USB3 CSI-2 TX Interface
TBD1
B MIPI_TX_CLK_HS_P 11
B
10M50DAF484 MIPI_TX_CLK_HS_N 11
MIPI_TX_DATA_HS_P[1:4] 11
MIPI_TX_DATA_HS_N[1:4] 11
MIPI_TX_CMOS_RST_1V8 11
MIPI_TX_CMOS_SCLK_1V8 11
MIPI_TX_CMOS_SDATA_1V8 11
MIPI_TX_GPIO1 11
MIPI_TX_GPIO2 11
MIPI_TX_GPIO3 11
MIPI_TX_GPIO4 11
MIPI_TX_GPIO5 11

Misc
JTAG_SAFE 15

A User DIP Switch A

USER_DIPSW[4:5] 18

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 4 of 25

 5 4 3 2 1

MAX10 BANKS 3 & 4

D D

U1B

MAX 10 BOTTOM BANKS User LVDS IO

BANK-3 ( VCCIO = 2.5V ) BANK-4 ( VCCIO = 2.5V ) USER_LVDS_P[0:8] 17

Y7 W11
Y8 DIFFIO_RX_B10N DIFFIO_RX_B25N Y11 USER_LVDS_N[0:8]
DIFFIO_RX_B10P DIFFIO_RX_B25P 17
MIPI_TX_DATA_LP_N2 AB2 AB10 OV5640_DATA_HS_N2
MIPI_TX_DATA_LP_P2 AB3 DIFFIO_RX_B12N DIFFIO_RX_B27N AB11 OV5640_DATA_HS_P2
Y3 DIFFIO_RX_B12P DIFFIO_RX_B27P AB12 OV5640_DATA_HS_N1
Y4 DIFFIO_RX_B14N DIFFIO_RX_B29N AB13 OV5640_DATA_HS_P1
MIPI_TX_DATA_LP_N3 AA5 DIFFIO_RX_B14P DIFFIO_RX_B29P W12
OV10640 Interface
MIPI_TX_DATA_LP_P3 AB5 DIFFIO_RX_B17N DIFFIO_RX_B35N W13
MIPI_TX_DATA_LP_N4 AB6 DIFFIO_RX_B17P DIFFIO_RX_B35P AA14 OV10640_DATA_HS_P[1:4]
DIFFIO_RX_B19N DIFFIO_RX_B38N 12
MIPI_TX_DATA_LP_P4 AB7 AB15
AA8 DIFFIO_RX_B19P DIFFIO_RX_B38P AA15 OV10640_DATA_HS_N[1:4]
DIFFIO_RX_B21N DIFFIO_RX_B40N 12
AB8 Y16
AA9 DIFFIO_RX_B21P DIFFIO_RX_B40P AB16 OV10640_DATA_HS_N4
C AB9 DIFFIO_RX_B23N DIFFIO_RX_B42N AA16 OV10640_DATA_HS_P4 C
MIPI_TX_DATA_LP_N1 V4 DIFFIO_RX_B23P DIFFIO_RX_B42P AB19 OV10640_DATA_HS_N2
MIPI_TX_DATA_LP_P1 V5 DIFFIO_RX_B2N DIFFIO_RX_B44N AB20 OV10640_DATA_HS_P2
OV5640 Interface
MIPI_TX_CLK_LP_N Y1 DIFFIO_RX_B2P DIFFIO_RX_B44P AA19
MIPI_TX_CLK_LP_P Y2 DIFFIO_RX_B4N DIFFIO_RX_B46N Y18 OV5640_DATA_HS_P[1:2]
DIFFIO_RX_B4P DIFFIO_RX_B46P 13
AA1 AB21 OV10640_DATA_HS_N1
AA2 DIFFIO_RX_B6N DIFFIO_RX_B50N AA20 OV10640_DATA_HS_P1 OV5640_DATA_HS_N[1:2]
DIFFIO_RX_B6P DIFFIO_RX_B50P 13
Y5 AB17 OV10640_DATA_HS_N3
Y6 DIFFIO_RX_B8N DIFFIO_RX_B58N AB18 OV10640_DATA_HS_P3
USER_LVDS_N4 W9 DIFFIO_RX_B8P DIFFIO_RX_B58P V11
USER_LVDS_P4 W10 DIFFIO_TX_RX_B11N DIFFIO_TX_RX_B24N V12
USER_LVDS_N1 W7 DIFFIO_TX_RX_B11P DIFFIO_TX_RX_B24P R12
USER_LVDS_P1 W8 DIFFIO_TX_RX_B13N DIFFIO_TX_RX_B26N P12
LI-USB3 CSI-2 TX Interface
R10 DIFFIO_TX_RX_B13P DIFFIO_TX_RX_B26P AA11
P10 DIFFIO_TX_RX_B15N DIFFIO_TX_RX_B28N AA12 MIPI_TX_CLK_LP_P
DIFFIO_TX_RX_B15P DIFFIO_TX_RX_B28P 11
USER_LVDS_N8 AA6 V13
USER_LVDS_P8 AA7 DIFFIO_TX_RX_B16N DIFFIO_TX_RX_B34N W14 MIPI_TX_CLK_LP_N
DIFFIO_TX_RX_B16P DIFFIO_TX_RX_B34P 11
USER_LVDS_N6 W5 R13
USER_LVDS_P6 W6 DIFFIO_TX_RX_B1N DIFFIO_TX_RX_B36N P13 MIPI_TX_DATA_LP_P[1:4]
DIFFIO_TX_RX_B1P DIFFIO_TX_RX_B36P 11
USER_LVDS_N0 Y10 Y13 USER_LVDS_N3
USER_LVDS_P0 AA10 DIFFIO_TX_RX_B22N DIFFIO_TX_RX_B37N Y14 USER_LVDS_P3 MIPI_TX_DATA_LP_N[1:4]
DIFFIO_TX_RX_B22P DIFFIO_TX_RX_B37P 11
U6 V14
U7 DIFFIO_TX_RX_B3N DIFFIO_TX_RX_B39N W15
USER_LVDS_N7 W4 DIFFIO_TX_RX_B3P DIFFIO_TX_RX_B39P U15
USER_LVDS_P7 W3 DIFFIO_TX_RX_B5N DIFFIO_TX_RX_B41N V16
USER_LVDS_N5 V7 DIFFIO_TX_RX_B5P DIFFIO_TX_RX_B41P AA17 USER_LVDS_N2
USER_LVDS_P5 V8 DIFFIO_TX_RX_B7N DIFFIO_TX_RX_B43N Y17 USER_LVDS_P2
R9 DIFFIO_TX_RX_B7P DIFFIO_TX_RX_B43P V15
P9 DIFFIO_TX_RX_B9N DIFFIO_TX_RX_B45N W16
B AA3 DIFFIO_TX_RX_B9P
VREFB3N0
DIFFIO_TX_RX_B45P
DIFFIO_TX_RX_B49N
Y19 B
AB4 W18
TBD3 DIFFIO_TX_RX_B49P AA13
VREFB4N0 AB14
TBD4

10M50DAF484

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 5 of 25

 5 4 3 2 1

MAX10 BANKS 5 & 6

D D
U1C LPDDR2 Interface
MAX 10 RIGHT BANKS LPDDR2_CA[0:9] 10
1.2V_VCCIO BANK-5 ( VCCIO = 1.2V ) BANK-6 ( VCCIO = 1.2V ) LPDDR2_DQ[0:15] 10
USER_DIPSW3 U19 H21 LPDDR2_CA3
V18 DIFFIO_RX_R19N DIFFIO_RX_R39N H22 LPDDR2_CA4 LPDDR2_DM[0:1]
DIFFIO_RX_R19P DIFFIO_RX_R39P 10
R7 47.5 MAX10_RUP U18 J21 LPDDR2_CA1
R8 47.5 MAX10_RDN U17 DIFFIO_RX_R1P/RUP DIFFIO_RX_R41N J22 LPDDR2_CA0 LPDDR2_CSn
DIFFIO_RX_R1N/RDN DIFFIO_RX_R41P 10
OV10640_DATA_LP_N3 W22 G19
OV10640_DATA_LP_P3 Y22 DIFFIO_RX_R20N DIFFIO_RX_R42N G20 LPDDR2_CKE
DIFFIO_RX_R20P DIFFIO_RX_R42P 10
OV5640_DATA_LP_N1 W20 F22 LPDDR2_CA2
OV5640_DATA_LP_P1 W19 DIFFIO_RX_R21N DIFFIO_RX_R43N G22 LPDDR2_CSn LPDDR2_CKn
DIFFIO_RX_R21P DIFFIO_RX_R43P 10
USER_PB2 Y21 M14 LPDDR2_DQ3
USER_PB1 Y20 DIFFIO_RX_R22N DIFFIO_RX_R44N/DQ2R M15 LPDDR2_DQ5 LPDDR2_CK
DIFFIO_RX_R22P DIFFIO_RX_R44P/DQ2R 10
USER_PB3 U20 E21 LPDDR2_CKE
V20 DIFFIO_RX_R23N DIFFIO_RX_R45N E22 LPDDR2_CA7 LPDDR2_DQS1
DIFFIO_RX_R23P DIFFIO_RX_R45P 10
OV10640_DATA_LP_N2 V22 N19 LPDDR2_DM0
OV10640_DATA_LP_P2 V21 DIFFIO_RX_R24N DIFFIO_RX_R46N/DM2R N18 LPDDR2_DQ0 LPDDR2_DQS1n
DIFFIO_RX_R24P DIFFIO_RX_R46P/DQ2R 10
OV5640_CLK_LP_N R14 M20 LPDDR2_DQ2
OV5640_CLK_LP_P R15 DIFFIO_RX_R25N/DQ1R DIFFIO_RX_R47P/DQ2R N20 LPDDR2_DQ1
DIFFIO_RX_R25P/DQ1R DIFFIO_RX_R47N/DQ2R
OV10640_CLK_LP_N T22
DIFFIO_RX_R26N DIFFIO_RX_R48N
F20 F21 and F20 are restricted pins OV10640 Interface
OV10640_CLK_LP_P T21 F21 while implementating LPDDR2.
USER_DIPSW2 T18 DIFFIO_RX_R26P DIFFIO_RX_R48P C22 LPDDR2_CA6
USER_DIPSW1 T19 DIFFIO_RX_R27N/DM1R DIFFIO_RX_R49N D22 LPDDR2_CA5 OV10640_CLK_LP_P
DIFFIO_RX_R27P/DQ1R DIFFIO_RX_R49P 12
USER_PB0 R20 L18 LPDDR2_DQ7
C T20 DIFFIO_RX_R28N/DQ1R DIFFIO_RX_R51N/DQ2R M18 LPDDR2_DQ4 OV10640_CLK_LP_N 12
C
DIFFIO_RX_R28P/DQ1R DIFFIO_RX_R51P/DQ2R
U22 and U21 are restricted pins U22
DIFFIO_RX_R29N DIFFIO_RX_R52N/DQ2R
L20 LPDDR2_DQ6
while implementating LPDDR2. U21
DIFFIO_RX_R29P DIFFIO_RX_R52P/DQ2R
L19 OV10640_DATA_LP_P[1:4] 12
OV10640_DATA_LP_N4 AA22
DIFFIO_RX_R2N DIFFIO_RX_R53N
F18 F18 and E19 are restricted pins
OV10640_DATA_LP_P4 AA21 E19 while implementating LPDDR2. OV10640_DATA_LP_N[1:4]
DIFFIO_RX_R2P DIFFIO_RX_R53P 12
OV5640_DATA_LP_N2 P14 E20
OV5640_DATA_LP_P2 P15 DIFFIO_RX_R30N/DQ1R DIFFIO_RX_R54N F19
OV10640_DATA_LP_N1 N22 DIFFIO_RX_R30P/DQ1R DIFFIO_RX_R54P K15 LPDDR2_DQS1n
OV10640_DATA_LP_P1 P21 DIFFIO_RX_R31N DIFFIO_RX_R55N/DQSN3R K14 LPDDR2_DQS1
P18 DIFFIO_RX_R31P DIFFIO_RX_R55P/DQS3R D19
USER_DIPSW0 R18 DIFFIO_RX_R32N/DQSN1R DIFFIO_RX_R56N C20
OV5640 Interface
P20 DIFFIO_RX_R32P/DQS1R DIFFIO_RX_R56P J18 LPDDR2_DQ15
P19 DIFFIO_RX_R33N/DQ1R DIFFIO_RX_R57N/DQ3R K18 LPDDR2_DQ10 OV5640_CLK_LP_P
DIFFIO_RX_R33P/DQ1R DIFFIO_RX_R57P/DQ3R 13
L22 and M21 are restricted pins L22
DIFFIO_RX_R34N DIFFIO_RX_R58N/DQ3R
K20 LPDDR2_DQ8
while implementating LPDDR2. M21 K19 LPDDR2_DQ9 OV5640_CLK_LP_N
DIFFIO_RX_R34P DIFFIO_RX_R58P/DQ3R 13
M22
DIFFIO_RX_R35N DIFFIO_RX_R59N
E17 E17 and F17 are restricted pins
VREF_1V2HSTL N21
DIFFIO_RX_R35P DIFFIO_RX_R59P
F17 while implementating LPDDR2. OV5640_DATA_LP_P[1:2] 13
P22 B21
R22 VREFB5N0 DIFFIO_RX_R60N B22 LPDDR2_CA9 OV5640_DATA_LP_N[1:2]
TBD5 DIFFIO_RX_R60P 13
J15 LPDDR2_DM1
DIFFIO_RX_R61N/DM3R J14 LPDDR2_DQ14
DIFFIO_RX_R61P/DQ3R A21 LPDDR2_CA8
DIFFIO_RX_R62N B20
DIFFIO_RX_R62P H18 LPDDR2_DQ13
User DIP Switch
DIFFIO_RX_R63N/DQ3R H19 LPDDR2_DQ11
DIFFIO_RX_R63P/DQ3R H20 LPDDR2_DQ12 USER_DIPSW[0:3]
DIFFIO_RX_R64N/DQ3R 18
J20 VREF_LPDDR2
DIFFIO_RX_R64P/DQ3R E18 LPDDR2_CKn
DIFFIO_RX_R70N/CK#_6 D18 LPDDR2_CK
B DIFFIO_RX_R70P/CK_6
VREFB6N0
D21 User Pushbuttons B
C21
TBD6
USER_PB[0:3] 18
10M50DAF484

Reference Voltages of 1.2V HSTL and LPDDR2

1.2V_VCCIO 1.2V_VCCIO

C4 R9 C6 R10
1.00k 1.00k
VREF_1V2HSTL 0.1uF VREF_LPDDR2 0.1uF

C8 R11 C9 R12
1.00k 1.00k
A 0.1uF 0.1uF A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 6 of 25

 5 4 3 2 1

MAX10 BANKS 7 & 8

D D

U1D

MAX 10 TOP BANKS User IO

BANK-7 ( VCCIO = 3.3V ) BANK-8 ( VCCIO = 3.3V ) USER_IO[0:9] 17

USER_IO0 A17 C7 USER_LED4
HDMI_INTR A18 DIFFIO_RX_T10N DIFFIO_RX_T39N C8 PMODB_D0
HDMI_VIDEO_DIN7 C15 DIFFIO_RX_T10P DIFFIO_RX_T39P A6 PMODA_D0
HDMI_SCL C16 DIFFIO_RX_T15N DIFFIO_RX_T41N B7 PMODA_D4
HDMI_VIDEO_DIN6 A16 DIFFIO_RX_T15P DIFFIO_RX_T41P D8 PMODB_D1
HDMI_VIDEO_DIN5 B16 DIFFIO_RX_T16N DIFFIO_RX_T42P A4 PMODA_D6
PMOD
HDMI_VIDEO_DATA_EN J13 DIFFIO_RX_T16P DIFFIO_RX_T43N A5 PMODA_D3 PMODA_D[7:0]
DIFFIO_RX_T17N DIFFIO_RX_T43P 17
HDMI_VSYNC H14 E9 PMODA_D5
HDMI_VIDEO_DIN20 C13 DIFFIO_RX_T17P DIFFIO_RX_T44N A2 PMODB_D3 PMODB_D[7:0]
DIFFIO_RX_T18N DIFFIO_RX_T45P 17
HDMI_VIDEO_DIN17 C14 A3 PMODB_D2
HDMI_VIDEO_DIN8 B14 DIFFIO_RX_T18P DIFFIO_RX_T45N B3 PMODB_D4
HDMI_VIDEO_DIN9 A14 DIFFIO_RX_T19N DIFFIO_RX_T46P B4 PMODA_D2
HDMI_VIDEO_DIN21 E15 DIFFIO_RX_T19P DIFFIO_RX_T46N B5 PMODA_D7
USER_IO2 E16 DIFFIO_RX_T1N DIFFIO_RX_T47P C4 USER_LED1
HDMI_VIDEO_DIN3 E13 DIFFIO_RX_T1P DIFFIO_RX_T47N E8 PMODA_D1
HDMI TX
HDMI_VIDEO_DIN19 D14 DIFFIO_RX_T20N DIFFIO_RX_T48P D5 USER_LED3
HDMI_VIDEO_DIN2 E12 DIFFIO_RX_T20P DIFFIO_RX_T49N C5 USER_LED2
C HDMI_VIDEO_DIN1 D13 DIFFIO_RX_T21P DIFFIO_RX_T49P B1 PMODB_D6
HDMI_VIDEO_DIN[23:0] 14 C
HDMI_VIDEO_DIN0 J12 DIFFIO_RX_T21N DIFFIO_RX_T51N B2 PMODB_D7 HDMI_HSYNC
DIFFIO_RX_T22N DIFFIO_RX_T51P 14
HDMI_HSYNC H13 C2 PMODB_D5
HDMI_VIDEO_DIN12 A12 DIFFIO_RX_T22P DIFFIO_RX_T53N C3 USER_LED0 HDMI_VSYNC
DIFFIO_RX_T23N DIFFIO_RX_T53P 14
HDMI_VIDEO_DIN10 A13 D7
HDMI_VIDEO_DIN4 D12 DIFFIO_RX_T23P VREFB8N0 C6 HDMI_VIDEO_DATA_EN
DIFFIO_RX_T24N TBD8 14
HDMI_VIDEO_DIN13 C12
HDMI_VIDEO_DIN16 A10 DIFFIO_RX_T24P HDMI_INTR
DIFFIO_RX_T25N 14
HDMI_VIDEO_DIN14 A11
FLASH_D1 C10 DIFFIO_RX_T25P HDMI_SDA
DIFFIO_RX_T26N 14
FLASH_D2 C11
HDMI_VIDEO_DIN15 B11 DIFFIO_RX_T26P HDMI_SCL
DIFFIO_RX_T27N 14
HDMI_VIDEO_DIN11 B12
MIPI_TX_CMOS_SCLK_3V3 J11 DIFFIO_RX_T27P
MIPI_TX_CMOS_SDATA_3V3 H12 DIFFIO_RX_T28N
FLASH_RESETn R250 0 FLASH_RESETn_MAX10 B8 DIFFIO_RX_T28P
FLASH_CLK A9 DIFFIO_RX_T31N Flash
USER_IO8 C17 DIFFIO_RX_T31P
USER_IO9 D17 DIFFIO_RX_T2N
FLASH_D0 C9 DIFFIO_RX_T2P FLASH_RESETn
DIFFIO_RX_T30N 15,25
MIPI_TX_CMOS_RST_3V3 B10
FLASH_D3 A7 DIFFIO_RX_T30P FLASH_CSn
DIFFIO_RX_T29P 25
FLASH_CSn A8
HDMI_VIDEO_DIN22 F15 DIFFIO_RX_T29N FLASH_CLK
DIFFIO_RX_T5N 25
USER_IO4 F16
USER_IO1 B19 DIFFIO_RX_T5P FLASH_D[0:3]
DIFFIO_RX_T6N 25
USER_IO3 C19
HDMI_SDA B17 DIFFIO_RX_T6P
USER_IO7 C18 DIFFIO_RX_T7N
B USER_IO5 A19 DIFFIO_RX_T7P
DIFFIO_RX_T8N LI-USB3 CSI-2 TX Interface B
USER_IO6 A20
HDMI_VIDEO_DIN18 E14 DIFFIO_RX_T8P
HDMI_VIDEO_DIN23 D15 DIFFIO_RX_T9N MIPI_TX_CMOS_SCLK_3V3
DIFFIO_RX_T9P 11
B15
A15 VREFB7N0 MIPI_TX_CMOS_SDATA_3V3
TBD7 11

10M50DAF484 MIPI_TX_CMOS_RST_3V3 11

User LED

USER_LED[0:4] 18

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 7 of 25

 5 4 3 2 1

MAX10 CLOCKS

D D

LPDDR2 Interface
U1E
LPDDR2_DQS0 10
MAX 10 CLOCK LPDDR2_DQS0n 10
BANK-2 ( VCCIO = 1.8V )
N4 P3
OV10640_24MHz N5 DIFFIO_RX_L28N/CLK0N DIFFIO_RX_L38N/DPCLK0 R3
M8 DIFFIO_RX_L28P/CLK0P DIFFIO_RX_L38P/DPCLK1 T5
CLK24M M9 DIFFIO_RX_L36N/CLK1N DIFFIO_RX_L59N/PLL_L_CLKOUTN T6
OV5640 Interface
DIFFIO_RX_L36P/CLK1P DIFFIO_RX_L59P/PLL_L_CLKOUTP
OV5640_CLK_HS_P 13
BANK-3 ( VCCIO = 2.5V ) OV5640_CLK_HS_N 13
OV5640_CLK_HS_N V9
OV5640_CLK_HS_P V10 DIFFIO_TX_RX_B18N/CLK6N
OV10640_CLK_HS_N R11 DIFFIO_TX_RX_B18P/CLK6P
OV10640_CLK_HS_P P11 DIFFIO_TX_RX_B20N/CLK7N
CLK100M_LPDDR2_BK DIFFIO_TX_RX_B20P/CLK7P OV10640 Interface
C OV10640_CLK_HS_P 12
C
BANK-4 ( VCCIO = 2.5V )
R17 W17 CLKOUT_LVDS_N OV10640_CLK_HS_N
DIFFIO_TX_RX_B57N/PLL_B_CLKOUTN 12
200 V17 CLKOUT_LVDS_P
DIFFIO_TX_RX_B57P/PLL_B_CLKOUTP OV10640_24MHz 12
CLK100M_LPDDR2_BKDIV

BANK-6 ( VCCIO = 1.2V )

R18 N15 L15 LPDDR2_DQS0n
N14 DIFFIO_RX_R38N/CLK2N DIFFIO_RX_R50N/DPCLK2/DQSn2R L14 LPDDR2_DQS0
Si5338
100.0 DIFFIO_RX_R38P/CLK2P DIFFIO_RX_R50P/DPCLK3/DQS2R
USER_CLKIN_N_MAX10 K21 G17 CLK50M_MAX10
DIFFIO_RX_R40N/CLK3N DIFFIO_RX_R69N/PLL_R_CLKOUTN 19
USER_CLKIN_P_MAX10 K22 H17
DIFFIO_RX_R40P/CLK3P DIFFIO_RX_R69P/PLL_R_CLKOUTP CLK24M 19
CLK125M 19
BANK-8 ( VCCIO = 3.3V )
CLK100M_LPDDR2 E10 CLK100M_LPDDR2
DIFFIO_RX_T38N/CLK4N 19
CLK125M USB_CLK E11
CLK50M_MAX10 J10 DIFFIO_RX_T38P/CLK4P E6 CLK100M_LPDDR2_BK
DIFFIO_RX_T40P/CLK5P DIFFIO_RX_T52N/PLL_T_CLKOUTN 19
H11 D6 HDMI_VIDEO_CLK
DIFFIO_RX_T40N/CLK5N DIFFIO_RX_T52P/PLL_T_CLKOUTP
R19 USB Blaster II
200 10M50DAF484
R270
CLK125M_DIV_R USB_CLK 15

0
R20 User LVDS
B 100.0 B
USER_CLKIN_P 17
R271
USER_CLKIN_P USER_CLKIN_N_MAX10 17
CLKOUT_LVDS_P 17
DNI
Note: CLK125M_LVDS is the clock CLKOUT_LVDS_N 17
source provided to external LVDS user interface.
USER_CLKIN_P is used for external sigle-ended
clock input.
USER_CLKIN_P/N is used for external differential HDMI
clock input. HDMI_VIDEO_CLK 14

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 8 of 25

 5 4 3 2 1

MAX10 CONFIGURATION

D D

Configuration

MAX10_nCONFIG 18

MAX10_RESETn 18
U1F
MAX10_CONFIG_SEL 18
MAX 10 Configuration
MAX10_nSTATUS 15
2.5V BANK-1B BANK-8
( VCCIO = 3.3V ) ( VCCIO = 3.3V )
R21 10.0K MAX10_JTAGEN K9 H9 MAX10_nCONFIG MAX10_CONF_DONE
DIFFIO_RX_L15P/JTAGEN NCONFIG 15
R23 1.00k MAX10_JTAG_TCK G2 H10 MAX10_CONFIG_SEL
R24 10.0K MAX10_JTAG_TMS H2 DIFFIO_RX_L17P/TCK BOOT_SEL D9 MAX10_RESETn 3.3V
MAX10_JTAG_TDI L4 DIFFIO_RX_L17N/TMS DIFFIO_RX_T42N/DEV_CLRN D10
C R25 10.0K
MAX10_JTAG_TDO R314 22.0 MAX10_JTAG_TDO_3V3 M5 DIFFIO_RX_L18N/TDI DIFFIO_RX_T44P/DEV_OE F7 MAX10_JTAGEN 16
C
DIFFIO_RX_L18P/TDO DIFFIO_RX_T48N/CRC_ERROR G9 MAX10_nSTATUS R27 10.0K
DIFFIO_RX_T50P/NSTATUS F8 MAX10_CONF_DONE R28 10.0K
DIFFIO_RX_T50N/CONF_DONE MAX10_JTAG_TCK 16
R22
DNI
MAX10_JTAG_TMS 16
10M50DAF484

MAX10_JTAG_TDI 16

MAX10_JTAG_TDO 16

B B

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 9 of 25

 5 4 3 2 1

LPDDR2 SDRAM x 16

D U2A
D
1.2V_VCCIO

LPDDR2_CA0 P3 L6 LPDDR2_DQS0
LPDDR2_CA1 N3 CA0 DQS0 L5 LPDDR2_DQS0n
LPDDR2_CA2 M3 CA1 DQS0# LPDDR2 Interface
LPDDR2_CA3 M2 CA2 G6 LPDDR2_DQS1 C241 R29 C242 R30
LPDDR2_CA4 M1 CA3 DQS1 G5 LPDDR2_DQS1n 1.00k 1.00k
LPDDR2_CA5 G2 CA4 DQS1# 1.8V U2B 0.1uF 0.1uF
LPDDR2_CA6 F2 CA5 LPDDR2_CA[0:9]
CA6 6
LPDDR2_CA7 F3
LPDDR2_CA8 E3 CA7 B6 G3 LPDDR2_VREFCA LPDDR2_DQ[0:15]
CA8 VDD1 VREFCA 6
LPDDR2_CA9 E2 N8 LPDDR2_DQ0 C1 J9 LPDDR2_VREFDQ
CA9 DQ0 M8 LPDDR2_DQ1 R1 VDD1 VREFDQ LPDDR2_DM[0:1]
DQ1 VDD1 6
M7 LPDDR2_DQ2 T6 1.2V_VCCIO
LPDDR2_CKE K1 DQ2 M9 LPDDR2_DQ3 VDD1 C10 LPDDR2_CSn
CKE DQ3 6
LPDDR2_CK J3 M6 LPDDR2_DQ4 F1 0.1uF R32 R34
LPDDR2_CKn H3 CK DQ4 L7 LPDDR2_DQ5 VDDCA H1 C11 1.00k 1.00k LPDDR2_CKE
CK# DQ5 VDDCA 6
R31 L8 LPDDR2_DQ6 1.2V_VCCIO N2 0.1uF
4.7k R33 LPDDR2_CSn L1 DQ6 L9 LPDDR2_DQ7 VDDCA LPDDR2_CKn
CS# DQ7 6
DNI G9 LPDDR2_DQ8
DQ8 G8 LPDDR2_DQ9 B5 C7 LPDDR2_CK
DQ9 VDD2 VDDQ 6
LPDDR2_DM0 K5 G7 LPDDR2_DQ10 D2 C10
LPDDR2_DM1 H5 DM0 DQ10 F6 LPDDR2_DQ11 G1 VDD2 VDDQ D5 LPDDR2_DQS0
DM1 DQ11 VDD2 VDDQ 8
F9 LPDDR2_DQ12 J7 E9
LPDDR2_ZQ D3 DQ12 F7 LPDDR2_DQ13 P2 VDD2 VDDQ F10 LPDDR2_DQS0n
ZQ DQ13 VDD2 VDDQ 8
F8 LPDDR2_DQ14 T5 H6 CAD Note:
DQ14 E8 LPDDR2_DQ15 VDD2 VDDQ J6 Place resistors near LPDDR2
C R35
B2 DQ15 VDDQ K6 VREFCA and VREFDQ pins
LPDDR2_DQS1 6 C
240 B3 NC0 VDDQ M10 LPDDR2_DQS1n
NC1 VDDQ 6
B7 N9
B8 NC2 VDDQ P5
B9 NC3 C3 VDDQ R7
C8 NC4 RFU0 K2 VDDQ R10
D6 NC5 RFU1 K3 VDDQ
D7 NC6 RFU2 L2
D8 NC7 RFU3 L3 E1
D9 NC8 RFU4 VSSCA N1
E5 NC9 C2 VSSCA J1
E6 NC10 C5 VSS VSSCA
E7 NC11 D1 VSS
J2 NC12 A1 H2 VSS C6
N5 NC13 DNU0 A2 J8 VSS VSSQ C9
N6 NC14 DNU1 A9 P1 VSS VSSQ D10
N7 NC15 DNU2 A10 R2 VSS VSSQ E10
P6 NC16 DNU3 B1 R5 VSS VSSQ F5
P7 NC17 DNU4 B10 VSS VSSQ G10
P8 NC18 DNU5 T1 VSSQ J5
P9 NC19 DNU6 T10 VSSQ L10
R3 NC20 DNU7 U1 VSSQ M5
R8 NC21 DNU8 U2 VSSQ N10
T2 NC22 DNU9 U9 VSSQ P10
T3 NC23 DNU10 U10 VSSQ R6
T7 NC24 DNU11 VSSQ R9
T8 NC25 VSSQ
T9 NC26
NC27
B B
LPDDR2_IS43LD16640A-25BL

LPDDR2_IS43LD16640A-25BL

LPDDR2 Power Decoupling

1.2V_VCCIO CAD Note: 1.8V CAD Note:

Place decoupling caps near LPDDR2. Place decoupling caps near LPDDR2.

C13 C14 C15 C16 C17 C244 C245 C246 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C243 C247

10uF 4.7UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 22nF 22nF 0.01uF 0.01uF 4.7nF 4.7nF 2200pF 2200pF 4.7UF 0.1uF 0.1uF 0.1uF

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 10 of 25

 5 4 3 2 1

MIPI CSI-2 TX D-PHY

D CAD Note: CAD Note:

D
Place resistors near FPGA side. TP25 Place resistors near FPGA side.
TP7 LI-USB3 CSI-2 TX Interface
MIPI_TX_DATA_LP_P3 R36 100.0 MIPI_TX_DATA3P
MIPI_TX_CLK_LP_P R37 100.0 MIPI_TX_CLKP TP26
TP8 R39
R38 MIPI_TX_DATA_HS_P3 R40 150 100.0
MIPI_TX_CLK_HS_P R41 150 100.0 MIPI_TX_CLK_HS_P 4
MIPI_TX_CLK_HS_N 4
TP27
TP10 MIPI_TX_DATA_HS_P[1:4] 4
MIPI_TX_DATA_HS_N3 R44 150 R45
MIPI_TX_CLK_HS_N R42 150 R43 TP28 100.0 MIPI_TX_DATA_HS_N[1:4] 4
TP11 100.0
MIPI_TX_DATA_LP_N3 R46 100.0 MIPI_TX_DATA3N MIPI_TX_CLK_LP_P 5
MIPI_TX_CLK_LP_N R47 100.0 MIPI_TX_CLKN
MIPI_TX_CLK_LP_N 5
MIPI_TX_DATA_LP_P[1:4] 5
CAD Note:
Place resistors near FPGA side. MIPI_TX_DATA_LP_N[1:4] 5
TP31

CAD Note: MIPI_TX_DATA_LP_P4 R49 100.0 MIPI_TX_DATA4P MIPI_TX_CMOS_RST_1V8 4

TP13 Place resistors near FPGA side. TP32
R52 MIPI_TX_CMOS_RST_3V3 7
MIPI_TX_DATA_LP_P1 R48 100.0 MIPI_TX_DATA1P MIPI_TX_DATA_HS_P4 R53 150 100.0
C TP14
R51 MIPI_TX_CMOS_SCLK_1V8 4
C
MIPI_TX_DATA_HS_P1 R50 150 100.0
TP33 MIPI_TX_CMOS_SCLK_3V3 7
MIPI_TX_DATA_HS_N4 R56 150 R57 MIPI_TX_CMOS_SDATA_1V8 4
TP15 TP34 100.0
MIPI_TX_CMOS_SDATA_3V3 7
MIPI_TX_DATA_HS_N1 R54 150 R55 MIPI_TX_DATA_LP_N4 R59 100.0 MIPI_TX_DATA4N
TP16 100.0 MIPI_TX_CLK24MHz 19
MIPI_TX_DATA_LP_N1 R58 100.0 MIPI_TX_DATA1N MIPI_TX_GPIO1 4
3.3V MIPI_TX_GPIO2 4
R61 DNI
3.3V_MIPITX MIPI_TX_GPIO3 4
1.8V MIPI_TX_GPIO4 4
CAD Note: C30
TP19 Place resistors near FPGA side. R64 DNI DNI MIPI_TX_GPIO5
J1 4
MIPI_TX_DATA_LP_P2 R60 100.0 MIPI_TX_DATA2P C29
TP20 36 G4
CAD Note: DNI 35 36 SP4 G3
MIPI_TX_DATA_HS_P2 R62 150 R63 Place C29 and C30 near J1 connector. 34 35 SP3
1.8V_MIPITX 33 34
100.0 33
32
31 32
30 31
MIPI_TX_DATA1P 29 30
B TP21 MIPI_TX_DATA1N 28 29
28
B
27
MIPI_TX_DATA_HS_N2 R65 150 R66 MIPI_TX_CLKP 26 27
TP22 MIPI_TX_CLKN 25 26
100.0 25
24
MIPI_TX_DATA_LP_N2 MIPI_TX_DATA2N MIPI_TX_DATA2P 23 24
R67 100.0 MIPI_TX_DATA2N 22 23
21 22
MIPI_TX_DATA3P 20 21
MIPI_TX_DATA3N 19 20
18 19
MIPI_TX_DATA4P 17 18
MIPI_TX_DATA4N 16 17
1.8V 3.3V 15 16
Pull-up Options for MIPI TX MIPI_TX_CMOS_RST_IO 15
14
MIPI_TX_CMOS_SDATA 13 14
MIPI_TX_CMOS_SCLK 12 13
R68 R303 MIPI_TX_CLK24MHz 11 12
1.8V 3.3V MIPI_TX_GPIO1 R273 DNI MIPI_TX_GPIO1_IO 10 11
DNI DNI 10
MIPI_TX_GPIO2 R274 DNI MIPI_TX_GPIO2_IO 9
8 9
MIPI_TX_CMOS_SCLK_1V8 R294 DNI MIPI_TX_GPIO3 R275 DNI MIPI_TX_GPIO3_IO 7 8
R308 R309 MIPI_TX_GPIO4 R276 DNI MIPI_TX_GPIO4_IO 6 7
MIPI_TX_CMOS_SCLK_3V3 R302 DNI MIPI_TX_CMOS_SCLK MIPI_TX_GPIO5 R277 DNI MIPI_TX_GPIO5_IO 5 6
DNI DNI 5
4
3 4
1.8V 3.3V 2 3 G2
MIPI_TX_CMOS_RST_1V8 R312 DNI 1 2 SP2 G1
1 SP1
A MIPI_TX_CMOS_RST_3V3 R313 DNI MIPI_TX_CMOS_RST_IO A
R305 R306
DNI DNI
FFC_CONN_1x36
C28
MIPI_TX_CMOS_SDATA_1V8 R307 DNI Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
DNI Copyright (c) 2015, Altera Corporation. All Rights Reserved.
MIPI_TX_CMOS_SDATA_3V3 R304 DNI MIPI_TX_CMOS_SDATA Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 11 of 25

 5 4 3 2 1

MIPI CSI-2 RX D-PHY OV10640

CAD Note: CAD Note:
D Place resistors near FPGA side.
R71 100.0
TP67 Place resistors near FPGA side.
TP57
D
OV10640_CLK_LP_P R72 100.0
OV10640_DATA_LP_P3
OV10640 CSI-2 RX Interface
OV10640_CLK_HS_P
OV10640_DATA_HS_P3 OV10640_CLK_HS_P 8
R73
200 R74 OV10640_CLK_HS_N 8
200
OV10640_DATA_HS_P[1:4] 5
OV10640_DATA_HS_N[1:4] 5
R75 C31
200 100 pF R76 C32 OV10640_CLK_LP_P 6
200 100 pF
OV10640_CLK_LP_N 6
OV10640_CLK_HS_N OV10640_DATA_LP_P[1:4] 6
OV10640_DATA_HS_N3
TP68 TP60 OV10640_DATA_LP_N[1:4] 6
R78 100.0 OV10640_DATA_LP_N3
R77 100.0 OV10640_CLK_LP_N OV10640_CMOS_RST 4
CAD Note: OV10640_CMOS_SCLK 4
Place resistors near FPGA side. TP63
OV10640_CMOS_SDATA 4
OV10640_DATA_LP_P4
C CAD Note:
R80 100.0
OV10640_24MHz 8
C
Place resistors near FPGA side. TP45
OV10640_DATA_HS_P4 OV10640_GYRO_INT 4
R79 100.0 OV10640_DATA_LP_P1
R82 OV10640_G_RDY 4
200
OV10640_DATA_HS_P1 OV10640_XM_INT2 4
OV10640_XM_INT1 4
R81
200 OV10640_FSIN 4
R84 C34
200 100 pF

OV10640_DATA_HS_N4 J2
R83 C33
200 100 pF TP66
36 G4
R85 100.0 OV10640_DATA_LP_N4 35 36 SP4 G3
34 35 SP3
OV10640_DATA_HS_N1 33 34
TP48 OV10640_FSIN 32 33
OV10640_XM_INT1 31 32
R86 100.0 OV10640_DATA_LP_N1 OV10640_XM_INT2 30 31
1.8V 29 30
OV10640_G_RDY 28 29
OV10640_GYRO_INT 27 28
OV10640_24MHz R94 DNI OV10640_24MHz_IO 26 27
B OV10640_CMOS_SCLK 25 26
25
B
OV10640_CMOS_SDATA 24
OV10640_CMOS_RST 23 24
CAD Note: R89 22 23
Place resistors near FPGA side. TP50 OV10640_DATA_HS_N4 21 22
2.0K 21
R92 OV10640_DATA_HS_P4 20
R87 100.0 OV10640_DATA_LP_P2 R91 OV10640_CMOS_SDATA 19 20
2.0K 19
2.0K OV10640_DATA_HS_N3 18
OV10640_CMOS_SCLK OV10640_DATA_HS_P3 17 18
OV10640_DATA_HS_P2 16 17
OV10640_DATA_HS_N2 15 16
OV10640_CMOS_RST OV10640_DATA_HS_P2 14 15
R88 13 14
OV10640_CLK_HS_N 12 13
200 12
C36 OV10640_CLK_HS_P 11
10 11
DNI OV10640_DATA_HS_N1 9 10
OV10640_DATA_HS_P1 8 9
7 8
R90 C35 1.8V 6 7
100 pF R246 0 1.8V_OV10640 5 6
200 5
3.3V 4
R247 0 3.3V_OV10640 3 4
C171
2 3 G2
OV10640_DATA_HS_N2 10uF 1 2 SP2 G1
C172
TP54 1 SP1
10uF
R93 100.0 OV10640_DATA_LP_N2
CAD Note:
A Place capacitors near J2 connector. FFC_CONN_1x36
A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 12 of 25

 5 4 3 2 1

MIPI CSI-2 RX D-PHY OV5640

D CAD Note:
D
Place resistors near FPGA side.

R95 100.0 OV5640_CLK_LP_P

3.3V

OV5640_CLK_HS_P

R96
200

R98 R99 R100 R101

DNI DNI DNI DNI
OV5640_SDC
R97 C37
200 100 pF OV5640_SDA

C38 C39 OV5640_CAM_RESETB

OV5640_CLK_HS_N DNI DNI

OV5640 CSI-2 RX Interface
R102 100.0 OV5640_CLK_LP_N
OV5640_CAM_PWRON
OV5640_CLK_HS_P 8

C OV5640_CLK_HS_N 8 C
OV5640_DATA_HS_P[1:2] 5
CAD Note: OV5640_DATA_HS_N[1:2] 5
Place resistors near FPGA side.
OV5640_CLK_LP_P 6
R103 100.0 OV5640_DATA_LP_P1
OV5640_CLK_LP_N 6
J3
OV5640_DATA_HS_P1 OV5640_DATA_LP_P[1:2] 6
OV5640_DATA_HS_N2 1
R104 OV5640_DATA_HS_P2 2 1 OV5640_DATA_LP_N[1:2]
2 6
200 3
4 3
OV5640_CLK_HS_N 5 4 OV5640_CAM_PWRON
5 4
3.3V OV5640_CLK_HS_P 6
7 6 OV5640_CLK24MHz
7 19
OV5640_DATA_HS_N1 8
R105 C40 OV5640_DATA_HS_P1 9 8 OV5640_SDC
9 4
200 100 pF 10
R248 OV5640_CAM_PWRON 11 10 OV5640_SDA
11 4
0 OV5640_CLK24MHz 12
OV5640_SDC 13 12 OV5640_CAM_RESETB
13 4
OV5640_DATA_HS_N1 OV5640_SDA 14
OV5640_CAM_RESETB 15 14 17
3.3V_OV5640 16 15 17 18
R106 100.0 OV5640_DATA_LP_N1 16 18

C173
B CAD Note: FFC CONN 1x16 B
10uF Place near J3 connector.

CAD Note:
Place resistors near FPGA side.

R107 100.0 OV5640_DATA_LP_P2

OV5640_DATA_HS_P2

R108
200

R109 C41
200 100 pF

OV5640_DATA_HS_N2

R110 100.0 OV5640_DATA_LP_N2

A A

Title
MAX 10 FPGA (10M50) Evaluation Kit

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 13 of 25

 5 4 3 2 1

HDMI (VIDEO ONLY)

HDMI TX
HDMI_HPD
D U3 5V 5V
HDMI_VIDEO_DIN[23:0] 7 D
HDMI_VIDEO_DIN0 62 18 TMDS_CLK_P C42 C43 HDMI_VIDEO_CLK
D0 TXC+ 8
HDMI_VIDEO_DIN1 61 17 TMDS_CLK_N 0.1uF 0.1uF HDMI_DDCSDA
HDMI_VIDEO_DIN2 60 D1 TXC- HDMI_HSYNC
D2 7
HDMI_VIDEO_DIN3 59 21 TMDS_DATA_P0 HDMI_DDCSCL
HDMI_VIDEO_DIN4 58 D3 TX0+ 20 TMDS_DATA_N0 HDMI_VSYNC
D4 TX0- 7
HDMI_VIDEO_DIN5 57 24 TMDS_DATA_P1
D5 TX1+

5
HDMI_VIDEO_DIN6 56 23 TMDS_DATA_N1 D1 D2 HDMI_VIDEO_DATA_EN
D6 TX1- 7
HDMI_VIDEO_DIN7 55 27 TMDS_DATA_P2 VDD GND IO6 IO5 VDD GND IO6 IO5
D7 TX2+ 26 TMDS_DATA_N2 HDMI_INTR
TX2- 7
HDMI_VIDEO_DIN8 54
HDMI_VIDEO_DIN9 52 D8 28 HDMI_INTR HDMI_SDA
D9 INT 7
HDMI_VIDEO_DIN10 50
HDMI_VIDEO_DIN11 49 D10 36 HDMI_SDA IO1 IO2 IO3 IO4 IO1 IO2 IO3 IO4 HDMI_SCL
D11 SDA 7
HDMI_VIDEO_DIN12 48 35 HDMI_SCL 82401646 82401646

4
HDMI_VIDEO_DIN13 47 D12 SCL 34 HDMI_DDCSDA
HDMI_VIDEO_DIN14 46 D13 DDCSDA 33 HDMI_DDCSCL
HDMI_VIDEO_DIN15 45 D14 DDCSCL 30 CEC_IO
D15 CEC 32 CEC_CLK
HDMI_VIDEO_DIN16 44 CEC_CLK
HDMI_VIDEO_DIN17 43 D16 5V
HDMI_VIDEO_DIN18 42 D17 J4
HDMI_VIDEO_DIN19 41 D18 29 3.3V_DVDD R111 R112 685119134923
HDMI_VIDEO_DIN20 40 D19 DVDD_3V 0 0
D20
HDMI 19-Pin Connector
HDMI_VIDEO_DIN21 39 1 1.8V_DVDD 18 14
HDMI_VIDEO_DIN22 38 D21 DVDD 11 5V_VCC RESERVED_NC
HDMI_VIDEO_DIN23 37 D22 DVDD 31 TMDS_DATA_P0 7 17
D23 DVDD 51 TMDS_DATA_N0 9 TMDS_DATA_P0 DDC_CEC_GND 5V
HDMI_VIDEO_CLK 53 DVDD 8 TMDS_DATA_N0
C R113 DNI
HDMI_VIDEO_DATA_EN 63 CLK 12 1.8V_PVDD TMDS_DATA_SHLD0 16 HDMI_DDCSDA R114 2.0K C
HDMI_HSYNC 64 DE PVDD TMDS_DATA_P1 4 SDA 15 HDMI_DDCSCL R115 2.0K
HDMI_VSYNC 2 HSYNC 13 TMDS_DATA_N1 6 TMDS_DATA_P1 SCL 13
R116 887 HDMI_IREF 14 VSYNC BGVDD 5 TMDS_DATA_N1 CEC
HDMI_HPD 16 R_EXT TMDS_DATA_SHLD1 19 HDMI_HPD R117 10.0K
3 HPD 15 1.8V_AVDD TMDS_DATA_P2 1 HOT_PLUG_DETECT
4 SPDIF AVDD 19 TMDS_DATA_N2 3 TMDS_DATA_P2
MCLK AVDD 25 2 TMDS_DATA_N2
5 AVDD TMDS_DATA_SHLD2
6 I2S0 TMDS_CLK_P 10
7 I2S1 65 TMDS_CLK_N 12 TMDS_CLK_P
8 I2S2 EPAD_GND 11 TMDS_CLK_N
I2S3 TMDS_DATA_SHLD_CLK

MTG1
MTG2
MTG3
MTG4
9
10 SCLK
22 LRCLK
PD

G1
G2
G3
G4
ADV7513BSWZ

R118 2.0K R119 DNI 1.8V_AVDD

B B
HDMI Power Decoupling

Note: Note:
Place 0.1uF capacitor near ADV7513 DVDD pins Place 0.1uF capacitor near ADV7513 PVDD and BGVDD pin HDMI_SDA R120 2.0K 3.3V_DVDD
1.8V L1 10uH 1.8V L2 10uH
1 2 1.8V_DVDD 1 2 1.8V_PVDD HDMI_SCL R121 2.0K

HDMI_INTR R122 2.0K

C44 C45 C46 C47 C48 C49 C50 C51

10uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF

Note: Note:
1.8V L3 10uH Place 0.1uF capacitor near ADV7513 AVDD pins 3.3V L4 10uH Place 0.1uF capacitor near ADV7513 DVDD_3V pin
1 2 1.8V_AVDD 1 2 3.3V_DVDD

C52 C53 C54 C55 C56 C57

10uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 14 of 25

 5 4 3 2 1

ON-BOARD USB BLASTER II-1

D J5 VBUS_5V
3.3V D
USB MINI-B
1 U4A
VBUS FX2_D_N
D-
2 C58 0.1uF MAX II
3 FX2_D_P BANK1
D+
4 R124 DNI U5 FX2_SCL B1 ( VCCIO = 3.3V ) J1 FX2_FLAGC
USB Blaster II
ID IOB1_1 IOB1_25
5 1 4 FX2_SDA R123 0 MAX_SDA C1 J2
GND VCC C2 IOB1_2 IOB1_26 K2 USB_CLK
IOB1_3 IOB1_27 8
R125 1M C3 L2
9
8
7
6

100K R126 FX2_RESETn 2 3 C4 IOB1_4 IOB1_28 M1 FX2_PA4 USB_RESETn

RESET MR IOB1_5 IOB1_29 4
FX2_PB0 D1 M2
MAX811 D2 IOB1_6 IOB1_30 N1 FX2_PA5 USB_WRn
IOB1_7 IOB1_31 4
D3 N2
IOB1_8 IOB1_32
C59 4.7nF FX2_PB4 D4 N4 FX2_PA0
Si510
3.3V FX2_PB1 E1 IOB1_9 IOB1_33 P1 FX2_PA6
U7 IOB1_10 IOB1_34
U6 3.3V E2 P2 CLK50M_MAXII 19
1 3 42 FX2_RESETn E3 IOB1_11 IOB1_35 P3
3 D+ 2 7 AVCC RESET 15 FX2_SCL R127 2.0K FX2_PB5 E4 IOB1_12 IOB1_36 P4 FX2_PA1
GND D- AVCC SCL 16 FX2_SDA R128 2.0K FX2_PB2 F1 IOB1_13 IOB1_37 R1 FX2_PA7
TPD2EUSB30 11 SDA F2 IOB1_14 IOB1_38 R2
Configuration
17 VCC 44 FX2_WAKEUP F3 IOB1_15 IOB1_39 R3
27 VCC WAKEUP IOB1_16 IOB1_40 MAX10_nSTATUS
VCC 9
32 29 FX2_FLAGA FX2_PB6 F4 R4 FX2_PA2
43 VCC CTL0 30 FX2_FLAGB FX2_PB3 G1 IOB1_17 IOB1_41 T1
55 VCC CTL1 31 FX2_FLAGC G2 IOB1_18 IOB1_42 T2 MAX10_CONF_DONE
VCC CTL2 IOB1_19 IOB1_43 9
G3 T4 FX2_PA3
Y1 9 1 FX2_SLRDn FX2_PB7 G4 IOB1_20 IOB1_44 U1
DMINUS RDY0 IOB1_21 IOB1_45
4

8 2 FX2_SLWRn FX2_FLAGB H1 U3
C 1 3 IFCLK = 48MHz DPLUS RDY1 H2 IOB1_22 IOB1_46 V1
MAXII_CONF_DONE 18 C
USB_CLK 13 54 FX2_FLAGA H4 IOB1_23 IOB1_47 V3
24.00MHz 24M_XTALIN 5 IFCLK CLKOUT IOB1_24 IOB1_48 W1
2

24M_XTALOUT 4 XTALIN IOB1_49

XTALOUT
C60 C61
FX2_PA0 33 18 FX2_PB0 USB_CLK K1 W2 C_USB_MAX_TCK R129 0 FX2_PD0
12pF 12pF FX2_PA1 34 PA0 PB0 19 FX2_PB1 CLK50M_MAXII L1 IOB1/GCLK0 TCK U2 C_USB_MAX_TDI R130 0 FX2_PD2
Flash
FX2_PA2 35 PA1 PB1 20 FX2_PB2 IOB1/GCLK1 TDI V2 C_USB_MAX_TDO R131 0 FX2_PD3
FX2_PA3 36 PA2 PB2 21 FX2_PB3 TDO T3 C_USB_MAX_TMS R132 0 FX2_PD1 FLASH_RESETn
PA3 PB3 TMS 7,25
FX2_PA4 37 22 FX2_PB4
FX2_PA5 38 PA4 PB4 23 FX2_PB5
FX2_PA6 39 PA5 PB5 24 FX2_PB6 EPM1270_M256FBGA
FX2_PA7 40 PA6 PB6 25 FX2_PB7
PA7 PB7
14 45 FX2_PD0
JTAG Interface
RESERVED PD0 46 FX2_PD1
6 PD1 47 FX2_PD2 JTAG_SAFE
AGND PD2 4
10 48 FX2_PD3
AGND PD3 49 FX2_PD4
12 PD4 50 FX2_PD5 JTAG_LOCK
GND PD5 16
26 51 FX2_PD6 U4D
28 GND PD6 52 FX2_PD7 MAX II
41 GND PD7
GND
BANK4
53 MAX10_CONF_DONE U13 ( VCCIO = 3.3V ) W17 EN5339
56 GND 57 FLASH_RESETn R249 0 FLASH_RESETn_MAXII U14 IOB4_1 IOB4_25 W18
GND EXPOSED_PAD U15 IOB4_2 IOB4_26 W3 1.2V_CORE_POK
IOB4_3 IOB4_27 22
CY7C68013A_QFN MAX10_nSTATUS U16 W4
U4 IOB4_4 IOB4_28 W5 1.2V_LED
IOB4_5 IOB4_29 18
U5 W6
B U6 IOB4_6
IOB4_7
IOB4_30
IOB4_31
W7 B
U7 W8
IOB4_8 IOB4_32
U8 W9
V14 IOB4_9 IOB4_33 Y1
VBUS_5V 3.3V Note: V15 IOB4_10 IOB4_34 Y10 MAXII_CONF_DONE
Place 0.1uF capacitors near CY7C68013A. V16 IOB4_11 IOB4_35 Y11 1.2V_CORE_POK
R133 10.0K FX2_WAKEUP V17 IOB4_12 IOB4_36 Y12
V18 IOB4_13 IOB4_37 Y14
C63 C64 C65 C66 C67 C68 C69 C70 V4 IOB4_14 IOB4_38 Y15
R134 C62 V5 IOB4_15 IOB4_39 Y16
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF IOB4_16 IOB4_40
20.0K 0.1uF V6 Y17 JTAG_SAFE
V7 IOB4_17 IOB4_41 Y18 USB_RESETn
W10 IOB4_18 IOB4_42 Y19 USB_WRn
W11 IOB4_19 IOB4_43 Y2 FX2_PD5
W13 IOB4_20 IOB4_44 Y3 FX2_PD4
W14 IOB4_21 IOB4_45 Y4 FX2_PD6
W15 IOB4_22 IOB4_46 Y5 FX2_PD7
W16 IOB4_23 IOB4_47 Y6 FX2_SLRDn
IOB4_24 IOB4_48
3.3V Y7 FX2_SLWRn
3.3V FX2_RESETn Y13 IOB4_49 Y8 JTAG_LOCK
J6 W12 IOB4/DEV_CLRn IOB4_50 Y9 1.2V_LED
R135 1.00K C_USB_MAX_TCK 1 2 IOB4/DEV_OE IOB4_51
C_USB_MAX_TDO 3 1 2 4
R136 1.00K C_USB_MAX_TMS 5 3 4 6 EPM1270_M256FBGA
7 5 6 8
C_USB_MAX_TDI 9 7 8 10
A 9 10
A
DNI

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 15 of 25

 5 4 3 2 1

ON-BOARD USB BLASTER II-2

D D
U4C
MAX10 USB Interface
U4B MAX II
MAX II BANK3 USB_DATA[7:0] 4
BANK2 3.3V MAX10_BYPASSn B20 ( VCCIO = 3.3V ) J20 USB_ADDR1
SI5338_INTR A1 ( VCCIO = 2.5V ) B14 C18 IOB3_1 IOB3_25 K19 USB_ADDR[1:0]
IOB2_1 IOB2_25 IOB3_2 IOB3_26 4
A10 B15 C19 K20 USB_DATA6
A11 IOB2_2 IOB2_26 B16 R141 1.00k USB_SDA C20 IOB3_3 IOB3_27 L19 USB_FULL
IOB2_3 IOB2_27 IOB3_4 IOB3_28 4
MAX10_JTAG_TDO A12 B17 D17 M19 USB_EMPTY
IOB2_4 IOB2_28 IOB3_5 IOB3_29 4
MAX10_JTAG_TDI A13 B18 D18 N17 USB_SCL
IOB2_5 IOB2_29 IOB3_6 IOB3_30 4
MAX10_JTAGEN A14 B19 D19 N19 USB_SDA
IOB2_6 IOB2_30 IOB3_7 IOB3_31 4
MAX10_JTAG_TCK A15 B2 R140 1.00k USB_SCL D20 N20
MAX10_JTAG_TMS A16 IOB2_7 IOB2_31 B3 IOB3_8 IOB3_32 USB_OEn
IOB2_8 IOB2_32 4
USB_DISABLEn E17 P17 USB_RDn
IOB3_9 IOB3_33 4
A17 B4 E18 P18
A18 IOB2_9 IOB2_33 B5 E19 IOB3_10 IOB3_34 P19
A19 IOB2_10 IOB2_34 B6 USB_DATA2 E20 IOB3_11 IOB3_35 P20 USB_DATA3
A2 IOB2_11 IOB2_35 B7 3.3V EXT_JTAG_TDO F17 IOB3_12 IOB3_36 R17 I2C_MAXII_SCL
IOB2_12 IOB2_36 IOB3_13 IOB3_37 19
A20 B8 F18 R18
A3 IOB2_13 IOB2_37 B9 F19 IOB3_14 IOB3_38 R19 I2C_MAXII_SDA
IOB2_14 IOB2_38 IOB3_15 IOB3_39 19
2.5V A4 C14 R142 1.00k USB_FULL F20 R20 USB_ADDR0
A5 IOB2_15 IOB2_39 C15 IOB3_16 IOB3_40
R137 4.7k IOB2_16 IOB2_40 EXT_JTAG_TMS G17 T17
I2C_MAXII_SDA A6 C16 G18 IOB3_17 IOB3_41 T18
I2C_MAXII_SCL A7 IOB2_17 IOB2_41 C17 G19 IOB3_18 IOB3_42 T19
JTAG Interface
R139 4.7k A8 IOB2_18 IOB2_42 C5 R138 1.00k USB_EMPTY G20 IOB3_19 IOB3_43 T20 USB_DATA1
A9 IOB2_19 IOB2_43 C6 EXT_JTAG_TDI H17 IOB3_20 IOB3_44 U17 MAX10_JTAGEN
IOB2_20 IOB2_44 IOB3_21 IOB3_45 9
B10 C7 H19 U18
C B11 IOB2_21 IOB2_45 D13 USB_DATA0 H20 IOB3_22 IOB3_46 U19
MAX10_JTAG_TCK
MAX10_JTAG_TMS
9
9
C
B12 IOB2_22 IOB2_46 D14 J19 IOB3_23 IOB3_47 U20 USB_OEn MAX10_JTAG_TDO
IOB2_23 IOB2_47 IOB3_24 IOB3_48 9
B13 D15 MAX10_JTAG_TDI 9
IOB2_24 IOB2_48 V19
D16 IOB3_49 V20 USB_DATA4
IOB2_49 D5 IOB3_50 W19 MAX10_BYPASSn
IOB2_50 IOB3_51 18
D6 EXT_JTAG_TCK M20 W20 USB_DATA5
IOB2_51 D7 USB_RDn L20 IOB3/GCLK2 IOB3_52 Y20 USB_DATA7
IOB2_52 D8 IOB3/GCLK3 IOB3_53 SI5338_INTR
IOB2_53 19
EPM1270_M256FBGA
EPM1270_M256FBGA JTAG_LOCK 15

U4E
MAX II 2.5V
MAX II Decoupling
Power
J4 K4
C71 GNDINT VCCINT
U12 U11
EXT_JTAG_TCK R143 DNI M17 GNDINT VCCINT L17 2.5V Note:
D12 GNDINT VCCINT D11 Place decoupling capacitors near MAXII
GNDINT VCCINT
DNI 3.3V
R144
1.00k H3 K3 C72 C73
J3 GNDIO VCCIO1 L3
M4 GNDIO VCCIO1 L4 0.1uF 0.1uF
B N3 GNDIO
GNDIO
VCCIO1
VCCIO1
M3 B
3.3V U9 2.5V
V8 GNDIO C9
V9 GNDIO VCCIO2 C10
V13 GNDIO VCCIO2 D10 3.3V 2.5V 3.3V 3.3V
USB Blaster Programming Header GNDIO VCCIO2
(uses JTAG mode only) R145 R146 H18 C11
1.00k 1.00k J17 GNDIO VCCIO2 3.3V
N18 GNDIO J18
3.3V 3.3V C8 GNDIO VCCIO3 K17 C74 C75 C76 C77 C78 C79 C80 C81
J7 D9 GNDIO VCCIO3 K18
R147 1.00k USB_DISABLEn 2 1 EXT_JTAG_TCK_R R148 22.0 EXT_JTAG_TCK C12 GNDIO VCCIO3 L18 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
4 2 1 3 EXT_JTAG_TDO_R R149 22.0 EXT_JTAG_TDO C13 GNDIO VCCIO3 3.3V
6 4 3 5 EXT_JTAG_TMS_R R150 22.0 EXT_JTAG_TMS M18 GNDIO U10
8 6 5 7 JTAG_LOCK_R R151 22.0 JTAG_LOCK GNDIO VCCIO4 V10
10 8 7 9 EXT_JTAG_TDI_R R152 22.0 EXT_JTAG_TDI VCCIO4 V11
10 9 VCCIO4 V12
2X5_100mil VCCIO4

EPM1270_M256FBGA

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 16 of 25

 5 4 3 2 1

PMOD, GPIO, LVDS USER IO

D D
3.3V 3.3V LVDS Termination
U8 U9
PMODA_IO3 1 5 PMODA_IO4 1 5 Note: Place near MAX 10 side.
PMOD PMODA_IO7
PMODA_IO6
3
4
IO1 VDD
IO2
PMODA_IO0
PMODA_IO1
3
4
IO1 VDD
IO2
PMODA_IO2 6 IO3 2 PMODA_IO5 6 IO3 2 USER_CLKIN_P R272 DNI
IO4 GND IO4 GND USER_CLKIN_N_MAX10
824013 824013
USER_LVDS_P0 R153 DNI
USER_LVDS_N0

USER_LVDS_P1 R154 DNI

PMOD
J8 USER_LVDS_N1
PMODA_D0 R156 200 PMODA_IO0 1 7 PMODA_IO4 R158 200 PMODA_D4 PMODA_D[7:0]
1 7 7
PMODA_D1 R157 200 PMODA_IO1 2 8 PMODA_IO5 R159 200 PMODA_D5 USER_LVDS_P2 R155 DNI
PMODA_D2 R160 200 PMODA_IO2 3 2 8 9 PMODA_IO6 R161 200 PMODA_D6 USER_LVDS_N2
PMODA_D3 R163 200 PMODA_IO3 4 3 9 10 PMODA_IO7 R164 200 PMODA_D7 PMODB_D[7:0]
4 10 7
5 11 USER_LVDS_P3 R162 DNI
3.3V 6 5 11 12 3.3V USER_LVDS_N3
6 12
2x6 PMOD Connector User LVDS IO
USER_LVDS_P4 R165 DNI
USER_LVDS_N4
USER_LVDS_P[0:8] 5
USER_LVDS_P5 R166 DNI
USER_LVDS_N5
C USER_LVDS_N[0:8] 5
C
USER_LVDS_P6 R167 DNI
3.3V 3.3V USER_LVDS_N6 USER_CLKIN_P 8
U10 U11 USER_LVDS_P7 R168 DNI
PMODB_IO0 1 5 PMODB_IO6 1 5 USER_LVDS_N7 USER_CLKIN_N_MAX10
IO1 VDD IO1 VDD 8
PMODB_IO1 3 PMODB_IO5 3
PMODB_IO4 4 IO2 PMODB_IO7 4 IO2 USER_LVDS_P8 R169 DNI
PMODB_IO2 6 IO3 2 PMODB_IO3 6 IO3 2 USER_LVDS_N8
IO4 GND IO4 GND
824013 824013 CLKOUT_LVDS_P R170 DNI
LVDS
CLKOUT_LVDS_N
CLKOUT_LVDS_P 8

CLKOUT_LVDS_N 8
J9
PMODB_D0 R171 200 PMODB_IO0 1 7 PMODB_IO4 R172 200 PMODB_D4
PMODB_D1 R173 200 PMODB_IO1 2 1 7 8 PMODB_IO5 R174 200 PMODB_D5
PMODB_D2 R175 200 PMODB_IO2 3 2 8 9 PMODB_IO6 R176 200 PMODB_D6
PMODB_D3 R177 200 PMODB_IO3 4 3 9 10 PMODB_IO7 R178 200 PMODB_D7
User IO

3.3V
5
6
4
5
10
11
11
12 3.3V
User LVDS IO 2.5V 2.5V USER_IO[0:9]
6 12 7
2x6 PMOD Connector J12
1 2
USER_CLKIN_IO_P 3 1 2 4 USER_LVDS_P2
USER_CLKIN_IO_N 5 3 4 6 USER_LVDS_N2
B 7 5
7
6
8
8 B
USER_LVDS_P0 9 10 USER_LVDS_P3
R179 R268 USER_LVDS_N0 11 9 10 12 USER_LVDS_N3
13 11 12 14
2.0K 2.0K 13 14
USER_LVDS_P1 15 16 CLKOUT_LVDS_P
USER_LVDS_N1 17 15 16 18 CLKOUT_LVDS_N
USER_CLKIN_P USER_CLKIN_N_MAX10 19 17 18 20
J14 19 20
3.3V 3.3V
R180 R269 Header 2x10 (DNI)
1.00k 1.00k
User GPIO USER_IO0
USER_IO1
1
3 IO1 IO2
2
4
USER_IO5
USER_IO6
5 IO3 IO4 6
USER_IO2 7 IO5 IO6 8 USER_IO7
USER_IO3 9 IO7 IO8 10 USER_IO8 2.5V 2.5V
11 IO9 IO10 12
USER_IO4 13 IO11 IO12 14 USER_IO9 J13
IO13 IO14 1 2
1 2
Note: USER_CLKIN_IO_P USER_LVDS_P5 3
3 4
4 USER_LVDS_P8
is used if external single-ended USER_LVDS_N5 5 6 USER_LVDS_N8
7 5 6 8
Header 2x7 (DNI)
clk needs to use on-chip PLL USER_LVDS_P6 9 7 8 10 USER_LVDS_P4
resource. USER_LVDS_N6 11 9 10 12 USER_LVDS_N4
USER_CLKIN_IO_P/N is used 13 11 12 14
for external differential clk input. USER_LVDS_P7 15 13 14 16
Values of R179,R180,R268, USER_LVDS_N7 17 15 16 18
17 18
and R269 might be adjusted 19
19 20
20
according to user input voltage.
A A
Header 2x10 (DNI)

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

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A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 17 of 25

 5 4 3 2 1

PUSHBUTTON, SWITCH, LED

D D

User DIP Switch

MAXII
User LED USER DIPSWITCH
1.2V_VCCIO
3.3V SW1 MAXII_CONF_DONE 15
1 8 USER_DIPSW0 R181 10.0K
D3 GREEN_LED 2 7 USER_DIPSW1 R182 10.0K 1.2V_LED 15

OPEN
USER_LED0 USER_LED0_R R183 150 3 6 USER_DIPSW2 R184 10.0K
4 5 USER_DIPSW3 R185 10.0K

D4 GREEN_LED DIPSWITCH4
USER_LED1 USER_LED1_R R186 150
ON = 0
User LED
OFF = 1 USER_LED[0:4] 7
D5 GREEN_LED
USER_LED2 USER_LED2_R R187 150 BOARD SETTINGS DIPSWITCH

3.3V
D6 GREEN_LED SW2 User Pushbutton
USER_LED3 USER_LED3_R R188 150 1 8 USER_DIPSW4 R189 10.0K
2 7 USER_DIPSW5 R190 10.0K

OPEN
3 6 MAX10_CONFIG_SEL R191 10.0K USER_PB[0:3] 6
D7 GREEN_LED 4 5 MAX10_BYPASSn R192 10.0K
USER_LED4 USER_LED4_R
C R193 150
DIPSWITCH4 C
Logic 0 = Device JTAG Bypass MAX10_nCONFIG 9
ON = 0 Logic 1 = Device JTAG Enable
OFF = 1
3.3V Note: MAX10_BYPASSn is used to bypass
the virtual JTAG device provided within the MAX10_RESETn 9
D8 GREEN_LED On-Board USB-Blaster II.
MAXII_CONF_DONE MAXII_CONF_DONE_R R194 390

D11 YELLOW_LED
User DIP Switch
1.2V_LED 1.2V_LED_R R278 390
USER_DIPSW[0:3] 6

USER_DIPSW[4:5]
User Pushbutton 4

1.2V_VCCIO MAX10_CONFIG_SEL 9

S1 MAX10_BYPASSn
Power LED 1
2
3
4
USER_PB0 R202 10.0K
16

PB Switch
S2
B 1 3 USER_PB1 R196 10.0K B
2 4
PB Switch
5V S3
1 3 USER_PB2 R195 10.0K
5V_LED_R R199 1.00k 2 4
PB Switch
2.5V S4
1 3 USER_PB3 R198 10.0K
2.5V_LED_R R200 150 2 4
PB Switch

D9 D10
YELLOW_LED YELLOW_LED
3.3V

S6
1 3 MAX10_nCONFIG R203 10.0K
2 4
PB Switch
S7
1 3 MAX10_RESETn R204 10.0K
2 4
PB Switch

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

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A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 18 of 25

 5 4 3 2 1

CLOCKING

D D

3.3V
L5
3.3V_SI5338

C82 C83 C84 C85 C86 BLM15AG221SN1

300mA
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

L6 1.8V
1.8V_SI5338
C87 DNI Programmable Clock
Y2 C88 BLM15AG221SN1 MAX 10
U14 300mA
25.00MHz

3
7 0.1uF
4 2 Si5338A_XTAL_25M_P 1 VDD1 24
Si5338A_XTAL_25M_N 2 CLKIN_P VDD2 11 CLK50M_MAX10
CLKIN_N VDDO3 8
3 15
C89 DNI 1 CLKIN VDDO2 16 2.5V
4 VDDO1 20 CLK24M
I2C_LSB VDDO0 8
5
6 FDBK_P 8 SI5338_INTR 4.7k
R205
FDBK_N INTR
C I2C_MAXII_SCL R206 22.0 12 9 CLK100M_LPDDR2_BK_R R207 0 CLK100M_LPDDR2_BK
CLK125M 8 C
SCL CLK3B 10 CLK100M_LPDDR2_R R208 0 CLK100M_LPDDR2 3.3V CMOS complimentary
I2C_MAXII_SDA R209 22.0 19 CLK3A CLK100M_LPDDR2
SDA 8
13 CLK125M_R R210 0 CLK125M 3.3V Single-Ended CMOS
CLK2B 14
CLK2A CLK100M_LPDDR2_BK 8
17
CLK1B 18 OV5640_CLK24MHz_R R211 0 OV5640_CLK24MHz 3.3V Single-Ended CMOS
CLK1A SI5338_INTR 16
21 MIPI_TX_CLK24MHz_R R212 DNI MIPI_TX_CLK24MHz
CLK0B 22 CLK24M_R R213 0 CLK24M 1.8V CMOS complimentary
CLK0A
MAXII
23
RSVD_GND 25 CLK50M_MAXII
EPAD 15

Si5338C-CUSTOM I2C_MAXII_SCL 16
I2C_MAXII_SDA 16
Notes:
Use Clock Control GUI to program Si5338 oscillator outputs.
(Defaults 100MHz, 125MHz, 24MHz, 24MHz)
DM385 CSI-2 TX Interface
I2C Address 70 HEX
OV5640_CLK24MHz 13
MIPI_TX_CLK24MHz 11
B B

3.3V
L9 U15
3.3V_SI510 6
VDD 4 CLK50M_MAX10_R R215 22.0 CLK50M_MAX10 3.3V CMOS
C240 R214 1.00k CLK50M_EN 2 CLKp 5 CLK50M_MAXII_R R216 22.0 CLK50M_MAXII 3.3V CMOS
BLM15AG221SN1
OE CLKn
300mA
0.1uF
3 1
GND NC

510MCA50M0000AAGR

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

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A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 19 of 25

 5 4 3 2 1

HOT SWAP and POWER 3.3V

D D

5V
DC Input
J10 5V_DCIN
1
2
3 5V_MONITOR

DC Input Jack 2.0 mm 5V

CAUTION:
R217 XJ1
J11
VBUS_5V When NOT using jumpers,
40.2K
1
R292 DNI
R293 DNI
solder R292 for power input from DC Jack,
2 or solder R293 for USB power.
2
SW3
609002115121
3 SOLDER ONLY ONE POWER OPTION,
3 R264 0 5V_UV AND SUGGEST NOT TO USE WITH JUMPER.
1 HEADER, 1x3-PIN
C220

5 47uF
4 R221
6
20.0K
POWER SW
C C
EN5329
3.3V_POK 21

POWER 3.3V
Hot Swap for DC Plug 5V

U16 R260 0 5V_R3.3

FDMC8878
5V_DCIN 1 5V_MONITOR
2 Notes: C90
R222 0.005 5 3 Place C90 near PVIN pin.
22uF
3.3V
2

U17 3.3V
V1 V2 17 3.3V_POK R281 10.0K
RSNS SNS

RSNS SNS

4 1.8V 5V 19 POK
20 PVIN 4
PVIN VOUT 5 R223
VOUT C91 C92 C93
R224 R225 R226 R227 C94 C95 R228 6
60.4K 3.3V_EN 18 VOUT 7 6.8pF 348K 22uF 22uF
69.8K ENABLE VOUT
10 10.0K 150uF 22uF 1K R279 R280
1

0 DNI 14 3.3V_VFB
5V_P VFB
B 16 B
5V_N

AVIN
5V_GATE

U18 R229
5V_PG
5V_FB

1 16 10 2
2 NC SENSE+ 15 11 TST2 PGND 3 78.7K
5V_UV 3 VDD SENSE- 14 R284 C96 12 TST1 PGND 8 Notes:
C207
5V_OV 4 UV ISET 13 5V_IMON TST0 PGND 9 Place C91, R223 and R229

NC(SW)0
NC(SW)1
NC(SW)2
NC(SW)3
NC(SW)4
5 OV IMON 12 DNI DNI 1.0UF PGND TP1 near EN5329QI VFB pin.
TIMER FB

PGND
PGND
6 11 15
R230 7 INTVCC /FLT 10 AGND

NC
8 GND PG 9
20.0K SOURCE GATE EN5329QI

13
1
21
22
23
24

25
26
LTC4218CGN Notes:
Place C96 near AVIN pin.

R231 1.00k
C97 C99
C98
0.1uF 0.1uF R232 R233
0.01uF
20.0K 20.0K TP2

Hot Swap Controller Circuit

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 20 of 25

 5 4 3 2 1

POWER 2.5V & 1.8V

D D

POWER 2.5V
EN5329

3.3V_POK 20
Notes:
5V 5V_R2.5 Place caps near EP5348UI. 2.5V
U19

R289 0 12 6
PVIN VOUT 7
VOUT C216 R290 C211 C251
C213
C215 11
Notes: AVIN 5 pF 200k 10uF 2.2uF 2.2uF
Place caps near EP5348UI. 2.2uF C212
4
0.1uF 10 VFB
R255 ENABLE
TP3 R291
DNI 2
PGND
C 63.0K
C

NC(SW)0
NC(SW)1
NC(SW)2
5
3.3V_POK R282 0 2.5V_ENABLE AGND

NC0
NC1
NC2
C175

3
8
9
1
13
14
DNI

EP5348UI

POWER 2.5V_VCCA POWER 1.8V Note:

Possible adjustment within
15% VID setting by parallel
RC combination.
C105 R235

DNI 0

5V U20
B 2.5V 2.5V_CORE 2.5V_VCCA
VSENSE
5 1.8V B
L7 742792022 R258 0 5V_R1.8 14 7
R236 0.1 1 2 PVIN VOUT 8
VOUT

C108 C109
C104 R257 13 C106 C107 C217 C218 C219
10uF 0.1uF Notes: 0 AVIN
Place C104 close to EP5358. 2.2uF 10uF 10uF DNI DNI 47uF
4
1.8V_ENABLE 12 VFB/NC4
ENABLE
11 Notes:
10 VS0 Place caps near EP5358HUI.
C176 9 VS1 TP4
DNI VS2
1 6
15 NC1 AGND 2
16 NC15 PGND 3
NC16 PGND
EP5358HUI

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

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Date: Thursday, March 24, 2016 Sheet 21 of 25

 5 4 3 2 1

POWER 1.2V

D D

POWER 1.2V_CORE

3.3V

5V
R239
10.0K
R253 0 5V_R1.2CORE Notes:
U21 Place C112, R240 and R243 1.2V_CORE_SENSE 1.2V_CORE
17 1.2V_CORE_POK near EN5329QI VFB pin.
R252 19 POK R238 0.01
PVIN EN5339
Notes: C111 DNI 20 4
Place C111 close to PVIN pin. 2.5V PVIN VOUT 5 C112 R240 C116 C248 1.2V_CORE_POK
C113 C114 C249 15
22uF VOUT 6
R283 0 1.2V_CORE_ENABLE 18 VOUT 7 15pF 348K DNI 47uF 47uF DNI DNI
ENABLE VOUT
C174 14 1.2V_CORE_VFB
VFB
C DNI 16 C
AVIN R243
C120 10 2
11 TST2 PGND 3 348K
1.0UF 12 TST1 PGND 8
TST0 PGND 9

NC(SW)0
NC(SW)1
NC(SW)2
NC(SW)3
NC(SW)4
Place a 1μ F cap PGND TP6
from the AVIN pin

PGND
PGND
15
to AGND pin. AGND

NC
EN5339QI

13
1
21
22
23
24

25
26
POWER 1.2V_VCCIO

POWER 1.2V_VCCD_PLL 5V 5V_R1.2VCCIO Notes: 1.2V_VCCIO

B U22 Place caps near EP5348UI. B
R254 0 12 6
1.2V_CORE 1.2V_VCCD_PLL PVIN VOUT 7
L8 742792022 VOUT C208 R285 C209 C250 R315
C118
1 2 C115 11
Notes: AVIN 5 pF 200k 10uF 2.2uF 2.2uF 51
Place caps near EP5348UI. 2.2uF C210
C121 C122 4 1.2V_VCCIO_VFB
0.1uF 10 VFB
10uF 0.1uF ENABLE
TP5 R286
1.8V 5V_R1.2VCCIO 2
PGND 200k

NC(SW)0
NC(SW)1
NC(SW)2
5
AGND

NC0
NC1
NC2
R241 R242
Notes: DNI 0
Place the 10uF capacitor close to ferrite bead.

3
8
9
1
13
14
Place the 0.1uF capacitor close to MAX 10 pin.
1.2V_VCCIO_ENABLE

C119
EP5348UI
DNI

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 22 of 25

 5 4 3 2 1

MAX 10 POWER & GROUND

D D

U1G

MAX 10 POWER
Note: 1.2V_CORE
According to MAX 10 pin 3.3V U1H
connection guideline N12 L6
N10 VCC VCCIO1A K7
PCG-01018-1.2, M13 VCC VCCIO1A M6
MAX 10 GROUND
"Tie the VCCINT pin to any M12 VCC VCCIO1B L7 K12
1.2V power domain if you M11 VCC VCCIO1B 1.8V Y9 GND K10
VCC GND GND
are not using ADC." L12
VCC VCCIO2
R6 Y15
GND GND
K3
Therefore, connect VCCINT L11
VCC VCCIO2
P7 Y12
GND GND
J6
to 1.2V_CORE for DC or DF L10 N7 W21 J2
K13 VCC VCCIO2 N6 V6 GND GND J19
production device migration. K11 VCC VCCIO2 2.5V V2 GND GND J16
1.2V_VCCD_PLL VCC U9 V19 GND GND G8
VCCIO3 U8 U13 GND GND G6
T7 VCCIO3 T9 U10 GND GND G21
C G16 VCCD_PLL1 VCCIO3 T11 T8 GND GND G18 C
VCCD_PLL2 VCCIO3 GND GND
Note: G7
VCCD_PLL3 VCCIO3
T10 T4
GND GND
G15
According to MAX 10 pin U16
VCCD_PLL4
2.5V T16
GND GND
F13
2.5V_VCCA U14 T14 F10
connection guideline VCCIO4 U12 R21 GND GND E7
PCG-01018-1.2, R8 VCCIO4 U11 R19 GND GND E2
"Tie the VCCA_ADC pin H15 VCCA1 VCCIO4 T13 P6 GND GND D4
to any 2.5V power domain H8 VCCA2 VCCIO4 T12 P2 GND GND D20
VCCA3 VCCIO4 GND GND
if you are not using ADC, T15
VCCA4
1.2V_VCCIO P17
GND GND
D16
and do not tie the VCCA_ADC 1.2V_CORE
VCCIO5
T17 N13
GND GND
D11
pin to GND." 2.5V_VCCA R17 N11 B9
J7 VCCIO5 R16 M7 GND GND B6
Therefore, connect VCCA_ADC H7 VCCINT VCCIO5 P16 M19 GND GND B18
to 2.5V_CORE for DC or DF 2.5V_VCCA VCCA_ADC VCCIO5 N16 M16 GND GND B13
production device migration. R267 DNI VCCIO5 1.2V_VCCIO M10 GND GND AB22
ADC_VREF H6 N17 L5 GND GND AB1
ADC_VREF VCCIO6 M17 L21 GND GND AA4
VCCIO6 L16 L17 GND GND AA18
G5 VCCIO6 K17 L13 GND GND A22
ANAIN1 VCCIO6 GND GND
Note: J5
ANAIN2 VCCIO6
K16
GND
A1
For ES device, connect ADC_VREF to NC VCCIO6
J17
when not using external voltage reference. H16
VCCIO6 3.3V L3 E5
For DC/DF production device, ADC_VREF G14 H5 DNU NC1 F6
pin is migrated to VCCA according to MAX VCCIO7 G13 REFGND NC2
10 Errata. VCCIO7 G12
VCCIO7 F14 10M50DAF484
VCCIO7 F12
VCCIO7 3.3V
B VCCIO8
G11 B
G10
VCCIO8 F9
VCCIO8 F11
VCCIO8

10M50DAF484

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

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Date: Thursday, March 24, 2016 Sheet 23 of 25

 5 4 3 2 1

DECOUPLING

D D

Notes:
1.2V_CORE Notes: 1.2V_VCCD_PLL Notes: 1.2V_VCCIO Place 100uF near LPDDR2 or between LPDDR2 and MAX10.
Place capacitor near MAX 10 pins. Place a 0.1uF capacitor close to each MAX 10 VCCD pin. Place 1.0uF and 0.1uF capacitors close to MAX 10 VCCIO5 and VCCIO6 pins.

C221 C222 C223

C145 C146 C147 C148 C232 C194 C149 C233 C234 C235 C236
1.0UF 1.0UF 1.0UF
0.1uF 0.1uF 0.1uF 0.1uF DNI 1.0UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

C C
C224 C225 C226 C227 C228 C229 C230 C231

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

1.8V Notes: 2.5V_VCCA Notes: 3.3V Notes:

Notes: 2.5V Place these capacitors close to MAX 10 VCCIO3 and VCCIO4 pins. Place these capacitors close to each MAX 10 VCCA pin. Place these capacitors close to MAX 10 VCCIO7 and VCCIO8 pins.
Place these capacitors close to MAX 10 VCCIO2. Place one 0.1uF close to MAX 10 VCCA_ADC pin.

C155 C156
C196 C197 C144 C239 C124 C206 C237 C238
0.1uF 0.1uF
4.7uF 0.22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

B B

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

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Date: Thursday, March 24, 2016 Sheet 24 of 25

 5 4 3 2 1

QSPI FLASH

D D

3.3V

C169 C170 Notes: FLASH_RESETn 7,15

Place the two caps near QSPI flash
QSPI FLASH 4.7uF 0.1uF
R244 FLASH_CSn 7
U23 2.0K
2
3.3V FLASH_D0 15 VCC FLASH_CLK
DQ0 7
FLASH_D1 8 3 FLASH_RESETn
FLASH_D2 9 DQ1 RESET 4
FLASH_D3 1 DQ2/VPP/W# DNU2 5 FLASH_D[0:3]
DQ3/HOLD# DNU3 7
R245 6
FLASH_CLK 16 DNU4 11
C DNI C DNU5 12 C
FLASH_CSn 7 DNU6 13
S# DNU7 14
DNU8
10
VSS
N25Q512A83GSF40F
Manufacturer = Micron
PART_NUMBER = N25Q512A83GSF40F

B B

A A

Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203

Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Title
MAX 10 FPGA 10M50 Evaluation Kit (6XX-44364R)

Size Document Number Rev

A3 <Doc> A1.2

Date: Thursday, March 24, 2016 Sheet 25 of 25