DESIGNWARE IP DATASHEET
Interface IP Subsystems
Highlights
• Accelerate interface IP subsystem
development for complex protocols, such
as DDR, PCIe®, USB, and Ethernet, as well
as multiprotocol subsystems
• Meet critical project schedules by using
Synopsys IP protocol and SoC design
experts to configure and customize the
pre-designed subsystem to the unique
SoC requirements
• Minimize the subsystem integration
effort through the use of pre-validated
subsystem and verification tests focused
on SoC integration
• Reduce overall development costs while
Total cost of IP Integration normalized
enabling designers to focus on their key
competencies
• Provide functionality and value over
simple integration of a PHY and controller
by including a common register interface
between the PHY and controller, debug
logic, and more
synopsys.com/designware
Overview
Customers are increasingly utilizing third-party standards-based IP in their
designs, but face several challenges. With more IP and more complex interface
protocols, the integration effort to incorporate all of the IP into an SoC can take
much longer. Companies are spending as much on integration effort as they
are on their IP while project schedules are getting shorter.
DesignWare® Interface IP Subsystems, one part of the IP Accelerated initiative,
reduce design risk and accelerate time-to-market. The DesignWare Interface
IP Subsystems consist of pre-validated, fully integrated solutions that utilize
Synopsys’ IP and tools for the specific SoC application. DesignWare Interface
IP Subsystems reduce the overall effort and cost of assembling and integrating
IP into an SoC, allowing designers to focus their efforts on differentiating their
product and speeding time-to-market.
250
200
Overall
savings
to cost of IP
150
100
Customer integration effort
50
DesignWare Interface IP Subsystem
IP cost
0
Today Future
Figure 1: Time-to-market savings with DesignWare Interface IP Subsystems
During the IP subsystem engagement, Synopsys experts assist in every
stage of SoC design and work directly with the designers to determine design
feasibility and performance metrics that are captured in a design specification.
Using this specification, Synopsys experts configure, integrate and verify
the IP and surrounding logic into a customized IP subsystem. Working with
designers to accurately capture design intent at both the block and chip levels,
Synopsys experts help to minimize iterations between the architecture and RTL
implementation, thereby reducing subsystem integration time.
Efficient Customization of Pre-Designed Subsystems
The key to providing a cost-effective customized IP subsystem that is specific to an SoC is leveraging a series of pre-designed
subsystem architectures, blocks, and testbenches. To ensure timely and efficient customization, Synopsys assembles and modifies
IP blocks, adds custom blocks or features to meet the customer specification, and then verifies the subsystem in the context of the
SoC. With this approach, Synopsys can quickly provide a customized IP subsystem for each design that reduces cost and time while
integrating the specified features. In addition, Synopsys’ customized IP subsystems provide extra functionality and value over simply
integrating a PHY and controller, e.g., common register interface between the PHY and controller, debug logic, and more.

Testbench environment

Clock
VIP Controller and reset
IP

Register
RAMs interface

Control
registers

PHY Debug
VIP module
IP

Figure 2: DesignWare Interface IP Subsystems include PHY, controller, and supplemental logic for clock, reset, DMA and
interrupts,power management, debug and test, and verification

Deliverables
• Pre-configured, pre-validated Synopsys IP for controllers, PHYs and verification IP (VIP)
• Supplemental subsystem logic for clock, reset, DMA, interrupts, and memory maps
• Power management, debug, and testability logic
• Complete subsystem verification environment that can also be leveraged for SoC verification:
––Scoreboard, checkers and monitors for easy SoC debug
––Comprehensive suite of tests that can be reused at SoC level

2
DesignWare Interface IP Subsystem Process
The process for developing and deploying DesignWare Interface IP Subsystems consists of five phases:

1. Capture: Synopsys and the design team analyze, define and capture the unique requirements for the SoC, which can include
performance requirements, configuration information, customization, target technology, package type, clocking and reset
requirements and signoff corners
2. Design: Using the specifications captured with the customers, Synopsys configures and customizes the interface subsystem to
the design requirements
3. Verification and Analysis: Utilizing the pre-designed interface subsystem verification environment, Synopsys verifies that the
interface subsystem meets the design requirements, design metrics, and quality goals defined in the Capture phase
4. Deploy: Synopsys deploys the subsystem to the customer, including on-site subsystem/SoC integration assistance
5. Post-Silicon Support: Upon return of the device from the fab, on-site assistance during SoC bring-up is available

About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP
portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired interface IP, wireless interface IP,
security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP
into SoCs, Synopsys’ IP Accelerated initiative offers IP Prototyping Kits, IP Virtualizer Development Kit and IP subsystems.
Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology
enables designers to reduce integration risk and accelerate time-to-market.

For more information on DesignWare IP, visit synopsys.com/designware .

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08/21/18.CS12066_Interface_IP_DS.