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REGULATION 2013

EE6303 LINEAR INTEGRATED CIRCUITS AND APPLICATIONS L T P C

3 0 03
UNIT I IC FABRICATION 9
IC classification, fundamental of monolithic IC technology, epitaxial growth, masking and etching, diffusion of
impurities. Realization of monolithic ICs and packaging. Fabrication of diodes, capacitance, resistance and
FETs.
UNIT II CHARACTERISTICS OF OPAMP 9
Ideal OP-AMP characteristics, DC characteristics, AC characteristics, differential amplifier; frequency response
of OP-AMP; Basic applications of op-amp – Inverting and Non-inverting Amplifiers-V/I & I/V
converters,summer, differentiator and integrator. UNIT III APPLICATIONS OF OPAMP 9
Instrumentation amplifier, Log and Antilog Amplifiers, first and second order active filters, comparators,
multivibrators, waveform generators, clippers, clampers, peak detector, S/H circuit, D/A converter (R- 2R
ladder and weighted resistor types), A/D converters using op-amps.
UNIT IV SPECIAL ICs 9
Functional block, characteristics & application circuits with 555 Timer IC-566 voltage controlled oscillator IC,
565-phase lock loop IC ,Analog multiplier ICs.
UNIT V APPLICATION ICs 9
IC voltage regulators –LM78XX,79XX Fixed voltage regulators - LM317, 723 Variable voltage regulators,
switching regulator- SMPS- LM 380 power amplifier- ICL 8038 function generator IC.
TOTAL: 45 PERIODS
TEXT BOOKS:
1. David A. Bell, ‘Op-amp & Linear ICs’, Oxford, 2013.
2. D. Roy Choudhary, Sheil B.Jani, ‘Linear Integrated Circuits’, II edition, New Age, 2003.
3. Ramakant A.Gayakward, ‘Op-amps and Linear Integrated Circuits’, IV edition, Pearson Education,
2003, PHI. 2000.
REFERENCES:
1. Fiore,‘Op-amps & Linear Integrated Circuits Concepts &
Applications’,Cengage,2010.
2

2. Floyd , Buchla, ‘Fundamentals of Analog Circuits’, Pearson, 2013.

3. Jacob Millman, Christos C.Halkias, ‘Integrated Electronics - Analog and Digital circuits system’, Tata
McGraw Hill, 2003.
4. Robert F.Coughlin, Fredrick F. Driscoll, ‘Op-amp and Linear ICs’, PHI Learning, 6th edition, 2012.
3

Department of Electrical and Electronics Engineering Detailed Lesson Plan

Name of the Subject& Code: EE 6303 & LINEAR INTEGRATED CIRCUITS
AND APPLICATIONS
Name of the Faculty:
TEXT BOOKS:
1. David A. Bell, ‘Op-amp & Linear ICs’, Oxford, 2013.

Sl. No

Unit

Topic / Portions to be Covered

Hours Required /
Planned
Cumulative Hrs
Books Referred
 UNIT I
IC FABRICATION

1 I IC classification 1 1 T2
2 I Fundamental of monolithic IC
technology 1 2 T2
3 I Epitaxial growth 1 3 T2
4 I Masking and etching 1 4 T2
5 I Diffusion of impurities 1 5 T2
6 I Realization of monolithic ICs and
packaging 1 6 T2
7 I Fabrication of diodes 1 7 T2

8 I Fabrication of capacitance 1 8 T2
9 I Fabrication of resistance 1 9 T2
10 I Fabrication of FETs 1 10 T2
UNIT II CHARACTERISTICS OF OPAMP
11 II Ideal OP-AMP characteristics1 11 T2
12 II DC characteristics 1 12 T2
13 II AC characteristics 1 13 T2
14 II Differential amplifier 1 14 T2
15 II Frequency response of OP-AMP 1 15 T2
16 II Basic applications of op-amp – Inverting
and Non-inverting Amplifiers
2 17 T2
17
II
V/I & I/V converters
1
18
T2

18
II
Summer, differentiator and integrator
2
20
T2

UNIT III APPLICATIONS OF OPAMP

19
III
Instrumentation amplifier
1
21
T2

20
III
Log and Antilog Amplifiers
1
22
T2

21
III
First and second order active filters
1
23
T2

22
III
Comparators
1
24
T2

23
III
Multivibrators
1
25
T2

24
III
Waveform generators
1
26
T2

25
III
Clippers, clampers, peak detector, S/H
circuit
2
28
T2

26
III
D/A converter (R- 2R ladder and
weighted resistor types) 1
29
T2

27 III A/D converters using op-amps 1 30 T2

UNIT IV SPECIAL ICs
28 IV Functional block of 555 Timer 1 31 T2
29 IV Characteristics of 555 Timer 1 32 T2
30 IV Application circuits with 555 Timer 2 34 T2
31 IV IC-566 voltage controlled oscillator IC 1 35 T2
32 IV IC 565-phase lock loop IC 1 36 T2
33 IV Analog multiplier ICs 2 38 T2
UNIT V APPLICATION ICs

34 V IC voltage regulators –LM78XX,79XX 2 40 T2

35 V Fixed voltage regulators 1 41 T2
36 V LM317, 723 Variable voltage regulators 2 43 T2
37 V Switching regulator 1 44 T2
38 V SMPS 1 45 T2
39 V LM 380 power amplifier 1 46 T2
40 V ICL 8038 function generator IC 1 47 T2
6

INDEX

Unit No Q.NO Content Page No

Cover page 1
Syllabus 2-3
Lesson plan 4-6
I 1-12 Part A 9-11
I 1-5 Part B 11-25
I 1 Steps involved in fabrication of
IC 1-14
I 2 Fabrication of diodes and
capacitors
14-17
I
3
Fabrication of Resistors & FET
17-21

I
4
Photolithography
21-23

I
5
Different IC packages
24-25

II
1-15
Part A
26-28

II
1-6
Part B
28-52

II
1
Dc characteristics of Op-amp
28-33

II
2
Ac characteristics of Op-amp
33-37

II
3
Differentiator & Integrator
37-41

II
4
Differential amplifier
42-45

II
5
Inverting and Non-inverting
amplifier
45-48

II
6
Applications of Op-amp
48-52

III 1-10 Part A 53-54

III 1-5 Part B 55-68
III 1 Instrumentation amplifier 55-58
III 2 Schmitt trigger 58-60
III 3 R-2R DAC 60-62
III 4 Successive approx. type ADC 62-64
III 5 II order LPF 64-68
IV 1-15 Part A 69-70
IV 1-4 Part B 71-79
IV 1 Monostable multivibrator 71-72
7
IV 2 Astable multivibrator 73-74
IV 3 PLL 75-77
IV 4 VCO 77-79
V 1-15 Part A 80-83
V 1-5 Part B 83-98
V 1 LM 380 power amplifier 83-87
V 2 IC 723 general purpose
regulator 87-88
V 3 IC 8038 Function generator 89-91
V 4 LM 317 IC 92-94
V
5
Optocoupler IC
94-98

University question papers

99-118
8

UNIT I
IC FABRICATION
Part - A
1. Define an Integrated circuit.
An integrated circuit(IC) is a miniature, low cost electronic circuit consisting of active and passive components
fabricated together on a single crystal of silicon. The active components are transistors and diodes and passive
components are resistors and

silicon.
The basic chemical reaction in the Epitaxial growth process of pure silicon is the Hydrogen reduction of silicon
tetrachloride
1200oC
SiCl 4 + 2H2 < > Si + 4 HCl

5. What are the two important properties of SiO2?

SiO2 is an extremely hard protective coating & is unaffected by almost all reagents except by
hydrochloric acid. Thus it stands against any contamination.
By selective etching of SiO2, diffusion of impurities through carefully defined windows in the SiO2 can
be accomplished to fabricate various components.
6. Explain the process of oxidation.
The silicon wafers are stacked up in a quartz boat & then inserted into quartz furnace tube. The Si wafers are
raised to a high temperature in the range of 950 to 1150oC & at the same time, exposed to a gas containing
O2 or H2O or both. The chemical action is
Si + 2H2O > SiO2 + 2H2
7. What is lithography?
Lithography is a process by which the pattern appearing on the mask is transferred to the wafer. It involves
two steps: the first step requires applying a few drops of photo resist to the surface of the wafer & the second
step is spinning the surface to get an even coating of the photo resist across the surface of the wafer.
8. What are the two processes involved in photolithography?
a) Making a photographic mask :
The development of photographic mask involves the preparation of initial artwork and its reduction,
decomposition of initial artwork or layout into several mask layers.
b) Photo etching :
Photo etching is used for the removal of SiO2 from desired regions so that the desired impurities can be
diffused.
9. Define diffusion. (April/May 2015)
The process of introducing impurities into selected regions of a silicon wafer is called diffusion. The rate at
which various impurities diffuse into the silicon will be of the order of 1µm/hr at the temperature range of 900oC
to 1100o C .The impurity atoms have the tendency to move from regions of higher concentrations to lower
concentrations.

10

10. What are the advantages of ion implantation technique? (April/May 2015)
• It is performed at low temperature. Therefore, previously diffused regions have a lesser tendency for
lateral spreading.
• In diffusion process, temperature has to be controlled over a large area inside the oven, whereas in ion
implantation process, accelerating potential & beam content are dielectrically controlled from outside.
11. What are the advantages of IC over discrete components? (April/May 2015) (Nov/Dec 2014) (Nov/Dec
2016)
The various steps in the fabrication of monolithic IC is described below
1. Wafer preparation 2. Epitaxial growth 3 .Oxidation
4. Isolation diffusion 5. Base diffusion 6.Emitter diffusion
7. Aluminum metallization

11

i. Wafer Preparation:
• The starting material called the substrate is a p-type silicon wafer. The wafers are usually 10cm
diameter and 0.4mm thickness.
• The resistivity is 10Ω/cm corresponding to the concentration of acceptor atom NA=1.4X1015atoms/cm
Step 1
Fig 1.3 Oxidation

12

iv. Isolation layer:

• In the circuit, four components have to be fabricated, so we required four island which are isolated(four
components are resistor, transistor, capacitor, diode)
Fig 1.4 Isolatioayer
• For this, SiO2 is removed from five different places using Photolithography.
• The wafer is next subjected to heavy p-type diffusion for a long time interval so that p-type impurities
penetrate the n-type epitaxial layer and reach the p-type substrate.
v. Base Diffusion:
• A new SiO2 layer is grown over entire pattern and a new pattern of opening formed using
photolithography technique.
• Now p-type mpurities such as Boron is diffused into the region of n-type epitaxial silicon the diffusion of
p-type silicon should be such that it should not penetrate through n-layer to the substrate.

Fig 1.5 Base diffusion

vi. Emitter Diffusion :
• A new type of SiO2 layer is grown over the entire wafer and selectively etched to open a new set of
windows and n-type impurity is diffused through them.
• This forms the transistor emitter and cathode region.

13

Fig 1.6 Emitter diffusion

The reason for using heavily doped n-region can be explained as follows:
• Aluminum normally used for making interconnection, is a p-type impurity in silicon and can produce an
unwanted rectifying contact with lightly doped n-material.
• However heavy concentration of Phosphorous (n+) layer makes a good ohmic contact with Al-layer.
Hence it is desirable to use heavily doped n- region.
vii. Aluminium Metallization:
• Now the IC chip is complete with all active and passive devices and only interconnect on between the
various components have to be made.
• Then a thin coating of Al is vacuum deposited over the entire surface of the wafer.
• The interconnect on between the components is then formed by photo resistive techniques.
• The undesired Al areas are etched away leaving a pattern interconnection between transistor, resistor,
diode, and capacitor is shown below.
Fig 1.7 Aluminium metallization

14

2. Explain the various methods of fabricating diodes and capacitors in monolithic integrated circuits.
(April/May 2015)
Fabrication of Diode:
• Diodes find extensive use in Integrated Circuits. The integrated diode is used as Schottky Barrier
Diode. The other name of this diode is metal semiconductor diode.
• The metal to semiconductor junction can be ohmic as well as rectifying. The ohmic contact is used
when a load is to be attached to a semiconductor
• The cross sectional view and symbol of a Schottky barrier diode as shown in figure. Contact 1 shown
in figure is a Schottky barrier and the contact 2 is an ohmic contact.
• The contact potential between the semiconductor and the metal generated a barrier for the flow of
conducting electrons from semiconductor to metal.

15

• When the junction is forward biased this barrier is lowered and the electron flow is allowed from
semiconductor to metal, where the electrons are in large quantities.
• The majority carriers carry the conduction current in the Schottky diode whereas in the PN junction
diode, minority carriers carry the conduction current and it incurs an appreciable time delay from ON state to
OFF state.
• This is due to the fact that the minority carriers stored in the junction have to be totally
removed.
Fig 1.9 Junction capacitor & its equivalent circuit
• There are two junctions in the diffused capacitor. They are J1 and J2. The two diodes are idealized
diodes.

16

• The parasitic capacitance C1 is inevitable due to the junction J1 between n- type epitaxial layer and the
substrate.
• The substrate must be held at the most negative point in the circuit to minimize C1.
• During the reverse biased condition J2 will produce the desired capacitance.
• The value of the capacitance C2 will depends upon the area of the junction, impurity
concentration of the n-type epitaxial layer and the voltage across the junction.
• The capacitor C2 is polarized and is obtained only when the junction J2 is reverse biased.
MOS and Thin film capacitor:
• Commonly used capacitor is the metal oxide semiconductor capacitor, the cross sectional view and the
equivalent circuit is,

Fig 1.10 MOS and Thin film capacitor

• It is basically a parallel plate capacitor with SiO2 as the dielectric. During emitter diffusion the heavily
doped n+ region formed in the lower plate. The thin film Al metallization is formed in upper plate of the
capacitor with SiO2 as the dielectric.
• In the equivalent circuit, the parasitic effect consist of a small series resistance R due to n+ region, a
collector substrate junction J1 and its associated capacitance C1.
Thin film Capacitors:
• Thin film capacitors structures used in thin dielectric film layer between two metal layers.

17
• It requires additional masking and deposition steps beyond the MOS structure. In thin film structure
aluminum or tantalum is used as capacitor plates Al2O5 or Ta2O5 as dielectric material.
• Ta2O5 is preferred for large value of capacitors. This is a destructive and irreversible failure
mechanism and may require over voltage protection.
Disadvantage:
• Thin film capacitor fails when the voltage rating exceeds due to breakdown of the dielectric.
3. Completely describe in detail the various stages involved in the fabrication of a R and FET in a
single chip. (April/May 2015)
Integrated Resistors:
• A resistor in a monolithic integrated circuit is obtained by utilizing the bulk resistivity of the diffused
volume of semiconductor region. The commonly used methods for fabricating integrated resistors are
a. Diffused resistor
b. Epitaxial resistor
c. Pinched resistor
d. Thin film techniques.
a. Diffused Resistor:
• The diffused resistor is formed in any one of the isolated regions of epitaxial layer during base or
emitter diffusion processes.
• This type of resistor fabrication is very economical as it runs in parallel to the bipolar transistor
fabrication.
• The N-type emitter diffusion and P-type base diffusion are commonly used to realize the monolithic
resistor.
• The diffused resistor has a severe limitation in that, only small valued resistors can be fabricated.
• The surface geometry such as the length, width and the diffused impurity profile determine the
resistance value.
• The commonly used parameter for defining this resistance is called the sheet resistance. It is defined
as the resistance in ohms/square offered by the diffused area.

18

• In the monolithic resistor, the resistance value is expressed by R = Rs L/W, where R= resistance
offered (in ohms), Rs = sheet resistance of the particular fabrication process involved (in ohms/square), L =
length of the diffused area and W = width of the diffused area.
• The sheet resistance of the base and emitter diffusion in 200Ω/square and 2.2Ω/square respectively.

b. Epitaxial Resistor:
• The sheet resistance

Fig 1.12 Pinched resistor

offered by the diffusion regions can be

increased by

narrowing down its cross-sectional area. This type of resistance is normally achieved in the base region. Figure
shows a pinched base diffused resistor.
• It can offer resistance of the order of mega ohms in a comparatively smaller area.

19

• In the structure shown, no current can flow in the N-type material since the diode realized at contact 2
is biased in reversed direction.
• Only very small reverse saturation current can flow in conduction path for the current has been reduced
or pinched.
• Therefore, the resistance between the contact 1 and 2 increases as the width narrows down and hence
it acts as a pinched resistor.

d. Thin film resistor:

Fabrication of FET:
Unipolar monolithic ICs use JFET or MOSFET as active device .The fabrication techniques of (i). JFET
(ii). MOSFET
(iii) CMOS is discussed below
JFET Fabrication:
The basic process of JFET Fabrication is same as in BJT fabrication

20
Fig 1.14 JFET fabrication
• The epitaxial layer which formed the col ector of the BJT is used as the n- channel of the JFET. The P+
gate is formed in the n-channel by the process of diffusion or Ion implantation. The n+ regions have been
formed the drain and source contact region to provide good ohmic contac .

4. Explain the process involved in the epitaxial photolithography.

(April/May 2015)

growth and

Epitaxial Growth:
• Epitaxy is described as arranged atoms in a single crystal fashion upon a single crystal substra e. The
basic chemical reaction used for the epitaxial growth of pure silicon is the hydrogen reaction of SiCl4

SiCl4+2H2 12 oC
• In an IC fabrication

Si+4HCL
epitaxial films with specific impurity concentration are

required. Th s is accomplished by introducing phosphine (PH3) for the n-type Bi-Borane (B2H6) for P-type
doping into the silicon-tetrachloride hydrogen gas stream.

Fig 1.15 Epitaxial growth

21

• The process is carried out in a reaction chamber consisting of a long cylindrical quartz tube encircled by
an RF induction coil.
• The silicon wafers are placed on a rectangular graphite rod called a boat. This boat is then placed in
the reaction chamber where the graphite is heated inductively to a temperature 12000C.
• The various gases required for the growth of desired epitaxial layers are introduced into the system
through a control console.
Photolithography:
It can be used to produce microscopically small circuit and device patterns on Si-wafers. Photolithography
involves two processes, namely
1. Making of a photographic mask
2. Photo etching
Making of a photographic mask:
It involves the following sequence of operations
1. The preparation of artwork
2. Its reduction
• The initial layout or artwork of an IC is normally done at a scale several hundred times larger than the
final dimension of the finished monolithic circuit. This is because for a tiny chip more accurate is the final mask.
This initial layout is then decomposed into several mask layers.
• The artwork is usually produced on a precision drafting machine known as coordinagraph.
• The coordinagraph has a cutting head that can be positioned accurately and moved along two
perpendicular axes.
• The coordinagraph out lines pattern cutting through the red mylar without damaging the clear layer
underneath.
• This rubylith pattern of individual mask is photographed and then reduced in step by a factor of 5 or 10
several times to finally obtain the exact image size.
• The final image size also must be repeated many times in a matrix array, so that many ICs will
be produced in one process.
• The photo repeating is done with a step and repeat camera. This is an imaging device with a
photographic plate on a removable platform.

22

Photo etching:
• Photo etching is used for the removal of SiO2 from desired regions so that the desired impurities can
be diffused. The wafer is coated with a film of photosensitive emulsion (Kodak Photo resist KPR). The
thickness of the film in the range 5000-10000A0
Fig 1.16 (c) Photo etching step 3
• The polymerized photo resist next fixed or curved, so that it becomes immune to certain chemicals
called etchants used in subsequent processing steps. The chip is immersed in the etching solution of HCl,
which removes the SiO2 from the area which are not protected by KPR

23

Fig 1.16 (d) Photo etching step 4

• After diffusion of impurities the photo resist is removed with a chemical solvent (H2SO4) and
mechanical abrasion. This etching process is a wet etching process and the chemical reagents used are in
liquid form.

5. Explain the different IC packages. MONOLITHIC IC PAKAGE:

There are 3 different package configurations are available they are
1. Metal can package
2. Ceramic flat package
3. Dual-in-line package
METAL CAN or TRANSISTOR PACKAGE:
• The chip is encapsulated in a metal or plastic case. The transistor pack is available with 3, 5, 8, 10 or
12 pins.
• The metal can package is best suited for power amplifiers because metal is good heat conductor and
consequently has a better dissipation capability than the flat back or dual-in-line package.
Fig 1.17 Metal can

24

• The metal can package permits the use of external heat sink. Most of the general purpose of Op-Amps
comes in 8, 10 or 12 pin packages.
• Voltage regulator ICs such as LM117 has 3-pins. Power Op-Amps and audio power amplifiers are
usually available in 5 pin packages.
CERAMIC FLAT PACKAGE
• The chip is enclosed in a rectangular ceramic case with terminal leads extending through the sides
and ends.
• The flat pack comes with 8, 10, 14 or 16 leads.
• Digital ICs are DIP packages; Metal can packages are also available with dual- in-line formed leads
(DIL-CAN) and with radial formed leads.
• Different outlines exist within each package style to accommodate various die sizes and number of
pins.
• For Example TO-99, TO-100 and TO-101 are some of the outlines available in a transistor.

25

Fig 1.19 Dual-in-line package

26

Part - A

UNIT II CHARACTERISTICS OF OP-AMP

1. What are the advantages of ICs over discrete circuits?

Minimization & hence increased equipment density.
Cost reduction due to batch processing.
Increased system reliability
Improved functional performance.
Matched devices.
Increased operating speeds
Reduction in power consumption
2. What is OPAMP?
An operational amplifier is a direct coupled high gain amplifier consisting of one or more differential amplifiers,
followed by a level translator and an output stage. It is a versatile device that can be used to amplify ac as well
as dc input signals & designed for computing mathematical functions such as addition, subtraction,
multiplication, integration & differentiation
.3. List out the ideal characteristics of OPAMP?
Characteristics of an ideal operational amplifier:
1. Open loop voltage gain AOL = ∞ (infinity)
2. Input impedance Ri = ∞ (infinity)
3. Output impedance Ro = 0 (zero)
4. Zero offset Vo = 0 (zero)
5. Band width BW = ∞ (infinity)
4. what are the different kinds of packages of IC741?
a) Metal can (TO) package
b) Dual- in- line package
c) Flat package or flat pack
5. What are the assumptions made from ideal op amp characteristics?
• The current drawn by either of the input terminals(non -inverting/inverting) is negligible.
• The potential difference between the inverting & non- inverting input terminals is zero.

27

6. Mention some of the linear applications of op – amps:

Adder, subtractor, voltage –to- current converter, current –to- voltage converters, Instrumentation amplifier,
analog computation, power amplifier, etc are some of the linear op-amp circuits.
7. Mention some of the non – linear applications of op-amps:-
Rectifier, peak detector, clipper, clamper, sample and hold circuit, log amplifier, anti –log amplifier, multiplier
are some of the non – linear op-amp circuits.
8. What are the areas of application of non- linear op- amp circuits?
Industrial instrumentation
Communication
Signal processing
9. Define input offset voltage.
A small voltage applied to the input terminals to make the output voltage as zero when the two input terminals
are grounded is called input offset voltage.
10. Define input offset current. State the reasons for the offset currents at the input of the op-amp.
The difference between the bias currents at the input terminals of the op-amp is called as input offset current.
The input terminals conduct a small value of dc current to bias the input transistors. Since the input transistors
cannot be made identical, there exists a difference in bias currents.
11. Define CMRR of an op-amp.
The relative sensitivity of an op-amp to a difference signal as compared to a common –mode signal is called
the common –mode rejection ratio. It is expressed in decibels. CMRR= Ad/Ac
12. Define slew rate.
The slew rate is defined as the maximum rate of change of output voltage caused by a step input voltage. An
ideal slew rate is infinite which means that op- amp’s output voltage should change instantaneously in
response to input step voltage.
13. Why IC 741 is not used for high frequency applications?
IC741 has a low slew rate because of the predominance of capacitance present in the circuit at higher
frequencies. As frequency increases the output gets distorted due to limited slew rate.

28

14. What causes slew rate?

There is a capacitor with- in or outside of an op-amp to prevent oscillation. It is this capacitor which prevents
the output voltage from responding immediately to a fast changing input.
15. Define thermal drift.
The bias current, offset current & offset voltage change with temperature. A circuit carefully nulled at 25oC may
not remain so when the temperature rises to 35oC.This is called thermal drift. Often, offset current drift is
expressed in nA/oC and offset voltage
 Input bias current IB as the average value of the base currents entering into the terminals of the op-
amp

29
By selecting proper value of Rcomp, V2 can be cancelled with V1 and the Vo = 0. The value of Rcomp is
derived a
V1 = I + R (or)
I + = V /R (2)
The node ‘a’ is at voltage (-V1). Because the voltage at the non-inverting input terminal is (-V1). So with Vi = 0
we get,
I1 = V1 / R1 (3)

30

I2 = V2 / Rf (4)
For compensation, Vo should equal to zero (Vo = 0, Vi = 0). i.e. from equation (1) V2 = V1. So that,
I2 = V1 / Rf (5)
KCL at node ‘a’ gives,
I-=I+I

A f / fa

V V R1 Rf

1 ( f / f )2

I 1

1 V
b B R R 1 RR
f 1 1 f

Assume I - = I + and using equation (4) & (8) we get

R1 Rf
V1
R1Rf

V1
Rcomp

Rcomp

R1Rf R1 Rf

R1 □ Rf

Rcomp = R1 || Rf (6)
i.e. to compensate for bias current, the compensating resistor, Rcomp should be equal to the parallel
combination of resistor R1 and Rf.
2. Input offset current:
Bias current compensation will work if both bias currents I + and I - are equal.
Since the input transistor cannot be made identical. There will always be some small difference
between I + and I -. This difference is called the offset current
|Ios| = I + - I - (1)
Offset current Ios for BJT op-amp is 200nA and for FET op-amp is 10pA. Even with bias current
compensation, offset current will produce an output voltage when Vi = 0.
V1 = I + R (2)
And I1 = V1/R1 (3)
KCL at node ‘a’ gives,
I2 = (I —I )

I I

I I

Rcomp

(Sub the value of I )

2 B 1
B B

2
R1

Again, V0 = I2 Rf – V1
Vo = I2 Rf - I + Rcomp
31

V I

I Rcomp R

I R

(4)

o B B

R1

f B comp

Substitute the value Rcomp in equation (4) and after algebraic manipulation,

V R

I I

The offset current can be minimized by keeping feedback resistance small.

• This is due to unavoidable imbalances inside the op-amp and one may have to apply a small voltage at
the input terminal to make output (Vo) = 0.
• This voltage is called input offset voltage Vos. This is the voltage required to be applied at the input for
making output voltage to zero (Vo = 0).

32
Fig 2.4 Input offset voltage & its equivalent circuit
Let us determine the Vos on the output of inverting and non-inverting amplifier. If Vi = 0 (Fig (b) and (c))
become the same as in figure (d). The voltage V2 at the negative input

terminal is given by,

V R1 V

2 R R o

V R1 Rf V

1 f

o 2
R1
V 1 Rf V
o R 2

Vios Vi V2

1
and Vi=0, Vios 0 V2

V2

33

V 1 Rf V
o R ios
1
This is the output offset voltage of an op-amp in closed loop configuration
4. Thermal drift:
A circuit nulled at 250C may not remain so the temperature rises to 350C.This is called drift. Bias current,
offset current, offset voltage change with temperature.
offset current drift is expressed as nA/oC
offset voltage drift is expressed as mV/oC.
These indicate the change in offset for each degree Celsius change in temperature.
2. Explain in detail about the AC characteristics of the OP-AMP. AC Characteristics:
• For small signal sinusoidal (AC) application one has to know the ac characteristics such as frequency
response and slew-rate.
Frequency Response:
• The variation in operating frequency will cause variations in gain magnitude and its phase angle.
• The manner in which the gain of the op-amp responds to different frequencies is called the frequency
response.
• Op-amp should have an infinite bandwidth Bw = ∞ (i.e) if its open loop gain in 90dB with
dc signal its gain should remain the same 90 dB through audio and onto high radio frequency.
• The op-amp gain decreases (roll-off) at higher frequency what reasons to decrease gain after a certain
frequency reached.
• There must be a capacitive component in the equivalent circuit of the op-amp.
• For an op-amp with only one break (corner) frequency all the capacitors effects can be represented by
a single capacitor C.
• Below fig is a modified variation of the low frequency model with capacitor C at the o/p.

34

Fig 2.5 Frequency response equivalent circuit

There is one pole due to R0 C and one -20dB/decade. The open loop voltage gain of
and phase angle of the open loop volt gain are fu of frequency can be written as,

Magnitude

A Aol

(2)

Phase angle
(3)

tan1 f

/f1

35

The magnitude and phase angle characteristics from equations (2) and (3)
• For frequency f<< f1 the magnitude of the gain is 20 log AOL in dB.
• At frequency f = f1 the gain in 3 dB down from the dc value of AOL in dB. This frequency f1 is called
corner frequency.
• For f > > f1 the fain roll-off at the rate off -20dB/decade or -6dB/decade.
 At the corner frequency f=f1 the phase angle is -450
-900 phase angle occurs at frequency (at f=∞)

The voltage transfer in a S-domain can be written as

A 1

Aol
j( f / f 1)

Aol
j( / 1)
36

Aol.1
A j 1

Aol.1 S 1

(4)

The transfer f0 of as op-amp with 3 break frequency can be assumed as,

A Aol

(1 jf / f 1)(1 jf /

f 1)(1

f / f 3)

0 < f1< f 2< f3

A Aol.1.2.3 (S 1)(S 2)(S 3)

0<ω1<ω2< ω3
• The rate at which the volt across the capacitor increases is given by

dVc / dt = I/C (1)

• I = Maximum amount furnished by the op-amp to capacitor C. Op-amp should have the either a higher
current or small compensating capacitors.
• For 741 IC, the maximum internal capacitor charging current is limited to about 15µA. So the slew rate
of 741 IC is

37

SR = dVc / dt |max = Imax/C.

• For a sine wave input, the effect of slew rate can be calculated as consider volt follower -> The input is
large amp, high frequency sine wave.
• If Vs = Vm Sinwt then output V0 = Vm sinwt . The rate of change of output is given by dV0/dt = Vm w
coswt.
(a) Differentiator:
• One of the simplest

of the op-amp circuits that contains capacitor in the

differentiating amplifier.
• As the name implies, the circuit performs the mathematical

operation of

differentiation (i.e) the output waveform is the derivative of the input waveform.
• The differentiator may be constructed from a basic inverting amplifier if an input resistor R1 is replaced
by a capacitor C1.

38

Fig 2.9 Differentiator circuit

voltage Vin with time.
The –sign indicates a 1800 phase shift of the output waveform V0 with respect to the input signal.
Phasor equivalent of output voltage is
V0 S Rf C1.SVi (S)

39

R C S jR C R C

f 1 f 1 f1

A f f 1

f where a

2RC

Input and Output Waveforms:

f 1

(2)

Fig 2.10 Input and output waveforms

The input signal will be differentiated properly, if the time period T of the input signal is larger than or equal to
RF C1 (i.e) T > RF C1

40
(b) Integrator:
• A circuit in which the output voltage waveform is the integral of the input voltage waveform is the
integrator or Integration Amplifier.
• Such a circuit is obtained by using a basic inverting amplifier configuration if the feedback resistor RF is
replaced by a capacitor CF .

i f

Equation (2) indicates that the output is directly proportional to the negative integral of the input volts and
inversely proportional to the time constant R1 CF . In phasor method the output voltage can be written as
41

Rf / Ri 1

(1 jf

/ fa )

Vo (s) sR C

Vi (s)

H ( j)

Rf

/ Ri 1 f

In steady state, put s = jω and we get

Vo ( j)

1
jR1C f

Vi ( j)

So the magnitude of the gain or integrator transfer function is

A Vo ( j)
Vi ( j)

1
jR1C f

1
R1C f

Ex: If the input is sine wave -> output is cosine wave. If the input is square wave -> output is triangular wave.
Fig 2.12 Input and output waveforms
• These waveform with assumption of R1 Cf = 1, Vout = 0V (i.e) C = 0.

42

• When Vin = 0 the integrator works as an open loop amplifier because the capacitor CF acts an open
circuit to the input offset voltage Vio. (Or)
• The Input offset voltage Vio and the part of the input is charging capacitor CF produce the error voltage
at the output of the integrator.

4. Explain in detail about differential amplifier using op-amp.

• The op-amp amplifies the difference between the two input signals is called differential amplifier.
Classify these arrangements according to the number of
Fig 2.13 Differential amplifier circuit with 1 op-amp
To analyze this circuit by deriving voltage gain and input resistance. This circuit is a combination of inverting
and non-inverting amplifier. (i.e)
• When Vx is reduced to zero the circuit is non-inverting amplifier and
• When Vy is reduced to zero the circuit is inverting amplifier.

43

Voltage Gain:
The circuit has 2 inputs Vx and Vy . Use superposition theorem, when Vy = 0V, becomes inverting
amplifier. Hence the output due to Vx only is
Rf Vx
Vox
1
Similarly, when Vx = 0V, becomes Non-inverting amplifier having a voltage divider network composed of R2
and R3 at the Non – inverting input.
larger than the source resistances. So that the loading of the signal sources does not occur.
Note: If we need a variable gain, we can use the differential amplifier. In this circuit R1 = R2 , RF = R3 and
the potentiometer Rp = R4.Depending on the position of the wiper in R voltage can be varied from the closed
loop gain of -2RF /R1 to the open loop gain of A.

44
o/p
R3

V2 1 R Vy (1)
2
By applying superposition theorem to the second stage, we can obtain the output voltage,
Rf Rf

V0 R

V2 1
R

Vx (2)

1 1
45

Sub. The value of V2 in eqn. (2)

Rf

R3

Rf
V0 R

1
R

Vy 1 R

Vx (3)

1 2 1
Since R1=R3 and Rf=R2
Rf
V0 1 R V V
1
R3 R1 Rf

V0 y R R R

Vy (4)

2 3 1
output is called as inverting amplifier. The basic circuit diagram of inverting amplifier is shown below

46

Fig 2.16 Inverting amplifier circuit

Analysis:

Current through the resistance R is,

I Vin VA

[V =V =0 Virtual ground]

A B
1

Vin
I= R1
Current through RF is,

I VA V0
RF
V0
RF

V n V0 RF RF

A V0
Vin

RF
R1

RF/R1 is called gain of amplifiers. Negative sign indicates that polarity of the output is opposite to that of the
input. So the inverting amplifier is also called as sign changer. Sign Changer:
Let K= RF/R1 is called scale factor.
V0=-KVin
Since the output voltage is changing according to the scale factor K and input voltage Vin the inverting
amplifier is called as Scale changer. The input and output waveforms are shown below
47

Fig 2.17 Inverting amplifier waveforms

If the value of RF/R1=1, then the output is exactly 180 phase shift with respect to the input. Hence it is called
as Phase shift circuit (or) phase inverter.
Non-inverting amplifier:
• An amplifier which amplifies the input without any phase shi t between them is called a non-inverting
amplifier.
The basic circuit diagram is shown below
Fig 2.18 Non-inverting amplifier circuit
Analysis:
I through R1 is,
I V VA
R1
Vin
R1

48

Current through RF is,

I VA V0 Vin V0

Vin
R1

RF
Vin
RF

RF
V0
RF

V0 Vin R1 R1

Vin
RF
Applications of op-amp:
It is classified into 2 types,
• Linear application
• Non-linear Application

49

6. Explain the basic applications of op-amp?

Summing Amplifier:
Op-amp may be used to design a circuit whose output is the sum of several input signals. Such a circuit is
called a summing amplifier or a summer.
Adder is classified as
Inverting summer
Non-inverting summer
I V2 VA
R2

V2
R2

(2)

Applying KCL at node A and as input op-amp current is zero, I=I1+I2 >(3)
From the output side

I VA V0
Rf

V0
Rf

(4)

50

Substitute eqn.(1), (2), (4) in eqn.(3)

V0
Rf

V1
R1

V2
R2

(5)

V Rf
0 R

V RfV
1 R

(6)

1` 2
If the three resistance are equal R1= R2= Rf
From the input side

I V1 VB
R1
I V2 VB
2 R

(2)

(3)

Input current of op-amp is zero

I1 + I2 = 0 >(4)

51

V1 VB
R1

V2 VB 0
R2

V1 V2
R R

1
VB R

1
R

1 2 1 2

V R2V1 R1V2

(5)

B R R
2
Now at node A

by using superposition principle.

52
Fig 2.22 Subtractor amplifier circuit
To find the output V01 due to V1 alone, make V2 = 0.
Then the circuit of figure as shown in the above becomes a non-inverting amplifier having input voltage V1/2 at
the non-inverting input terminal and the output becomes

V V1 1 R V

(1)

01 2 R 1
Similarly the output V02 due to V2 alone (with V1 grounded) can be written simply for an inverting amplifier
as

V RV V

(2)

02 R2 2
Thus the output voltage Vo due to both the inputs can be written as
V0 V01 V02
V0 V1 V2
Thus the output voltage is the difference between the two inputs and hence it act as the subtractor.

53

UNIT-III APPLICATIONS OF OPAMP

Part – A
1. What is the need for an instrumentation amplifier?
In a number of industrial and consumer applications, the measurement of physical quantities is usually done
with the help of transducers. The output of transducer has to be amplified So that it can drive the indicator or
display system. This function is performed by an instrumentation amplifier.
2. What is a sample and hold circuit? Where it is used?
A sample and hold circuit is one which samples an input signal and holds on to its last sampled value until the
input is sampled again. This circuit is mainly used in digital interfacing, analog to digital systems, and pulse
code modulation systems.
3. What is a comparator?
A comparator is a circuit which compares a signal voltage applied at one input of an opamp with a known
reference voltage at the other input. It is an open loop op - amp with output ± Vsat .
4. What is a multivibrator?
Multivibrators are a group of regenerative circuits that are used extensively in timing applications. It is a wave
shaping circuit which gives symmetric or asymmetric square output. It has two states either stable or quasi-
stable depending on the type of multivibrator.

5. Draw the circuit of log amplifier using op-amps

54

6. Draw the circuit of log amplifier using op-amps

7. What is a zero crossing detector?
Zero crossing detector(ZCD) is a voltage comparator that switches the output between
+Vsat and –Vsat. The output is driven into –Vsat when the input signal passes through zero to positive
direction. Conversely, when input signal passes through zero to negative direction, the output switches to
+Vsat.
8. What are the applications of comparator?
• Zero crossing detectors
• Window detector
• Time marker generator
• Phase detector
9. Define conversion time.
It is defined as the total time required converting an analog signal into its digital output. It depends on the
conversion technique used & the propagation delay of circuit components. The conversion time of a
successive approximation type ADC is given by T (n+1) where T---clock period Tc---conversion time n- no. of
bits.
10. What are the different types of filters?
• Based on functions: Low pass filter, High pass filter, Band pass filter, Band reject filter
• Based on order of transfer function : first, second, third higher order filters.
• Based on configuration: Bessel, Chebychev, Butterworth filters.

55

Part - B
1. Draw and explain the working of Instrumentation amplifier using Op-Amp and derive its output voltage
equation.
• In a number of industrial and consumer applications, one is required to measure and control physical
quantities.
• Some typical examples are measurement and control of temperature, humidity, light intensity, water
flow etc. these physical quantities are usually measured with help of transducers.
Fig 3.1 Basic differential amplifier circuit
Consider the basic differential amplifier,
The output voltage Vout is given by,

56

R2 1 R2

V0 R V2 R V1 1 R

R4

1 1 3 1
R4

V
R3

R4

V1

R 1 R

2V

1 1V
0 R 2 R R 1
1 3 2
R4

For

R1 R3 R2 R4

we obtain

• In the circuit of figure 6(a), source V1 sees an input impedance = R3+R4 (=101K) and the impedance
seen by source V2 is only R1 (1K).
• This low impedance may load the signal source heavily.
• Therefore, high resistance buffer is used preceding each input to avoid this loading effect as shown in
figure 6(b).
• The op-amp A1 and A2 have differential input voltage as zero. For V1=V2, that is, under common mode
condition, the voltage across R will be zero.

Fig 3.2 Instrumentation amplifier circuit

57

As no current flows through R and R’ the non-inverting amplifier. A1 acts as voltage follower, so its output
V2’=V2.
Similarly op-amp A2 acts as voltage follower having output
V1’=V1.
However, if V1≠V2, current flows in R and R’, and (V2’-V1’)>(V2-V1). Therefore, this circuit has
differential gain and CMRR more compared to the single op-amp circuit of figure 6(a).

R1

R 1 2

In equation (2), if we choose R2 = R1 = 25K (say) and R’ = 25K; R = 50Ω, then a gain=1001
The difference gain of this instrumentation amplifier R, however should never be made zero, as this will make
the gain infinity. To avoid such a situation, in a practical circuit, a fixed resistance in series with a
potentiometer is used in place of R.

58
Fig 3.3 Instrumentation amplifier practical circuit
• Figure 3.3 shows a differential instrumentation amplifier using Transducer Bridge. The circuit uses a
resistive transducer whose resistance changes as a function of the physical quantity to be measured.
• The bridge is initially balanced by a dc supply voltage Vdc so that V1=V2. As the physical
quantity changes, the resistance RT of the transducer also changes, causing an unbalance in the
bridge (V1≠V2). This differential voltage now gets amplified by the three op-amp differential
instrumentation amplifier.
Applications:
• Temperature indicator
• Temperature controller
• Light intensity meter
2. With a neat circuit diagram, explain the working of Schmitt trigger using Op-Amp. (May 2015)
Schmitt Trigger:

Fig 3.4 Schmitt trigger circuit

59
Fig 3.5 Schmitt trigger circuit waveforms
• This circuit converts an irregular shaped waveform to a square wave or pulse. The circuit is known as
Schmitt Trigger or squaring circuit.
• The input voltage Vin triggers (changes the state of) the o/p V0 every time it exceeds certain voltage
levels called the upper threshold Vut and lower threshold voltage.
• These threshold voltages are obtained by using theh voltage divider R1 – R2, where the voltage across
R1 is feedback to the (+) input.
• The voltage across R1 is variable reference threshold voltage that depends on the value of the output
voltage.
• When V0 = +Vsat, the voltage across R1 is called “upper threshold” voltage Vut. The input voltage Vin
must be more positive than Vut in order to cause the output V0 to switch from +Vsat to –Vsat. As long as Vin <
Vut , V0 is at +Vsat, using voltage divider rule.
• Similarly, when V0 = -Vsat, the voltage across R1 is called lower threshold voltage Vlt . the Vin must
be more negative than Vlt in order to cause V0 to switch from –Vsat to +Vsat.
• In other words, for Vin > Vlt , V0 is at –Vsat.

60

• Thus, if the threshold voltages Vut and Vlt are made larger than the input noise voltages, the positive
feedback will eliminate the false o/p transitions.
• Also the positive feedback, because of its regenerative action, will make V0 switch faster between
+Vsat and –Vsat. Resistance Rcomp R1 || R2 is used to minimize the offset problems.
• The comparator with positive feedback is said to exhibit hysteresis, a dead band condition. (i.e) when
the input of the comparator exceeds Vut its output switches from +Vsat to –Vsat and reverts to its original
state, +Vsat when the input goes below Vlt.
• The hysteresis voltage is equal to the difference between Vut and Vlt.

Therefore

Vref = Vut – Vlt Vref = R1

R1 + R2 [+Vsat -(-Vsat)]

3. With a neat circuit diagram explain the operation of R-2R D/A converter. (May 2015)
• An enhancement of the binary-weighted resistor DAC is the R-2R ladder network. This type of DAC
utilizes Thevenin’s theorem in arriving at the desired output voltages.
• The R-2R network consists of resistors with only two values - R and 2xR.
• If each input is supplied either 0 volts or reference voltage, the output voltage will be an analog
equivalent of the binary value of the three bits.
• VS2 corresponds to the most significant bit (MSB) while VS0 corresponds to the least significant bit
(LSB).

61

Fig 3.6 R-2R ladder type D/A circuit

Vout = - (VMSB + Vn + VLSB) = - (VRef + VRe /2 + VRef/ 4)
• An alternative to the binary-weighted-input DAC is the so-cal ed R/2R DAC,
which uses fewer unique resistor values.
• A disadvantage of the former DAC design was its requirement of several different precise input resistor
values: one unique value per binary input bit.
• Manufacture may be simplified if there are fewer different resistor values to
purchase, stock, and sort prior to assembly.
• Of course, we could take our last DAC circuit and modify it to use a single input resistance value, by
connecting multiple resistors together in series
Fig 3.7 Ladder type D/A circuit
• Mathematically analyzing this ladder network is a bit more complex than for the previous circuit, where
each input resistor provided an easily-calculated gain for that bit.
• For those who are interested in pursuing the intricacies of this circuit further,
you may opt to use Thevenin's theorem for each binary input (remember to

62

consider the effects of the virtual ground), and/or use a simulation program like SPICE to determine circuit
response.
• Either way, you should obtain the following table of figures:

| Binary | Output voltage |

---------------------------------
| 000 | 0.00 V |
---------------------------------
4. Explain the working of successive approximation type A/D converter. (May 2016)
• Successive-approximation ADC is a conversion technique based on a successive-approximation
register (SAR).

63

• This is also called bit-weighing conversion that employs a comparator to weigh the applied input
voltage against the output of an N-bit digital-to-analog converter (DAC).
• The circuit operates as follows, With the arrival of start command, the SAR sets MSB d1=1 with the
other bits 0.
• Hence the trail bit is 10000000. It is then converted to Vd by DAC and compared with analog input
voltage Va by using the comparator.
If Va > Vd, then change the next LSB is set to 1, by keeping MSB as 1.
11010100 10000000 1 (initial output)
11000000 1
11100000 0
11010000 1
11011000 0
11010100 1
11010110 0
11010101 0
11010100

64

• A comparison of the speed of 8-bit tracking ADC and SAR type ADC is given

below, from the figure

it is noted that the conversion time of

tracking ADC

increases with the increase in the number of bits. But the conversion type of SAR ADC remains constant
irrespective of the number of bits used.

Fig 3.9 Success ve approximation type A/D converter waveform

5. Explain the second order low pass filter with a neat diagram. Derive its frequency response and plot the
same. (May 2016)
• A second order LPF having a gain 40dB/decade 1in stop band. First orders LPF can be converted into
a II order type simply by using an additional RC network. The gain of the II order filter is set by R1 and RF,
while the high cut off frequency f s determined by R2,C2, R3 and C3.It is also called as Sallen-Key filter

Fig 3.10 Second order LPF circuit

65

Fig 3.11 Second order LPF circuit frequency response

This above fig transferred into S domain.

Fig 3.12 Second order LPF circuit frequency response S domain
In this c rcuit a l the components and the circuit parameters are expressed in the S- domain where S = jω .
R
V0 1 R VB A V
i
A 1 Rf

Where 0
i

VB= voltage at node B

Apply KCL at node A

I1 = I2 + I3
Let Y1 = 1/R, Y2 = 1 / R, Y3 = Y4 = SC
(Vi-VA) Y1 = (VA - VB) Y2 + (VA - V0) Y3 >(1)
Vi Y1 = VA (Y1 + Y2 + Y3) - VB Y2 - V0 Y3 >(2)

66

The gain of the op-amp is

V0 A

V V0

V 0

B A

---------------->(3)

Sub (3) in (2)

Vi Y1 = VA(Y1+ Y2+ Y3)-

Apply KCL at node B

V0 Y2- V0 Y3 >(4)
A0

The transfer function of low pass second order hydraulic electrical and mechanical system can be written as

HS

2
0 h
S2 S 2 >(7)

h h

Where A0 = gain,
ωh = 1/RC = upper cutoff frequency in radians per seconds. α = (3- A0) = damping coefficient
67
put S = jω in eqn.(7)

H ( j)

j/ 2

A0
j /h 1

The normalized expression for LPF is

H ( j)

A0

S2 S1

Where Sn = jω/ωh = Normalized frequency.

The frequency response for different values of α is shown in figure.
filters more likely damped a =1.06.
• A Bessel filter is heavily damped and has a damping coefficient of 1.73. This gives better pulse
response however causes attenuation in the upper end of the pass band.
Filter Design:
1. Choose a value for a high cut off freq (fH ).

68

2. To simplify the design calculations, set R2 = R3 = R and C2 = C3 = C then choose a value of c<=1µf.

3. Calculate the value of R using eqn.

R 1 2f H C

4. Finally, because of the equal resistor (R2 = R3) and capacitor (C2 = C3 ) values, the pass band volt
gain AF = 1 + RF / R1 of the second order had to be = to
1.586. RF = 0.586 R1 . Hence choose a value of R1 < =100kΩ and
69

Part - A

UNIT IV SPECIAL ICs

1. What are the applications of 555 Timer?

• Astable multivibrator
• Monostable multivibrator
• Missing pulse detector
• Linear ramp generator
• RS flip flop
• Two comparator
• Discharge transistor.
6. List the features of 555 Timer?
• It has two basic operating modes: monostable and astble
• It is available in three packages. 8 pin metal can , 8 pin dip, 14 pin dip.
• It has very high temperature stability.

70

7. Define duty cycle?

The ratio of high output and low output period is given by a mathematical parameter called duty cycle. It is
defined as the ratio of ON Time to total time.
8. Define VCO.
A voltage controlled oscillator is an oscillator circuit in which the frequency of oscillations can be controlled by
an externally applied voltage.
9. List the features of 566 VCO.
• Wide supply voltage range(10-24V)
• Very linear modulation characteristics
• High temperature stability
10. What does you mean by PLL?
A PLL is a basically a closed loop system designed to lock output frequency and phase to the frequency and
phase of an input signal.
11. Define lock range.
When PLL is in lock, it can trap freq changes in the incoming signal. The range of frequencies over which the
PLL can maintain lock with the incoming signal is called as lock range.
12. Define capture range.
The range of frequencies over which the PLL can acquire lock with the input signal is called as capture range.
13. Define pull-in time.
The total time taken by the PLL to establish lock is called pull-in time.
14. List the applications of 565 PLL.
• Frequency multiplier
• Frequency synthesizer
• FM detector
15. What are the two types of analog multiplier Ics?
a) IC AD 533
b) IC AD 534

71

Part - B
1) Discuss in detail about Monostable multivibrator using 555 timer IC
Block Diagram of 555 Timer IC:

Fig 4.1 Block Diagram of 555 Timer IC

• From the above figure, three 5k internal resistors act as voltage divider providing bias voltage of 2/3
Vcc to the upper comparator & 1/3 Vcc to the lower comparator. It is possible to vary time electronically by
applying a modulation voltage to the con rol voltage input terminal.
MONOSTABLE OPERATION:
Fig. 4.2. 555 connected as a Monostable Multivibrator
72

Model Graph:

Fig. 4.3. Model graph

• Initially when the output is low, i.e. the circuit is in a stable state, transistor Q1 is ON & capacitor C is
shorted to ground. The output remains low.
• During negative going trigger pulse, transistor Q1 is OFF, which releases the short circuit across the
external capacitor C & drives the output high.
• Now the capacitor C starts charging toward Vcc through RA. When the voltage across the capac tor
equals 2/3 Vcc, upper comparator switches from low to high. i.e. Q = 0 the transistor Q1 = OFF ; the output is
high.
• Since C is unclamped, voltage across it rises exponentially through R towards Vcc with a time constant
RC.
• A er the t me period, the upper comparator resets the FF, i.e. Q = 1, Q1 = ON; the output is low. i.e
discharging the capacitor C to ground potential (Fig.c) The vo tage across the capacitor as in fig (b) is given by
Vc = Vcc (1-e- / C) (1)
Therefore At t = T, Vc = 2/3 Vcc
2/3 Vcc = Vcc(1-e-T/RC) or T = RC ln (1/3) or T = 1.1RC seconds (2)
If the reset is applied Q2 = OFF, Q1 = ON, timing capacitor C immediately discharged. The output now will be
as in figure (d & e). If the reset is released output will still remain low until a negative going trigger pulse is
again applied at pin 2.
73

2) Explain astable multivibrator using 555 timer with neat sketch The 555 timer as an Astable
Multivibrator:
• An Astable multivibrator, often called a free running multivibrator, is a rectangular wave generating
circuit.
• Unlike the monostable multivibrator, this circuit does not require an external
trigger to change the state of the output, hence the name free running.
• However, the time during which the output is ei her high or low is determined by 2 resistors and
capacitors, which are externa ly connected to he 555 timer.

Fig 4.4 Astable Multivibrator

Model Graph
Fig. 4.5. Model graph
74

The above figures show the 555 timer connected as an astable multivibrator and its model graph
Initially, when the output is high :
• Capacitor C starts charging toward Vcc through RA & RB.
• However, as soon as voltage across the capacitor equals 2/3 Vcc. Upper comparator triggers the FF &
output switches low.
When the output becomes Low:
• Capacitor C starts discharging through RB and transistor Q1, when the voltage across C equals 1/3
Vcc, lower comparator output triggers the FF & the output goes High.
• Then cycle repeats. The capacitor is periodically charged & discharged between 2/3 Vcc & 1/3 Vcc
respectively.
• The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc equal to the time the output is
high & is given by
tc = ln 2(RA+RB)C (1)
Where [ln 2 = 0.69]
= 0.69 (RA+RB)C
Where, RA & RB are in ohms. And C is in farads.
Similarly, the time during which the capacitors discharges from 2/3 Vcc to 1/3 Vcc is equal to the time, the
output is low and is given by,
tc = RB C ln 2
td = 0.69 RB C (2)
where, RB is in ohms and C is in farads.
Thus the total period of the output waveform is
T = tc + td = 0.69 (RA+2RB)C (3)
This, in turn, gives the frequency of oscillation as,
f 0 = 1/T = 1.45/(RA+2RB)C (4)
Equation 4 indicates that the frequency f 0 is independent of the supply voltage Vcc. Often the term duty cycle
is used in conjunction with the astable multivibrator. The duty cycle is the ratio of the time tc during which the
output is high to the total time period T. It is generally expressed as a percentage.

% duty cycle = (tc / T )* 100

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% DC = [(RA+RB)/ /(RA+2RB)] * 100

3) Explain phase locked loop with neat sketch:

Fig 4.6 Basic Block Diagram of a PLL Phase locked loop construction and operation:
• The PLL consists of i) Phase detector ii) LPF iii) VCO. The phase detector or comparator compares the
input frequency fIN with feedback frequency fOUT.
• The output of the phase detector is proportional to the phase difference between fIN & fOUT.
• The output of the phase detector is a dc voltage & therefore is often referred to as the error voltage.
• The output of the phase detector is then applied to the LPF, which removes the high frequency noise
and produces a dc level. This dc level in turn, is input to the VCO.
• The output frequency of VCO is directly proportional to the dc level.
• The VCO frequency is compared with input frequency and adjusted until it is equal to the input
frequencies.
• PLL goes through 3 states, i) free running ii) Capture iii) Phase lock.
• Before the input is applied, the PLL is in free running state. Once the input frequency is applied the
VCO frequency starts to change and PLL is said to be in the capture mode.
• The VCO frequency continuous to change until it equals the input frequency and the PLL is in phase
lock mode.
• When Phase locked, the loop tracks any change in the input frequency through its repetitive action.
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• If an input signal vs of frequency fs is applied to the PLL, the phase detector compares the phase and
frequency of the incoming signal to that of the output vo of the VCO.
• If the two signals differ in frequency of the incoming signal to that of the output vo of the VCO. If the two
signals differ in frequency and/or phase, an error voltage ve is generated.
• The phase detector is basically a multiplier and produces the sum (fs + fo) and difference (fs - fo)
components at its output.
• The high frequency component (fs + fo) is removed by the low pass filter and the difference frequency
component is amplified then applied as control voltage vc to VCO.
• The signal vc shifts the VCO frequency in a direction to reduce the frequency difference between fs
and fo.
• Once this action starts, we say that the signal is in the capture range. The VCO continues to change
frequency till its output frequency is exactly the same as the input signal frequency. The circuit is then said to
be locked.
• Once locked, the output frequency fo of VCO is identical to fs except for a finite phase difference φ.
• This phase difference φ generates a corrective control voltage vc to shift the VCO frequency from f0 to
fs and thereby maintain the lock. Once locked, PLL tracks the frequency changes of the input signal. Thus, a
PLL goes through three stages (i) free running, (ii) capture and (iii) locked or tracking.
Capture range:
• The range of frequencies over which the PLL can acquire lock with an input signal is called the capture
range. This parameter is also expressed as percentage of fo.
Pull-in time:
• The total time taken by the PLL to establish lock is called pull-in time. This depends on the initial phase
and frequency difference between the two signals as well as on the overall loop gain and loop filter
characteristics.

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(a) Phase Detector:

• Phase detector compares the input frequency and VCO frequency and generates DC voltage i.e.,
proportional to the phase difference between the two frequencies.
• Depending on whether the analog/digital phase detector is used, the PLL is called either an
analog/digital type respectively.
• Even though most monolithic PLL integrated circuits use analog phase detectors.
• Example for Analog: Double-balanced mixer , Example for Digital: Ex-OR, Edge trigger, monolithic
Phase detector.
(b) Low – Pass filter:
• The function of the LPF is to remove the high frequency components in the output of the phase detector
and to remove the high frequency noise.
• LPF controls the characteristics of the phase locked loop. i.e, capture range, lock ranges, bandwidth
• Lock range (Tracking range): The lock range is defined as the range of frequencies over which the PLL
system follows the changes in the input frequency fIN.
• Capture range: Capture range is the frequency range in which the PLL acquires phase lock. Capture
range is always smaller than the lock range.
• Filter Bandwidth: Filter Bandwidth is reduced, its response time increases. However reduced Bandwidth
reduces the capture range of the PLL. Reduced Bandwidth helps to keep the loop in lock through momentary
losses of signal and also minimizes noise.

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4. Explain Voltage Controlled Oscillator (VCO) with neat diagram

• A common type of VCO available in IC form is Signetics NE/SE566. The pin configuration and basic
block diagram of 566 VCO are shown in figures below.
charging current.
• The voltage across the capacitor C1 is applied to the inverting input terminal of Schmitt trigger via
buffer amplifier.
• The output voltage swing of the Schmitt trigger is designed to Vcc and 0.5 Vcc. If Ra = Rb in the
positive feedback loop, the voltage at the non-inverting input terminal of Schmitt trigger swings from 0.5 Vcc to
0.25 Vcc.

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• When the voltage on

the capacitor c1 exceeds 0.5 Vcc during

charging, the

output of the Schmitt trigger goes LOW (0.5 Vcc).

• The capacitor now discharges and when it is at 0.25 Vcc, the output of Schmitt trigger goes HIGH
(Vcc). Since the source and sink currents are equal, capacitor charges and discharges for the same amount
of time.
• This gives a triangular voltage waveform across c1 which is also available at pin
4. The square wave output of the Schmitt trigger is inverted by buffer amplifier at pin 3. The output waveforms
are shown near the pins 4 and 3.
The output frequency of the VCO can be given as follows:

where V+ is Vcc.
• The output frequency of the VCO can be changed either by (i) R1, (ii) c1 or (iii) the voltage vc at the
modulating input terminal pin 5.
• The voltage vc can be varied by connecting a R1R2 circuit as shown in the figure below.
• The components R1and c1 are first selected so that VCO output frequency lies
n the centre of the operating frequency range. Now the modulating input
voltage is usually varied from 0.75 Vcc to Vcc which can produce a frequency var at on of about 10 to 1.

Fig. 4.8. SE/NE 566 pin diagram

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Part - A

UNIT – V APPLICATION ICs

1. What are the limitations of three terminal regulators? (April/May 2015)

• No short circuit protection
• Output voltage (+ve or –ve) is fixed
2. How current boosting is achieved in a 723 IC? (April/May 2015)
The current boosting is achieved in a 723 IC by adding a boost transistor Q1 to the voltage regulator
3. How power amplifies is classified? Mention any one power amplifier IC? (April/May 2015)
A variety of monolithic as well as hybrid power amplifiers are commercially available. LM 380 is a popular
power audio amplifier
4. What is an opto-coupler? (April/May 2015), (April/May 2012)
Opto-coupler IC is a combined package of a photo-emitting device and a photo- sensing device.
• Better isolation between the two stages.
• Impedance problem between the stages is eliminated.
• Wide frequency response
• Easily interfaced with digital circuit
• Compact and light weight
• Problems such as noise, transients, contact bounce, are eliminated
5. What is meant by thermal shut down applied to voltage regulators? (Nov/Dec 2014)
The IC has a temperature sensor (built-in) which turns off the IC when it becomes too hot (usually 125°C to
150°C). The output current will drop and remains there until the IC has cooled significantly.

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6. Draw the internal block diagram of a function generator IC (Nov/Dec 2014)

7. What is a switching regulator? (Nov/Dec 2014)
Switching regulators are those which operate the power transistor as a high frequency on/off switch, so that the
power transistor does not conduct current continuously. This give improved efficiency over series regulators.
8. Draw the pin diagram of IC 8038 (Nov/Dec 2014)

Sine adjust Sine out Triangle out

Duty cycle Frequency adjust
+Vcc

F.M bias

NC NC
Sine adjust

-VEE Or GND

Timing Capacitor Square out

FM sweep out

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9. State the need for protection diodes in voltage regulators based on LM 317 regulators (April/May 2014),
(Nov/Dec 2012)
When external capacitors are used with LM 317, it is sometimes necessary to add protection diodes to prevent
the capacitors from discharging through low current points into the regulators. Protection diodes are included
for use with outputs greater than 25V and high value of output capacitance.
10. What is an isolation amplifier? (Nov/Dec 2012), (Nov/Dec 2011)
An isolation amplifier is an amplifier that offers electrical isolation between its input and output terminals. Easy
to use, ultra low leakage 18 pin DIP package
• Better isolation between the two stages.
• Impedance problem between the stages is eliminated.
• Wide frequency response
• Easily interfaced with digital circuit
• Compact and light weight
• Problems such as noise, transients, contact bounce, are eliminated
11. Define load regulation (Nov/Dec 2013)
It is defined as the change in output voltage for a change in load current and of V0. Typical value of load
regulation for 7805 is 15mV for 5mA < I0 < 1.5A
12. What are the applications of switch mode power supplies? (April/May 2012)
• Adjustable high voltage constant current sources
• Battery powered systems
• Telecommunication circuits
• Personal computers
• Printers
• Video games
• Motor and industrial control systems
• Automotive applications
13. Why do switching regulators have better efficiency than series regulator? (April/May 2012)
Switching regulators have better efficiency than series regulator because the switching regulator have applied
a very high frequency signal (40 kHz and above), the transistors used are acting as the switches and become
alternately

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ON and OFF at a frequency of 20 kHz. The time duration, power consumption, size and cost is very small
when compared with series regulator.
14. What are the disadvantages of linear voltage regulator? (Nov/Dec 2011)
• Low efficiency
• Use of step down transformer is bulky and expensive
• Weight is high
• Response to load variation is fast
15. What are the advantages of switched capacitor filter over active filters?
9. Bandwidth of 100 KHz at Pout = 2W & RL = 8Ω
Introduction:
• Small signal amplifiers are essentially voltage amplifiers that supply their loads with larger amplifier
signal voltage.
• On the other hand, large signal or power amplifier supply a large signal current to current operated
loads such as speakers & motors.
• In audio applications, however, the amplifier called upon to deliver much higher current than that
supplied by general purpose op-amps.
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• This means that loads such as speakers & motors requiring substantial currents cannot be driven
directly by the output of general purpose op-amps. However there are two possible solutions,
• To use discrete or monolithic power transistors called power boosters at the output of the op-amp
• To use specialized ICs designed as power amplifiers.
85
Fig 5.2 Pin diagram

LM380 circuit description:

It is connected of 4 stages,
i. PNP emitter follower
ii. Different amplifier
iii. Common emitter

Fig 5.3 Block diagram

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iv. Emitter follower

(i) PNP Emitter follower:
• The input stage is emitter follower composed of PNP transistors Q1 & Q2 which drives the PNP Q3-Q4
differential pair.
• The choice of PNP input transistors Q1 & Q2 allows the input to be referenced to ground
• i.e., the input can be direct coupled to either the inverting & non-inverting terminals of the amplifier.
(ii) Differential Amplifier:
• The current in the PNP differential pair Q3-Q4 is established by Q7, R3 & +V.
• The current mirror formed by transistor Q7, Q8 & associated resistors then establishes the collector
current of Q9.
• Transistor Q5 & Q6 constitute of collector loads for the PNP differential pair.
• The output of the differential amplifier is taken at the junction of Q4 & Q6 transistors & is applied as an
input to the common emitter voltage gain.
(iii) Common Emitter:
• Common Emitter amplifier stage is formed by transistor Q9 with D1, D2 & Q8 as a current source
load.
• The capacitor C between the base & collector of Q9 provides internal compensation & helps to
establish the upper cutoff frequency of 100 KHz.
• Since Q7 & Q8 form a current mirror, the current through D1 & D2 is approximately the same as the
current through R3.
• D1 & D2 are temperature compensating diodes for transistors Q10 & Q11 in that D1 & D2 have the
same characteristics as the base-emitter junctions of Q11. Therefore the current through Q10 & (Q11-Q12) is
approximately equal to the current through diodes D1 & D2.
(iv) (Output stage) - Emitter follower:
• Emitter follower formed by NPN transistor Q10 & Q11. The combination of PNP transistor Q11 & NPN
transistor Q12 has the power capability of NPN transistors but the characteristics of a PNP transistor.
• The negative dc feedback applied through R5 balances the differential amplifier so that the dc output
voltage is stabilized at +V/2

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• To decouple the input stage from the supply voltage +V, by pass capacitor in order of micro farad
should be connected between the by-pass terminal (pin 1) & ground (pin 7).
• The overall internal gain of the amplifier is fixed at 50. However gain can be increased by using positive
feedback.

2. Draw and explain the functional diagram of 723 general purpose regulator (April/May 2012), (Nov/Dec
2012), (Nov/Dec 2011)
Features of IC723:
i. Unregulated dc supply voltage at the input between 9.5V & 40V
ii. Adjustable regulated output voltage between 2 to 3V
iii. Maximum load current of 150 mA (ILmax = 150mA)
iv. With the additional transistor used, ILmax upto 10A is obtainable
v. Positive or Negative supply operation
vi. Internal Power dissipation of 800mW
vii. Built in short circuit protection
viii. Very low temperature drift
ix. High ripple rejection
The simplified functional block diagram can be divided in to 4 blocks.
i. Reference generating block
ii. Error Amplifier
iii. Series Pass transistor
iv. Circuitry to limit the current
(i) Reference Generating block:
The temperature compensated Zener diode, constant current source & voltage reference amplifier together
from the reference generating block. The Zener diode is used to generate a fixed reference voltage internally.
Constant current source will make the Zener diode to operate at affixed point & it is applied to the Non –
inverting terminal of error amplifier. The Unregulated input voltage} Vcc is applied to the voltage reference
amplifier as well as error amplifier.
(ii) Error Amplifier:
Error amplifier is a high gain differential amplifier with 2 inputs (inverting & non inverting). The Non-inverting
terminal is connected to the internally generated

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reference voltage. The Inverting terminal is connected to the full regulated output voltage.

Fig 5.4 Pin diagram of IC723

(iii) Series Pass Transistor:

Q1 is the internal series pass transistor which is driven by the error amplifier. This

transistor actually acts as a

variable resistor & regulates the output

voltage. The

collector of transistor Q1 is connected to the Un-regulated power supply. The

maximum col ector voltage of Q1 is limited to 36Volts. The maximum current which can be supplied by Q1 is
150mA.
(iv) Circu try to lim t the current:
• The internal transistor Q2 is used for current sensing & limiting. Q2 is normally OFF transistor. It turns
ON when the IL exceeds a predetermined limit. Low voltage, Low current s capable of supplying load voltage
which is equal to or between 2 to 7Volts.

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3. Explain the working of IC 8038 function generator (April/May 2015),

(Nov/Dec 2013), (Nov/Dec 2011), (Nov/Dec 2010)

Fig 5.5 Functional block diagram of Function generator

Fig. 5.6. Output waveform

It consists of two current sources, two comparators, two buffers, one FF and a sine wave converter.

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Pin description:
Pin 1 & Pin 12: Sine wave adjusts:
• The distortion in the sine wave output can be reduced by adjusting the 100KΩ pots connected between
pin12 & pin11 and between pin 1 & 6.
Pin 2 Sine Wave Output:
• Sine wave output is available at this pin. The amplitude of this sine wave is 0.22 Vcc.
Where} 5V ≤ Vcc ≤ } 15 V.
Pin 3 Triangular Wave output:
• Triangular wave is available at this pin. The amplitude of the triangular wave is 0.33Vcc.
Where} 5V ≤ Vcc ≤ } 15 V.
Pin 4 & Pin 5 Duty cycle / Frequency adjust:
• The symmetry of all the output wave forms & 50% duty cycle for the square wave output is adjusted by
the external resistors connected from Vcc to pin 4. These external resistors & capacitors at pin 10 will decide
the frequency of the output wave forms.
Pin 6 + Vcc:
• Positive supply voltage the value of which is between 10 & 30V is applied to this pin.
Pin 7: FM Bias:
• This pin along with pin no8 is used to TEST the IC 8038.

Pin 9: Square Wave Output:

• A square wave output is available at this pin. It is an open collector output so that this pin can be
connected through the load to different power supply voltages. This arrangement is very useful in making the
square wave output.
Pin 10: Timing Capacitors:
• The external capacitor C connected to this pin will decide the output frequency along with the resistors
connected to pin 4 & 5.
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Pin 11: -VEE or Ground:

• If a single polarity supply is to be used then this pin is connected to supply ground & if supply voltages
are to be used then (-) supply is connected to this pin.
Pin 13 & Pin 14: NC (No Connection) Important features of IC 8038:
• All the outputs are simultaneously available.
• Frequency range: 0.001Hz to 500 kHz
• Low distortion in the output wave forms.
• Low frequency drifts due to change in temperature.
• Easy to use
Parameters:
(i) Frequency of the output wave form:
• The output frequency dependent on the values of resistors R1 & R2 along with the external capacitor C
connected at pin 10.
• If RA= RB = R & if RC is adjusted for 50% duty cycle then fo = RC 0.3; RA = R1,
RB = R3, RC = R2
(ii) Duty cycle / Frequency Adjust: (Pin 4 & 5):
• Duty cycle as well as the frequency of the output wave form can be adjusted by controlling the values of
external resistors at pin 4 & 5.
• The values of resistors RA & RB connected between Vcc * pin 4 & 5 respectively along with the
capacitor connected at pin 10 decide the frequency of the wave form.
• The values of RA & RB should be in the range of 1kΩ to 1MΩ.
(iii) FM Bias:
• The FM Bias input (pin7) corresponds to the junction of resistors R1 & R2.
• The voltage Vin is the voltage between Vcc & pin8 and it decides the output frequency.
• The output frequency is proportional to Vin as given by the following expression For RA = RB (50%
duty cycle).
fo = CRAVcc
1.5Vin ; where C is the timing capacitor

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With pin 7 & 8 connected to each other the output frequency is given by fo = RC 0.3 where R = RA = RB for
50% duty cycle.
(iv) FM Sweep input (pin 8):
• This input should be connected to pin 7, if we want a constant output frequency. But if the output
frequency is supposed to vary, then a variable dc voltage should be applied to this pin. The voltage between
Vcc & pin 8 is called Vin and it decides the output frequency as, 1.5 Vin fo = C RA Vcc
• A potentiometer can be connected to this pin to obtain the required variable voltage required to change
the output frequency.
4. What are IC voltage regulators? Explain the principle of IC LM 317 as a voltage regulator (Nov/Dec
2010)
Classifications of IC voltage regulators:
IC Voltage Regulator:
• Fixed Volt Reg. Adjustable O/P Volt Reg Switching Reg
• Positive/negative
• Fixed & Adjustable output Voltage Regulators are known as Linear Regulator.
• A series pass transistor is used and it operates always in its active region.
Switching Regulator:
• Series Pass Transistor acts as a switch.
• The amount of power dissipation in it decreases considerably.
• Power saving result is higher efficiency compared to that of linear.
Adjustable Voltage Regulator:
Advantages of Adjustable Voltage Regulator over fixed voltage regulator are,
• Adjustable output voltage from 1.2v to 57 v
• Output current 0.10 to 1.5 A
• Better load & line regulation
• Improved overload protection
• Improved reliability under the 100% thermal overloading

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Adjustable Positive Voltage Regulator (LM317):

Fig. 5.7. LM317 circuit

• LM317 series adjustable 3 terminal posi ive voltage regu ator, the three terminals are Vin, Vout &
adjustment (ADJ).
• LM317 requires only 2 external resistors to set the output voltage.
• LM317 produces a voltage of 1.25v between its output & adjustment terminals. This voltage is called as
Vref.
• Vref (Reference Voltage) is a constant; hence current I1 f ows through R1 will also be constant.
Because resistor R1 sets current I1. It is called “current set” or “program resistor”.

• Resistor R2 is called
as “Output set” resistors, hence current through this

resistor is the sum of I1 & Iadj

• LM317 s designed in such as that Iadj is very small & constant with changes in ine voltage & load
current.

The output voltage V is, Vo=R1I1+ (I1+Iadj) R2 (1)

Where = Vref/R1
Vo = (Vref/R1) R1 + Vref/R1 + Iadj R2
= V f + (Vref/R1) R2 + Iadj R2
Vo = Vref [1 + R2/R1] + Iadj R2 (2)
R1 = Current (I1) set resistor R2 = output (Vo) set resistor
Vref = 1.25v which is a constant voltage between output and ADJ terminals.
Current Iadj is very small. Therefore the second term in (2) can be neglected. Thus the final expression for the
output voltage is given by
Vo= 1.25v [1 + R2/R1] (3)

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Eqn (3) indicates that we can vary the output voltage by varying the resistance R2. The value of R1 is normally
kept constant at 240 ohms for all practical applications. Practical Regulator using LM317:

Fig. 5.8. Practical Regulator using LM317

• If LM317 is far away from the input power supply, then 0.1µf disc type or 1µf tantalum capacitor should
be used at the input of LM317.
• The output capacitor Co is optional. Co should be in the range of 1 to 1000µf.
• The adjustment terminal is bypassed with a capacitor C2 this w ll improve the r pp e rejection rat o
as high as 80 dB is obtainable at any output level.
• When the filter capaci or is used, it is necessary to use the protective diodes.
• These diodes do not allow the capacitor C2 to discharge through the low
current po nt of the regulator.
• These diodes are required only for high output voltages (above 25v) & for higher values of output
capacitance 25µf and above.

5. Explain in detail about optocouplers (April/May 2012), (Nov/Dec 2013)

• Optocouplers or Optoisolators is a combination of light source & light detector in the same package.

• They are used to couple

signal from one point to other optically,

by providing a

complete electric isolation between them.

• This kind of isolation is provided between a low power control circuit & high power output circuit, to
protect the control circuit.
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• Depending on the type of light source & detector used we can get a variety of optocouplers. They are
as follows,
(i) LED – LDR optocoupler
(ii) LED – Photodiode optocoupler
(iii) LED – Phototransistor optocoupler Characteristics of optocoupler:
(i) Current Transfer Ratio (CTR)
(ii) Isolation Voltage
Fig. 5.9. Optocoupler circuit and its waveform

• LED photodiode shown in figure, here the infrared LED acts as a light source & photodiode is used as a
detector.
• The advantage of using the photodiode is its high linearity. When the pulse at the input goes high, the
LED turns ON. It emits light. This light is focused on the photodiode.
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• In response to this light the photocurrent will start flowing though the photodiode. As soon as the input
pulse reduces to zero, the LED turns OFF & the photocurrent through the photodiode reduces to zero. Thus
the pulse at the input is coupled to the output side.

(ii) LED – Phototransistor Optocoupler:

• This is the most popularly used optocoupler, because it does not need any additional amplification.
• When the pulse at the input goes high, the LED turns ON. The light emitted by the LED is focused on
the CB junction of the phototransistor.
• In response to this light photocurrent starts flowing which acts as a base current for the phototransistor.

97

• The collector current of phototransistor starts flowing. As soon as the input pulse reduces to zero, the
LED turns OFF & the collector current of phototransistor reduces to zero. Thus the pulse at the input is
optically coupled to the output side.
Advantages of Optocoupler:
• Control circuits are well protected due to electrical isolation.
• Wideband signal transmission is possible.
• Due to unidirectional signal transfer, noise from the output side does not get coupled to the input side.
• Interfacing with logic circuits is easily possible.
• It is small size & light weight device.
Disadvantages:
• Slow speed.
• Possibility of signal coupling for high power signals.
Applications:
• Optocouplers are used basically to isolate low power circuits from high power circuits.
• At the same time the control signals are coupled from the control circuits to the high power circuits.
Optocoupler IC:
The optocouplers are available in the IC form MCT2E is the standard optocoupler IC which is used popularly
in many electronic application.
• This input is applied between pin 1& pin 2. An infrared light emitting diode is connected between these
pins.
• The infrared radiation from the LED gets focused on the internal phototransistor.
• The base of the phototransistor is generally left open. But sometimes a high value pull down resistance
is connected from the Base to ground to improve the sensitivity.
• The block diagram shows the opto-electronic-integrated ciruit (OEIC) and the major components of a
fiber-optic communication facility.

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Fig. 5.11 Block diagram of opto-electronic- ntegrated circuit
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