International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) – TCET, Mumbai, India
Design of 32 bit (MIPS) RISC PROCESSOR
Using FPGA
R M Kubde D B Bhoyar
Department of Electronic Engg Department of Electronic Engg
Yeshwantrao Chavan College Of Yeshwantrao Chavan College Of
Engg. Nagpur, India Engg. Nagpur, India
+91-9823935309 +91-9923448822
rupa_kubde@yahoo.co.in dinesh_bhoyar@rediffmail.com
ABSTRACT
The proposed work is aimed at designing general purpose 32 bit
RISC(MIPS) processor. The system is design using VHDL
language and this source code can be use as IP (Intellectual
Property) core which can be targeted to any FPGA for several
applications. Emphasis is given on simple working solution with
minimum possible area. RISC processor has to be implemented
on FPGA (Field Programmable Gate Array)... It uses different
instructions. Simulation of entire processor is done to verify the
functionality. The source code can also be verified for synthesis
purpose. Objective of this project is designing 32-bit
RISC(MIPS) processor. The RISC design ideally suited to
participate in a powerful trend in the embedded processor
market – the "system-on-a-chip”. This paper describes current
work utilizing rapid prototyping approach to simulate,
synthesize, and implement prototype digital system and
computer architectures using PCs with student versions of
commercial VHDL based CAD tools and a low cost board with
a large CPLD or FPGA. VGA video output generated directly
by the CPLD chip is used to display graphics or textual data
eliminating the need for a logic analyzer.
Categories and Subject Descriptors
B [Hardware]:B.5.1 Design, B.5.2 Design aids
General Terms
Design, simulation
Keywords
System-on –a – chip, CPLD chip, prototype digital system,
VGA video output
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ICWET’10, February 26–27, 2010, Mumbai, Maharashtra, India.
Copyright 2010 ACM 978-1-60558-812-4…$10.00.
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R S KHEDIKAR
Department of Electronic Engg
Yeshwantrao Chavan College Of
Engg. Nagpur, India
+91-9767031658
rakhikhedikar@yahoo.co.in
INTRODUCTION
Microprocessors and Microcontrollers have traditionally been
designed around two philosophies: Complex Instruction Set
Computer (CISC) and Reduced Instruction Set Computer
(RISC). The CISC concept is an approach to the instruction set
architecture (ISA) design that emphasizes doing more with each
instruction using a wide variety of addressing modes, variable
number of operands in various locations in its instruction set. As
a result Instruction is of widely varying lengths and execution
time is more. Thus demanding a very complex control unit,
which occupies a large real state on chip. On the other hand,
RISC processor works on reduced number of instructions, fixed
instruction length, more general purpose registers, load – store
architecture and simplified addressing modes which makes
individual instruction execute faster, achieve a net gain in
performance and an overall simpler design with less silicon
consumption as compared to CISC. This gives the RISC
architecture more room to add on-chip peripheral, interrupt
controller and programmable timer. The above feature makes
RISC design ideally suited to participate in powerful trend in the
embedded processor market – “system-on –a – chip”.
Computer organization and design is a common engineering
course where students learn concepts of modern computer
architecture. Students often learn computer design by
implementing individual sections of a computer microprocessor
using a simulation-only approach that limits a students
experience to software design. This project targets the computer
architecture courses and presents an FPGA (Field Programmable
Gate Array) implementation of a MIPS RISC (Reduced
Instruction Set Computer) Processor via VHDL (Very high
speed integrated circuit Hardware Description Language)
design. The goal of this project is to enhance the simulator based
approach by integrating some hardware design to help the
computer architecture students gain a hands-on experience in
hardware-software integration and achieve a better
understanding of both the MIPS single-cycle and pipelined
processors.
Instruction Formats
Looking at the MIPS processor core instruction table you can
see that we have assigned different formats for certain
instructions. This is because different instructions use different
operands and hence different formats needed to be constructed
for them. The following section describes three formats that are
 International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) – TCET, Mumbai, India
used. such as ADD, SUB, AND etc.
Mnemonic Format Opcode Function Instruction
Field 6 5 5 5 5 6
field field
size bits bits bits bits bits bits
ADD R 0 32 Add
Register Format (R-type)
The most common style of instruction is the R-type. The R- ADDI I 8 -- Add
type instruction has two read registers and one write register. immediate
ADDU R 0 33 Add
unsigned
(31 to 26) (25 to 21) (20 to16) (15 to11) (10 to 6) (5 to 0)
SUB R 0 34 Subtract
R-
Opc
Forma Rs Rt Rd shift Function SUBU R 0 35 Subtract
ode unsigned
t
AND R 0 36 Bitwise
AND
All of the instructions have a 6-bit opcode, which is used to OR R 0 37 Shift left
logical
determine what type of instruction is to be executed. Each of the
SEL R 0 0 Bitwise
register specifications in all of the instructions is 5-bits wide. OR
The first two 5-bit register specifications are the two read SRL R 0 2 Shift right
registers and the last 5-bit register specification is the logical
destination register, that the instruction will use. The last 6-bits SLT R 0 42 Set if less than
in the instruction are used as function bits. This function bits
LUI I 15 -- Load upper
specify what the actual instruction that will be performed.
immediate
Immediate Format (I-type)
LW I 35 -- Load word
(31 to 26)(25 to 21) (20 to 16) (15 to 0)
I- R R Address/Immediate SW I 43 -- Store
Opcode
Format s t value word
The I-type is similar to the R-type except the second read BEQ I 4 -- Branch on
equal
register and the 5 function bits are replaced by a 16-bit
BNE I 5 -- Branch on not
immediate value. Each I-type opcode can have only one equal
instruction because it has no function bits like the R-type. J J 2 -- Jump
Branch Type Format (J- type)
(31 to 26) (25 to 0) JAL J 3 -- Jump &link
(used to
J- call )
Opcode Branch target address
Format Jump
JR R 0 8 register (used
The J-type format consists of a 6-bit opcode and remaining to return)
bit indicates branching address. The execution unit generates the ALU result which is
then applied to data memory which selects the memory location
Working of Block Diagram in which the result is to be stored when memory write signal is
RISC processor consists of Instruction fetch unit, decoder unit, high or memory location from which data is being loaded into
control unit, execution unit, and data memory unit. register when memory to register and memory read signals are
As shown below in figure 8 of block diagram the fetching high.
unit comprises of Program counter, two adders and instruction
memory. PC is 8-bit register, which contains the address of Table 1.MIPS PROCESSOR CORE INSTRUCTIONS:
memory location of instruction memory where opcode is
present. Instruction opcode is of 32 bit hence to fetch next VGA Video from a CPLD or FPGA:-
instruction in normal operation PC will be incremented by 4 in In the past, the limited I/O features and debugging information
adder 1. When branching instructions are used the available on CPLD and FPGA demo boards has been a problem
corresponding branching address is generated in adder 2 using on complex designs. To support this new laboratory
sign extended and shift left 2 blocks. The mux decides whether development work, a VHDL based VGA video output feature
the address transferred to PC is a branching address or address was developed using hardware inside the CPLD or FPGA. Only
of next instruction. A 32-bit instruction from instruction five signals or pins are required, two Sync signals and three
memory is splited into two groups .Instruction opcode and data, RGB color signals. A simple resistor and diode circuit is used to
instruction opcode (31- 26) is fed to control unit, which convert TTL to the analog RGB signals. This circuit and a VGA
generates different control signals as defined by the opcode. The connector is already installed on the Altera UP1 board.
remaining data is given to decoder on which the operation is
performed. Last 6 bits of instruction code is function opcode (5- Figure 1.VGA Video from a CPLD or FPGA
0), which along with the two bit ALUOp (1-0) signal is fed to RESULTS:
ALU control block. The ALU control block generates the
Simulation Results:-
control signals, which defines the operation performed by ALU

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International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) – TCET, Mumbai, India

Figure
5. Simulation result of Data Memory stage

Figure 2. Simulation Result of Fetch unit

Figure 6.Simulation of CPU/Output waveform

Figure 3. Simulation Result of Decode unit

Figure 7. MIPS with Video Output generated by UP1Board

CONCLUSION
Figure 4. Simulation Result of Execute unit
Result of the design tends to the following conclusion
Design described in HDL can be easily targeted to
different Technology and also can be easily reconfigure
for different application requirement. Also with the help

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 International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) – TCET, Mumbai, India
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