3.

5 ANALOG TO DIGITAL CONVERSION TECHNIQUES

Analog to digital converters are used to convert the analog input signal from the real world into
binary equivalent for internal processing of the microprocessor. There are different types of ADCs are
available and some of them are
(i) Single slop ADC (ii) Dual slope ADC
(iii) Successive approximation ADC (iv) Flash ADC
3.5.1 Single Slop ADC
The single slope ADC is based on comparison technique. It consists of a ramp generator and a BCD
counter (as shown in figure 3.20). Initially the ramp generator and BCD counter both are reset. In this
ADC, a comparator is used, which compares the analog input and output of ramp generator. If analog
input is high, the comparator gives high output; otherwise low output. The high output of the comparator
enables the AND gate which allows clock to reach to the counter. The clock signal increments the counter
and output of ramp generator. This process is repeated till the output of ramp generator reaches to equal
or more than analog input.
Note : Single slope ADC is generally not used because of very less resolution and variations in ramp generator
due to time, temperature and input voltage sensitivity.

3.5.2 Dual Slope ADC

Dual slope ADC is designed with an integrator and a counter. It is an indirect method for A/D
conversion. This ADC involves a technique in which analog voltage and a reference voltage are converted
into time periods by the integrator and then measured by the counter. The figure 3.21 shows the block
diagram for dual slope ADC.
The switch S1 as shown in figure 3.21 connects either to the analog input voltage (Vin) or a negative
reference voltage (– Vref). Initially (t = 0) switch S1 connects the analog voltage Vin for a fixed count.
Thus the output voltage of the integrator is given

T1
1 Vi
VOC = −
R1C1 ∫ Vi dt =−
R1C1
T1
0 .....(3.1)
where R1C1 is the integrator time constant and input voltage Vi is assumed constant over the
integration time period (0 to T1).
After T1 time period, the control logic, switches the integrator input to the reference voltage (Vref) and
counter is reset. Since the polarity of Vref is opposite to the input voltage, the capacitor of the integrator
circuit starts discharging. The counter starts counting again from zero as the capacitor begins to discharge
for the period T 2. This results in a ramp with opposite slope, and counter is stopped when the ramp
crosses the zero level. Now the output of integrator is given as

T2
1 Vref
VOD = −
R1C1 ∫ Vref dt =−
R1C1
T2
0 .....(3.2)
The integrator output voltage ramp to a voltage and get back upto 0. Therefore, the charge voltage is
equal to discharge voltage. From equation (3.1) and equation (3.2), we can write

Vi Vref
T1 = T2
⇒ R1C1 R1C1
Vi
T2 = T1
Vref
.....(3.3)
 The equation (3.3) shows that T2 is directly proportional to input analog voltage (Vi) whereas Vi and
T1 are constants.
The actual conversion of analog voltage (Vin) into a digital count occurs during T2. The counter
contents are digital output. Therefore, We can write
 Counts 
=  T2
digital output  Second  .....(3.4)
From equation (3.3), substitute the value of T2
 Counts   Vi 
=   T1
digital output  Second   Vref  .....(3.5)
The equation (3.5) shows the digital output obtained by the dual slope ADC.
Advantages :
(i) It is highly accurate
(ii) Its cost is low
(iii) It is immune to temperature caused variations in R1 and C1.
Limitation : (i) Its speed is low.

3.5.3 Successive Approximation ADC

The successive approximation ADC is based on the searching strategy called binary search. The block
diagram of successive approximation ADC is shown in figure 3.22. It consists of a DAC, a comparator
and a successive approximation register (SAR).
SOC EOC

Analog
input +
(V i) SAR
_
D1
D2
D3
Dn
Output of DAC
DAC

Fig. 3.22: Successive approximation ADC

The analog input voltage (Vi) is applied to the positive terminal of comparator. When start of
conversion (SOC) signal is received by the SAR, the most significant bit of SAR is set to ‘1’. Now the
binary code stored in SAR is transferred to the DAC. DAC converts the digital signal into equivalent
analog signal which is compared with analog input. The comparator output will be high if analog input is
higher than output of DAC. This high signal, now, set the next bit to the MSB. If the output of comparator
is low, the MSB will be rest and next bit to the MSB will be set. This process is repeated till the desired
output is received. The end of conversion is indicated by EOC signal.
For a 3–bit successive approximation ADC the conversion process is shown in figure 3.23.

Fig. 3.23: Conversion process of 3 bit successive approximation resistor (SAR)

In case of 3–bit successive approximation ADC, the most significant bit (MSB) is D3 = 1. The count
value (710) is converted in analog form with the help of DAC. The output of DAC is compared with the
analog input voltage.
If analog input is higher than the output of DAC, then D3 = 1 and D2 = 1; otherwise D3 = 0 and D2 =
1. The same process is repeated with D2 = 1, then with D1 = 1.
The Time for one analog to digital conversion must depend on both clock’s period T and number of
bits n. It is given as,
TC = T(n + 1)
where TC = Conversion time
T = Clock period
and n = number of bits
3.5.4 Flash ADC
The flash ADC is the fastest ADC in all the ADCs. Flash ADCs, also known as a simultaneous or
parallel comparator ADC, because the fast conversion speed is accomplished by providing 2n – 1
comparators and simultaneously comparing the input signal with unique reference levels spaced 1LSB
apart.
A 3–bit flash ADC is shown in figure 3.24. This ADC needs 7(23 – 1) comparator. One of input of
each comparator is connected with the analog input and other input to the reference voltage level
generated by the reference voltage divider. The reference voltage is equal to the full scale input signal
voltage.
The code resulting from the comparators is applied to the encoder which converts the code coming
from comparators to the binary code.
 Vref

R/2
13
V
14 ref C7
R
11 V
14 ref C6
R
9V
14 ref C5 D3 (LSB)
R
7 Encoder
V
14 ref C4 D2
R
5
V
14 ref C3 D1 (MSB)
R
3 V
14 ref C2
R
1 V
14 ref C1
R/2
Vin
Fig. 3.24 : 3–Bit Flash ADC

3.6 INTERFACING OF A/D CONVERTER

The ADC 0801 is an 8 bit successive approximation A/D converter. This is a 20 pin IC. The input
voltage can range from 0 to 5V and operates with a single power supply of + 5V. The pin diagram for
ADC 0801 in figure 3.25.
The ADC 0801 has two inputs VIN(+) and VIN(–) for the differential analog signal. When the analog
signal is single ended, one pin (according to polarity) is used and other is grounded. The ADC 0801
requires a clock siganl at CLK IN, the frequency range of clock signal can be from 100kHz to 800kHz.
CS 1 20 VCC
RD 2 19 CLK OUT
WR 3 18 DB0
CLK IN 4 17 DB1
INTR 5 16 DB2
V IN (+) 6 ADC 15 DB3
0801
VIN (− ) 7 14 DB4
Analog GND 8 13 DB5
Vref/2 9 12 DB6

Digital GND 10 11 DB7

Fig. 3.25: Pin diagram for ADC 0801

The ADC 0801 is designed to be microprocessor compatible. There are three pins, named are used to
interface the ADC with the microprocessor. The block diagram for ADC interfacing with microprocessor
8085 is shown figure 3.26.
 DB7

Fig. 3.26: Interfacing of ADC 0801 with the microprocessor

To start the conversion from analog to digital signal, the CS and WR signals are asserted low. When
WR goes low, the internal SAR is reset, and output lines go into high impedance state. When WR makes
transition from low high, the conversion beings.
When conversion is completed, the signal INTR goes low and data is placed on data bus. The INTR
signal can be used to inform the microprocessor that the conversion is completed and digital data is
available at data bus. When microprocessor reads the data by asserting RD , the INTR is reset.
3.7 DIGITAL–TO–ANALOG CONVERTER (DAC)
A digital–to–analog converter accepts an n–bit input word (b 1, b 2, b3, b4 bn) in binary form and
produces an analog signal proportional to it. This analog form may be sent to real world which deals with
the analog form. Depending on the output, DAC can be broadly classified in three categories :
(i) Current Output DAC
(ii) Voltage Output DAC
(iii) Multiplying type DAC
The current output DAC provides current as the output signal, as its name suggests. The voltage
output DAC internally converts the current signal into voltage signal. It requires some additional time to
convert current signal into voltage signal hence slower than the current output DAC. The multiplying type
DAC output represents the product of the input signal and the reference source. The symbol for DAC is
shown in figure 3.27.

Binary Inputs
Fig. 3.27: DAC circuit symbol
If there are four digital inputs, the DAC is known as 4–bit DAC. Each digital input requires an
electrical signal representing either a logic ‘1’ or a logic ‘0’.
3.7.1 Parameters of DAC
There are various performance parameters of DAC. These are discussed as follows :
(i) Resolution
Resolution is defined as the ratio of change in output voltage (analog) resulting from a change of one
least significant bit (LSB) at the input (digital). For an n–bit DAC resolution is given as
Vof
Resolution = (2n − 1) Volts/LSB …..(3.6)
where Vof is full scale output voltage.
(ii) Accuracy
Accuracy shows the relation between actual value and theoretical value. Ideally, the accuracy of the
DAC should not be less than ± 1/2 LSB. Mathematically
Resolution
Minimum Accuracy = 2 …..(3.7)
Vof
Minimum Accuracy = 2(2 − 1) Volts
n
…..(3.8)
(iii) Conversion Time
It is a time required to convert the digital input into equivalent analog output. It is also known as
setting time of DAC. Minimum conversion time is desired to speed up the digital–to–analog conversion.
It depends on the response time of the switches used in designing of DAC.
(iv) Stability
The performance of DAC changes according to age, temperature and power supply variations. So all
the relevant parameters must be specified over the full temperature and power supply ranges. The stability
factor shows the consistency in the analog output signal with the change in age, temperature and power
supply conditions.
Example 3.8: Find out the resolution of an 8–bit DAC, if the full scale output voltage is 5.1V.
Solution : From the definition of the resolution
Vof
Resolution = (2n − 1)
 5.1
=
(28 − 1) V/LSB
= 20m V/LSB
Example 3.9: The digital input for a 4–bit DAC is (1011)2. The DAC has an output voltage
range of 0 – 2.55V. Calculate resolution, worst accuracy and output voltage.
Solution : For given DAC
Vof = 2.55V
n=4
Input Data(D) = (1011)2 = (11)10
Therefore,
Vof 2.55
=
Resolution = (2 n − 1) 24 − 1 = 0.17V/LSB
Vof 2.55
=
Worst Accuracy = 2(2 − 1) 2(2 − 1) = 85mV
n 4

The output voltage = Resolution × Input data in decimal

= 0.17 × 11 Volts
= 1.87 Volts.
Example 3.10: An 8–bit DAC has resolution of 10mV/LSB. Find the output voltage range and
output voltage if input is (0010 1100)2.
Solution : For given DAC
n=8
resolution = 10mV/LSB
Input data (0010 1100)2 = (44)10
From the definition of resolution
Vof
Resolution = (2n − 1)

⇒ Vof = (2n – 1) × Resolution

= (28 – 1) × 10mV
= 2.55V
It means output voltage range is (0 – 2.55V).
The output voltage = Resolution × Input data in decimal
= (44 × 10)mV
= 0.44V
3.8 DIGITAL TO ANALOG CONVERSION TECHNIQUES
There are mainly two techniques used for digital to analog conversion.
(i) Binary weighted resistor network.
(ii) R/2R ladder network.
In both the techniques, an op–amp circuit is used. The network (Binary weighted resistor or R/2R
ladder) generates the weighted current according to digital input and op–amp circuit converts this current
into proportional voltage. Therefore, such DACs are known as current driven DACs.
3.8.1 Binary Weighted Resistor DAC
The binary weighted resistor DAC uses current scaling resistors 2R, 4R, 8R, … 2nR. For n bit DAC, n
binary weighted currents are derived from a reference voltage Vref Via current scaling registers. These
currents are summed with the help of an op–amp.
The circuit for binary weighted resistor DAC is shown in figure 3.28.

Fig. 3.28: Binary weighted resistor DAC

As shown in figure 3.28, the binary inputs control the switches of circuit. When digital input is logic
‘1’, it connects the corresponding resistance to the reference voltage Vref; otherwise it leaves resistor
open.
For the ON switch, current I =
and for the OFF switch, current I = 0.
Therefore, the total current from current scaling resistors is given as
IT = I1 + I2 + I3 + … + In
The output voltage is the voltage across RF and it is given as
V0 = – ITRf = – (I1 + I2 + I3 + … + In) Rf

 V V V V 
= −  D1 ref + D 2 ref + D3 ref + L + D n nref  R f
 2R 4R 8R 2 R
Vref D D D D 
=− R f  1 + 2 + 3 +L+ n 
R  2 4 8 2n 
If Rf = R, then V0 is given as
D D D D 
V0 = −Vref  1 + 2 + 3 + L + n 
 2 4 8 2n  .....(3.9)
This equation gives the analog output voltage which is proportional to the input digital signal.
Limitations :
(i) Wide range of resistor values are required (2R, 4R, 8R, … 2nR)
(ii) Resistor values have restrictions on both higher and lower ends. High value resistors can not be
fabricated in ICs whereas low value resistors have loading effect.
(iii) Finite resistance of the switches becomes significant for small current scaling resistors and there
may be error in output analog voltage.
3.8.2 R/2R Ladder Network DAC
The limitations of the binary weighted resistor DAC are overcome by the R/2R ladder network DAC.
The circuit for R/2R ladder network DAC is shown in figure 3.29. This includes the resistance of only
two values R and 2R. Each bit of the digital input connects the corresponding switch either to ground or
to the inverting terminal of op-amp which is at the virtual ground.
 Fig. 3.29: R/2R Ladder network DAC

Note : Number of bits can be expanded for R/2R ladder network DAC by adding more sections of same R/2R
values.
The currents flowing through the R/2R ladder networks are given as
Vref
I1 =
2R
Vref / 2 Vref
I2 = =
2R 4R
Vref / 4 Vref
I3 = =
2R 8R
Vref /(2 n − 1) Vref
In = =
2R 2n R
The output voltage is
V0 = – RfIT
= – Rf (I1 + I2 + I3 + … + In)
 V V V V 
= − R f  D1 ref + D 2 ref + D3 ref + L + D n ref 
 2R 4R 8R 2n R 

Vref D D D D 
=− ⋅ R f  1 + 2 + 3 + L+ n 
R  2 4 8 2n 

When Rf = R, the output voltage is given as

D D D D 
V0 = −Vref  1 + 2 + 3 + L + nn 
 2 4 8 2  …..(3.10)
This equation gives the analog output voltage which is proportional to the input digital signal.
Note : Since each digital signal connects the corresponding switch to the ground or virtual ground (inverting
terminal of op–amp) terminal, all ladder node voltage remain constant with changing input signal.

3.9 INTERFACING OF D/A CONVERTER

The 1408 is an 8 bit R/2R ladder type DAC. The output of 1408 DAC is current which is linear
product of an eight bit digital input. The settling time for this DAC is 300n sec. Figure 3.32 shows the pin
diagram for 1408 DAC.
 O/P range control 1 16 Compensation

GND 2 15 Vref

VEE 3 14 Vref

Current output 4 13 VCC

DAC
1408
(MSB) A1 5 12 A8 (LSB)

A2 6 11 A7

A3 7 10 A6

A4 8 9 A5

Fig. 3.32: Pin diagram for DAC 1408

The DAC 1408 has eight input lines (A1 – A8). The input line A1 is MSB and A8 is LSB; the
convension of labelling MSB to LSB is opposite to that of what is normally used for the data bus in
microprocessor. It requires 2mA reference current for full scale input and two power supplies VCC = + 5V
and VEE = – 15V.
The DAC 1408 consists of eight high speed current switches, R/2R ladder network and reference
current amplifier. Since the output of DAC 1408 is in current, we need an op–amp circuit which convert
the analog current signal to the analog voltage signal.The interfacing of DAC 1408 with 8085
microprocessor is shown in figure 3.33.
LATCH DAC 1408
R14
I7 07 A1 14 Vref
I6 06 A2 2.5K Rf
I5 05 A3
I4 04 A4 I0
_
Data Bus 4
I3 03 A5
+ V0
I2 02 A6
I1 01 A7 15 Op amp
I0 CS 00 A8 3 16 2 1
A7 2.5K R15

VEE
A0

IOW
Fig. 3.33: Interfacing of DAC 1408 with the 8085 microprocessor