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DESCRIPTION FEATURES
The MP1583 is a step-down regulator with a • 3A Output Current
built-in internal Power MOSFET. It achieves 3A • Programmable Soft-Start
of continuous output current over a wide input • 100mΩ Internal Power MOSFET Switch
supply range with excellent load and line • Stable with Low ESR Output Ceramic Capacitors
regulation. • Up to 95% Efficiency
Current mode operation provides fast transient • 20μA Shutdown Mode
response and eases loop stabilization. • Fixed 385KHz Frequency
• Thermal Shutdown
Fault condition protection includes
cycle-by-cycle current limiting and thermal • Cycle-by-Cycle Over Current Protection
shutdown. An adjustable soft-start reduces the • Wide 4.75V to 23V Operating Input Range
stress on the input source at startup. In • Output Adjustable from 1.22V to 21V
shutdown mode the regulator draws 20μA of • Under-Voltage Lockout
supply current.
APPLICATIONS
The MP1583 requires a minimum number of • Distributed Power Systems
external components, providing a compact • Battery Chargers
solution.
• Pre-Regulator for Linear Regulators
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
Efficiency Curve
INPUT VIN = 10V
4.75V to 23V
2 1 10nF 100
IN BS 15μ H OUTPUT VOUT=5.0V
OPEN = 7 3
EN SW 2.5V 90
AUTOMATIC 3A
STARTUP MP1583
EFFICIENCY (%)
8 5
10.5kΩ
10μ F SS FB VOUT=2.5V
GND COMP 80
CERAMIC
4 6
B330A 22μ F VOUT=3.3V
10kΩ 70
5.6nF CERAMIC
10nF
3.9kΩ 60
50
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
LOAD CURRENT (A)
MP1583_EC01
ORDERING INFORMATION
Part Number* Package Top Marking Free Air Temperature (TA)
MP1583DN SOIC8E MP1583DN –40°C to +85°C
MP1583DP PDIP8 MP1583DP –40°C to +85°C
PACKAGE REFERENCE
TOP VIEW
SOIC8N/PDIP8
BS 1 8 SS
IN 2 7 EN
SW 3 6 COMP
GND 4 5 FB
EXPOSED PAD
(SOIC8N ONLY)
CONNECT TO PIN 4 MP1583_PD01
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
Shutdown Supply Current VEN = 0V 20 30 µA
Supply Current VEN = 2.8V, VFB =1.4V 1.0 1.2 mA
Feedback Voltage VFB 4.75V ≤ VIN ≤ 23V 1.194 1.222 1.250 V
Error Amplifier Voltage Gain AVEA 400 V/V
Error Amplifier Transconductance GEA ΔICOMP = ±10μA 500 800 1120 µA/V
High-Side Switch On-Resistance RDS(ON)1 0.1 Ω
Low-Side Switch On-Resistance RDS(ON)2 10 Ω
High-Side Switch Leakage Current VEN = 0V, VSW = 0V 0 10 µA
Current Limit 4.0 4.9 6.0 A
Current Sense to COMP Transconductance GCS 3.8 A/V
Oscillation Frequency fS 335 385 435 KHz
Short Circuit Oscillation Frequency VFB = 0V 25 40 55 KHz
Maximum Duty Cycle DMAX VFB = 1.0V 90 %
Minimum Duty Cycle VFB = 1.5V 0 %
EN Shutdown Threshold Voltage 0.9 1.2 1.5 V
Enable Pull Up Current VEN = 0V 1.1 1.8 2.5 µA
EN UVLO Threshold VEN Rising 2.37 2.54 2.71 V
EN UVLO Threshold Hysteresis 210 mV
Soft-Start Period CSS = 0.1µF 10 ms
Thermal Shutdown 160 °C
VOUT=2.5V
80 VOUT
2V/div.
VOUT=3.3V
70
IL
1A/div.
60
50
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
LOAD CURRENT (A) MP1583-TPC02
MP1583-TPC01
VEN VEN
5V/div. 5V/div.
VOUT VOUT
2V/div. 2V/div.
IL IL
1A/div. 1A/div.
1ms/div.
MP1583-TPC03 MP1583-TPC04
PIN FUNCTIONS
Pin # Name Description
High-Side Gate Drive Bootstrap Input. BS supplies the drive for the high-side N-Channel MOSFET
1 BS
switch. Connect a 4.7nF or greater capacitor from SW to BS to power the high-side switch.
Power Input. IN supplies the power to the IC. Drive IN with a 4.75V to 23V power source. Bypass
2 IN IN to GND with a suitably large capacitor to eliminate noise on the input to the IC. See Input
Capacitor
Power Switching Output. SW is the switching node that supplies power to the output. Connect the
3 SW output LC filter from SW to the output load. Note that a capacitor is required from SW to BS to
power the high-side switch.
4 GND Ground. (Note: For the SOIC8E package, connect the exposed pad on backside to Pin 4).
Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive voltage
5 FB
divider from the output voltage. The feedback threshold is 1.222V. See Setting the Output Voltage
Compensation Node. COMP is used to compensate the regulation control loop. Connect a series
6 COMP
RC network from COMP to GND to compensate the regulation control loop. See Compensation
OPERATION
The MP1583 is a current-mode step-down The voltage at COMP is compared to the
regulator. It regulates input voltages from 4.75V to internally measured switch current to control the
23V down to an output voltage as low as 1.222V, output voltage.
and is able to supply up to 3A of load current.
The converter uses an internal N-Channel
The MP1583 uses current-mode control to MOSFET switch to step-down the input voltage to
regulate the output voltage. The output voltage is the regulated output voltage. Since the MOSFET
measured at FB through a resistive voltage requires a gate voltage greater than the input
divider and amplified through the internal error voltage, a boost capacitor connected between
amplifier. The output current of the SW and BS drives the gate. The capacitor is
transconductance error amplifier is presented at internally charged when SW is low.
COMP where a RC network compensates the
An internal 10Ω switch from SW to GND is used
regulation control system.
to insure that SW is pulled to GND when SW is
low in order to fully charge the BS capacitor.
IN 2
INTERNAL CURRENT
REGULATORS SENSE
AMPLIFIER + 5V
OSCILLATOR Σ
SLOPE
COMP --
1 BS
40/385KHz
CLK
+ + S Q
R Q
3 SW
1.2V -- SHUTDOWN -- CURRENT
COMPARATOR 1μ A COMPARATOR
EN 7
LOCKOUT
COMPARATOR 7V
--
1.8V
2.54V + + -- 4 GND
APPLICATION INFORMATION
COMPONENT SELECTION Choose an inductor that will not saturate under
Setting the Output Voltage the maximum inductor peak current.
The output voltage is set using a resistive The peak inductor current can be calculated by:
voltage divider from the output voltage to the
FB pin. The voltage divider divides the output VOUT ⎛ V ⎞
I LP = I LOAD + × ⎜⎜ 1 − OUT ⎟⎟
voltage down to the feedback voltage by the 2 × fS × L ⎝ V IN ⎠
ratio:
Where ILOAD is the load current.
R2
V FB = VOUT Table 1 lists a number of suitable inductors
R1 + R 2
from various manufacturers. The choice of
Where VFB is the feedback voltage and VOUT is which inductor to use mainly depends on the
the output voltage. price vs. size requirements and any EMI
Thus the output voltage is: requirements.
VOUT ⎛ V ⎞
L= × ⎜⎜ 1 − OUT ⎟⎟
f S × ΔI L ⎝ VIN ⎠
Where VIN is the input voltage, fS is the 385KHz
switching frequency and ΔIL is the peak-to-peak
inductor ripple current.
The MP1583 can be optimized for a wide range In this case, a third pole set by the
of capacitance and ESR values. compensation capacitor (C6) and the
compensation resistor (R3) is used to
Compensation Components
compensate the effect of the ESR zero on the
The MP1583 employs current mode control for
loop gain. This pole is located at:
easy compensation and fast transient response.
The system stability and transient response are 1
controlled through the COMP pin. COMP is the f P3 =
2π × C 6 × R 3
output of the internal transconductance error
amplifier. A series capacitor-resistor The goal of compensation design is to shape
combination sets a pole-zero combination to the converter transfer function to get a desired
control the characteristics of the control system. loop gain. The system crossover frequency
(where the feedback loop has unity gain) is
The DC gain of the voltage feedback loop is:
important.
VFB Lower crossover frequencies result in slower
AVDC = RLOAD × GCS × AVEA ×
VOUT line and load transient responses, while higher
crossover frequencies could cause system
Where AVEA is the error amplifier voltage gain, instability. A good standard is to set the
GCS is the current sense transconductance and crossover frequency to approximately one-tenth
RLOAD is the load resistor value. of the switching frequency. The switching
The system has two poles of importance. One frequency for the MP1583 is 385KHz, so the
is due to the compensation capacitor (C3) and desired crossover frequency is around 38KHz.
the output resistor of error amplifier while the Table 3 lists the typical values of compensation
other is due to the output capacitor and the load components for some standard output voltages
resistor. These poles are located at: with various output capacitors and inductors.
G EA The values of the compensation components
f P1 = have been optimized for fast transient
2π × C 3 × AVEA responses and good stability at given conditions.
1 Table 3—Compensation Values for Typical
f P2 = Output Voltage/Capacitor Combinations
2π × C 2 × RLOAD
(Please reference Fig. 3 and Fig. 4)
Where GEA is the error amplifier
VOUT C2 R3 C3 C6
transconductance.
22μF
2.5V 3.9kΩ 5.6nF None
The system has one zero of importance, due to Ceramic
the compensation capacitor (C3) and the 22μF
3.3V 4.7kΩ 4.7nF None
compensation resistor (R3). This zero is located Ceramic
at: 5V
22μF
7.5kΩ 4.7nF None
Ceramic
1
f Z1 = 12V
22μF
16.9kΩ 1.5nF None
2π × C 3 × R3 Ceramic
560μF Al.
The system may have another zero of 2.5V 91kΩ 1nF 150pF
30mΩ ESR
importance, if the output capacitor has a large 560μF Al
capacitance and/or a high ESR value. The zero 3.3V 120kΩ 1nF 120pF
30mΩ ESR
due to the ESR and capacitance of the output 470μF Al.
5V 100kΩ 1nF 120pF
capacitor is located at: 30mΩ ESR
220μF Al.
1 12V 169kΩ 1nF 39pF
f ESR = 30mΩ ESR
2π × C 2 × RESR
1 f
SW
< S
1 BS
IN
2π × C2 × R ESR 2
C5
2
3
R1
C6 SS/REF 8 efficiency of the regulator, the applicable
EN 7
6
FB 5
conditions of external BST diode are:
R2
COMP
SGND z VOUT=5V or 3.3V; and
VOUT
z Duty cycle is high: D= >65%
4 GND VIN
SW
C2
L1 regulator to BST pin, as shown in Fig.4
External BST Diode
IN4148
BST
C1 D1 CBST
MP1583
SW 5V or 3.3V
PGND C5 L +
COUT
Top Layer
Figure 4—Add Optional External Bootstrap
Diode to Enhance Efficiency
The recommended external BST diode is
IN4148, and the BST cap is 0.1~1µF.
Bottom Layer
Figure 3―PCB Layout (Double Layer)
Figure 5—3.3V output 3A solution with Murata 22µF, 10V Ceramic Output Capacitor
PACKAGE INFORMATION
SOIC8E (EXPOSED PAD)
0.189(4.80) 0.124(3.15)
0.197(5.00) 0.136(3.45)
8 5
1 4
0.051(1.30)
0.067(1.70)
0.0075(0.19)
SEATING PLANE
0.0098(0.25)
0.000(0.00)
0.013(0.33) 0.006(0.15)
0.020(0.51) SIDE VIEW
0.050(1.27)
BSC
GAUGE PLANE
0.010(0.25) BSC
0.024(0.61) 0.050(1.27)
0.016(0.41)
0o-8o 0.050(1.27)
0.063(1.60)
DETAIL "A"
0.103(2.62) 0.213(5.40)
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
0.138(3.51) OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
RECOMMENDED LAND PATTERN 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
PDIP8
0.325(8.255)
0.387 (9.830) PIN 1 IDENT. 0.300(7.620)
0.367 (9.322)
0.260 (6.604)
0.240 (6.096)
3°~11°
0.014 (0.356)
0.008 (0.200) Lead Bend
0.392(9.957)
0.065 (1.650) 0.332(8.433)
0.050 (1.270)
0.040 (1.016)
0.020 (0.508)
0.145(3.683)
0.134(3.404)
0.035 (0.889)
0.015 (0.381)
0.140(3.556)
0.120(3.048) 0.100 BSC(2.540)
0.021(0.533)
0.015(0.381)
NOTE:
1) Control dimension is in inches
. Dimension in bracket is millimeters.
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.