Logic Family

Digital Electronics (EC 2011)

Contents
• Introduction
• Important parameters
• CMOS Logic
• Transistor-Transistor Logic (TTL)
• Open Collector Logic
• Emitter-coupled Logic (ECL)
Introduction
Important Parameters
• Propagation delay (𝑡𝑝𝑑 )
• A pulse through a gate takes a certain amount of time to propagate from
input to output.
𝑡𝑝𝐿𝐻 +𝑡𝑝𝐻𝐿
• It is expressed as 𝑡𝑝𝑑 =
2
• 𝑡𝑝𝐿𝐻 is the time delay when the output changes from logic 0 to logic 1
• 𝑡𝑝𝐻𝐿 is the time delay when the output changes from logic 1 to logic 0
Important Parameters
• Fan-in Fan-in = 2

• The number of inputs of a gate

• Fan-out
• Maximum number of standard loads that the output of the gate can drive
without degrading its normal operation.
• Example,

Fan-out=3
Important Parameters
• Power dissipation
𝐼𝑐𝑐(𝑎𝑣𝑔)
• It can be measured as 𝑃𝑑 = 𝑉𝑐𝑐 ×
𝑁
• 𝑉𝑐𝑐 is the gate supply voltage and 𝐼𝑐𝑐(𝑎𝑣𝑔) is the average current drawn from the
supply by the entire IC and 𝑁 is the number of gates in the IC.
𝐼 +𝐼
• Now, 𝐼𝑐𝑐(𝑎𝑣𝑔) = 𝐶𝐶𝐻 𝐶𝐶𝐿
2
• 𝐼𝐶𝐶𝐻 is the current drawn by the IC when all the gates are in HIGH state and 𝐼𝐶𝐶𝐿 is
the current drawn by the IC when all the gates are in LOW state
• Speed Power Product = 𝑡𝑝𝑑(𝑔𝑎𝑡𝑒) × 𝑃𝑑(𝑔𝑎𝑡𝑒)
• Figure of merit of an IC family
• Smaller the product, better the overall performance
• A low value is desirable
Important Parameters
• Speed Power Product
• SPP = 𝑡𝑝𝑑(𝑔𝑎𝑡𝑒) × 𝑃𝑑(𝑔𝑎𝑡𝑒)
• Figure of merit of an IC family
• Smaller the product, better the overall performance
• A low value is desirable
MOSFET
• Metal Oxide Semiconductor Field Effect Transistor
• Two types
• p-channel
• n-channel
MOSFET

n-channel p-channel
CMOS Logic
• Complementary Metal Oxide Semiconductor
• Contains both n-channel and p-channel MOSFETs in the circuit
• CMOS Inverter
• 𝑄1 : p-channel
• 𝑄2 : n-channel
CMOS Inverter
High input, Low output

p-channel

n-channel

Low input, High output

CMOS NAND Gate
2-input NAND gate

A B Q1 Q2 Q3 Q4 Output
L L ON ON OFF OFF H
L H ON OFF OFF ON H
H L OFF ON ON OFF H
H H OFF OFF ON ON L

L: Low, H: High
CMOS NOR Gate
2-input NOR gate

A B Q1 Q2 Q3 Q4 Output
L L ON ON OFF OFF H
L H ON OFF OFF ON L
H L OFF ON ON OFF L
H H OFF OFF ON ON L

L: Low, H: High
TTL NAND Gate
• Transistor-Transistor Logic
TTL NAND Gate
• Configuration
• Multiple emitter transistor Q1
• Transistor Q2 acts as phase splitter
• Arrangements of transistors Q3, Q4 and diode D
• Known as totem-pole
• Diode D does not allow Q3 and Q4 to conduct simultaneously.
TTL NAND Gate
• Operation
• Inputs A=B=HIGH
• Base-emitter junction of Q1 is reverse-biased, but collector-base junction of
Q1 is forward-biased
• Turns on Q2; current flowing from Q2’s emitter to the base of Q3
• Q3 is turned ON producing low level of output voltage. So output is logic 0.
• Inputs (A=B=LOW or A=LOW or B=LOW)
• Base-emitter junction(s) is (are) forward-biased, collectror-base junction is
reverse-biased
• Q2 is OFF, hence Q3 is OFF
• But Q4 is ON and produces HIGH level output voltage. So output is logic 1.
TTL NAND Gate
• Advantages
• Low power dissipation
• Very fast output rise-time
• Disadvantages
• Outputs cannot be wire ANDed
• That is, the outputs of the gates cannot be tied together to obtain AND operation of
those outputs
• For few nanoseconds, Q3 and Q4 conduct simultaneously resulting in large
current flow
• may damage the circuit
Open-Collector Inverter
with external
Resistor R

No external
Resistor R
Open-Collector Inverter
• Operation
• When input is HIGH
• Base-emitter junction of Q1 is reverse-biased, but collector-base junction of Q1 is
forward-biased
• Q2 is turned ON, current flows from emitter of Q2 to base of Q4
• Q4 is turned ON connecting the output to the ground.
• Hence output is LOW.
• When input is LOW
• Base-emitter junction of Q1 is forward-biased, but collector-base junction of Q1 is
reverse-biased
• Q2 is turned OFF, no current flows from emitter of Q2 to base of Q4
• Q4 is turned OFF and output is pulled to 𝑉𝑐𝑐 through resistor R.
• Hence output is HIGH.
Open-Collector Gates
• Advantage
• Outputs of gates can be wired ANDed.
• Require less area as compared to totem-pole TTL

• Disadvantage
• Slow output response, cannot be used in high-speed switching applications
Emitter-Coupled Logic
• Characteristics
• Transistors never saturate.
• High speed with propagation delay of 1ns.
• Negative logic levels
• -0.9 V for logic 1 and -1.7 V for logic 0
• Low noise margin (about 250 mV)
• Produces output and its complement
• No need of inverter
• Large fan-out because of low output impedance
• Large power dissipation per gate (𝑃𝑑 = 40 𝑚𝑊)
ECL OR-NOR Gate

I/O characteristics

Logic symbol

Circuit diagram
Working of ECL OR-NOR Gate
• When inputs A and B are LOW (-1.7 V)
• Q2 is ON, Q1A and Q1B are OFF
• The value of R2 makes the collector voltage of Q2 HIGH
• Emitter voltage of Q4 becomes LOW (-1.7 V), so OR output is LOW
• Emitter voltage of Q3 becomes HIGH (-0.9 V), so NOR output is HIGH
• When input A or B is HIGH or both are HIGH (-0.9 V)
• Either Q1A or Q1B is ON or both are ON, Q2 is OFF
• Collectors of Q1A and Q1B are at High-level
• Emitter voltage of Q3 becomes LOW (-1.7 V), so NOR output is LOW
• Emitter voltage of Q4 becomes HIGH (-0.9 V), so OR output is HIGH
Advantages and Disadvantages
• Advantages
• Fast switching speed
• Gates can be wired ORed
• no noise spikes
• Same circuit generates output and its complementary.
• Disadvantages
• High cost
• Low noise margin
• Negative supply voltage and logic level, making it incompatible with TTL and MOS
circuits
• Application
• Super fast computers
Logic Family
Digital Electronics (EC 2011)