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The pcb is often marked with a + sign for the cathode end.
SEMICONDUCTOR MATERIALS
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The circuit enables the forward bias voltage across the diode
to be set anywhere from zero to the maximum positive
voltage of the battery.
During the first half cycle of the waveform shown on the left,
A is positive and B is negative.
The diode is forward biased and current flows around the
circuit formed by the diode, the transformer winding and the
load.
Since the current through the load, and the voltage across the
load are in the same proportions, then the voltage across the
load is as shown in the right hand diagram, during the first
half cycle.
During the second half cycle, A and the anode are negative,
B and the cathode are positive.
The diode is reverse biased and no current flows.
This is indicated by the horizontal line in the right hand
diagram.
There is one pulse for every cycle in. i.e 50 pulses per
second (in the UK)
Since there are two pulses for each cycle of input, there are
100 pulses per second out (in the UK).
CLASS A CLASS
B CLASS C
With class C bias the bias point is set well below cut off.
Collector current can only be made to flow by increasing the
bias point considerably above its present value.
The emitter voltage is 0.6 volts lower than the base voltage.
The positive power supply rail is joined to the zero volts rail
by C3. As far as ac is concerned, both rails are joined
together.
TR2 and TR3 are biased in class B, which means that they
are normally non conducting when there is no signal input.
If the two inputs are joined together, then the output voltage
should be midway between the two supply rails, i.e. zero
volts.
If it is not, then there are two connections for adding a
potentiometer, to remove this OFFSET.
In fact the bandwidth (the point at which the output has fallen
by 3 dB) is only 1 kHz.
Gain is 1+ R2/R1
At switch on, the voltage across the capacitor is zero and the
output is at +12 volts.
The buzzer is not energised.
SET and RESET cannot affect the outputs unless the clock
pulse is high.
The D type flip-flop has only one input (D for Data) apart from
the clock.
During clock pulse D, data goes low for a period, but Q stays
high.
Data goes high for a period during clock pulse E, but Q stays
low.
A couple of definitions :-
The clock of the slave is fed via an inverter so that the falling
edge of the origonal clock pulse becomes a rising edge.
The slave clock pulse is an inverted version of the clock pulse
shown in the lower diagram.
The preset and clear are independent of the clock pulse and
are ASYNCHRONOUS inputs.
Note that the J and K inputs are taken high so that the flip-
flops toggle on the clock pulses.
Looking at the diagram below the count starts with ABCD all
low, giving a count of 0000.
After 12 pulses, A and B are low and C and D are high, 1100,
equivalent to decimal 12.
The count can be set to 0000 by pulsing the Reset line low.
The flip-flops cannot change state until the preceding one has
done so.
This means gives rise to a delay in the the system due to the
propagation delay of each stage.
SYNCHRONOUS COUNTERS
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Bear in mind, that when J and K are both low, a flip-flop will
not change state, upon the arrival of a clock pulse.
When J and K are both high, then Q will toggle upon the
arrival of a clock pulse.
The two AND gates are decoders, which recognise the state
of the A, B and C outputs.
The first and second flip-flops are now set to toggle on the
next clock pulse.
After four more clock pulses, this data will be shifted out of
the register.
Copyright Graham Knott 1999
They are then clocked out,one after the other, in serial form.
When the ramp voltage and the analogue voltage are the
same, the output of the comparator goes low.
When the ramp voltage and the analogue voltage are the
same, the output of the comparator goes low.