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use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
entity chessboard is
� � Port ( clk,reset : in �STD_LOGIC;
begin
process(clk)
variable c : std_logic := '0';
begin
if clk' event and clk = '1' then
c := not c;
end if;
crtclk <= c;
end process;
process (reset,crtclk)
begin
end process;
end behavioral;