This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2018.2823379, IEEE Journal
of Emerging and Selected Topics in Power Electronics
Switched-Boost Modified Z-Source Inverter
Topologies with Improved Voltage Gain
Capability
Anish Ahmad, Member, IEEE, Vinod Kumar Bussa, Student Member, IEEE
R. K. Singh, Senior Member, IEEE, and R. Mahanty, Member, IEEE

Abstract—This paper presents three-phase switched-boost
modified Z-source inverter (ZSI) topologies with improved boost
capabilities. In the proposed ZSIs, the voltage gain is increased
significantly by adding one auxiliary switch and one diode
without using additional passive components. The concept is
applied to traditional ZSI, discontinuous input current quasi-ZSI
(qZSI), and continuous input current qZSI resulting into three
new inverter topologies; switched-boost ZSI (SB-ZSI),
discontinuous input current qZSI (DC-qZSI), and continuous
input current qZSI (CC-qZSI). Anatomization of operating
principle, steady state analysis, voltage gain, voltage stress,
current stress, stored energy analysis, power loss, total harmonic
distortion, and efficiency analysis are carried out to highlight the
advantages of the proposed inverters as compared to the
conventional ZSIs. Finally, the operation of the proposed CC-
qZSI is validated through simulation and experimental results.
Index Terms— Buck-Boost Converter, Inverters, Power
Conversion, Quasi-ZSI (qZSI), Z-source Inverter (ZSI)
I. INTRODUCTION
T HE converters are essential parts of the domestic, comer-
cial and industrial necessities of energy conversion from
one form into another. The classical converters are voltage‐fed
and current‐fed converters [1]-[3]. The classical voltage‐fed
converter is realized by connecting a dc voltage source in
parallel with a large capacitor. It behaves as a buck inverter
for dc‐ac power conversion and behaves as a boost converter
for ac‐to‐dc power conversion. The shoot‐through problem in
voltage‐fed caused by misgating due to electromagnetic
interference (EMI) is one of the main causes of concern in
terms of inverter’s reliability [4]-[6]. However, the current‐fed
converter is realized by connecting a dc voltage source in
series with a large inductor. It behaves as a boost inverter for
dc-ac power conversion and a buck converter for ac-dc power
conversion. The open circuit operation, which may happen
due to misgating of switches caused by EMI, is a serious
problem in current‐fed converter [7]-[9].
Manuscript received August 21, 2017; revised November 30, 2017;
accepted March 18, 2018. (Corresponding author: Anish Ahmad.)
A. Ahmad, V. K. Bussa, R. K. Singh and R. Mahanty are with the
Department of Electrical Engineering, Indian Institute of Technology
(Banaras Hindu University) Varanasi India 221005
(e-mail: aahmad.rs.eee13@iitbhu.ac.in; vinod.rs.eee14@iitbhu.ac.in;
rksingh.eee@iitbhu.ac.in; rmahanty.eee@itbhu.ac.in).
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1
The disadvantages of classical voltage‐fed and current‐fed
converters are eliminated by impedance source network. The
Z-source converters are one of the most promising converter
topologies which overcome the disadvantages of classical
converters. The power conversion concept of Z-source
converters is successfully applied in different applications
such as hybrid electric vehicles (HEV), multilevel inverters,
renewable power conversions, matrix converter, motor drives
and other industrial applications [10]-[16]. The traditional Z-
source inverter (ZSI) [17] is shown in Fig.1. The ZSI has
many advantages over conventional voltage‐fed and current‐
fed converters which includes buck-boost and inherent shoot-
through protection abilities. The ZSI has single conversion
stage and has increased reliability against EMI.
D1 L1
Gs1 Gs3 Gs5
Vin S1 S3 S5
Vsn a b
c
C1
L2
C2
Gs4
S4
Gs6
S6
Gs2
S2
Fig. 1. Classical Z- source inverter (ZSI).
Classical ZSI consists of two capacitors and two inductors
of symmetrical values. Switched boost inverter (SBI) is
derived from inverse Watkins–Johnson topology [18] has
similar characteristics as ZSI. The SBI has less number of
components count over classical ZSI but has less voltage gain
compared to ZSI. Both ZSI and SBI utilize shoot-through duty
cycle in the inverter leg to improve reliability against EMI but
both have discontinuous input current profile.
The disadvantages of discontinuous input current profile of
ZSI is overcome by the continuous input current qZSI with
same gain factor and have reduced capacitor voltage stress.
Different variants of quasi-Z- source inverter (qZSI) is
presented in [19]. Continuous input current based qZSI and
discontinuous input current qZSI are shown in Figs. 2(a) and
2(b) respectively. Current-fed switched inverter (CFSI) has
similar characteristics as ZSI with continuous input current
[20]. Quasi- switched boost inverter (qSBI) discussed in [21]
gives similar characteristics as CFSI. Another variant of qSBI,
known as embedded qSBI is reported in [21]. The difference
between embedded qSBI and continuous input current type
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2018.2823379, IEEE Journal
of Emerging and Selected Topics in Power Electronics
2

qZSI is that the embedded qSBI save one extra capacitor and stress, current stress, stored energy analysis, power loss, total
inductor but at the cost of one additional active switch and one harmonic distortion (THD), and efficiency analysis are carried
diode compared to qZSI. The current rating required for out to show the advantages of the proposed three-phase
switches and diodes in qSBI is low and has higher efficiency inverters as compared to the conventional ZSIs. Simulation
as compared to qZSI [22]. The ZSI, qZSI, and qSBI are and experimental studies are presented to validate the
having same boost factor and if 𝐷𝑠 is shoot-through duty performance of the proposed three-phase CC-qZSI.
cycle, the boost factor of these inverters is 𝐵 = 1/(1 − 2𝐷𝑠 ).
Further, ac output voltage depends on modulation index (M) , II. PROPOSED TOPOLOGIES OF MODIFIED ZSIS
B and peak ac voltage 𝑉𝑜 = 𝑀. 𝐵. 𝑉𝑖𝑛 . It may be noted that ac The proposed three topologies of modified ZSIs are shown
output voltage is restricted by M and there is a constraint on in Fig. 3. The proposed switched-boost ZSI (SB-ZSI),
𝐷𝑠 and M that 𝑀 + 𝐷𝑠 ≤ 1 [20]. For high boost factor, inverter discontinuous input current qZSI (DC-qZSI) and continuous
needs to be operated with higher values of 𝐷𝑠 . However, input current qZSI (CC-qZSI) are shown in Figs. 3(a), 3(b)
higher values of 𝐷𝑠 is restricted because of components and 3(c) respectively. In the proposed ZSIs, one of the
voltage stresses and poor power quality of output. Moreover, capacitor is switched using a switch and a diode, without using
at higher values of 𝐷𝑠 , the effect of parasitic components additional passive components unlike the traditional voltage-
become more dominant which results into reduction in voltage fed ZSI and qZSI. The proposed topologies consists of two
gain significantly. states; shoot-through state (𝐷𝑠 𝑇𝑠 ) and non-shoot-through
C1

L1
C1
- +
L2 L1 D1
- +
L2
state (1 − 𝐷𝑠 ) 𝑇𝑠 .
D1
C
- 1+
D1 L1 L1
Gs1 Gs3 Gs5 Gs1 Gs3 Gs5 D1 L2
Vin
+
-

Vin S1 S3 S5 S1 S3 S5
C2 +
Vsn a b C2 Vsn a b Gso
c - c
Gs1 Gs3 Gs5 So
Gs4 Gs6 Gs4 Gs6 Gs2
Vin S1 S3 S5 D2 Gs1 Gs3 Gs5
Gs2 S3 S5
S4 S6 S2 S4 S6 S2 a b
S1
Vsn

+
-
c Vsn a b
C2 c
(a) (b) +
C1 - Gso
+
C2 - Gs4 Vin
Gs6 Gs2
Fig. 2. Traditional quasi-ZSIs (qZSIs) (a) discontinuous continuous input So D2 S4 S6 S2
Gs4 Gs6 Gs2
S4 S6 S2
current qZSI and (b) continuous input current qZSI. L2 C2

(a) (b)
C1
Improved voltage gain in inverters can be achieved by - +
L1 D1 L2
cascading of different topologies [23], switched-inductor
topologies [24]-[27], switched-capacitor topologies [28]-[32]
Gs1 Gs3 Gs5
Vin
and coupled inductor topologies [33],[34]. For increasing Vsn
S1
a
S3
b
S5
c
output voltage using switched-inductor and switched- + C2
Gso - Gs4 Gs6 Gs2
capacitors, number of passive components increases which So D2 S4 S6 S2

eventually increases the converter weight, volume, and size.

(c)
Further, the leakage inductance of the coupled inductors Fig. 3. Topologies of proposed modified ZSIs (a) switched-boost ZSI (SB-
increases power losses and thus deteriorates the efficiency. ZSI), (b) discontinuous input current qZSI (DC-qZSI), and (c) continuous
In this paper, three-phase topologies of switched-boost input current qZSI (CC-qZSI).
modified Z-source inverters (ZSIs) with improved boost L1 IL 1 L1
IL1 Vsn Vs n
capability are presented. The improved voltage gain is + VL1 - + VL 1 -
achieved by adding one auxiliary switch and one diode
without using additional passive components. The proposed Vin Vi n
Is n
concept is applied to traditional ZSI, discontinuous input IC1 IC2 IC 1 IC 2
current quasi-ZSI (qZSI) and continuous input current qZSI. + + + +
C1 - VC1 C1 - VC 1
C2 - VC2 C2 - VC 2
In this way, three inverter topologies switched-boost ZSI (SB- - VL2 + - VL 2 +
ZSI), discontinuous input current qZSI (DC-qZSI) and L2 IL2 L2 IL 2
continuous input current qZSI (CC-qZSI) are evolved. The
(a) (b)
proposed topologies give high voltage gain at low 𝐷𝑠 as
Gso DsTs (1-Ds)Ts
compared to the traditional ZSIs. The proposed ZSIs can be Gsi
t
applied to dc-dc and dc-ac power conversion for renewable Vso Vc2

t
energy sources where low voltage input and high voltage gain Vc2
VL1 t
is required. Since for the proposed ZSIs, M+Ds≤ 1, operating Vin -Vc1

at low Ds gives the flexibility to operate with wide ranges of Vsn Vc1 -VL1

M. This enables the proposed topologies to give higher ac Vc1+Vc2

t

voltage gain compared to traditional ZSIs. To validate the VL2 t

Vin -Vc2
proposed ZSIs, pulse width modulation (PWM) control (c) (d)
technique discussed in [27] has been used to verify the
Fig. 4. Operating waveforms of proposed SB-ZSI: (a) equivalent circuit in
operation of the proposed three phase inverter. Detailed shoot-through interval, (b) equivalent circuit in non-shoot-through interval, (c)
analysis and comparison in terms of voltage gain, voltage key voltage waveforms, and (d) transfer characteristics.

2168-6777 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2018.2823379, IEEE Journal
of Emerging and Selected Topics in Power Electronics
3

A. Operating Principle of the Proposed SB-ZSI 𝑉𝑠𝑛 1

𝐵= = (14)
𝑉 𝑖𝑛 𝐷𝑠2 −3𝐷𝑠 +1
The equivalent circuits for shoot-through and non-shoot- The transfer characteristics of proposed SB-ZSI is plotted in
through states are presented in Figs. 4(a) and 4(b). The Fig. 4(d).
voltages across the inductors are 𝑉𝐿1 , 𝑉𝐿2 and the currents
through inductors are 𝐼𝐿1 and 𝐼𝐿2 respectively. The current B. Operating Principle of the Proposed DC-qZSI
through the capacitors are 𝐼𝑐1 , 𝐼𝑐2 and the voltage across the The proposed DC-qZSI equivalent circuits of shoot-through
capacitors are 𝑉𝑐1 and 𝑉𝑐2 respectively. The switching voltage interval and non-shoot-through interval are shown in Figs. 5(a)
waveforms are shown in Fig. 4(c). and 5(b). The voltages across the inductors are 𝑉𝐿1 , 𝑉𝐿2 and
1) Shoot-through interval currents through inductors are 𝐼𝐿1 and 𝐼𝐿2 . The current through
The diodes D1 and D2 are reverse biased and switch So the capacitors are 𝐼𝑐1 , 𝐼𝑐2 and voltage across the capacitors are
conduct. In this interval, one of the inverter legs is also 𝑉𝑐1 and 𝑉𝑐2 . The switching voltage waveforms are shown in
conducted. The input current is discontinuous as traditional Fig. 5(c). Moreover, the transfer characteristic of proposed
ZSI. The voltage across the inductors and current through DC-qZSI is plotted in Fig. 5(d).
the capacitors in the shoot-through interval can be written
C C
as: - 1+ IC1 - 1+ IC1
𝑑 𝑖𝐿1 L1 IL2 L2 L1
IL1 Vsn IL1 IL2 L2 Vsn
𝐿1 = 𝑉𝑐2 (1) + VL1 - + VL2 - + VL1 - + VL2 -
𝑑𝑡
𝑑𝑖𝐿2
𝐿2 = 𝑉𝑐1 + 𝑉𝑐2 (2) IC2 IC2
𝑑𝑡

+
-

+
Isn

-
C2 C2
𝑑𝑉𝑐1 Vin Vin
𝐶1 = −𝐼𝐿2 (3)
𝑑𝑡
𝑑 𝑉𝑐2
𝐶2 = −𝐼𝐿1 −𝐼𝐿2 (4) C2 C2

𝑑𝑡 (a) (b)
2) Non-shoot-through interval Gso
Gsi
DsTs (1-Ds)Ts
t
During the non-shoot-through behavior of proposed SB- Vso Vc2

ZSI switches, switch So is turned-OFF and inverter bridge t

Vin+Vc1+Vc2
is in power interval. In this case, both the diodes are in VL1 t
-Vc2
conduction mode. The voltage across the inductors and Vin+Vc1+Vc2
Vsn
current through the capacitors in non-shoot-through t
Vin+Vc2
interval are obtained as follows: VL2 t
𝑑𝑖𝐿1 -Vc1
𝐿1 = 𝑉𝑖𝑛 − 𝑉𝑐1 (5)
𝑑𝑡 (c) (d)
𝑑𝑖𝐿2
𝐿2 = 𝑉𝑖𝑛 − 𝑉𝑐2 (6) Fig.5. Operating waveforms of DC-qZSI: (a) equivalent circuit in shoot-
𝑑𝑡 through interval, (b) equivalent circuit in non-shoot-through interval, (c) key
𝑑𝑉𝑐1 voltage waveforms, and (d) transfer characteristics.
𝐶1 = 𝐼𝐿1 −𝐼𝑠𝑛 (7)
𝑑𝑡
𝑑𝑉𝑐2 1) Shoot-through interval
𝐶2 = 𝐼𝐿2 −𝐼𝑠𝑛 (8)
𝑑𝑡 In this mode of operation, the diodes 𝐷1 and 𝐷2 are reverse
Under steady state condition, the average current through biased, and one of the inverter legs is also conducted as shown
the capacitor and average voltage across the inductor over one in Fig. 5(a). The inductor voltages and capacitor currents are
switching cycle should be zero [35]. By applying volt-seconds given as follows:
𝑑𝑖 𝐿1
balance principle to the 𝐿1 and 𝐿2 over one switching period, 𝐿1 = 𝑉𝑖𝑛 + 𝑉𝑐1 +𝑉𝑐2 (15)
𝑑𝑡
(9) and (10) are obtained as 𝑑𝑖𝐿2
(1−𝐷𝑠 )2
𝐿2 = 𝑉𝑖𝑛 + 𝑉𝑐2 (16)
𝑑𝑡
𝑉𝑐1 = 𝑉𝑖𝑛 (9) 𝑑𝑉𝑐1
𝐷𝑠2 −3𝐷𝑠 +1 𝐶1 = −𝐼𝐿1 (17)
1−𝐷𝑠 𝑑𝑡
𝑉𝑐2 = 𝑉𝑖𝑛 (10) 𝑑𝑉𝑐2
𝐷𝑠2 −3𝐷𝑠 +1 𝐶2 = −𝐼𝐿1 −𝐼𝐿2 (18)
𝑑𝑡
By applying charge-seconds balance principle to 𝐶1 and 𝐶2 2) Non-shoot-through interval
over one switching period, (11) and (12) are obtained as The non-shoot-through behavior of proposed DC-qZSI is
1−𝐷
𝐼𝐿1 = 2 𝑠 𝐼𝑠𝑛 (11) shown as an equivalent circuit in Fig. 5(b). Applying KVL in
𝐷𝑠 −3𝐷𝑠 +1
𝐷𝑠2 −3𝐷𝑠 +2 the equivalent circuit of the non shoot-through interval is
𝐼𝐿2 = 𝐼 (12)
𝐷𝑠2 −3𝐷𝑠 +1 𝑠𝑛 written as follows:
From Figs. 4(a) and (b), the switched node voltage across 𝑑𝑖𝐿1
𝐿1 = − 𝑉𝑐2 (19)
𝑑𝑡
the inverter bridge can be written as 𝑑𝑖𝐿2
𝑉 𝐿2 = −𝑉𝑐1 (20)
𝑉𝑠𝑛 = 2 𝑖𝑛 (13) 𝑑𝑡
𝐷𝑠 −3𝐷𝑠 +1 𝑑𝑉𝑐1
𝐶1 = 𝐼𝐿2 −𝐼𝑠𝑛 (21)
The Boost factor (B) is defined as 𝑑𝑡
𝑑𝑉𝑐2
𝐶2 = 𝐼𝐿1 −𝐼𝑠𝑛 (22)
𝑑𝑡

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2018.2823379, IEEE Journal
of Emerging and Selected Topics in Power Electronics
4

Applying volt-seconds balance principle to 𝐿1 and 𝐿2 over 𝑑𝑉

𝐶2 𝑐2 = −𝐼𝐿1 −𝐼𝐿2 (32)
𝑑𝑡
one switching period, (23) and (24) are obtained as
𝐷𝑠 (1−𝐷𝑠 )
2) Non-shoot-through interval
𝑉𝑐1 = 𝑉 (23) Equivalent circuit in the non-shoot-through interval is
𝐷𝑠2 −3𝐷𝑠 +1 𝑖𝑛

𝑉𝑐2 =
𝐷𝑠
𝑉 (24) shown in Fig. 6(b). In this mode of operation, the switch 𝑆𝑜 is
𝐷𝑠2 −3𝐷𝑠 +1 𝑖𝑛 reverse biased, and inverter bridge operates in power mode.
Applying charge-seconds balance principle to 𝐶1 and 𝐶2 The inductor voltages and capacitor currents in non-shoot-
over one switching period, (25) and (26) are obtained as through interval are given as follows:
1−𝐷
𝐼𝐿1 = 2 𝑠 𝐼𝑠𝑛 (25) 𝐿1
𝑑𝑖 𝐿1
= 𝑉𝑖𝑛 − 𝑉𝑐2 (33)
𝐷𝑠 −3𝐷𝑠 +1 𝑑𝑡
(1−𝐷𝑠 )2 𝑑𝑖𝐿2
𝐼𝐿2 = 𝐼 (26) 𝐿2 = −𝑉𝑐1 (34)
𝐷𝑠2 −3𝐷𝑠 +1 𝑠𝑛 𝑑𝑡
𝑑𝑉𝑐1
From Fig. 5(a) and 5(b) the switched node voltage across 𝐶1 = 𝐼𝐿2 −𝐼𝑠𝑛 (35)
𝑑𝑡
the inverter bridge can be written as 𝑑𝑉𝑐2
(1−𝐷𝑠 ) 𝐶2 = 𝐼𝐿1 −𝐼𝑠𝑛 (36)
𝑉𝑠𝑛 = 𝑉𝑖𝑛 + 𝑉𝑐1 + 𝑉𝑐2 = 𝑉 (27) 𝑑𝑡
𝐷𝑠2 −3𝐷𝑠 +1 𝑖𝑛 Applying volt-seconds balance principle to the 𝐿1 and 𝐿2
The Boost factor (B) is defined as over one switching period, (37) and (38) are obtained.
𝑉𝑠𝑛 (1−𝐷𝑠 ) 𝐷
𝐵= = (28) 𝑉𝑐1 = 2 𝑠 𝑉𝑖𝑛 (37)
𝑉 𝑖𝑛 𝐷𝑠2 −3𝐷𝑠 +1 𝐷𝑠 −3𝐷𝑠 +1
1−𝐷𝑠
C. Operating Principle of the Proposed CC-qZSI 𝑉𝑐2 = 𝑉 (38)
𝐷𝑠2 −3𝐷𝑠 +1 𝑖𝑛
The proposed CC-qZSI topology equivalent circuits for Applying charge-seconds balance principle to the 𝐶1 and 𝐶2
shoot-through and non-shoot-through states are shown in Figs. over one switching period, (39) and (40) are obtained.
6(a) and (b) respectively. The voltages across the inductors are 1−𝐷
𝐼𝐿1 = 2 𝑠 𝐼𝑠𝑛 (39)
𝐷𝑠 −3𝐷𝑠 +1
𝑉𝐿1 , 𝑉𝐿2 and the currents through inductors are 𝐼𝐿1 and 𝐼𝐿2 .
(1−𝐷𝑠 )2
The current through the capacitors are 𝐼𝑐1 , 𝐼𝑐2 and the voltage 𝐼𝐿2 = 𝐼 (40)
𝐷𝑠2 −3𝐷𝑠 +1 𝑠𝑛
across the capacitors are 𝑉𝑐1 and 𝑉𝑐2 . The switching voltage From Figs. 6(a) and (b) the switched node voltage across
waveforms are shown in Fig. 6(c). the inverter bridge can be written as
VC1 VC 1 I 𝑉
- + IC1 - + C1 𝑉𝑠𝑛 = 𝑉𝑐1 + 𝑉𝑐2 = 2 𝑖𝑛 (41)
L1 C1 L2 𝐷𝑠 −3𝐷𝑠 +1
IL1 Vsn IL 1 L 1 C 1 L2
Vs n The Boost factor (B) is defined as
+ VL1 - + VL2 - + VL 1 - + VL 2 -
Vin Vi n 𝑉 1
𝐵 = 𝑠𝑛 = 2 (42)
𝑉 𝑖𝑛 𝐷𝑠 −3𝐷𝑠 +1
+ IC2 VC 2+
IC 2 Is n
VC2 The transfer characteristics of proposed CC-qZSI is shown
- C2 - C2
in Fig. 6(d). From this plot, it is clear that proposed inverter
(a) (b) gives improved boost factor as compared to the traditional
Gso DsTs (1-Ds)Ts
qZSI.
Gsi
t
Vso Vc2 D. Passive Components Design
t
Vin +Vc1+Vc2 In three-phase ZSI/qZSI, the capacitors and inductors are
VL1 t
Vin -Vc2 designed to limit the ripple voltage and switching frequency
Vsn Vc1+Vc2 current ripple. Thus, for the proposed three-phase CC-qZSI, the
Vc2 t inductors and capacitors are obtained as follows:
VL2 t
-Vc1
𝐷𝑠 𝑉 𝐿𝑖
(c) (d) 𝐿𝑖 = (43)
𝛥𝑖𝐿𝑖 % 𝐼𝐿𝑖 𝑓𝑠 𝐾𝑠ℎ 𝑡
𝐷𝑠 𝐼𝑐𝑖
Fig. 6. Operating waveforms of proposed CC-qZSI: (a) equivalent circuit in 𝐶𝑖 = (44)
shoot-through interval, (b) equivalent circuit in non-shoot-through interval, (c) 𝛥𝑉 𝑐𝑖 % 𝑉 𝑐𝑖 𝑓𝑠 𝐾𝑠ℎ 𝑡
key voltage waveforms, and (d) transfer characteristics.
where i =1and 2. 𝑉𝐿1 and 𝑉𝐿2 are the voltages across the
1) Shoot-through interval inductors 𝐿1 and 𝐿2 , 𝐼𝐿1 and 𝐼𝐿2 are the currents flowing
In this mode of operation, the diodes 𝐷1 and 𝐷2 are reverse through 𝐿1 and 𝐿2 , ∆𝑖𝐿1 and ∆𝑖𝐿2 represent percentage ripple
biased as shown in Fig. 6(a). The inductor currents 𝐼𝐿1 and currents in 𝐿1 and 𝐿2 during shoot-through interval 𝐷𝑠 . 𝑉𝑐1
𝐼𝐿2 built-up-to maximum value through the capacitor 𝐶1 and and 𝑉𝑐2 are the voltages across the capacitors 𝐶1 and 𝐶2 ,
𝐶2 . The inductor voltages and capacitor currents are given as 𝐼𝑐1 and 𝐼𝑐2 are the currents flowing through 𝐶1 and 𝐶2 . ∆𝑉𝑐1
follows: and ∆𝑉𝑐2 represent percentage ripple voltages in 𝐶1 and 𝐶2
𝑑𝑖𝐿1
𝐿1 = 𝑉𝑖𝑛 + 𝑉𝑐1 +𝑉𝑐2 (29) during 𝐷𝑠 . 𝑓𝑠 is the switching frequency and 𝐾𝑠ℎ𝑡 is a
𝑑𝑡
𝑑𝑖𝐿2 coefficient factor, which is equal to the number of shoot-
𝐿2 = 𝑉𝑐2 (30)
𝑑𝑡 through intervals in one switching cycle. The corresponding
𝑑𝑉𝑐1
𝐶1 = −𝐼𝐿1 (31) voltage and current expressions of capacitors and inductors are
𝑑𝑡
given as follows:

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5

𝐷𝑠2 −3𝐷𝑠 +2 topologies are given in Table I and Table II respectively. The
𝑉𝐿1 = 𝑉
𝐷𝑠2 −3𝐷𝑠 +1 𝑖𝑛 proposed SB-ZSI and CC-qZSI has same boost factor, where as
1−𝐷𝑠
𝑉𝐿2 = 𝑉 the DC-qZSI has comparatively lower boost factor. The
𝐷 2 −3𝐷 +1 𝑖𝑛
𝑠 𝑠
𝑃𝑜 capacitor voltage stress of CC-qZSI has lower than SB-ZSI
𝐼𝐿1 = with continuous input current. The switch current stress of the
𝑉 𝑖𝑛
1−𝐷𝑠 𝑃𝑜 SB-ZSI is higher than the DC-qZSI and CC-qZSI. Therefore,
𝐼𝐿2 =
𝑉 𝑖𝑛 CC-qZSI is used in comparative analysis, simulation and
𝐷𝑠
(45)
𝑉𝑐1 = 𝑉𝑖𝑛 experimentally verifications.
𝐷𝑠2 −3𝐷𝑠 +1
1−𝐷𝑠
𝑉𝑐2 = 𝑉 TABLE I
𝐷𝑠2 −3𝐷𝑠 +1 𝑖𝑛
VOLTAGE STRESSES OF THE ELEMENTS IN PROPOSED INVERTERS
𝑃
𝐼𝐶1 = 𝑜
𝑉 𝑖𝑛 SB-ZSI DC-qZSI CC-qZSI
(2−𝐷𝑠 )𝑃𝑜
𝐼𝐶2 = 𝐷𝑠
𝑉 𝑖𝑛
𝐶1 (1 − 𝐷𝑠 )2 𝐷𝑠 (1 − 𝐷𝑠 )
𝑉 𝑉 𝑉
where 𝑃𝑜 is the output power. By substituting (45) in (43) and 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛
(44), the inductances and capacitances can be obtained as (1 − 𝐷𝑠 ) 𝐷𝑠 (1 − 𝐷𝑠 )
𝐶2 𝑉 𝑉 𝑉
follows: 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛
𝐷𝑠 𝐷𝑠2 −3𝐷𝑠 +2
𝐿1 = 𝑉2 (46) 1 (1 − 𝐷𝑠 ) 1
𝑃𝑜 𝑓𝑠 𝐾𝑠ℎ 𝑡 𝛥𝐼𝐿1 % 𝐷𝑠2 −3𝐷𝑠 +1 𝑖𝑛 𝐷1 − 𝑉 − 𝑉 − 𝑉
𝐷𝑠 1 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛
𝐿2 = 𝑉2 (47)
𝑃 𝑓 𝐾 𝛥𝐼 % 𝐷 2 −3𝐷 +1 𝑖𝑛
𝑜 𝑠 𝑠ℎ 𝑡 𝐿2 𝑠 𝑠 (1 − 𝐷𝑠 ) 𝐷𝑠 (1 − 𝐷𝑠 )
𝑃𝑜 𝐷𝑠2 −3𝐷𝑠 +1
𝐷2 − 𝑉 − 𝑉 − 𝑉
𝐶1 = (48) 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛
𝑓𝑠 𝐾𝑠ℎ 𝑡 𝛥𝑉𝑐1 % 2
𝑉𝑖𝑛
𝑃𝑜 (2−𝐷𝑠 )𝐷𝑠 𝐷𝑠2 −3𝐷𝑠 +1 (1 − 𝐷𝑠 ) 𝐷𝑠 (1 − 𝐷𝑠 )
𝑆𝑜 𝑉 𝑉 𝑉
𝐶2 = 2 (49) 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛
𝑓𝑠 𝐾𝑠ℎ 𝑡 𝛥𝑉𝑐2 % (1−𝐷𝑠 )𝑉𝑖𝑛
1 (1 − 𝐷𝑠 ) 1
𝑆𝑖 𝑉 𝑉 𝑉
In order to operate the inverter in continuous conduction 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑖𝑛
mode, the minimum inductor currents (𝐼𝐿𝑖_𝑚𝑖𝑛 ) should be
greater than 0. This is equal to the peak value of the phase TABLE II
CURRENT STRESSES OF THE ELEMENTS IN PROPOSED INVERTERS
current (𝐼𝑎𝑛 ). Mathematically, it is written as,
1 SB-ZSI DC-qZSI CC-qZSI
𝐼𝐿𝑖_𝑚𝑖𝑛 = 𝐼𝐿𝑖 − ∆𝑖𝐿𝑖 ≥ 𝐼𝑎𝑛 (50)
2
By putting the value of inductor currents 𝐼𝐿1 and ∆𝑖𝐿𝑖 in (50), 1 − 𝐷𝑠 (1 − 𝐷𝑠 ) (1 − 𝐷𝑠 )
𝐿1 𝐼 𝐼 𝐼
following is obtained 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛
3𝑉𝑎𝑛 𝐼𝑎𝑛 𝐶𝑜𝑠ø 𝑉𝑐1 𝐷𝑠
− ≥ 𝐼𝑎𝑛 (51) 𝐿2 𝐷𝑠2 − 3𝐷𝑠 + 2 (1 − 𝐷𝑠 )2 𝐷𝑠2 − 2𝐷𝑠 + 1
𝑉 𝑖𝑛 2𝐿1 𝐼𝐿1 𝐾𝑠𝑡 ℎ 𝑓𝑠 𝐼 𝐼 𝐼
𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛 𝐷𝑠2− 3𝐷𝑠 + 1 𝑠𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛
After simplification of the (51), the critical inductances 𝐿1𝑐 of
the inductor 𝐿1 is obtained as 1 1 1
𝐷1 𝐼 𝐼 𝐼
𝑉𝑐1 𝐷𝑠 𝑉 𝑖𝑛 𝑍𝑎𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛
𝐿1𝑐 ≥ (52)
2𝑉𝑎𝑛 𝐼𝐿1 𝐾𝑠𝑡 ℎ 𝑓𝑠 (3𝑉𝑎𝑛 𝑐𝑜𝑠 ø−𝑉 𝑖𝑛 )
𝐷2 𝐷𝑠2 − 3𝐷𝑠 + 2 (1 − 𝐷𝑠 ) (1 − 𝐷𝑠 )
where 𝑍𝑎𝑛 = 𝑅𝐿 + 𝑗𝑋𝐿 , 𝑅𝐿 is the resistive load per phase, 𝑋𝐿 𝐼 𝐼 𝐼
𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛
is inductive load per phase, and 𝑐𝑜𝑠ø is power factor of the
𝑆𝑜 𝐷𝑠2 − 3𝐷𝑠 + 2 (1 − 𝐷𝑠 ) (1 − 𝐷𝑠 )
load. Similarly, for inductor 𝐿2 , the critical inductances 𝐿2𝑐 is 𝐼 𝐼
𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛
𝐼
𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛
𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛
calculated as
𝑉𝑐1 𝐷𝑠 𝑉 𝑖𝑛 𝑍𝑎𝑛 𝑆𝑖 𝐷𝑠2 − 4𝐷𝑠 + 3 𝐷𝑠2 − 3𝐷𝑠 + 2 𝐷𝑠2 − 3𝐷𝑠 + 2
𝐿2𝑐 ≥ (53) 𝐼 𝐼 𝐼
2𝑉𝑎𝑛 𝐼𝐿2 𝐾𝑠𝑡 ℎ 𝑓𝑠 (3(1−𝐷𝑠 )𝑉𝑎𝑛 𝑐𝑜𝑠 ø−𝑉 𝑖𝑛 ) 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛 𝐷𝑠2 − 3𝐷𝑠 + 1 𝑠𝑛

It is important to mention that for single-phase system, both

high frequency and low frequency ripples (double line
frequency) are present. However, in three-phase system, the
double line frequency ripples do not exist. Therefore, in order
to reduce peak-to-peak ripple, dominated by double line
frequency ripples, higher values of passive components are
required in single-phase case as compared to three-phase case.
Thus, for the proposed three-phase inverter, lesser value of
capacitors and inductors are required as compared to single-
phase case.
E. Voltage and Current Stress
The voltage and current stresses of the proposed ZSI
III. PWM CONTROL TECHNIQUE
To verify the operation of the proposed three-phase
continuous input current qZSI (CC-qZSI), the PWM control
technique discussed in [27] is used as shown in Fig. 7. Fig.
7(a) shows the analog representation of PWM generation. Fig.
7(b) shows the PWM waveforms in which the high-frequency
triangular waveform (Vtri) is compared with two shoot-through
signals (𝑉𝑝𝑡 ℎ and 𝑉𝑛𝑡 ℎ ) and three reference sinusoidal signals
(𝑉𝑎 , 𝑉𝑏 , and 𝑉𝑐 ). The two shoot-through signals are equal in
magnitude but opposite in polarity. The constraint of shoot-
through duty cycle (𝐷𝑠 ) and modulation index (M) is given as:
𝐷𝑠 + 𝑀 ≤ 1 (54)

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2018.2823379, IEEE Journal
of Emerging and Selected Topics in Power Electronics
6

The peak ac gain factor (𝐺) is given as higher than the proposed CC-qZSI. Higher number of
𝑉 𝑀 inductors are used in the [25], [26], and [29] as compared to
𝐺= 𝑜 = 2 (55)
𝑉 𝑖𝑛 𝐷𝑠 −3𝐷𝑠 +1
the proposed CC-qZSI. However, [21] has less passive
components but has low boost factor in comparison to the
From the constraint (54), it is clear that the gain is depended proposed CC-qZSI. Inverter discussed in [19] has lower boost
upon the M and DS. Fig. 7(c) shows a plot of G versus DS and factor compared to the proposed CC-qZSI and switched
M. It may also be observed from Fig. 7 (c) that the maximum inverter reported in [27] has identical boost factor as that of
operating value of Ds and M is governed by 𝐷𝑠 + 𝑀 ≤ 1. the CC-qZSI but has two additional diodes. High gain inverter
The output phase voltage (rms) is given by discussed in [42] has higher boost factor with same number of
𝑀𝐵 𝑉 𝑖𝑛
𝑉𝑎𝑛 = 𝑉𝑏𝑛 = 𝑉𝑐𝑛 = (56) components count. However, inverter discussed in [42] is
2 2
The output line voltage (rms) is given as analyzed for single-phase system.
𝑀𝐵𝑉 𝑖𝑛 3
𝑉𝑎𝑏 = 𝑉𝑏𝑐 = 𝑉𝑐𝑎 = (57) TABLE III
2 2
COMPARASION OF THE PROPOSED CC-QZSI WITH OTHERS ZSIS
Va (t)
AND
OR Gs1 Reference Sw. Di. L C B G
Vb (t)
AND
OR Gs3 Proposed 1 𝑀
CC-qZSI 7 2 2 2
Vc (t)
𝐷𝑠2 − 3𝐷𝑠 + 1 𝑀2 + 𝑀 − 1
AND
OR Gs5
qZSI 1 𝑀
Vtri (t)
[19] 6 1 2 2
AND
OR Gs4 1 − 2𝐷𝑠 2𝑀 − 1
qSBI 1 𝑀
OR Gs6
[21] 7 2 1 1
AND
1 − 2𝐷𝑠 2𝑀 − 1
OR Gs2
SL-qZSI 1 + 𝐷𝑠 2𝑀 − 𝑀2
AND
[25] 6 4 3 2
Vpst 1 − 2𝐷𝑠 − 𝐷𝑠2 4𝑀 − 𝑀2 − 2
Gso
Vnst
NAND
cSL-qZSI 1 𝑀
[26] 6 7 4 2
1 − 3𝐷𝑠 3𝑀 − 2
(a) (b) SB-ZSI 1 𝑀
[27] 7 4 2 2
1 − 3𝐷𝑠 + 𝐷𝑠2 𝑀2 + 𝑀 − 1
E-boost 1 1
[29] 6 3 3 3
2𝐷𝑠2 − 3𝐷𝑠 + 1 2𝑀 − 1
ASL/SL- 1 + 𝐷𝑠 2𝑀 − 𝑀2
qZSI[30] 7 5 2 1
1 − 3𝐷𝑠 3𝑀 − 2
HG-qSBI 1 𝑀
[42] 7 2 2 2
2𝐷𝑠2 − 4𝐷𝑠 + 1 2𝑀2 − 1
Sw. = Switches for 3-phase system, Di. = Diodes, L=Inductor, C=Capacitor

B. Voltage and Current Stress

(b)
Fig.7. Behavior of modulation and duty cycle (a) analog model of PWM
generation (b) PWM waveform for switches and (c) relation among G, M and
Ds.
IV. COMPARATIVE ANALYSIS
In this section, the detailed comparative analysis is
performed in terms of components count, voltage gain, cost
function, power loss, efficiency, voltage stress, and current
stress of the proposed CC-qZSI with other conventional ZSIs.
As the proposed inverter is a transformer less continuous input
current quasi Z source inverter (CC-qZSI). Therefore, to make
fair comparison, only transformer less continuous input
current profile based ZSIs are considered and ripple input
current profile inverters as well as discontinuous input current
based ZSIs are not taken in to account.
A. Components Count and Gain
Table III shows the comparison of components count and
boost factor among the proposed inverter and the conventional
ZSIs. From Table III, it is clear that the number of diodes used
in the literature [25]-[27], [29], and [30] are comparatively
The voltage and current expressions of the components are
given in the Table IV. The voltage stress is defined as the ratio
of voltage across the switch to G.𝑉𝑖𝑛 [28]. The total capacitor
voltage, diode voltage, switch voltage, diode current, and
switch current stresses are analyzed as shown in Fig. 8. Fig.
8(a) shows the comparative analysis of boost factor (B) with
the variations in shoot-through duty cycle (Ds). From Fig. 8(a),
it is clear that inverters reported in [26], [30] and [42] have
higher boost factor but [26] has two more inductors and five
more diodes as compared to CC-qZSI. Inverter reported in
[30] has three additional diodes as compared to CC-qZSI but
saves one capacitor. It can be observed from Figs. 8(b) and (c)
that the capacitors and diode voltage stresses, of the proposed
CC-qZSI is less. However, total switch voltage stress of [21],
[27], and [30] is higher than proposed CC-qZSI as shown in
Fig. 8(d). From Fig. 8(e), it is clear that the proposed CC-qZSI
has least total switch current stress as compared to other ZSIs.
The total diode current stress of the proposed CC-qZSI is
lesser as shown in Fig. 8(f) as compared to [25]-[27], [30].
Literature [42] has highest voltage gain which makes total
capacitor voltage stress lesser than the CC-qZSI. However,
diode voltage, switch voltage, and diode current stresses are

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of Emerging and Selected Topics in Power Electronics
7

TABLE IV
COMPARASION OF VOLATGE AND CURRENT EXPRESSIONS WITH OTHERS Z- SOURCE INVERTERS
Attributes Proposed qZSI qSBI SL-qZSI cSL-qZSI SB-ZSI E-boost ZSI ASL/SL- HG-qSBI
qZSI [30]
CC-qZSI [19] [21] [25] [26] [27] [29] [42]

𝑉𝑐1 /𝑉𝑖𝑛 𝐷𝑠 𝐵 (𝐵 + 1) 𝐵 2𝐷𝑠 𝐵 (1 − 𝐷𝑠 )𝐵 𝐵 𝐷𝑠 𝐵 𝐵 (1 − 𝐷𝑠 )𝐵

2 (1 + 𝐷𝑠 ) (1 + 𝐷𝑠 )
𝑉𝑐2 /𝑉𝑖𝑛 (1 − 𝐷𝑠 )𝐵 (𝐵 + 1) NA (1 − 𝐷𝑠 )𝐵 2𝐷𝑠 𝐵 𝐷𝑠 𝐵 𝐷𝑠 𝐵 NA 𝐷𝑠 𝐵
2 (1 + 𝐷𝑠 ) (1 + 𝐷𝑠 )
𝑉𝑐3 /𝑉𝑖𝑛 NA NA NA NA NA NA (1 − 2𝐷𝑠 )𝐵 NA NA
𝐼𝐿1 /𝑖𝑠𝑛 (1 − 𝐷𝑠 )𝐵 (𝐵 + 1) (𝐵 + 1) (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )2 𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵
2 2 (1 + 𝐷𝑠 )
𝐼𝐿2 /𝑖𝑠𝑛 (1 − 𝐷𝑠 )2 𝐵 (𝐵 + 1) NA (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )2 𝐵 (1 − 𝐷𝑠 )2 𝐵 (1 − 𝐷𝑠 )𝐵 1 − 3𝐷𝑠 + 2𝐷𝑠2 𝐵
2 (1 + 𝐷𝑠 ) (1 + 𝐷𝑠 )
𝐼𝐿3 /𝑖𝑠𝑛 NA NA NA (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 NA (1 − 𝐷𝑠 )𝐵 NA NA
(1 + 𝐷𝑠 )
𝐼𝐿4 /𝑖𝑠𝑛 NA NA NA NA (1 − 𝐷𝑠 )𝐵 NA NA NA NA
𝑖𝐷1 /𝑖𝑠𝑛 𝐵 𝐵 (𝐵 + 1) 𝐵 (1 + 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )2 𝐵 (1 − 𝐷𝑠 )𝐵 𝐵
2 (1 + 𝐷𝑠 )
𝑖𝐷2 /𝑖𝑠𝑛 (1 − 𝐷𝑠 )𝐵 NA (𝐵 − 1) (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 𝐷𝑠 (2 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵
2 (1 + 𝐷𝑠 ) (1 + 𝐷𝑠 )
𝑖𝐷3 /𝑖𝑠𝑛 NA NA NA (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 NA
(1 + 𝐷𝑠 ) (1 + 𝐷𝑠 )
𝑖𝐷4 /𝑖𝑠𝑛 NA NA NA (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 NA 2𝐷𝑠 𝐵 NA
(1 + 𝐷𝑠 ) (1 + 𝐷𝑠 )
𝑖𝐷5 /𝑖𝑠𝑛 NA NA NA NA (1 − 𝐷𝑠 )𝐵 NA NA (1 − 𝐷𝑠 )𝐵 NA
(1 + 𝐷𝑠 )
𝑖𝐷6 /𝑖𝑠𝑛 NA NA NA NA (1 − 𝐷𝑠 )𝐵 NA NA NA NA
𝑖𝐷7 /𝑖𝑠𝑛 NA NA NA NA (1 − 𝐷𝑠 )𝐵 NA NA NA NA
𝑣𝐷1 /𝑉𝑖𝑛 −𝐵 −𝐵 −𝐵 −𝐵 −2𝐵 −𝐵 −𝐵 2𝐷𝑠 𝐵 −𝐵
−
(1 + 𝐷𝑠 )
𝑣𝐷2 /𝑉𝑖𝑛 −𝐵(1 − 𝐷𝑠 ) NA −𝐵 (1 − 𝐷𝑠 )𝐵 (1 − 𝐷𝑠 )𝐵 −𝐵 −(1 − 2𝐷𝑠 )𝐵 2𝐷𝑠 𝐵 −𝐵(1 − 𝐷𝑠 )
− − −
(1 + 𝐷𝑠 ) (1 + 𝐷𝑠 ) (1 + 𝐷𝑠 )
𝑣𝐷3 /𝑉𝑖𝑛 NA NA NA 𝐷𝑠 𝐵 −𝐵(1 − 𝐷𝑠 ) −𝐵(1 − 𝐷𝑠 ) −𝐷𝑠 𝐵 2(1 − 𝐷𝑠 )𝐵 NA
− −
(1 + 𝐷𝑠 ) (1 + 𝐷𝑠 )
𝑣𝐷4 /𝑉𝑖𝑛 NA NA NA 𝐷𝑠 𝐵 𝐷𝑠 (1 + 2𝐷𝑠2 )𝐵 −𝐵𝐷𝑠 NA −𝐵 NA
− −
(1 + 𝐷𝑠 ) (1 + 𝐷𝑠 )
𝑣𝐷5 /𝑉𝑖𝑛 NA NA NA NA 2𝐷𝑠 𝐵 NA NA −𝐵 NA
−
(1 + 𝐷𝑠 )
𝑣𝐷6 /𝑉𝑖𝑛 NA NA NA NA −𝐵(1 − 𝐷𝑠 ) NA NA NA NA
𝑣𝐷7 /𝑉𝑖𝑛 NA NA NA NA 2𝐷𝑠 𝐵 NA NA NA NA
−
(1 + 𝐷𝑠 )
𝑣𝑠𝑜 /𝑉𝑖𝑛 (1 − 𝐷𝑠 )𝐵 NA 𝐵 NA NA 𝐵 NA 𝐵 (1 − 𝐷𝑠 )𝐵
𝑖𝑠𝑜 𝐼𝐿1 NA 𝐼𝐿1 NA NA 𝐼𝐿1 NA 2𝐼𝐿1 𝐼𝐿1
𝑖𝑠𝑛 𝐼𝐿1 + 𝐼𝐿2 2𝐼𝐿1 𝐼𝐿1 𝐼𝐿1 + 𝐼𝐿2 + 𝐼𝐿3 2𝐼𝐿1 + 2𝐼𝐿3 𝐼𝐿1 + 𝐼𝐿2 𝐼𝐿1 + 𝐼𝐿2 + 𝐼𝐿3 2𝐼𝐿1 𝐼𝐿1 + 𝐼𝐿2

comparable but have higher switch current stress as compared The magnetic energy stored in the inductor and the stored
to CC-qZSI. energy in the capacitor is defined as 𝐸𝐿𝑊 and 𝐸𝐶𝑊
respectively.
C. Stored Energy Analysis and Reliability 2
𝑁 𝐿𝑖 𝐼𝑎𝑣𝑖
In this section, the stored energy in passive elements is The stored energy in the inductors 𝐸𝐿𝑊 = 𝑖=0 2 (58)
discussed for determining the size, weight, and cost estimation 𝐶𝑖 𝑉𝑐𝑖2
of the inverters [37]-[38]. The cost and volume of the system The stored energy in the capacitors 𝐸𝐶𝑊 = 𝑁 𝑖=0 2 (59)
increase linearly with the stored energy. However, for where N is number of inductors and Iav is the average inductor
switching elements cost function also depends upon the current. The stored energies in the conventional qZSI are
voltage and current stresses of the active elements. The calculated using:
expressions for the stored electrostatic and magnetic energies 𝑃𝑜 𝐷𝑠 (1−𝐷𝑠 )
𝐸𝐿𝑊 = (60)
are calculated assuming that the passive components are the 𝑓𝑠 𝐾𝑠ℎ 𝑡 𝛥𝐼𝐿 % (1−2𝐷𝑠 )
𝑃𝑜 𝐷𝑠
ideal and same amount of ripple is considered for all the 𝐸𝐶𝑊 = (61)
2𝑓𝑠 𝐾𝑠ℎ 𝑡 𝛥𝑉𝑐 % (1−2𝐷𝑠 )
analysis.

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of Emerging and Selected Topics in Power Electronics
8

(a) (b)
Fig.9. Comparative analysis of stored energy.

where n is the number of devices (switches and diodes),

𝐼𝑛 _𝑎𝑣 and 𝐼𝑛 _𝑝𝑘 are the average and peak current flowing
through the device, respectively, and 𝑉𝑛 is the peak voltage
across the devices. Thus, for conventional qZSI, the SDPs are
calculated as follows:

1+2𝐷𝑠 8
(c) (d) (𝑆𝐷𝑃)𝑎𝑣 = 𝑃 + 𝑃 (66)
1−2𝐷𝑠 𝑜 𝐶𝑜𝑠ø𝜋 𝑜
1
𝑆𝐷𝑃 𝑝𝑘 = 𝑃𝑜
1−𝐷𝑠 1−2𝐷𝑠
8 4 4
+ max 𝑃 ,( 𝑃 + 𝑃) (67)
𝑀𝐶𝑜𝑠 ø 𝑜 𝑀𝐶𝑜𝑠 ø 𝑜 1−2𝐷𝑠 𝑜

For the proposed CC-qZSI, the SDPs are obtained as follows:

2−4𝐷𝑠2 +2𝐷𝑠3 8
(𝑆𝐷𝑃)𝑎𝑣 = 𝑃 + 𝑃 (68)
(e) (f) 1−3𝐷𝑠 +𝐷𝑠2 𝑜 𝐶𝑜𝑠ø𝜋 𝑜
Fig. 8. Comparative analysis: (a) boost factor variation with Ds, (b) capacitor 2−2𝐷𝑠 +𝐷𝑠3
(𝑆𝐷𝑃)𝑝𝑘 = 𝑃
voltage stress, (c) diode voltage stress, (d) switch voltage stress, (e) switch 1−𝐷𝑠 (1−3𝐷𝑠 +𝐷𝑠2 ) 𝑜
current stress, and (f) diode current stress. 8 4 4−2𝐷𝑠
+ max 𝑃 ,( 𝑃 + 𝑃) (69)
𝑀𝐶𝑜𝑠 ø 𝑜 𝑀𝐶𝑜𝑠 ø 𝑜 1−3𝐷𝑠 +𝐷𝑠2 𝑜

5𝐵+4
where 𝐷𝑠 = 1.5 − . The total stored energy (𝐸𝐿𝑊 +
4𝐵
𝐸𝐶𝑊 ) of the proposed inverter is compared with the
conventional qZSI as shown in Fig. 9. It can be observed from
Fig. 9 that the proposed inverter requires lesser stored energy
when B >1.8 for 0.5 kW power output. However, for 1 kW
output power, the conventional qZSI is suited for B < 1.75. It
is also clear from Fig. 9 that the proposed inverter require
lesser stored energy when operating at B =1.75 for 1kW power
rating. In this way, it can be concluded that for higher power
rating, the proposed inverter is suitable as it significantly saves
size, weight, and cost of the passive elements.
The cost function depends both on passive elements as well
as active elements. The passive components are analyzed by
the stored energy analysis. However, for active elements cost
function depends upon the voltage and current stresses of
these elements. So, for cost analysis of active elements, the
switch device power (SDP) analysis is carried out. The SDP of
switching elements is expressed as the product of voltage and
current stresses. The total SDP of an inverter is defined as the
aggregate of SDP of all the switching devices used in the
circuit [41]. The total SDP is a measure of the total switching
devices. Thus, SDP is an important cost indicator of active
elements used in the inverter. The SDP analyses of the active
elements are given below.
Total Average SDP = (𝑆𝐷𝑃)𝑎𝑣 = 𝑛1 𝑉𝑛 𝐼𝑛 _𝑎𝑣 (64)
and Total Peak SDP = (𝑆𝐷𝑃)𝑝𝑘 = 𝑛1 𝑉𝑛 𝐼𝑛 _𝑝𝑘 (65)
(𝑆𝐷𝑃 )
The analysis of the
𝑃𝑜
ratio of both peak as well as average
value with respect to the boost factor (B) is shown in Fig. 10.
It is clear from Fig. 10 that the SDP requirement is reduced
when power factor increases linearly. From the analysis it is
clear that the proposed CC-qZSI has less peak SDP to Po ratio
as compared to conventional qZSI when operating at B ≥ 2.
Further, for operating around B = 4, the proposed CC-qZSI
requires less average SDP to Po ratio as compared to
conventional qZSI. So, the proposed CC-qZSI is beneficial
when operating at the boost factor (B) higher than 2 as
compared to the conventional qZSI.
The shoot-through problem caused due to misgating
because of EMI noises is the one of the major threats to the
reliability of the classical voltage source inverters. As the
proposed ZSIs has inherent shoot through ability, misgating
problem is addressed in it similar to the classical ZSI. The
reliability of the inverter depends on many factors, such as
voltage stress, power rating, and temperature [39]. As, the
proposed inverter has lesser voltage and current stresses, lesser
stored energy in passive components, its reliability increases.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2018.2823379, IEEE Journal
of Emerging and Selected Topics in Power Electronics
9

(a) (b)

(a) (b) Fig. 11. Power loss and efficiency analysis (a) power loss distributions and (b)
efficiency.

V. EXTENSION FOR ENHANCE BOOST CAPABILITY

The boost capability of the proposed CC-qZSI is further
extendable (n-stage) as shown in Fig.12. By extending the
proposed CC-qZSI to n- number of stages, the boost capability
can further be increased. It can be observed from Fig. 12 that
two capacitors (C1 and C2), diode (D1), and inductor (L2) form
(c) (d) one cell and n- number of such cells can be connected in
Fig. 10. Switch device power (SDP) comparative analysis (a) peak SDP cascade and thus, even higher boost factor can be achieved.
variation at pf = 0.7 (b) peak SDP variation at pf = 1.0 (c) average SDP The operation of the extended CC-qZSI is similar to the basic
variation at pf = 0.7 (d) average SDP variation at pf = 1.0 CC-qZSI, which is discussed in section II C. In the shoot-
through interval all the diodes are in non-conduction modes.
All the diodes conduct in non-shoot-though mode. A brief
D. Power Loss and Efficiency
discussion about the n-stage CC-qZSI is as follows:
For the power loss analysis the parameters are defined as 1)
The capacitor voltages are obtained by applying volt-
on-state resistance of active switch is 𝑟𝑠 and forward voltage
seconds balance principle to the 𝐿1 , 𝐿2 ,…… 𝐿𝑛+1 over one
drop is 𝑉𝐹𝑆 , 2) series resistance of the diode is 𝑟𝐷 and forward
switching period.
voltage drop is 𝑉𝐹𝐷 , and 3) the resistances of inductors and 𝐷𝑠 𝑉 𝑖𝑛
capacitors are represented by 𝑟𝐿 and 𝑟𝐶 , respectively. In this 𝑉𝑐1 = 𝑉𝑐3 = 𝑉𝑐(2𝑛−1) = (70)
𝑛𝐷 𝑠2 −(𝑛+2)𝐷𝑠 +1
work, the power loss calculation method discussed in [40], 𝐷𝑠 𝑉 𝑖𝑛
𝑉𝑐4 = 𝑉𝑐6 = 𝑉𝑐(2𝑛) = (71)
[41] is used for components power loss calculations. The 𝑛𝐷 𝑠2 −(𝑛+2)𝐷𝑠 +1
(1−𝑛𝐷𝑠 )𝑉 𝑖𝑛
power loss of proposed CC-qZSI and conventional qZSI are 𝑉𝑐2 = (72)
𝑛𝐷 𝑠2 −(𝑛+2)𝐷𝑠 +1
calculated for the parameters given in Table V for V in= 65 V
and boost factor B = 5.26. It is clear from Fig. 11 that 𝑉𝑠𝑛 = 𝑉𝑐2 + {𝑉𝑐1 + 𝑉𝑐3 + ⋯ . +𝑉𝑐 2𝑛−1 } (73)
conduction losses are maximum and capacitor losses are
minimum. The conduction and switching losses are lesser in 𝑉𝑠𝑛 depends upon the extended capacitor voltages as shown
the proposed cc-qZSI as compared to conventional qZSI. It is in Fig. 12. Voltage 𝑉𝑐1 = 𝑉𝑐3 and 𝑉𝑐4 = 𝑉𝑐6 as is clear from
clear from Fig. 11 (a) that the total power loss of the (70) and (71). The boost factor (B) for n-stage CC-qZSI can
conventional qZSI is 53.5W and the total power loss of the be written as follows.
proposed inverter is 45 W. 𝑉𝑠𝑛 1
𝐵= = (74)
Fig. 11(b) shows the calculated efficiency at different 𝑉 𝑖𝑛 𝑛𝐷 𝑠2 −(𝑛+2)𝐷𝑠 +1

operating output power loads for 65 V input. From Fig. 11(b), For two extensions ( n = 2) Boost factor (B) is given as
it is clear that the proposed inverter has maximum efficiency 1
Boost factor (B) = (75)
of 90.6 %, whereas the conventional qZSI has maximum 2𝐷𝑠2 −4𝐷𝑠 +1

efficiency of 89.1%. This shows that the proposed inverter has From (75) it is clear that the extendable CC-qZSI is capable
higher efficiency than the conventional qZSI. of giving even higher boost factor.

TABLE V n=1 n=2 nth

COMPONENTS PARAMETERS FOR POWER LOSS CALCULATIONS C
- 1+
C
- 3+
C2n-1
- +
L1 D1 L2 D3 L3 Dn+1 Ln+1
Components Specification
+
+ Gs1 Gs3 Gs5
-
Switches (FGH75T65SQD) 𝑉𝐹𝑆 = 1.1V , 𝑟𝑆 = 138mΩ Vin - C4 C2n S1
a
S3
b
S5
Vsn c
Diodes (40EPF06) 𝑉𝐹𝐷 = 0.85V , 𝑟𝐷 = 112mΩ +
Gso - C2 Gs4 Gs6 Gs2
ESR of C1 and C2 𝑟𝐶1 = 125mΩ, 𝑟𝐶2 = 61mΩ, So S4 S6 S2

Parasitic resistance of L1 and L2 𝑟𝐿1 =150mΩ, 𝑟𝐿2 = 155mΩ D2

Fig. 12. Proposed extended CC-qZSI.
Boost Factor(B) 5.26
Power rating 500W

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of Emerging and Selected Topics in Power Electronics
10

VI. SIMULATION STUDIES 𝑮𝒔𝟏

𝑮𝒔𝟓
The proposed CC-qZSI is designed for 𝐷𝑠 = 0.3 and M= 0.7 𝑮𝒔𝟒
using PSIM 10.0. The frequency of reference sinusoidal signal 𝑮𝒔𝟐
is 50 Hz and the frequency of carrier triangular waveform is
𝑮𝒔𝟑
10 kHz. The capacitors (𝐶1 , 𝐶2 ) values are 470 𝜇𝐹 and
𝑮𝒔𝒐
690 𝜇𝐹; inductor values are 𝐿1 = 0.81 mH, 𝐿2 = 0.85 mH; and
per phase resistive load is 43 Ω. The ac filter inductors and 𝑮𝒔𝟔
capacitors per phase values are 1 mH and 10 µF, respectively.
The simulated waveforms are given in Fig. 13. The proposed (a) (b)
CC-qZSI gives 𝑉𝑐1 =102.8 V, 𝑉𝑐2 = 239.5 V; line output Fig.15. PWM signals at 𝐷𝑠 = 0.3 and M = 0.7: (a) gating signal to switches
voltage (𝑉𝑎𝑏 = 𝑉𝑏𝑐 = 𝑉𝑐𝑎 ) = 416V (pk-pk); phase output S1, S3, S4, and S6 and (b) gating signal to switches S5, S2, and S6.
voltage (𝑉𝑎𝑛 = 𝑉𝑏𝑛 = 𝑉𝑐𝑛 ) = 244V (pk-pk); and phase output 𝑰𝑳𝟏 𝑰𝑳𝟏
current (𝐼𝑎𝑛 = 𝐼𝑏𝑛 = 𝐼𝑐𝑛 ) = 5.5A (pk-pk) for input voltage
𝑉𝑖𝑛 =65 V as shown in Fig. 13(a). The values of the boost 𝑰𝑳𝟐 𝑰𝑳𝟐
factor (B) = 5.26 and peak ac gain (𝐺) = 3.68. The diode
voltage stresses, inductor currents, and switch voltage stresses 𝑽𝒄𝟐 𝑽𝒄𝟐
are shown in Fig. 13(b). 𝑽𝒄𝟏
𝑽𝒄𝟏

(a) (b)
Fig. 16. Steady state results: (a) inductors currents and capacitor voltages of
the proposed CC-qZSI and (b) zoomed view of (a).

The voltage across switches and diodes are shown in the

Fig. 17. During non-shoot–through duty interval, the voltage
across 𝐷1 , 𝑉𝐷1 = 179.4 V and 𝐷2 , 𝑉𝐷2 = 137.6 V. The voltage
across the switches are 𝑉𝑠𝑜 = 207 V and 𝑉𝑠𝑛 = 298 V,
respectively during non-shoot-through duty interval. The
experimental output line voltages are 𝑉𝑎𝑏 = 𝑉𝑏𝑐 = 𝑉𝑐𝑎 = 396 V
(a) (b) (pk- pk) as shown in Fig. 18(a). The steady state output phase
Fig.13. Simulation results of the proposed CC-qZSI: (a) steady state capacitor voltages are shown in Fig. 18(b). It is clear from Fig. 18(b)
voltages, output line voltages, output phase voltages, and currents and (b)
voltage across the diodes, switches, and inductors current.
that the experimental phase voltages are 𝑉𝑎𝑛 = 𝑉𝑏𝑛 = 𝑉𝑐𝑛 =
206 V (pk- pk).
VII. EXPERIMENTAL VERIFICATIONS
To verify the operation of the proposed CC-qZSI, 𝑽𝒔𝒐
experimental prototype of 500W is developed and PWM
signals are generated using TMS320F28335 DSP kit. The 𝑽𝒔𝒏
experimental setup of proposed work is shown in Fig. 14. The
list of components and their attributes are given in Table V. 𝑽𝑫𝟐
Component values and other specifications are same as
discussed in the studies. The experimental waveforms of the 𝑽𝑫𝟏
PWM signal at gate terminals of the switches for 𝐷𝑠 = 0.3 and
M = 0.7 are shown in Fig. 15. The steady state operation of the
Fig.17. Switches and diodes voltages.
proposed CC-qZSI is given in Fig. 16. It is clear from Fig.
16(a) that the voltage across the capacitors 𝑉𝑐1 and 𝑉𝑐2 are
86.2 V and 215 V, respectively. Fig. 16 (b) shows the zoomed 𝑽𝒊𝒏 𝑽𝒂𝒏 𝑽𝒄𝒏 𝑽𝒃𝒏
view of the results shown in Fig. 16(a).
𝑽𝒄𝒂 𝑽𝒃𝒄 𝑽𝒂𝒃

𝑰𝒂𝒏

(a) (b)
Fig. 18. Steady state output voltages of proposed CC-qZSI (a) input voltage
Fig.14. Experimental setup of the proposed work.
with output line voltages (b) output phase current and voltages.

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of Emerging and Selected Topics in Power Electronics
The harmonics spectrum of output phase voltage is shown
in Fig. 19. It can be observed from Fig. 19 (a) that the THD of
the proposed CC-qZSI is 1.25% at a load voltage of 74.14 V.
Further, it can be observed from Fig. 19 (b) that for the same
load voltage, the THD of the conventional qZSI is 2.87%.
Thus, it is clear that the conventional qZSI has higher THD as
compared to the proposed CC-qZSI.
The efficiency analysis has also been carried out
experimentally and comparative analysis of calculated and
experimental efficiency is shown in Fig. 20. The experimental
efficiency is measured for the boost factor 5.26 and dc input
voltage of 65 V for conventional qZSI and the proposed CC-
qZSI. It is clear from Fig. 20 that the maximum efficiency of
the proposed CC-qZSI is 89.2%, whereas the maximum
efficiency of the conventional qZSI for the same input voltage
is 87.7%. However, the maximum calculated efficiency of the
proposed CC-qZSI is 90.6% and that of conventional qZSI is
89.1%. It can also be observed from Fig. 20 that if the input
voltage is increased to 90 V, the proposed CC-qZSI gives
maximum measured efficiency of 90.6%. It can be observed
from the results of Fig. 20 that the proposed CC-qZSI has
higher efficiency than the conventional qZSI for the same
input voltage.
(a) (b)
Fig. 19. Experimental harmonics spectrum (a) proposed CC-qZSI and (b)
conventional qZSI.
Fig. 20. Comparative efficiency analysis.
VIII. CONCLUSION
In this paper, three topologies of switched-boost modified
ZSIs with improved boost capability are presented. In the
proposed ZSIs, the voltage gain is increased significantly by
adding one auxiliary switch and one diode without using
additional passive components. The concept is applied to
traditional ZSI, discontinuous input current qZSI, and
continuous input current qZSI, and thus, three new three-phase
inverter topologies; SB-ZSI, DC-qZSI, and CC-qZSI are
proposed. The proposed inverters are suitable for renewable
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11
energy applications where high voltage gain is required from a
low input voltage. In order to bring out the advantages of the
proposed three-phase inverters, comparative analysis among
the proposed three-phase inverters and conventional high
voltage gain Z-source inverters regarding power losses,
efficiency, voltage and current stresses, number of elements,
THD, cost function, and reliability are carried out. The
comparative analysis shows that the proposed CC-qZSI has
higher boost factor (B) and higher efficiency with lesser
capacitor voltage and switch current stresses, as compared to
conventional qZSI. Moreover, proposed CC-qZSI has lesser
stored energy in the passive components and lesser peak SDP
to output power ratio as compared to conventional qZSI when
operating at B ≥ 2. Finally, the operation of the proposed CC-
qZSI is verified through simulation and experimental results.
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2168-6777 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2018.2823379, IEEE Journal
of Emerging and Selected Topics in Power Electronics
13

R. K. Singh (S’08-M’13-SM’16) R. Mahanty (M’15) received the B. Sc.

received B. Tech. degree in Electrical (Engg.) and M. Tech. degrees from Regional
Engineering from College of Engineering College, Jamshedpur (presently
Technology, Pantnagar, India in 2001, National Institute of Technology,
M. Tech. degree in Electrical Machines Jamshedpur), India in 1987 and 1991,
and Drives from Indian Institute of respectively. He obtained his Ph. D. degree
Technology (Banaras Hindu University), from Institute of Technology, Banaras Hindu
Varanasi, India in 2003 and Ph. D. University, (presently Indian Institute of Technology (Banaras
degree in Electrical Engineering, Indian Institute of Hindu University)), India in 2005.
Technology Kanpur, India in 2013. He is currently a Professor with the Department of
He is working as an Associate Professor in the Department of Electrical Engineering, Indian Institute of Technology
Electrical Engineering, Indian Institute of Technology (Banaras Hindu University), Varanasi, India. His research
(Banaras Hindu University), Varanasi, India since 2005. His interests include power quality improvement, multilevel
research interests include renewable power conversion for inverters, and dc-dc converters.
hybrid microgrid, power conversion for electric
vehicles/hybrid electric vehicles, optimal charging/discharging
of energy storage system, and converter modeling and control.

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