IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO.

12, DECEMBER 2007 1311

PMOS-Only Sleep Switch Dual-Threshold Voltage

Domino Logic in Sub-65-nm CMOS Technologies
Zhiyu Liu, Student Member, IEEE, and Volkan Kursun, Member, IEEE

Abstract—A circuit technique is proposed in this paper for si-

multaneously reducing the subthreshold and gate oxide leakage
power consumption in domino logic circuits. Only p–channel sleep
transistors and a dual-threshold voltage CMOS technology are uti-
lized to place an idle domino logic circuit into a low leakage state.
Sleep transistors are added to the dynamic nodes in order to re-
duce the subthreshold leakage current by strongly turning off all of
the high-threshold voltage transistors. Similarly, the sleep switches
added to the output nodes suppress the voltages across the gate in-
sulating layers of the transistors in the fan-out gates, thereby mini-
mizing the gate tunneling current. The proposed circuit technique
lowers the total leakage power by up to 77% and 97% as compared
to the standard dual-threshold voltage domino logic circuits at the
high and low die temperatures, respectively. Similarly, a 22% to
44% reduction in the total leakage power is observed as compared
to a previously published sleep switch scheme in a 45-nm CMOS
technology. The energy overhead of the circuit technique is low,
justifying the activation of the proposed sleep scheme by providing
a net savings in total energy consumption during short idle periods. Fig. 1. Comparison of the maximum gate oxide leakage current of an nMOS
transistor (V = V =V =V ) in two successive CMOS technology
Index Terms—Dynamic CMOS, electron tunneling, gate oxide generations.
tunneling, hole leakage, low-leakage sleep mode, multithreshold
voltage, subthreshold leakage current.

gate dielectric layer. The variation of the with the supply

I. INTRODUCTION
EATURE size scaling in MOSFETs requires reducing the
F supply and threshold voltages. The lowering of threshold
voltages leads to an exponential increase in the subthreshold
leakage current. Several circuit techniques based on multiple
threshold voltage (multiple ) CMOS technologies are de-
scribed in the literature for reducing the subthreshold leakage
current [1]–[6], [15], [16], [22]. The effect of these multiple
CMOS circuit techniques on the gate oxide leakage current
characteristics, however, has not been explored until recently.
In the CMOS technologies with a gate insulator thicker
than 20 , the gate oxide leakage current is orders
of magnitude smaller than the subthreshold leakage current
[8], [10]. The has, therefore, typically been
ignored in the previous CMOS technologies. is caused by
the direct tunneling of the electrons and holes through the insu-
lating gate dielectric layer. The tunneling probability of carriers
increases with the scaling of the gate oxide thickness in
each new technology generation. The tunneling probability also
has a strong dependence on the voltage difference across the
Manuscript received August 11, 2005; revised May 28, 2006. This work
was supported by a Grant from the Wisconsin Alumni Research Foundation
(WARF).
The authors are with the Department of Electrical and Computer Engi-
neering, University of Wisconsin–Madison, Madison, WI 53706-1691 USA
(e-mail: zhiyuliu@wisc.edu).
Digital Object Identifier 10.1109/TVLSI.2007.903947
1063-8210/$25.00 © 2007 IEEE
voltage in two successive CMOS technologies (45 and
65 nm) is shown in Fig. 1. While advancing from the 65-nm
technology node to the 45-nm technology node, the reduction
of by 3 increases the by up to 14.9 times depending
on the voltage difference across the gate oxide, as illustrated in
Fig. 1.
The is in the range of 12–16 in the current CMOS
technologies [7], [8], [10]. Such a thin leads to a signifi-
cant gate tunneling current. The variation of the gate oxide and
subthreshold leakage currents of an nMOS transistor with the
supply voltage at two different die temperatures is shown in
Fig. 2, assuming a 45-nm CMOS technology. At 110 C, the
is 6.7 times higher than the gate oxide leakage cur-
rent (operating at the nominal supply voltage 0.8 V) as illus-
trated in Fig. 2. Alternatively, at the room temperature, the
is 2.5 times higher than the subthreshold leakage current. Due
to the aggressive scaling of , the gate dielectric tunneling has
become a primary leakage mechanism. Particularly at the low
die temperatures during long idle periods, most of the power
consumption of a CMOS circuit could occur due to gate oxide
leakage. New circuit techniques aimed at simultaneously re-
ducing the subthreshold and gate oxide leakage currents are,
therefore, highly desirable.
A circuit technique for lowering the gate oxide leakage cur-
rent in domino logic circuits is presented in [11]. Using P-type
(predischarge) domino is proposed in order to exploit the lower
gate oxide leakage current characteristics of the pMOS tran-
sistors as compared to the nMOS transistors. The transistors
1312 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 12, DECEMBER 2007
Fig. 2. Comparison of the subthreshold and gate oxide leakage currents of an
nMOS transistor for various supply voltages at two different die temperatures.
I :V = 0 and V = V .I :V = V
V .
in a p-type domino circuit, however, must be sized larger for
achieving similar speed as compared to an n-type domino cir-
cuit. Although this technique can be effective for reducing the
leakage current, the area and active power consumption are sig-
nificantly increased.
In this paper, a new circuit technique with lower overheads
of delay and energy is proposed to reduce both the subthreshold
and gate oxide leakage currents in domino logic circuits. pMOS
sleep transistors are utilized along with a dual threshold voltage
(dual- ) CMOS technology to ensure that an idle domino cir-
cuit is placed into a low leakage state. The proposed technique
reduces the total leakage power by up to 77% and 96.9% as com-
pared to the standard dual- domino logic circuits at 110 C
and 25 C, respectively.
The paper is organized as follows. The leakage current char-
acteristics of the domino gates are described in Section II. The
new circuit technique to reduce the total leakage power con-
sumption is presented in Section III. The simulation results are
given in Section IV. Some conclusions are offered in Section V.
II. LEAKAGE CURRENT CHARACTERISTICS OF
DYNAMIC CMOS CIRCUITS
The leakage current characteristics of dynamic CMOS cir-
cuits are explored in this section. The subthreshold and gate
oxide leakage currents produced by the nMOS and pMOS
transistors are described in Section II-A. The leakage current
characteristics of the previously published sleep switch dual-
domino logic circuit techniques in the literature are discussed
in Sections II-B and II-C.
A. Comparison of Leakage Currents in n-Channel and
p-Channel Devices
The subthreshold and gate oxide leakage currents pro-
duced by the nMOS and pMOS transistors are illustrated in
Fig. 3. has four components, as shown in Fig. 3(a):
gate-to-channel tunneling current , gate-to-drain tunneling
current , gate-to-source tunneling current , and
gate-to-body tunneling current . The tunneling current
Fig. 3. Maximum gate oxide and subthreshold leakage current states in nMOS
and pMOS transistors. (a) Maximum gate oxide leakage current state. (b) Max-
imum subthreshold leakage current state.
= V =
Fig. 4. Comparison of the gate oxide leakage current produced by the same
sized nMOS and pMOS transistors for various voltages applied across the gate
insulator in a 45-nm CMOS technology. V = V =V =V .
from the gate terminal to the conducting channel is shared
between the source and drain terminals [14]. and are the
edge tunneling currents from the gate terminal to the source and
drain terminals through the gate-to-source and gate-to-drain
overlap areas, respectively. is typically several orders of
magnitude smaller than the other three components of the gate
tunneling current [9]. The highest gate oxide leakage current is
observed when a transistor operates in the active region with the
maximum voltage difference across the gate-to-source and the
gate-to-drain terminals, as illustrated in Fig. 3(a). Alternatively,
the highest subthreshold leakage current is observed when a
cutoff transistor is biased with the maximum voltage difference
between the source and drain terminals, as depicted in Fig. 3(b).
In a technology utilizing silicon-dioxide as the gate dielec-
tric material, the probability of hole tunneling is much smaller
than the probability of electron tunneling through the gate oxide
(discussed in Appendix I). The for a pMOS device is,
therefore, significantly lower as compared to an nMOS device
with the same and the same voltage difference across the
gate insulator. A comparison of the gate oxide leakage currents
produced by the n-channel and p-channel devices with similar
physical dimensions (width, length, and ) in a 45-nm CMOS
technology is shown in Fig. 4. The produced by an nMOS
transistor is up to 40 times (depending on the voltage difference
across the gate oxide) higher as compared to a pMOS transistor,
as illustrated in Fig. 4.
LIU AND KURSUN: PMOS-ONLY SLEEP SWITCH DUAL-THRESHOLD VOLTAGE DOMINO LOGIC
Fig. 5. Two-input standard dual-V domino OR gate. High-V transistors are
represented with a thick line in the channel region.
B. Dual- Domino Logic
Employing dual- transistors for subthreshold leakage cur-
rent reduction in domino logic circuits was first proposed by
Kao [3]. A two-input standard dual- domino OR gate is shown
in Fig. 5. The critical signal transitions that determine the delay
of a domino logic circuit occur along the evaluation path. In a
dual- domino circuit, therefore, all of the transistors that can
be activated during the evaluation phase have a low- . Alter-
natively, the precharge phase transitions are not critical for the
performance of a domino logic circuit. Therefore, those transis-
tors that are active during the precharge phase have a high-
[22].
Provided that all of the high- transistors are cutoff in a
dual- domino logic circuit, the subthreshold leakage current
is significantly reduced as compared to a low- circuit [5].
The clock is gated high, turning off the high- pull-up tran-
sistor when a domino logic circuit is idle. In a standard dual-
domino logic circuit, the modes of the remaining high- tran-
sistors (other than the pull-up transistors) are determined by the
input vectors applied after the clock is gated high [15].
A sleep switch technique that places an idle domino logic cir-
cuit into a low subthreshold leakage current state, regardless of
the input vectors, is presented in [15]. A high- nMOS switch
is added to the dynamic node of a domino gate as shown in
Fig. 6. The operation of this transistor is controlled by a sep-
arate sleep signal. During the standby mode of operation, the
clock signal is gated high, turning off the high- pull-up tran-
sistor of each domino gate. The sleep signal transitions high,
turning on the sleep switch. The dynamic node of the domino
gate is discharged through the sleep switch and the output node
transitions to high. Following the low-to-high transition of the
output of a sleep switch dual- domino gate, the subsequent
gates (fed by the noninverting signals) also evaluate and dis-
charge in a domino fashion. After the node voltages settle to a
steady state, all of the high- transistors are cutoff, thereby re-
ducing the subthreshold leakage current [15].
Similar subthreshold leakage current reduction techniques
based on discharging and charging the dynamic and output
nodes, respectively, of all of the domino gates in a dynamic
1313
Fig. 6. Two cascaded dual-V domino OR gates in the sleep mode. The dom-
inant gate oxide leakage current conduction paths in the sleep mode are illus-
trated with arrows. H: high. L: low. High-V transistors are represented with a
thick line in the channel region.
Fig. 7. Two cascaded two-input dual-V domino OR gates with high-V sleep
transistors. The dominant gate oxide leakage current conduction paths in the
sleep mode are illustrated with arrows. H: high. L: low. High-V transistors are
represented with a thick line in the channel region.
circuit have been proposed in [2]–[4]. The high output of an
idle domino gate, however, places the fan-out domino circuits
into the highest gate oxide leakage current state, as illustrated
in Fig. 6. The techniques proposed in [2]–[4], [15], and [16],
therefore, increase the gate oxide leakage current while re-
ducing the subthreshold leakage current. In the sub-65-nm
CMOS technologies, the significant increase in the gate oxide
leakage current could negate the subthreshold leakage current
reduction provided by these techniques, thereby increasing the
total leakage power consumption in the sleep mode.
C. NMOS Sleep Switch Dual- Domino Logic
In addition to setting the dynamic node voltage low for re-
ducing the subthreshold leakage current [15], the output node of
a domino logic circuit should also be placed into a low voltage
state in order to suppress the gate oxide leakage current into
the fan-out gates. A technique to force both the dynamic and
output nodes of a domino logic circuit into a low voltage state
in the standby mode is proposed in [17]. Two high- nMOS
sleep transistors N1 and N2 are placed at the dynamic and output
nodes, respectively, as illustrated in Fig. 7.
In the standby mode, the clock is gated high. The sleep signal
is set high turning on N1 and N2. The dynamic and output nodes
are discharged through N1 and N2, respectively. P3 is cutoff
to avoid a static dc current path through P4 and N2. After the
dynamic and output nodes are discharged, the two nMOS sleep
transistors (N1 and N2) are both in the maximum gate oxide
leakage current state [see Fig. 3(a)]. The sleep transistors (N1,
N2, and P3) are required within every domino gate in a dynamic
circuit designed with the technique presented in [17]. The gate
oxide leakage current overhead of the nMOS sleep transistors,
1314 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 12, DECEMBER 2007
Fig. 8. Two-input dual-V domino OR gate with low-V (P1 and P2) and
high-V (P3) pMOS sleep transistors. High-V transistors are represented with
a thick line in the channel region.
therefore, imposes a serious limitation to the leakage current
reduction that can be provided by this technique.
III. PMOS-ONLY SLEEP SWITCH DUAL- DOMINO LOGIC
A new circuit technique with enhanced effectiveness to si-
multaneously reduce the subthreshold and gate oxide leakage
currents in domino logic circuits is proposed in this paper. Only
p-type sleep transistors are employed in order to reduce the gate
oxide leakage current overhead of the new sleep switch cir-
cuit technique. Since the gate tunneling current produced by a
pMOS transistor is much smaller than an nMOS transistor, the
pMOS-only sleep switch circuit technique offers a significant
reduction in the total leakage current as compared to the previ-
ously published schemes.
The proposed circuit technique is illustrated in Fig. 8. Two
low- pMOS sleep transistors P1 and P2 are added to the dy-
namic and output nodes, respectively. Provided that the dynamic
node is discharged in the sleep mode, the pMOS transistor (P4)
in the output inverter is turned on. The output inverter and P2
produce a static dc current if P4 is directly connected to .A
high- pMOS sleep transistor (P3) is employed in series with
P4 in order to eliminate the static dc current path through P4
and P2 and to suppress the subthreshold leakage current pro-
duced by the output inverter in the sleep mode.
In the active mode, the sleep signal is set high. P1 and P2
are cutoff and P3 (driven by the inverted sleep signal) is turned
on. The proposed domino circuit operates similar to a stan-
dard domino gate. In the standby mode, the clock is gated high,
turning off the high- pull-up transistor. The sleep signal is set
low, turning on P1 and P2. P3 is cutoff by the inverted sleep
signal. The dynamic node is discharged to a voltage level equal
to the threshold voltage of a low- pMOS transistor
through P1.
The dynamic and output nodes are eventually discharged to
a steady-state voltage less than (after P1 and P2 are
cutoff) by the high subthreshold leakage currents of the low-
transistors in the pull-down network and the output inverter and
the gate-oxide leakage current into the fan-out gates. After the
node voltages settle to a steady state, all of the high- transis-
tors are strongly cutoff, significantly reducing the subthreshold
Fig. 9. Two-input dual-V domino OR gate with high-V pMOS sleep transis-
tors. High-V transistors are represented with a thick line in the channel region.
leakage current. Similarly, the voltages across the gate insu-
lating layers of most of the transistors are suppressed, thereby
lowering the gate oxide leakage current.
Provided that a dual- CMOS technology is employed, the
noise immunity of a domino logic circuit is weakened due to the
high- keeper transistor [5], [15]. Using low- sleep transis-
tors could further increase the noise vulnerability of the domino
circuits since the sleep switches can be turned on by coupling
noise to the sleep signal line. An alternative pMOS-only sleep
switch technique based on high- sleep transistors is also pro-
posed in this paper. Three high- pMOS sleep transistors (P3,
P5, and P6) are employed with the second proposed technique,
as illustrated in Fig. 9. The current produced by a high- tran-
sistor is smaller as compared to a low- transistor with sim-
ilar physical dimensions. Employing high- sleep transistors,
therefore, enhances the noise immunity as compared to the first
proposed technique. Due to the reduced current provided by
the high- sleep transistors, however, the discharging speed
of the dynamic and output nodes is reduced while entering the
sleep mode. The size of the high- sleep transistors should be
increased in order to maintain a similar sleep delay as com-
pared to the first proposed technique. The active power con-
sumption of the second proposed technique is, therefore, higher
as compared to the first proposed technique (for example, for
an eight-input domino OR gate, the active mode power consump-
tion is increased by 2.3% as compared to the first proposed tech-
nique while maintaining a similar sleep delay).
IV. SIMULATION RESULTS
BSIM4 device models are used in this paper for an accu-
rate estimation of the gate oxide leakage current [14]. The fol-
lowing circuits are simulated in a 45-nm CMOS technology
( 0.22 V, 0.35 V,
and 0.8 V): cascaded multistage two-input domino AND
gates (AND2), cascaded multistage two-input, four-input, and
eight-input domino OR gates (OR2, OR4, and OR8, respectively),
and a 16-bit domino multiplexer (MUX16). All of the circuits
(other than MUX16) are composed of three stages. Each gate
drives a fan-out of four. The domino gates in the first stage are
footed while the domino gates in the second and third stages are
footless. All of the circuits are designed with the following three
techniques: standard dual- domino (dual- ), the technique
LIU AND KURSUN: PMOS-ONLY SLEEP SWITCH DUAL-THRESHOLD VOLTAGE DOMINO LOGIC
Fig. 10. Comparison of the active mode power consumption of the three
domino circuit techniques. The active mode power consumption is normalized
to the power consumption of the standard dual-V technique for each circuit.
presented in [17] (dual- -YWK), and the circuit technique pro-
posed in this paper as illustrated in Fig. 8 (dual- -LK). The
sleep mode data are measured at 25 C and 110 C assuming
long and short idle periods, respectively. Alternatively, the ac-
tive mode data are measured at a worst case temperature of
110 C. A 3-GHz clock is applied to the circuits. To have a rea-
sonable comparison, the circuits are sized to have a similar worst
case propagation delay with each technique.
A. Area Overhead and Active Mode Power
The layouts of the circuits are drawn assuming MOSIS deep
submicrometer design rules [21]. As shown in Fig. 8, a high-
pMOS transistor (P3) is placed in series with the low- pMOS
transistor of the output inverter in the dual- -LK circuits. Phys-
ical size of pMOS transistors in the output inverters of dual-
-LK circuits must be increased to provide an evaluation delay
similar to the standard dual- circuits. Furthermore, two extra
pMOS sleep transistors (P1 and P2) are added to the dynamic
and output nodes. The areas of the proposed pMOS sleep switch
circuits are, therefore, increased by up to 82% (OR2) as com-
pared to the standard dual- circuits based on the layout area
comparison.
The active power consumption of the domino circuits is
shown in Fig. 10. In the dual- -YWK and dual- -LK circuits,
two pMOS transistors are placed in series in the pull-up path of
the output inverter. The driving capability of the output inverter
is, therefore, degraded. Since P3 has a high- , the pull-up
strength of the output inverter is further reduced. Increasing
the physical size of the dual- -LK and dual- -YWK circuits
in order to provide a propagation delay similar to the standard
dual- circuits increases the parasitic capacitance. Further-
more, the parasitic capacitance at the dynamic and output
nodes is increased due to the sleep transistors. The dual- -LK
technique therefore increases the active mode power con-
sumption by 6% (MUX16) to 21% (AND2) as compared to
the standard dual- domino logic circuit technique. Similarly,
the dual- -YWK technique increases the active mode power
consumption by 3% (OR8) to 14% (AND2) as compared to
the standard dual- domino circuits. For a higher fan-in, the
active power consumption overheads of the dual- -LK and
1315
TABLE I
STEADY-STATE NODE VOLTAGES (MILLIVOLTS) WITH
THE DUAL-V -LK TECHNIQUE
dual- -YWK techniques become smaller since the parasitic
capacitance introduced by the sleep transistors become less
important as compared to the parasitic capacitance of the
pull-down network transistors.
The dual- -LK technique increases the active power con-
sumption by 1.9% (MUX16) to 10.7% (OR2) as compared to
the dual- -YWK technique. This difference is primarily due to
the higher parasitic capacitance of the pMOS sleep transistors
(P1 and P2 in Fig. 8) as compared to the nMOS sleep transistors
(N1 and N2 in Fig. 7).
B. Sleep Mode Leakage Power Consumption at
High Temperature
In the dual- -LK circuits, the pMOS sleep transistors are
not capable of directly discharging the dynamic and output
nodes to zero volts ( rise problem). The high subthreshold
leakage currents of the low- transistors in the pull-down net-
work and the output inverter and the gate-oxide leakage current
into the fan-out gates continue to discharge the dynamic and
output nodes after P1 and P2 are turned off. The steady-state
dynamic and output node voltages in the dual- -LK domino
circuits are both below , as listed in Table I.
The subthreshold leakage current produced by a domino logic
circuit strongly depends on the dynamic and output node volt-
ages [5]. Two input conditions are simulated to evaluate the
leakage current in the sleep mode with the standard dual-
technique. The first condition assumes that all of the inputs ap-
plied to the first stage gates are low (high dynamic node voltage
state). The second condition assumes that all of the inputs ap-
plied to the first stage gates are high (low dynamic node voltage
state). The total leakage power consumption characteristics of
the domino circuits with the three techniques at 110 C are
shown in Fig. 11. The leakage power reduction offered by the
proposed circuit technique is listed in Table II.
The dual- -LK technique reduces the total leakage power
by 81.9% to 97.3% as compared to the standard dual- circuits
driven with low inputs, as listed in Table II. For a higher fan-in,
the leakage power reduction provided by the dual- -LK tech-
nique is enhanced (OR2: 87.6% versus OR8: 95.5%).
For a dual- CMOS technology to be effective for reducing
the subthreshold leakage current, the inputs to a standard
dual- domino gate must be maintained high during the sleep
mode. Maintaining the inputs high ensures that the subthreshold
leakage current is produced by the high- transistors. A high
input vector, therefore, reduces the leakage power consumption
by 57.1% (AND2) to 88.6% (OR4) as compared to a low input
vector. The leakage reduction provided by the high input vector
is smaller for AND2 as compared to the other circuits since
1316 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 12, DECEMBER 2007
Fig. 11. Comparison of the leakage power consumption of the domino circuits
with the three circuit techniques at 110 C. The leakage power is normalized to
the leakage power of the standard dual-V technique with low inputs for each
circuit.
TABLE II
LEAKAGE POWER REDUCTION PROVIDED BY THE DUAL-V -LK TECHNIQUE
AS COMPARED TO THE DUAL-V -YWK AND STANDARD DUAL-V
TECHNIQUES AT 110 C
the subthreshold leakage current produced by the pull-down
network of AND2 is reduced by the stack effect when the inputs
are maintained low.
A high input vector places the transistors in the pull-down net-
work of a standard dual- domino logic gate into the highest
gate oxide leakage current state. Since the gate oxide leakage
current of a low- nMOS transistor is significantly higher than
the subthreshold leakage current of a high- transistor (see
Appendix II), the gate tunneling current produced by the pull-
down network dominates the total leakage power consumption
of a standard dual- domino gate when the inputs are main-
tained high. The dual- -LK technique suppresses both the sub-
threshold and the gate oxide leakage by discharging the dynamic
and output nodes. The dual- -LK technique thereby reduces
the total leakage power by 45.6% to 77.0% as compared to the
standard dual- circuits with high inputs, as listed in Table II.
The sleep switches at the dynamic and output nodes are
sized much smaller than the precharge transistor, pull-down
network transistors, and the transistors in the output inverter in
the dual- -YWK and dual- -LK circuits. Particularly for the
wide fan-in gates, the gate oxide leakage current of the sleep
switches is a relatively small portion of the total leakage current
produced at a high die temperature. The difference between
the total leakage power consumption of the dual- -YWK and
dual- -LK techniques is within 10.7% (OR4) at 110 C.
C. Sleep Mode Leakage Power Consumption at Room
Temperature
The total leakage power consumption characteristics of the
domino circuits with the three techniques at the room temper-
Fig. 12. Comparison of the total leakage power consumption of the domino
circuits with the three circuit techniques at 25 C. The leakage power is nor-
malized to the leakage power of the standard dual-V technique with low inputs
for each circuit.
TABLE III
TOTAL LEAKAGE POWER REDUCTION PROVIDED BY THE DUAL-V -LK
AS COMPARED TO THE DUAL-V -YWK AND STANDARD DUAL-V
TECHNIQUES AT 25 C
ature are shown in Fig. 12. The leakage power reduction of-
fered by the proposed circuit technique is listed in Table III. The
dual- -LK technique reduces the total leakage power by 87.7%
to 96.4% as compared to the standard dual- circuits driven
with low inputs, as listed in Table III. For a higher fan-in, the
leakage power savings provided by the dual- -LK technique is
increased (OR2: 91.6% versus OR8: 96.4%).
The gate oxide leakage current produced by the nMOS
transistors is the dominant source of the total leakage power
consumption at the room temperature (see Appendix II). A high
input vector places the transistors in the pull-down network into
the maximum gate oxide leakage current state. The leakage
power reduction provided by the proposed circuit technique is,
therefore, higher when the standard dual- domino circuits
are driven with high inputs. The dual- -LK technique reduces
the total leakage power by 90.2% to 96.9% as compared to the
standard dual- circuits with high inputs, as listed in Table III.
The standard dual- circuits driven by high inputs consume
more power than the standard dual- circuits driven by low
inputs in the sleep mode, as illustrated in Fig. 12. This result
indicates a dramatic change in the node voltage dependent
leakage power characteristics of the standard domino logic
circuits fabricated in technologies subject to significant gate di-
electric tunneling current [18]–[20]. The subthreshold leakage
currents produced by AND2 and MUX16 are reduced by the
stack effect when the inputs are low [15]. Therefore, the shift
in the leakage power characteristics is more significant in the
gates with stacked pull-down transistors.
LIU AND KURSUN: PMOS-ONLY SLEEP SWITCH DUAL-THRESHOLD VOLTAGE DOMINO LOGIC
An nMOS sleep transistor can produce a significantly higher
gate oxide leakage current as compared to a pMOS transistor
(see Appendix I). The high- nMOS sleep switches proposed in
[17] cause a significant increase in the total leakage current of an
idle dual- domino gate. The highest gate oxide leakage current
produced a pMOS transistor is more than an order of magnitude
smaller than the highest gate oxide leakage current produced by
an nMOS transistor. Furthermore, there is zero voltage differ-
ence across the gate insulator layers of P1 and P2 (see Fig. 8)
throughout the idle mode with the dual- -LK technique
. The proposed pMOS-only sleep switch technique,
therefore, effectively eliminates the gate oxide leakage current
overhead introduced by the sleep transistors. The dual- -LK
technique reduces the total leakage power by 22.2% to 43.8% as
compared to the dual- -YWK technique, as listed in Table III.
D. Energy Overhead at High Temperature
The energy overhead of a dual- -LK circuit for imple-
menting a low leakage sleep mode is discussed in this section.
The circuit is assumed to be operating at a worst case tem-
perature of 110 C before entering the idle mode. The energy
overhead of the proposed circuit technique is low, providing
a net savings in total energy consumption shortly after the
beginning of the idle mode. The energy overhead data are
measured at this worst case high die temperature assuming the
junction temperature does not significantly change during the
short duration of time at the beginning of the idle mode.
When a sleep switch domino logic circuit is idle, the clock is
gated high. The sleep signal should be applied after the low-to-
high edge of the clock signal propagates to the gates in the last
stage of a clock-delayed domino logic circuit. Activating the
sleep switches after the low-to-high transition of the clock en-
sures that no short-circuit power is consumed while entering the
sleep mode. The dynamic and output nodes in all of the domino
gates are discharged through the sleep transistors. After the node
voltages settle, all of the high- transistors are strongly cut off,
minimizing the subthreshold leakage current. Similarly, the gate
oxide leakage current is minimized by discharging the output
nodes. After the clock is gated and the sleep switches are acti-
vated, it takes 2.4 to 7.5 ns (depending upon the circuit type) to
place the circuits into a low leakage state.
Before the end of an idle mode, the sleep signal transitions
high, cutting off the sleep switches attached to the dynamic and
output nodes while activating the sleep transistors in the output
inverters. Disabling the dynamic and output node sleep transis-
tors before activating the clock is necessary to avoid short-cir-
cuit current while leaving the idle mode. The clock is reactivated
and all of the dynamic nodes are recharged to activate (wake-up)
a sleeping domino circuit. The reactivation time is equal to the
time it takes to precharge a domino circuit.
The energy overhead of a three-stage sleep switch circuit
composed of four-input domino OR gates with a fan-out of four
is evaluated in this section. Changing the mode of operation
of the sleep transistors to place a dual- domino logic circuit
into standby mode requires a specific amount of energy. Ad-
ditional energy is dissipated at the end of an idle period while
precharging the dynamic nodes in order to reactivate a domino
logic circuit. Depending upon the input vectors, some or none
1317
Fig. 13. Cumulative standby energy dissipation of the dual-V -LK and stan-
dard dual-V circuits for two different input vectors. The step change of the
dual-V -LK energy characteristics at the first nanosecond is the energy over-
head for implementing a sleep mode with the dual-V -LK technique.
of the dynamic nodes in the standard dual- circuits are dis-
charged during the sleep mode. Alternatively, all of the dynamic
nodes in a pMOS-only sleep switch domino logic circuit are dis-
charged during the sleep mode, independent of the input vec-
tors. The activation energy required by the sleep switch circuit
technique is, therefore, higher than the standard dual- circuit
technique. In order to justify the proposed sleep switch circuit
technique to force a circuit into a low leakage state, the total en-
ergy consumed to enter and leave the sleep mode must be less
than the total savings in standby leakage energy.
The cumulative energy dissipated in the standby mode by
the standard dual- and the dual- -LK circuits is shown in
Fig. 13. The leakage energy per cycle is assumed to be con-
stant. The cumulative energy of a standard dual- domino cir-
cuit is only affected by the subthreshold and gate oxide leakage
currents during the standby mode. Alternatively, both the cumu-
lative leakage energy and the energy overhead of entering and
leaving the sleep mode are included in the energy characteris-
tics of the dual- -LK circuit. The total energy overhead of the
dual- -LK circuit technique is independent of the duration of
the idle mode (assuming the duration of idle mode is longer than
the time needed to enter the low leakage sleep mode, 3.7 ns for
the dual- -LK circuit under consideration). The total energy
overhead of the proposed technique is included as an energy
step in the first nanosecond of the standby mode (see Fig. 13).
Similar to the dual- energy characteristics, after entering the
sleep mode, the dual- -LK circuit energy consumption is due
to only the leakage currents. Since the standby leakage energy of
dual- -LK is significantly lower than the standard dual- cir-
cuit, the dual- -LK energy characteristics have a much smaller
slope as compared to the energy characteristics of the standard
domino circuit (see Fig. 13). A specific amount of time in the
idle mode, also dependent upon the input vectors, is necessary
for the cumulative leakage energy of a standard dual- circuit
to exceed the cumulative energy of a dual- -LK circuit.
The intersection of the dual- -LK and standard dual- cu-
mulative energy characteristics are evaluated to determine the
necessary minimum duration of the sleep mode such that the
pMOS-only sleep switch circuit technique offers a net savings
1318 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 12, DECEMBER 2007
in energy as compared to a standard dual- circuit. As illus-
trated in Fig. 13, the cumulative standby energy of the standard
dual- and dual- -LK circuits exhibit different behavior de-
pending upon the input vectors. The leakage current produced
by the standard dual- circuit is smaller for a high input vector
as compared to a low input vector (see Fig. 11). Alternatively,
the leakage current of the dual- -LK is virtually independent of
the input vector. However, depending upon the input vector, the
relative energy overhead of the dual- -LK scheme changes. For
low inputs, none of the dynamic nodes of the standard dual-
circuit are discharged during the standby mode. Alternatively,
all of the dynamic nodes are discharged in the dual- -LK. The
relative energy overhead of the dual- -LK circuit technique re-
quired to charge the dynamic nodes to reactivate the circuit (to
transition from the standby mode to the active mode) is, there-
fore, higher for a low input vector. As shown in Fig. 13, a min-
imum duration of 8.9 and 100 ns is required in the idle mode
for the dual- -LK circuit technique to provide a net savings in
energy as compared to the standard dual- circuit with the low
and high input vectors, respectively.
V. CONCLUSION
In sub-65-nm CMOS technologies, both the subthreshold
and gate dielectric leakage currents need to be suppressed for
reducing the standby power consumption. A circuit technique
based on pMOS-only sleep transistors and a dual- CMOS
technology is presented in this paper for simultaneously re-
ducing the subthreshold and gate oxide leakage currents in
domino logic circuits.
Both the dynamic and output nodes in a domino logic cir-
cuit are discharged through pMOS sleep transistors in the idle
mode. Placing the dynamic node into a low voltage state reduces
the subthreshold leakage current by strongly turning off all of
the high threshold voltage transistors. Furthermore, placing the
output node into a low voltage state suppresses the gate dielec-
tric tunneling currents into the fan-out gates. The proposed cir-
cuit technique also exploits the intrinsically high subthreshold
and gate oxide leakage currents in scaled nanometer CMOS
technologies for placing an idle domino logic circuit into a min-
imum leakage state.
The circuit technique reduces the leakage power by up to
77.0% to 96.9% as compared to the standard dual- domino cir-
cuits in the sleep mode at the high and low die temperatures, re-
spectively. Furthermore, by employing pMOS-only sleep tran-
sistors, the presented circuit technique reduces the total leakage
power by up to 43.8% as compared to a previously published
sleep technique based on nMOS sleep transistors. The energy
overhead of the circuit technique is low, providing a net energy
savings during idle periods as short as 8.9 ns.
APPENDIX I
In a technology with silicon dioxide as the gate dielectric ma-
terial, the tunneling current of a pMOS device is primarily due
to the hole tunneling from the valence band (HVB) in the silicon
substrate. The electron tunneling from the polysilicon conduc-
tion band is negligible since the electron concentration in the
p+ polysilicon gate is low in a pMOS device. Alternatively, the
Fig. 14. Energy band diagrams of pMOS and nMOS transistors under inversion
bias. (a) Energy band diagram of a pMOS transistor. (b) Energy band diagram of
an nMOS transistor. E : Bottom of the conduction band. E : Top of the valence
band. E : Fermi energy level.
electron tunneling from the conduction band (ECB) of the sil-
icon substrate is the dominant tunneling mechanism in an nMOS
transistor. The HVB of the polysilicon is negligible due to the
smaller number of holes as compared to the electrons in the gate
of an nMOS device. The energy barrier heights for the HVB and
ECB are 4.5 and 3.1 eV, respectively, as illustrated in Fig. 14
[12], [13]. The probability of hole tunneling is, therefore, much
smaller than the probability of electron tunneling through the
gate oxide. The for a pMOS device is significantly lower
as compared to an nMOS device with similar physical dimen-
sions (width, length, and ) and voltage difference across the
gate insulator. The produced by a low- nMOS transistor
is 47 times and 30 times higher than the produced by a
low- pMOS transistor at 110 C and 25 C, respectively (see
Appendix II). Replacing the nMOS sleep transistors with pMOS
sleep transistors is, therefore, an effective method for reducing
the gate oxide leakage current of an idle sleep switch dual-
domino gate.
APPENDIX II
A comparison of the normalized subthreshold and gate oxide
leakage currents produced by the low threshold voltage (low- )
and high threshold voltage (high- ) transistors in a dual-
CMOS technology is listed in Table IV. The gate oxide leakage
current of a low- nMOS transistor is 4.7 times and 159.1
times higher than the subthreshold leakage current of a high-
pMOS transistor at the high and low die temperatures, respec-
tively. The difference between the subthreshold leakage currents
of the high- nMOS and pMOS transistors is less than 20%. As
discussed in Sections II-B and II-C, maintaining inputs high is
preferable to reduce the subthreshold leakage current in an idle
dual- domino gate. When the inputs are maintained high, the
majority of gate tunneling current in an idle wide fan-in dual-
domino gate is produced by the low- pull-down network tran-
sistors while the subthreshold leakage currents are produced
by the high- transistors. The gate oxide leakage current of a
low- nMOS transistor is much higher than the subthreshold
leakage currents of the high- transistors at both high and low
temperatures. The gate tunneling, therefore, becomes the dom-
inant leakage mechanism in an idle dual- domino gate when
the inputs are high. When the gate-oxide tunneling phenomenon
LIU AND KURSUN: PMOS-ONLY SLEEP SWITCH DUAL-THRESHOLD VOLTAGE DOMINO LOGIC
TABLE IV
NORMALIZED SUBTHRESHOLD AND GATE OXIDE LEAKAGE CURRENTS OF THE
LOW-V AND HIGH-V TRANSISTORS AT TWO DIFFERENT DIE TEMPERATURES
Transistor width = 1 m. Transistor length = 45 nm. Low-V = 0.22 V.
High-V = 0.35 V. V = 0.8 V. I : V = 0 and V = V .
I : V = V = V = V . For each temperature, the currents
are normalized to the subthreshold leakage current produced by the high-V
pMOS transistor.
is significant, a small size active nMOS sleep switch can pro-
duce a considerably higher leakage current as compared to a
larger cutoff high- pMOS transistor. For example, the
produced by an active 0.1 m wide high- nMOS sleep tran-
sistor is equal to the produced by a cutoff 12.4 m
wide high- pMOS pull-up transistor in a dual- domino gate
at room temperature.
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Zhiyu Liu (S’05) received the B.S. and M.S. degrees
in engineering physics from Tsinghua University,
Beijing, China, in 2000. He is currently pursuing
the Ph.D. degree in electrical and computer engi-
neering from the University of Wisconsin-Madison,
Madison, under the supervision of Prof. Kursun.
His research interests include low-power and high-
performance integrated circuit design and emerging
CMOS technologies.
Volkan Kursun (S’01–M’04) received the B.S.
degree in electrical and electronics engineering
from the Middle East Technical University, Ankara,
Turkey, in 1999, and the M.S. and Ph.D. degrees
in electrical and computer engineering from the
University of Rochester, Rochester, NY, in 2001 and
2004, respectively.
In 2004, he became an Assistant Professor with the
Department of Electrical and Computer Engineering,
University of Wisconsin-Madison, Madison. In 2000,
he was with Xerox Corporation, Webster, NY, where
he performed research on mixed-signal thermal inkjet integrated circuits. During
the summers of 2001 and 2002, he was with Intel Microprocessor Research Lab-
oratories, Hillsboro, OR, where he was responsible for the modeling and design
of high frequency monolithic power supplies. His current research interests in-
clude low-voltage, low-power, and high-performance integrated circuit design,
modeling of semiconductor devices, and emerging integrated circuit technolo-
gies. He has more than 60 publications and four issued and three pending patents
in the areas of high-performance integrated circuits and emerging semicon-
ductor technologies. He is the author of the book Multi-Voltage CMOS Circuit
Design (Wiley, 2006).
Dr. Kursun is a member of the technical program and organizing committees
of a number of IEEE and ACM conferences and serves on the editorial boards
of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI)
SYSTEMS, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS
BRIEFS, and the Journal of Circuits, Systems, and Computers.