G31M04 Schematic Foxconn Precision Co. Inc.: Fab.A Data: 2007/6/15 Page Index

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Foxconn Precision Co. Inc.

D G31M04 Schematic D
Fab.A
Data: 2007/6/15
Page Index
01. Index Page 25. ICH7 -1
02. Topology 26. ICH7 -2
03. Rest Map 27. ICH7 -3
04. Clock Distribution 28. REAR USB
C
05. Power Delivery Map 29. TPM C
06. Power Sequence 30. PCIE1X

07. BLANK 31. PCI Slot
08. CK505 ClockGen 32. LAN-RTL8101E/RTL8111C
09. Power / MISC Connectors 33. AUDIO 662
10. Voltage Regulator Down 11 34. AUDIO PORT
11. OUTPUT CAP 35. Super I/O ITE8718F/GX
12. 1D25V 1D5V FSB 36. Keyboard / Mouse / Fan
13. STR1D8V 3D3_DUAL 37. Serial / Parallel
14. LGA775 -1 38. FRONT USB
B
15. LGA775 -2 39. changlist B
16. Broadwater -GMCH -1

19. DDR2 Channel A Termination
20. DDR2 Channel A DIMM1, 2
21. DDR2 Channel B Termination
22. DDR2 Channel B DIMM1, 2
23. PCI Express x16 Gfx Slot
A 24. VGA Connector A
FOXCONN PCEG
Title
Index Page
Size Document Number Rev
C G31M04 A
Date: Wednesday, September 12, 2007 Sheet 1 of 41

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Cedar Mill, Presler ,

Conroe & Allendale
VRD 11 LGA775 Processor
3 Phase PWM
D
Socket T D
800/1066/1333 FSB
CK-505 Clock
PCI Express x 16 Channel A DDR2

PCI Express x16 Port DDR2 667/800
External Graphics
DIMM1
Card
GMCH DDR2 667/800 Channel B DDR2

VGA Connector
Broadwater DIMM1
C C
Back Panel
PCIe port
USB2.0 Port 7 LAN
4 Lanes
USB2.0 Port 8 Reltek
Direct Media Interface (DMI)
USB2.0 Port 9 Controller Link
USB2.0 Port 10
SPI Flash
PCI Slot 1X2
ICH7
B
Header B
USB2.0 Port 1
Serial ATA ⒑
LPC I/F
USB2.0 Port 2 SATA Connector 1
AHCI, RAID0,1,5,10
USB2.0 Port 3 SATA Connector 2
USB2.0 Port 4 SPI Flash SATA Connector 3

(BIOS) SATA Connector 4
HDA Codec
TPM
TPM(Optional) Realtek ALC662
LPC I/F
Super I/O
IT8718/GX
A A
Floppy
Serial & Parallel
Drive Connector
FOXCONN PCEG
Title
TOPOLOGY
C G31M04 A

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CPU
(Cedar Mill/Presler/Conroe/Allendale)
CPU_PWRGD
LGA775 processor
CPURST#
D D
ATX
Power
Vtt_PwrGd CK505
Translation PWRGD_3V
PWRGD_PS PWROK CPURST#
Circuitry PCI Express x16
PS_ON#
GMCH
Broadwater
C
RSTIN# C
ICH7
ICH_PWRGD
CK_PWRGD
SLP_M#
PCIRST#
PLTRST#
Front Panel PWROK ACZ_RST#

RST# Audio
FR_RST SYS_RESET# LAN_RSTSYNC
B B
SW_ON PWRBTN#
RSMRST#
RCIN#
SLP_S3#
RST#
TPM
RST#
RST#
Power on/off KBRST PCI Slot 1
circuit RSMRST#
Super IO
RST# PCIe Slot
SLP_S3# PCIe LAN
PSOUT
PSIN RST#
A IDE Controller A
PSOUT#
RSMRST circuit FOXCONN PCEG

Title
Reset Map
C G31M04 A

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CPU
D
CPU 200/266/333 MHz Diff Pair D
MCH 200/266/333 MHz Diff Pair
PCI Express 100 MHz Diff Pair PCI Express x16 Gfx Channel A DDR2
DIMM1
GMCH
DOT 96 MHz Diff Pair Broadwater
Channel B DDR2
DIMM1
PCI Express/DMI 100 MHz Diff Pair
C C
CK-505
PCI Express/DMI 100 MHz Diff Pair
USB/SIO 48 MHz
ICH 33 MHz
REF 14 MHz
SPI Clock SPI
ICH7
Azalia Bit Clock
B
PCI 33 MHz PCI Slot 1 B
TPM 33 MHz TPM
32.768KHz
HD Audio
SIO 33 MHz Super I/O
SATA 100 MHz Diff Pair

PCI Express 100 Mhz Diff Pair
A A
FOXCONN PCEG
Title
Clock Distribution
C G31M04 A

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3.3V Super I/O

1
ATX P/S 3.3V

Icc(Max)=50mA
Proceessor
Vccp (CPU Vcore)
5V 5VSB VRD 11 Voltage=1.15~1.5V 3.3SBV
12V Switching Icc(Max)=50mA(S0) 5V
Icc(Max)=125A
Three Phase 3-Phases Swithing
5VDUAL 3.3SBV
D
DDR2 Channel A Icc(Max)= Icc(Max)=38mA(S3)
D
1.2V FSB 5VSB

10A Vtt=5.3A
Vdd (Core)=1.8V
Ivdd(Max)=TBD(per channel)
5VDUAL
USB2.0 10 Ports Icc(Max)=
+5V DUAL=5A(S0, S1)
Vtt (Core)
0.9V Single Phase Switch Broadwater GMCH +5V DUAL=20mA(S3) 4.345A(S0,S1)
22mA(S3)
Ivterm(Max)=200mA 5V to 1.8V
(per channel) Ivdd(Max)=TBD FSB_Vtt
Linear 1.8V PS2
LDO 1.2V FSB Vtt
1.8V to 0.9V to 1.2V Icc(Max)=1.3A +5V DUAL=345mA(S0, S1)
Ivterm(Max)=1.2A 6A +5V DUAL=2mA(S3)
DDR2 Channel B
1.8V VCCSM FWH
Vdd (Core)=1.8V 1.8V VCC_SMCLK
Ivdd(Max)=TBD(per channel) 3.3V=107mA(S0, S1)
GMCH 1.25 V Vcore (Core Logic) PCI Express X16

Vtt (Core) 3.3V 21.34A 1.25V
0.9V Switching Icc(Max)=18.8A(Integrated)
slot (1)
Ivterm(Max)=200mA 12V
(per channel) *1.25V (DMI&PCIe) +12V=5.5A
VCCA_EXP 2.5A
C
3.3VSB C
1.25V Icc(Max)=0.375A(wake)
VCC_CL 3.8A
Icc(Max)=0.02A(no wake)
+3.3V=3A
3.3V VCCA_DAC 70mA
3.3V VCC3_3 15.8mA
PCI Express X1
Per slot (1)
+12V=0.5A
HDA Codec
3.3VSB
Vcc LDO Icc(Max)=0.375A(wake)
5V 12V ICH7 Icc(Max)=0.02A(no wake)
Icc(Max)=200mA to 5V
1.25V VCCDMI 40mA
Vcc +3.3V=3A
3.3V Linear 1.25V 1.2V VCC_CPU_IO 14mA
Icc(Max)=40mA to 1.05V
V_1P05V_ICH 1.05V (Core) VCC1_05
2A 1.17A PCI Per Slot (X2)
1.5V (USB &SATA) VCC1_5A -12V
B
1.12A Icc(Max)=0.1A -12V B
Linear 1.8V
to 1.5V 1.5V (PCIe)VCC1_5B
V_1P5V_ICH 0.77A 5V
2.2A 1.5V VCCGLAN1_5 Icc(Max)=5A
5V
74mA
3.3V
RTC Icc(Max)=7.6A
5VSB Battery RTC=5uA
12V
3.3V VccCL3_3 12mA Icc(Max)=0.5A
5V_STBY to 3.3SB 3.3V VccSUS3_3 141mA
1.5A 3.3V VccLAN (10/100) 12mA 3.3VSB
3.3V VccSUSHDA 4mA Icc(Max)=0.375A(wake)
3.3V VCC3_3 310mA Icc(Max)=0.02A(no wake)
3.3V
3.3V VccGLAN3_3 1mA
3.3V VccHDA 4mA
Nineveh GbE Lan

3.3V STBY
A IO LED 15.5nA A
1.8V ANALOG 418.2mA BJT

CK505
1.0V Internal 1.8
to 1.0 VR core Vdd (Core) FOXCONN PCEG
277.2mA 3.3V
Title
Ivdd(Max)=250mA
Power Delivery Map
C G31M04 A

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2 1
S0->S5
+12V_SYS +12V_SYS
S5->S0
D D
+5V_DUAL +5V_SYS +5V_SYS +5V_DUAL
+3D3V_DUAL +3D3V_SYS +3D3V_SYS +3D3V_DUAL

+1D8V_STR +1D8V_STR
VTT_DDR
VTT_DDR
VTT_VR VTT_VR
Vcc Vcc
1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD VIDPWRGD PS_ONJ
C
PS_ONJ C
S0->S3 S3->S0
+12V_SYS +12V_SYS
+5V_SYS +5V_DUAL +5V_DUAL +5V_SYS
+3D3V_SYS +3D3V_DUAL +3D3V_DUAL +3D3V_SYS

B B
+1D8V_STR +1D8V_STR +1D8V_STR +1D8V_STR
VTT_DDR
VTT_DDR
VTT_VR VTT_VR
Vcc Vcc
1ms to 10ms
Vcc_PWRGD
Vcc_PWRGD
VRM_OUTEN
VRM_OUTEN
VIDPWRGD PS_ONJ VIDPWRGD
PS_ONJ
A A
FOXCONN PCEG
Title
Power Sequence
C G31M04 A

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D D
C C
B B
A FOXCONN PCEG A
Title
BLANK
A G31M04 A

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FB17
2
0 Dummy
1
+/-5% r0805h6
FB18 0 Dummy 3D3V_CLK CP7 X_COPPER 3D3V_CLK_SATA_25M
4.7uFC105
10nFC108
10nFC111
6.3V, X5R, +/-10%
25V, X7R, +/-10%
16V, Y5V, +80%/-20%

+/-5% r0805h6
CP8 X_COPPER 3D3V_CLK
1
25V, X7R, +/-10%
25V, X7R, +/-10%
25V, X7R, +/-10%
25V, X7R, +/-10%
25V, X7R, +/-10%

4.7uFC101
10nFC128
10nFC107
10nFC140
10nFC134
10nFC112
6.3V, X5R, +/-10%
Dummy
* * *
2
D
* * * * * * D
3D3V_SYS
2
Change to 0Ohm RES or not
FB19 0 Dummy
+/-5% r0805h6
CP11 X_COPPER 3D3V_CLK_REF_A
10nFC136
10nFC119
25V, X7R, +/-10%
16V, Y5V, +80%/-20%
C138
1
4.7uF
3D3V_CLK_48M * 6.3V, X5R, +/-10% * *
25V, X7R, +/-10%

10nFC121
2
1
3D3V_CLK * Dummy
TBD
2
3D3V_CLK
R83
4.7K
* +/-5%
r0402h4
Reserved U8
1 64
**RLATCH 25Mhz_0F_2x
2 63
3D3V_CLK 3 GND GND 62 3D3V_CLK_SATA_25M
*
R89 4.7K +/-5% r0402h4 24M_1394 VDD VDD25Mhz_STB 3D3V_CLK_SATA_25M
4 61
**GSEL/24.576Mhz VDDSATA_STB
31
35
CK_33M_PCI2
CK_33M_SIO
CK_33M_PCI2
CK_33M_SIO
*1 2 33
RN12 3D3V_CLK 5
6 VDDPCI SATACLKT_LR
60
59
SATA_100M_P_ICH
SATA_100M_N_ICH
CK_SATA_100M_P_ICH
CK_SATA_100M_N_ICH
26
26
*
3 4 +/-5% R91 4.7K Dummy GND SATACLKC_LR
7 58
*
CK_33M_ICH 5 6 8p4r0603h7 +/-5% r0402h4 **DOC1 GND R93 33 +/-5% r0402h4
27 CK_33M_ICH 8 57 CK_14M_ICH 25
7 8 PCICLK0 REF0_2x/FSLC ICS_FSBSEL2
9 56 ?
*
CK_33M_TPM R94 33 +/-5% @TF ICS_FSBSEL1 10 *Freerun/PCICLK1_2x GND 55 X2

29 CK_33M_TPM FSLB/PCICLK2_2x X1
*1 RN16
9,14,25 ICH_SYS_RSTJ 11
12
SELRSET/RESET#/PCICLK32 X2
54
53 3D3V_CLK_REF_A *
**
C CK_33M_PCI1 2 33 R96 4.7K Dummy 13 PCICLK4 VDDREF_STB 52 R97 0 +/-5% r0402h4 Reserved C102 XTAL 14.318MHz C103 C
ICS9LPRS511
31 CK_33M_PCI1 3 4 +/-5% **DOC0 SDATA SMB_DATA_MAIN 20,22,29,36
CK_48M_ICH +/-5% r0402h4 3D3V_CLK_48M R99 0 +/-5% r0402h4 Reserved 27pF 27pF
25 CK_48M_ICH
35 CK_48M_SIO
CK_48M_SIO 5
7
6 8p4r0603h7
8
ICS_FSBSEL0
14
15
VDD48
FSLA/USB_48MHz
SCLK
GND
51
50
SMB_CLK_MAIN 20,22,29,36 * +/-5% * +/-5%
16 49 200M_P_CPU c0402h6 c0402h6
CK_200M_P_CPU 14
*
R1014.7K +/-5% r0402h4 *SEL24_48#/24_48Mhz CPUT_LR0 200M_N_CPU

17 48
GND CPUC_LR0 CK_200M_N_CPU 14
VRMPWRGD 18 47 3D3V_CLK
96M_P_GMCH Vtt_PwrGd/WOL_STOP# VDDCPU 200M_P_GMCH
16 CK_96M_P_GMCH 19 46 CK_200M_P_GMCH 16
96M_N_GMCH DOT96T_LR/PCIeT_LR0 CPUT_LR1 200M_N_GMCH
20 45
16 CK_96M_N_GMCH DOT96C_LR/PCIeC_LR0 CPUC_LR1 CK_200M_N_GMCH 16
21 44 3D3V_CLK
GND VDDI/O
32 CK_PE_100M_P_LAN 22 43
PCIeT_LR1 GNDA 3D3V_CLK_REF_A
32 CK_PE_100M_N_LAN 23 42
24 PCIeC_LR1 VDDA_STB 41
30 CK_PE_100M_P_1PORT_2 PCIeT_LR2 PCIeT_LR8
25 40
30 CK_PE_100M_N_1PORT_2
26 PCIeC_LR2 PCIeC_LR8 39 PE_100M_P_GMCH
GND PCIeT_LR7 CK_PE_100M_P_GMCH 16
PE_100M_P_16PORT 27 38 PE_100M_N_GMCH
23 CK_PE_100M_P_16PORT PCIeT_LR3 PCIeC_LR7 CK_PE_100M_N_GMCH 16
PE_100M_N_16PORT 28 37
23 CK_PE_100M_N_16PORT PCIeC_LR3 GND
29 36
PCIeT_LR4 PCIeT_LR6
30 35
PCIeC_LR4 PCIeC_LR6 PE_100M_P_ICH
31 34 CK_PE_100M_P_ICH 25
3D3V_CLK 32 GND PCIeT_LR5 33 PE_100M_N_ICH
VDDPCIEX PCIeC_LR5 CK_PE_100M_N_ICH 25
ICS9LPRS511EGLF-T
CK_33M_PCI1
3D3V_CLK
CK_33M_PCI2
*R103
8.2K
50V, NPO, +/-5%
50V, NPO, +/-5%
+/-5%
B
C120 C106 r0402h4 B
10pF 10pF VRMPWRGD
* * VRMPWRGD 10,14,25
Dummy Dummy
FSB SELECT
Host Clock
FSBSEL2 FSBSEL1 FSBSEL0 Frequency
1 0 0 333MHz
0 0 0 266MHz
0 1 0 200MHz
* * *
ICS_FSBSEL0 R1002.2K +/-5% r0402h4 FSBSEL0

0 0 1 133MHz
CK_48M_SIO
ICS_FSBSEL1 R90 +/-5% FSBSEL1
CK_48M_ICH 2.2K r0402h4
CK_33M_SIO ICS_FSBSEL2 R95 2.2K +/-5% r0402h4 FSBSEL2

Reserved
CK_33M_ICH
CK_14M_ICH
CK_33M_TPM
50V, NPO, +/-5%
50V, NPO, +/-5%
FSB_VTT
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
C126 C124 C110 C104 C116 C115

10pF 10pF 10pF 10pF 10pF 10pF
* * * * * *
A Dummy Dummy Dummy Dummy Dummy Dummy A
RN11
*1 2 FSBSEL0
FSBSEL0 14
3 4 FSBSEL1
5 6 FSBSEL1 14
FSBSEL2
7 8 FSBSEL2 14
470
+/-5%
8p4r0603h7 FOXCONN PCEG
Title
CK505 Clock Gen
C G31M04 A

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2
3D3V_SYS 5V_SYS
1
5V_SB
C454 C510 C462 C461
5V_SB -12V_SYS 3D3V_SYS 3D3V_SYS 12V_SYS 5V_SB * 0.1uF

16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
5V_SYS
5V_SYS
*R350
4.7K 13
+3.3V3 +3.3V1
PWR1
1
D +/-5% 14 2 D
r0402h4 -12V +3.3V2 12V_SYS
15 3
GND4 GND1 -12V_SYS 12V_SYS
35 PS_ONJ 16 4
PSON +5V1
17 5
C463 GND5 GND2
18 6
GND6 +5V2
1
Del R32, R33, Q3
* 0.1uF
16V, Y5V, +80%/-20%
19
20
GND7 GND3
RSVD PWR0K
7
8 PWRG_ATX
PWRG_ATX 13,35
* C464 * C496 * C425
21 9 0.1uF 0.1uF 0.1uF
2
+5V3 +5V_AUX C465
22 10
+5V4 +12V_1
23
24
+5V5
GND8
+12V_2
+3.3V4
11
12
* 0.1uF
16V, Y5V, +80%/-20% 25V, X7R, +/-10% 25V, X7R, +/-10% 25V, X7R, +/-10%
HM1512E-EP1 Dummy
3D3V_SYS 3D3V_SYS
C141 C251
* 10nF
25V, X7R, +/-10% * 10nF
25V, X7R, +/-10%
Dummy Dummy
5V_SYS 3D3V_SB 5V_SYS

VCC_DUAL
R348 R361
C 330 * 8.2K
*R352 C
+-5% +/-5% R349 4.7K
r0402h4 330 +/-5%
FP1 +-5% r0402h4 3D3V_SYS 1D25V_MCH
1 2
HDD_LEDJ 3 4 C329 C208
*
26 HDD_LEDJ
8,14,25 ICH_SYS_RSTJ
5
7
6
8
R371
33 +/-5%
PBTNJ_SIO 35 * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
9 X C460 C497 C501
1
Header_2X5_K10 * 220pF
Dummy * 220pF
Dummy * 10nF
C459 C483 25V, X7R, +/-10%
2
* 220pF 220pF
50V, NPO, +/-5% 50V, NPO, +/-5% *
Dummy Dummy TBD 3D3V_SYS 5V_SYS 5V_SYS
C284 C285
* R347
10K * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
+/-5%
r0402h4
C
Reserved
Front Panel Switch/LED
*
B R346 1K PWR_LED 25
+/-1% r0402h4
HD_LED+ 1 2 Power MMBT3904_NL Reserved
E
HD_LED- 3 4 Power LED(Green) Change to 5% or not
Q37
B
GND 5 6 Power button B
Reset button 7 8 Power
NC 9 10 Key
SPEAKER HEADER
SPEAKER
1
5V_SYS 1
3
Confirm must use or not
3
4
5V_SYS RN48 4
*1 2
Header_1X4_K2
Reserved
3 4 BUZ
5 6
+
7 8
*R369
4.7K 100 Ohm BUZZER
+/-5% +/-5% -
r0402h4 8p4r0603h7
Buzzer
D43
C
1 Dummy
*
25 SPKR
3 R364 2.2K B Q44 C469
MMBT3904_NL
35 SIO_BEEP 2 +/-5% r0402h4
* 0.1uF
16V, Y5V, +80%/-20%
E
A A
BAT54C
33 BEEP_PC
FOXCONN PCEG
Title
Power/MISC Connectors
Custom G31M04 A

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C245
R167 r0402h4
3
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*
Dummy 1K
*
+/-1%
Dummy
1nF
50V, X7R, +/-10% R160
C246 2.2K
1
4.7nF * +/-1%
*
50V, X7R, +/-10% RT1
D T D
2
Del R60 10K
R159 +/-1%
* 0 Dummy
+/-5%
R161
1
120pF
*
*
C247 VIN
1
R162
2
15K50V, NPO, +/-5%
+/-1% 2.43K
14
15
16
r0402h4 U13 +/-1% Q6 C87
1
2 Dummy AOD452
* 4.7uF
FB
IDROOP
VDIFF
13 25V, Y5V, +80%/-20% PHASE1
COMP R173 2.2 R176
2
*
VCCP R158 100 31 C2631 225V, X7R, +/-10% G 6.2k Ohm
*
BOOT1
1
14 VCC_SENSE
+/-1% r0402h4
Dummy C244 18 32
+/-5%
r0805h6
0.22uF R79
2.2 *R80
10K
+/-1%
r0402h4 * 25V, X7R, +/-10%
C274
S
VSEN UGATE1 L17
1
* 10nF +/-5% +/-5% 0.1uF
2
25V, X7R, +/-10% 33 r0805h6 r0402h4 2 1
PHASE1
*
14 VSS_SENSE Dummy 17
D
2
RGND R72
*
R157 100 Dummy 30 Q12 Q7 2.2 Choke 400nH

+/-1% r0402h4 LGATE1 +/-5%
5V_SYS R177 2.2 C262 10 12V_VRM G G r0805h6
1 VCC
+/-5% r0805h6
* 0.1uF
ISEN1-
34 R179
PHASE1 AOD472 AOD472
1
* C97
S
R169 R166
25V, X7R, +/-10% 35 VCCP 1nF
2
*
ISEN1+
1
2.2
C 5V_SYS 12
* C273 50V, X7R, +/-10% C
2
OFS 0.1uF +/-5%
R183 100
r0805h6 VIN
2
* *
68K R168 +/-1% 25V, X7R, +/-10% C250

45 29
+/-1% FS PVCC1_2
30K
+/-1% C2541
Dareen 1/27/07
2 10nF 11
* 1uF
16V, X7R, +/-10% Q25
D
Dummy 120K REF R170 2.2 AOD452 C137
1
+/-1%25V, X7R, +/-10% 27 C2401 225V, X7R, +/-10%
* 4.7uF PHASE2
*
BOOT2 +/-5% 0.22uF R117 25V, Y5V, +80%/-20% R165 VCCP
26 r0805h6 2.2 G 6.2k Ohm
2
*
UGATE2
1
R174
+/-1%
100KOhm
r0402h4
9
SS
25
+/-5%
r0805h6 *R119
10K
+/-1%
r0402h4 * 25V, X7R, +/-10%
C243
S
PHASE2 L24
+/-5% 0.1uF
2
r0402h4 2 1
*
5V_SYS 8 28
D
OVPSEL LGATE2 R149
Del R196 12V_VRM Q28 Q29 2.2 Choke 400nH
+/-5%
46 G G r0805h6
35 PVID7 VID7 R164
35 PVID6 47 20 PHASE2 R193 AOD472 AOD472
VID6 ISEN2-
1
35 PVID5 48 19 VCCP 2.2
* C199
S
VID5 ISEN2+
1
35
35
PVID4
PVID3
1
2
VID4 * C238
0.1uF
+/-5% 1nF
50V, X7R, +/-10%
2
VID3 100 r0805h6 VIN
35 PVID2 3
2
VID2 +/-1% 25V, X7R, +/-10% C286
35 PVID1 4 42
VID1 PVCC3
5
* 1uF Q5
D
35 PVID0 VID0 R186 2.2 16V, X7R, +/-10% AOD452 C81
1
B 40 C2821 225V, X7R, +/-10%
* 4.7uF PHASE3 B
*
VID_SELECT:VR10.1<0.6V; 0.6<VR11<3.0V BOOT3 +/-5% 0.22uF R77 25V, Y5V, +80%/-20% R192
14,25 VID_SELECT 6 39 r0805h6 2.2 G 6.2k Ohm
2
VRSEL UGATE3
1
PGOOD is Open-Drain 38
+/-5%
r0805h6 * R81
10K
+/-1%
r0402h4 * 25V, X7R, +/-10%
C283
S
PHASE3 L16
37 +/-5% 0.1uF
2
8,14,25 VRMPWRGD PGOOD r0402h4 2 1
*
D
D
41 R71
LGATE3 Q13 Q8 2.2 Choke 400nH
+/-5%
R182
43 PHASE3 G G r0805h6
ISEN3- AOD472 AOD472
44 VCCP
ISEN3+
1
1
11 VRM_EN 36
* C290
* C95
S
EN 0.1uF 1nF
EN voltage must 100 50V, X7R, +/-10%
2
2
higher than 0.850V +/-1% 25V, X7R, +/-10%
23 5V_SYS
EN_PH4
7 24
DRSEL PWM4
22
ISEN4-
49
GND
A 21 A
ISEN4+
ISL6312CRZ
FOXCONN PCEG
Title
Voltage Regulator Down 11
Custom G31M04 A
Date: Thursday, September 27, 2007 Sheet 10 of 39

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EC20
* 1800uF
6.3V, +/-20%
Dummy
12V_VRM
D D
EC21
4
* 1800uF
6.3V, +/-20%
PWR2
Dummy Input LC circuit
3
EC30 EC45 EC44 EC42 HM3502E-P1 VIN
L14
* 680uF * 680uF * 680uF * 680uF 1.2uH@100KHz Dareen 1/27/07
*
4V,+/-20% 4V,+/-20% 4V,+/-20% 4V,+/-20%
ce35d80h90 ce35d80h90 ce35d80h90 ce35d80h90 C89 EC18 EC15 EC13 EC24
1
Reserved Reserved Reserved Reserved
* 0.1uF
25V, Y5V, +80%/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
2
Dummy
EC34 EC33 EC31 EC32
* 680uF
4V,+/-20%
* 680uF
4V,+/-20%
* 680uF
4V,+/-20%
* 680uF
4V,+/-20%
ce35d80h90 ce35d80h90 ce35d80h90 ce35d80h90
Reserved
C C
VTT_OUT_RIGHT
TC2 TC1 *R256

1K
* 100uF
2V,+30/-20%
* 100uF
2V,+30/-20%
VTT_OUT_RIGHT VCC_DUAL +/-5%
r0402h4
ctxh15 ctxh15 VTT_PWRGD 14
Dummy Dummy
*R226
D
20K
*R253
4.12K
+/-1% Q33
+/-1% G
2N7002-7-F
S
R248
*
*
R235 100KOhm B Q32 0 CP17
C197 C203 C211 C217 C196 C195 +/-1% r0402h4 MMBT3904_NL +/-5% X_COPPER
* 10uF
* 10uF
* 10uF
* 10uF
* 10uF
* 10uF Dummy Dummy
E
6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
C316
*
B 2.2uF VRM_EN 10 B
6.3V, Y5V, +80%/-20%
* C280
2.2uF
C201 C228 C223 C202 C226 C221 6.3V, Y5V, +80%/-20%
* 10uF
* 10uF
6.3V, X5R, +/-10%6.3V, X5R, +/-10% * 10uF
6.3V, X5R, +/-10% * 10uF
6.3V, X5R, +/-10% * 10uF
6.3V, X5R, +/-10% * 10uF
6.3V, X5R, +/-10%
Dummy Reserved Reserved Dummy Dummy Dummy
C215 C209 C227 C222 C216 C210

* 10uF
6.3V, X5R, +/-10% * 10uF
6.3V, X5R, +/-10% * 10uF
6.3V, X5R, +/-10% * 10uF
6.3V, X5R, +/-10% * 10uF
6.3V, X5R, +/-10% * 10uF
6.3V, X5R, +/-10%
Dummy Dummy Dummy Dummy Dummy Dummy
A A
FOXCONN PCEG
Title
OUTPUT CAP
Custom G31M04 A

5 4 3 2 1

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4
C296
12V_SYS
3
QQ:453100829 2 1
A C 125V_PHASE
*
*
L25
*
12V_SYS R198 10 1N4148W 1uH@1KHz
+/-5% 1uF
16V, X7R, +/-10%
close to Q61 Drain

C293 1uF 16V, X7R, +/-10%
*
R224 C267 EC68 C271
1
14.3K
* 0.1uF
* 330uF
* 4.7uF
D
D D
5
+/-1% U14 25V, X7R, +/-10% +/-20% 25V, Y5V, +80%/-20%
1 Q30
VCC
2
Rocset BOOT
7 2 R184 0 +/-5% G
COMP/OCSET UGATE AOD452 1D25V_MCH
L26 Need to change to RUBYCON 16MBZ470MEFC8X11.5
*
S
6 8 125V_PHASE 1D25V_MCH
FB PHASE
GND
4
LGATE R190 2.5uH@100KHz
D
*R200 APW7120KE-TRL 2.2
1
200 Q31 +/-5% C294 EC50 EC49 C292
* * *
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

+/-1% 1000uF 1000uF 10uF
* 0.1uF
2.2uF C224
2.2uF C231
2.2uF C239
1uF C252
1uF C234
1uF C198
10V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%

r0402h4 R188 0 +/-5% G C289 6.3V, +/-20%
16V, Y5V, +80%/-20% 6.3V, +/-20%
1
AOD472 2.2nF
* 50V, X7R, +/-10% * * * * * *
S
Near MOSFET
2
VOUT= 0.8V(1+R638 / R658)
R638,R658 must less than 1k
Pull FB trace out after Cout
*
R223 115 Ohm +/-1% r0402h4
R203 C308
*
220 18nF
+/-1% 50V, Y5V, +80%/-20%
Dummy Dummy
1D25V FOR CHIP
C C
12V_SYS
2D5V_REF 12V_SYS
1D8V_STR
3D3V_SB 2D5V_REF
50 mils
1
R112 C158
* U10D
4
*R111
33 Ohm
910
+/-1%
0.1uF
12
2
+
+/-1% 25V, X7R, +/-10% 14
D
U10A 1D5V_CORE 13
4
-
Q36
@1.5V 1D5V_REF 3 LM324DR2G
2
11
+
Q24
C146 1 2
1 G
AP15N03H
1A
1
-
1uF R400 TL431NSL
* 50 mils
S
10V, Y5V, +80%/-20% 100 Dummy LM324DR2G R303

11
Dummy +/-1%
*R113 C153 1K
2
+/-1% *
Reserved 1.5K 0.1uF +/-1%
16V, Y5V, +80%/-20%
Can change to 0402 or not
Dummy EC57 C411
* 1000uF
6.3V, +/-20% * 0.1uF
16V, Y5V, +80%/-20%
B B
Check to dummy or not
1D5V_SYS
2D5V_REF
1D8V_STR
12V_SYS
50 mils
2D5V_REF R121
1D8V_STR * 1K
+/-1%
50 mils r0402h4
D
3D3V_SB 12V_SYS
*R116 FSB_VTT 1D5V_CORE U10B 1D05V_SYS
4
10K Q34
+/-1% @1.05V 1.8V 5
+
R110 r0402h4
* 7 G
1A
D
1K U10C 6 AP15N03H
C
4
-
+/-5% Q27 D24 50 mils
S
1D5V_CORE Reserved VREF1D2 @1.2V 1.8V 10 LM324DR2G R127
11
+
r0402h4 8 G R124 C163 1K
9 AP15N03H 1N4148W * 750
* 0.1uF +/-1%
C
-
*R114 +/-1% 16V, Y5V, +80%/-20%
S
470 B Q26 LM324DR2G R125 Can change to 0402 or not

Dummy EC55 C166
11
+/-5% MMBT3904_NL
*R118 C160 1K
* 680uF
* C362
* 0.1uF
+/-1% *
Reserved 10K 1uF +/-1% 4V,+/-20% 10uF 16V, Y5V, +80%/-20%
6.3A 50 mils
C
10V, Y5V, +80%/-20% ce35d80h90

B Q23 r0402h4 Can change to 0402 or not
Dummy EC37 C154 C164 6.3V, Y5V, +80%/-20%
C147
MMBT3904_NL
Reserved
* 1000uF
6.3V, +/-20% * 10uF
* 0.1uF
6.3V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
Dummy Dummy
Need to Check Change to Dummy
E
1uF
A * 10V, Y5V, +80%/-20% Dummy A
Reserved
1D05V_SYS
TBD
FSB_VTT FSB_VTT
C156 C155 FOXCONN PCEG

0.1uF 0.1uF
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% Title
1D25V 1D5V FSB
FSB_VTT Size
C
Document Number
G31M04
Rev
A

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DDR_VTT
D D
VCC_DUAL
D41 D40
12V_SYS 1 1
3 3 C466 18V_PHASE
*
1.8V Voltage
*
5V_SB 2 2 1uF L38
16V, X7R, +/-10% 1uH@1KHz
*
R328 10 1D8V_STR 3D3V_SYS
BAT54C BAT54C
1.8V Power requires
+/-5%
17A maximum current
close to Q61 Drain
5V_SB C456 EC60
*
R339
1uF
16V, X7R, +/-10% EC69
* 1000uF
6.3V, +/-20% U22
1
*R360 Open 14.3K
* C482 * 470uF
* C487 1 8 VTT_DDR
D
5
4.7K +/-1% U20 0.1uF +/-20% Dummy VIN VCNTL 7
10uF VCNTL
+/-5% L 1 Q45 c0805h14 R362 6
*
VCC
2
L r0402h4 Rocset BOOT 25V, X7R, +/-10% 10V, Y5V, +80%/-20% 100KOhm VCNTL 5
Open R368 0 +/-5% +/-1% VCNTL
7 2 G
H COMP/OCSET UGATE AOD452 1D8V_STR r0402h4 4
C
L37 VOUT
16V, Y5V, +80%/-20%

Open
*
S
L B Q43 6 8 18V_PHASE 3 2
1
MMBT3904_NL FB PHASE C499 C477 REFEN GND
* *
GND
L 4 10uF 10uF RT9173 C467 EC59 C458
E
1
LGATE 2.5uH@100KHz
R359 c0805h14 c0805h14
*R358 C468
* 0.1uF * 1000uF
* 4.7uF
C
2
First H R335 Need to Apply 2.2 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20% 100KOhm 0.1uF 6.3V, +/-20% Dummy
* APW7120KE-TRL
*
3
*
R354 1K B Q42 91 Ohm Q38 +/-5% C439 EC61 EC62 +/-1% 16V, Y5V, +80%/-20%
2
25 SLP_S4J
S5
+/-5%
L
r0402h4 MMBT3904_NL +/-1%
R327 0 +/-5% G C486 * 0.1uF * 1000uF
6.3V, +/-20%
16V, Y5V, +80%/-20%
* 1000uF
6.3V, +/-20%
r0402h4
E
1
AOD472 2.2nF
S0 H Don't in CIS * 50V, X7R, +/-10%
S
Near MOSFET Need to Check Change to Dummy
2
S3 H
VOUT= 0.8V(1+R638 / R658)

R638,R658 must less than 1k
Pull FB trace out after Cout
*
R337 115 Ohm
C +/-1% C
*
R336 220 +/-1% C453 18nF

*
Dummy Dummy 50V, Y5V, +80%/-20%
R334 R333
442 Ohm 1.02KOhm
+/-1% +/-1%
Reserved r0402h4
35 SIO_GP10_DDR_VOL_3
35 SIO_GP41_DDR_VOL_5
1D8V_STR
VCC_DUAL
U19
B
3D3V_SB B
3
Vin
2 Max. output current = 3A
Vout
1
ADJ
AZ1084D-ADJTRE1 *R340
301
12V_SYS 5V_SB
+/-1%
3D3VADJ 5V_SB * R353

EC63 C478 EC58 1K
* 1000uF
6.3V, +/-20% * 1uF
10V, Y5V, +80%/-20% R341
* 1000uF
6.3V, +/-20%
915 series failure issue L
+/-5%
* 499 H PWOK+ r0402h4
* R357
S
+/-1%
D
PWOK+ G APM2301AAC-TRL 1K
Q41 +/-5%
A
5V_SYS
Q39 PWOKJ r0402h4
G
D39 2N7002-7-F
D
B120-13-F
S
G
D
C
Q40
Q46
AP15N03H G PWRG_ATX
D
PWRG_ATX 9,35
2N7002-7-F
Vout=Vref(1+R2/R1)+IadjR2 VCC_DUAL
S
R1 is Up Resistor.
Iadj=50uA
Vref=1.25V
A A
3D3V_DUAL 5V_DUAL
FOXCONN PCEG
Title
STR 1D8V 3D3V_DUAL 5V_DUAL
C G31M04 A

5 4 3 2 1

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HDJ[63..0] 16
16 HAJ[35..3]
HAJ[35..3]
HAJ3
3
U11A
QQ:453100829 2
3 OF 7
1
L5 D2
HAJ4 P6 A03# ADS# C2 HADSJ 16 U11C
2 OF 7 HAJ5 A04# BNR# HBNRJ 16 TESTHI_0
M5 D4 P2 F26
U11B A05# HIT# HITJ 16 26 SMIJ SMI# TESTHI00
HAJ6 L4 H4 TP_RSPJ K3 W3 TESTHI_1
A06# RSP# TP1 26 A20MJ A20M# TESTHI01
HAJ7 M4 G8 R3 P1 TESTHI_11
A07# BPRI# HBPRIJ 16 26 FERRJ FERR#/PBE# TESTHI11
HDJ0 B4 G16 HDJ32 HAJ8 R4 B2 K1 W2 TESTHI_12
D00# D32# A08# DBSY# HDBSYJ 16 26 INTR LINT0 TESTHI12
HDJ1 C5 E15 HDJ33 HAJ9 T5 C1 L1 F25
D01# D33# A09# DRDY# HDRDYJ 16 26 NMI LINT1 TESTHI02
HDJ2 A4 E16 HDJ34 HAJ10 U6 E4 N2 G25
D02# D34# A10# HITM# HITMJ 16 26 IGNNEJ IGNNE# TESTHI03
HDJ3 C6 G18 HDJ35 HAJ11 T4 AB2 HIERRJ M3 G27
D03# D35# A11# IERR# 26 STPCLKJ STPCLK# TESTHI04
HDJ4 A5 G17 HDJ36 HAJ12 U5 P3 G26
HDJ5 D04# D36# HDJ37 HAJ13 A12# INIT# INITJ 26 TESTHI05
D B6 F17 U4 C3 15 HVCCA A23 G24 D
HDJ6 D05# D37# HDJ38 HAJ14 A13# LOCK# HLOCKJ 16 VCCA TESTHI06 TESTHI_2_7
B7 F18 V5 E3 15 HVSSA B23 F24
HDJ7 A7 D06# D38# E18 HDJ39 HAJ15 V4 A14# TRDY# AD3 TP_BINITJ HTRDYJ 16 VCC_PLL D23 VSSA TESTHI07 AK6 FORCEPHJ
D07# D39# A15# BINIT# TP2 RSVD5 FORCEPH
HDJ8 A10 E19 HDJ40 HAJ16 W5 G7 C23 G6
D08# D40# A16# DEFER# HDEFERJ 16 15 HVCCIOPLL VCCIOPLL RSVD11
HDJ9 A11 F20 HDJ41 N4 F2 HGTLREF_1
HDJ10 B10 D09# D41# E21 HDJ42 P5 RSVD1 EDRDY# AB3 TP_MCERRJ L2 TESTHI_13
D10# D42# 16 HREQJ[4..0] RSVD2 MCERR# TP3 TESTHI13 TESTHI_13 26
HDJ11 C11 F21 HDJ43 HREQJ0 K4 VID0 AM2 AH2
D11# D43# REQ0# 35 VID0 VID0 RSVD12
HDJ12 D8 G21 HDJ44 HREQJ1 J5 U2 TP_APJ0 VID1 AL5 N1
D12# D44# REQ1# AP0# TP4 35 VID1 VID1 PWRGOOD CPU_PWRG 25
HDJ13 B12 E22 HDJ45 HREQJ2 M6 U3 TP_APJ1 VID2 AM3 AL2 PROCHOTJ
D13# D45# REQ2# AP1# TP5 35 VID2 VID2 PROCHOT#
HDJ14 C12 D22 HDJ46 HREQJ3 K6 VID3 AL6 M2
D14# D46# REQ3# 35 VID3 VID3 THERMTRIP# THERMTRIPJ 26
HDJ15 D11 G22 HDJ47 HREQJ4 J6 F3 HBR0J VID4 AK4
D15# D47# HAJ[35..3] REQ4# BR0# HBR0J 16 35 VID4 VID4
HDBIJ0 A8 D19 HDBIJ2 R6 G3 TESTHI_8 VID5 AL4
16 HDBIJ0 DBI0# DBI2# HDBIJ2 16 16 HAJ[35..3] 16 HADSTBJ0 ADSTB0# TESTHI08 35 VID5 VID5
C8 G20 G5 G4 TESTHI_9 VID6 AM5 A13 HCOMP0
16 HDSTBNJ0 DSTBN0# DSTBN2# HDSTBNJ2 16 35 PECI PCREQ# TESTHI09 35 VID6 FC11 COMP0
B9 G19 H5 TESTHI_10 VID7 AM7 T1 HCOMP1
16 HDSTBPJ0 DSTBP0# DSTBP2# HDSTBPJ2 16 TESTHI10 35 VID7 FC12 COMP1
HAJ17 AB6 VID_SELECT AN7 G2 HCOMP2
A17# 10,25 VID_SELECT FC16 COMP2
HDJ16 G9 D20 HDJ48 HAJ18 W6 J16 TP_DPJ0 F28 R1 HCOMP3
D16# D48# A18# DP0# TP6 8 CK_200M_P_CPU BCLK0 COMP3
HDJ17 F8 D17 HDJ49 HAJ19 Y6 H15 TP_DPJ1 G28 J2 HCOMP4
D17# D49# A19# DP1# TP8 8 CK_200M_N_CPU BCLK1 COMP4
HDJ18 F9 A14 HDJ50 HAJ20 Y4 H16 TP_DPJ2 T2 HCOMP5
D18# D50# A20# DP2# TP9 COMP5
HDJ19 E9 C15 HDJ51 4 mils width, 10 mils spacing HAJ21 AA4 J17 TP_DPJ3 AE8
D19# D51# A21# DP3# TP10 TP11 SKTOCC#
HDJ20 D7 C14 HDJ52 HAJ22 AD6 N5
HDJ21 D20# D52# HDJ53 HAJ23 A22# HGTLREF_1 RSVD13
E10 B15 AA5 H2 AE6
HDJ22 D21# D53# HDJ54 HAJ24 A23# GTLREF1 HGTLREF_0 RSVD14 H_TEST
D10 C18 AB5 H1 35 THERMDA AL1 C9
HDJ23 D22# D54# HDJ55 HAJ25 A24# GTLREF0 MCH_GTLREF_CPU THERMDA RSVD15 HGTLREF_0
F11 B16 AC5 E24 AK1 G10
D23# D55# A25# CS_GTLREF MCH_GTLREF_CPU 16 35 THERMDC THERMDC RSVD16
HDJ24 F12 A17 HDJ56 HAJ26 AB4 D16
HDJ25 D24# D56# HDJ57 HAJ27 A26# RSVD17
D13 B18 AF5 AN3 A20
HDJ26 D25# D57# HDJ58 HAJ28 A27# VCCSENSE RSVD18
E13 C21 AF4 G23 AN4 E23
HDJ27 D26# D58# HDJ59 HAJ29 A28# RESET# HCPURSTJ 16 VSSSENSE RSVD19
G13 B21 AG6 10 VCC_SENSE AN5 F23
HDJ28 D27# D59# HDJ60 HAJ30 A29# VCC_MB_REG RSVD21
F14 B19 AG4 B3 10 VSS_SENSE AN6 J3
HDJ29 G14 D28# D60# A19 HDJ61 HAJ31 AG5 A30# RS0# F5 HRSJ0 16 VSS_MB_REG RSVD24
HDJ30 D29# D61# HDJ62 HAJ32 A31# RS1# HRSJ1 16 Changed pin name MS_ID1
F15 A22 AH4 A3 V1
HDJ31 D30# D62# HDJ63 HAJ33 A32# RS2# HRSJ2 16 MSID1 MS_ID0
G15 B22 AH5 F29 from RSV W1
HDBIJ1 G11 D31# D63# C20 HDBIJ3 HAJ34 AJ5 A33# RSVD9 MSID0
16 HDBIJ1 DBI1# DBI3# HDBIJ3 16 A34#
G12 A16 HAJ35 AJ6
16 HDSTBNJ1 DSTBN1# DSTBN3# HDSTBNJ3 16 A35#
E12 C17 AC4 THERMDA/THERMDC Y1 CPU_BOOT
16 HDSTBPJ1 DSTBP1# DSTBP3# HDSTBPJ3 16 RSVD3 BOOTSELECT TP12
AE4 1. width=10 mils, spacing=10 mils. V2 TP_CPU_V2
RSVD4 LL_ID0 TP13
AD5 2. route the lines in parallel AA2 TP_CPU_AA2
16 HADSTBJ1 ADSTB1# LL_ID1 TP14
Socket-IntelPrescottCPU
C 1 OF 7 C
* *
R228 62 HTCK
VTT_OUT_LEFT VTT_OUT_RIGHT +/-5% r0402h4
R215 1D5V_CORE
51 Ohm R227 62 HTRSTJ
*
R232 62 HTDO +/-5% r0402h4
VTT_OUT_LEFT * +/-5%
r0402h4
+/-5% r0402h4 Dummy
CP13
Dummy X_COPPER In Design Guide is NC
Place at CPU end of route
*
R204 62 +/-5% r0402h4 HBR0J U11D 4 OF 7 FSB_VTT

* *
MS_ID0 R216 51 Ohm +/-5% r0402h4 VCC_PLL HTCK AE1 A29

Place at CPU end of route VTT_OUT_RIGHT HTDI AD1 TCK VTT1 B25
C149 C150 HTDO TDI VTT2
AF1 B29
1
MS_ID1 R214 51 Ohm +/-5% r0402h4 10uF 10nF HTMS TDO VTT3
* * 25V, X7R, +/-10% HTRSTJ
AC1
AG1
TMS
TRST#
VTT4
VTT5
B30
C29
RN23 TESTHI_9 R246 130 +/-1% r0402h4 FORCEPHJ 10V, Y5V, +80%/-20% Reserved A26
2
51 7 8 TESTHI_8 MSID0: NC = 2005 Mainstream / Value, 2006 65W FMB VTT6
B27
+/-5% 5 6 TESTHI_10 Vss = 2005 Performance FMB R245 130 +/-1% r0402h4 PROCHOTJ HBPM0J VTT7
AJ2 C28
8p4r0603h7 * 3 4 H_TEST MSID1: Vss = 2005 Performance,2005 Mainstream/Value,2006 65W FMB HBPM1J AJ1 BPM0# VTT8 A25
1 2 VTT_OUT_RIGHT HBPM2J BPM1# VTT9
placed near pin D23, within 500 mils AD2 A28
HBPM3J BPM2# VTT10
AG2 A27
RN32 VID2 VTT_OUT_RIGHT HBPM4J BPM3# VTT11
AF2 C30
7 8 680 VID4 HBPM5J BPM4# VTT12
AG3 A30
RN31 TESTHI_12 5 6 +/-5% VID5 BPM5# VTT13
C25
* **
51 7 8 TESTHI_11 *3 4 8p4r0603h7 VID0 R219 62 +/-5% r0402h4 HIERRJ ICH_SYS_RSTJ AC2

VTT14
C26
8,9,25 ICH_SYS_RSTJ
+/-5% 5 6 TESTHI_1 1 2 DBR# VTT15 C27 VRMPWRGD 8,10,25
8p4r0603h7 3 4 TESTHI_13 R217 62 +/-5% r0402h4 HCPURSTJ VTT16
AK3 B26
*R254
* 1 2 ITPCLKOUT0 VTT17
RN33 VID3 Place at CPU end of route AJ3 D27 0
*
7 8 680 VID6 PROCHOTJ R244 0 +/-5% ITPCLKOUT1 VTT18 +/-5%
D28
*
R208 49.9 +/-1% r0402h4 HCOMP4 5 6 +/-5% VID7 R247 1K +/-1% r0402h4 VID_SELECT r0402h4 Dummy ICH_THRM_UP 25,35 FSBSEL0 G29 VTT19 D25 Dummy
B 3 4 8 FSBSEL0 BSEL0 VTT20 B
Reserved 10 mils width * 8p4r0603h7 VID1 FSBSEL1 H30 D26 r0402h4
1 2 8 FSBSEL1 FSBSEL2 BSEL1 VTT21
7 mils spacing to low speed signals Stuff to enable Thermal event G30 B28
8 FSBSEL2 BSEL2 VTT22 VTT_PWRGD 11
14mils spacing to high speed signals D29
VTT23
max. 1200mils D30
FSB_VTT VTT_OUT_RIGHT VTT24 VTT_OUT_RIGHT VTT_OUT_LEFT
AM6
**
R207 49.9 +/-1% r0402h4 HCOMP2 VTTPWRGD

AA1 VTT_OUT_RIGHT
* *
R156 49.9 +/-1% r0402h4 HCOMP0 R123 51 Ohm +/-5% r0402h4 TESTHI_0 VTT_OUT1 VTT_OUT_LEFT
J1
VTT_OUT2 F27
VTT_OUT_LEFT VTT_SEL TP21
10 mils width R122 51 Ohm +/-5% r0402h4 TESTHI_2_7 Socket-IntelPrescottCPU
7 mils spacing to low speed signals RN24 HBPM2J
14mils spacing to high speed signals 7 8 51 HBPM3J
max. 1200mils
5 6 +/-5% HTDI R206
*3 4 8p4r0603h7 HTMS 51 Ohm
1 2 * +/-5%
***
R209 49.9 +/-1% r0402h4 HCOMP3 r0402h4 VTT_OUT_RIGHT VTT_OUT_LEFT

R210 49.9 +/-1% r0402h4 HCOMP1 RN25 HBPM1J
R211 49.9 +/-1% r0402h4 HCOMP5 7 8 51 HBPM0J TP_CPU_G1 C335 C313
VTT_OUT_LEFT 5 6 TP_CPU_G1 15
Dummy +/-5% HBPM5J 0.1uF 0.1uF
*3
1
4
2
8p4r0603h7 HBPM4J * *
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
Place BPM termination near CPU reserve for Kentsfield CPU support Dummy Dummy
VTT_OUT_RIGHT VTT_OUT_RIGHT
GTLREF voltage should be 0.63*VTT

R251
* 115 Ohm *R255
115 Ohm
12 mils width, 15 mils spacing
divider should be within 1.5" of the GTLREF pin
+/-1% +/-1% 0.22nF caps should be placed near CPU pin
A place series resistor as close to divider A
*
*
R231 10 HGTLREF_0 R230 10 HGTLREF_1
+/-1% +/-1%
C300
C325
* *R250
200
*
C301
220pF
C312
1uF * *R249
200 * 220pF
50V, NPO, +/-5%
1uF +/-1% 50V, NPO, +/-5% 10V, Y5V, +80%/-20% +/-1%
10V, Y5V, +80%/-20%
FOXCONN PCEG
Title
LGA775-1
C G31M04 A

5 4 3 2 1

VCCP
AG22
5
U11E 5 OF 7
AK12
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VCCP VCCP
4
AF9
U11F 6 OF 7
AL23
3
H22
QQ:453100829
U11G 7 OF 7
D5
2 1
FSB_VTT
VCCP1 VCCP93 VCCP185 VSS41 VSS126 VSS211

K29 AH22 AF22 A12 H21 A9
AM26
VCCP3 VCCP95
T29 AH11
VCCP187 VSS43
L25 H20
VSS128 VSS213
D3 PLL Supply Filter
AL8 AM14 AJ14 J7 H19 B1
VCCP4 VCCP96 VCCP188 VSS44 VSS129 VSS214 R120
AE12 AM25 AH19 AE28 H18 B5
VCCP5 VCCP97 VCCP189 VSS45 VSS130 VSS215 0
AE11 AE9 AH29 AE29 AB7 B8
VCCP6 VCCP98 VCCP190 VSS46 VSS131 VSS216 +/-5%
W23 Y29 AH27 K5 H17 AJ4
W24 AK25 AG28 J4 AJ24 AE26
D W25 AK19 AL26 AE30 AM17 AH1 D
VCCP9 VCCP101 VCCP193 VSS49 VSS134 VSS219 TP_CPU_E29
T25 AG15 AM12 AN20 AC3 E29 TP15
Y28 J22 J24 AF10 H14 V7
AL18 T24 J13 AE24 P28 C13
AC25 AG21 T28 AM24 V6 AK24
VCCP13 VCCP105 VCCP197 VSS53 VSS138 VSS223 HVCCIOPLL
W30 AM21 W28 AN23 AK2 AB30 14 HVCCIOPLL
Y30 J25 J12 H9 P27 L6
AN14 U30 J27 H8 P26 L7
VCCP16 VCCP108 VCCP200 VSS56 VSS141 VSS226 HVCCA
AD28 AL21 AG19 H13 AM28 AB29 14 HVCCA
Y26 AG25 AL9 AC6 AJ13 M1
AC29 AJ18 AD30 AC7 W4 AB28
VCCP19 VCCP111 VCCP203 VSS59 VSS144 VSS229 EC36
M29 J19 AF21 AH6 P25 E8
U24
J23
VCCP21 VCCP113
AH30
J15
Y24
AK14
VCCP205 VSS61
C16
AM16
AJ20
W7
VSS146 VSS231
AG20
AN17
* 100uF
+/-20%
AC27 AG12 J9 AE25 P23 AB27
AM18 AJ22 M27 AE27 AG13 AB26
AM19 J20 AF14 AJ28 AG16 AN16
AB8 AH18 J30 AJ7 AG17 M7
VCCP26 VCCP118 VCCP210 VSS66 VSS151 VSS236 HVSSA
AC26 AH26 AG18 F19 C7 AB25 14 HVSSA
J8 W27 AA8 AH13 Y2 AB24
VCCP28 VCCP120 VCCP212 VSS68 VSS153 VSS238 Notes:
J28 AL25 AG8 AD7 L30 AB23
VCCP29 VCCP121 VCCP213 VSS69 VSS154 VSS239 1. Cap. should be within 1.5" mils of the VCCA and VSSA pins
T30 AN8 AL29 AH16 L29 N3
VCCP30 VCCP122 VCCP214 VSS70 VSS155 VSS240 2. VCCA route should be parallel and next to VSSA route to
AM9 AH14 AD29 AK17 D15 AA30
VCCP31 VCCP123 VCCP215 VSS71 VSS156 VSS241 minimize loop area
AF15 U27 W8 E17 AL27 F4
VCCP32 VCCP124 VCCP216 VSS72 VSS157 VSS242 3. VCCIOPLL route should be parallel and next to VSSA route
AC8 T23 AH8 AH17 Y7 AG10
VCCP33 VCCP125 VCCP217 VSS73 VSS158 VSS243 to minimize loop area
AE14 R8 N24 AH20 L27 AE13
VCCP34 VCCP126 VCCP218 VSS74 VSS159 VSS244 3. Min. 12 mils trace from the filter to the processor pins
N23 AK22 AN22 AE5 AA29 AF30
VCCP35 VCCP127 VCCP219 VSS75 VSS160 VSS245 4. The inductors should be close to the cap.
C W29 AN29 J14 AH23 N6 H28 C
U29 AG11 K26 AE7 N7 F7
AC24 AK26 AF19 AM13 AA28 AF29
AC23 J10 N8 AH24 AN13 AF28
Y23 AJ15 AF12 AJ30 AA27 G1 TP_CPU_G1 14
AN26 AG26 M28 AJ10 AA26 AF27
AN25 AN9 AK9 AF3 P4 AF26
AN11 AH15 AK5 AA25 AF25
VCCP43 VCCP135 VSS83 VSS168 VSS253
AN18 AF18 AJ16 AA24 AN28
Y27 AL15 C10 AF6 P7 AN27
VCCP45 VCCP137 VSS1 VSS85 VSS170 VSS255
Y25 J26 D12 AK29 E26 AF24
VCCP46 VCCP138 VSS2 VSS86 VSS171 VSS256 VTT_OUT_RIGHT
AD24 J18 AJ17 V30 AF23
AE23 J21 C24 F22 R2 AG24
AE22 AG27 K2 AH3 V29 AF17
AN19 AK15 C22 AK10 V28 AN24
V8 AF11 AN1 AM10 R5 H3
K8 AD23 B14 F16 V27
**
VCCP52 VCCP144 VSS8 VSS92 VSS177 R218 49.9 +/-1% r0402h4 HCOMP6
AE21 AM15 K7 AJ23 R7 P24
VCCP53 VCCP145 VSS9 VSS93 VSS178 VSS263 Dummy
AM30 AF8 AE16 F13 E20 AE20
VCCP54 VCCP146 VSS10 VSS94 VTT_OUT_LEFT VSS179 VSS264 R220 49.9 +/-1% r0402h4 HCOMP7
AE19 AK21 B11 AG7 AN10 AE17
VCCP55 VCCP147 VSS11 VSS95 VSS180 VSS265 Reserved
AC30 AG30 AL10 F10 V25 E27
AE15 AJ21 AK23 L26 T3 T7
VCCP57 VCCP149 VSS13 VSS97 R213 VSS182 VSS267 10 mils width
M30 AM11 H12 AD4 V24 R30
K27
VCCP58
VCCP59
VCCP150
VCCP151
AL11 AF7
VSS14
VSS15
VSS98
VSS99
H11 *
51 Ohm V23
VSS183
VSS184
VSS268
VSS269
AJ27 7 mils spacing to low speed signals
14mils spacing to high speed signals
M24 AJ11 AK7 L24 +/-5% T6 AB1
VCCP60 VCCP152 VSS16 VSS100 r0402h4 VSS185 VSS270 max. 1200mils
AN21 K30 H7 L23 AL7 AM4
T8 AL14 E14 AM23 E25 V26
B AC28 AN30 L28 A15 U1 AA23 B
N25 AH25 Y5 AH10 R29 AL28
AE18 AL12 E11 H29 TP17 R28 AF20
VCCP65 VCCP157 VSS21 VSS105 VSS190 VSS275 R155 24.9 HCOMP8
W26 AJ9 AL16 B24 R27 AG23
VCCP66 VCCP158 VSS22 VSS106 VSS191 VSS276 +/-1%
AD25 AK11 AL24 L3 R26
M8 AG14 AK13 H27 R25
N30 N29 TP68 AL3 A21 U7
AD26 AL30 D21 AE2 R24
VCCP70 VCCP162 VSS26 VSS110 VSS195 15 mils width
AJ26 AJ25 AL20 AJ29 R23
*
VCCP71 VCCP163 VSS27 VSS111 VSS196 7 mils spacing to low speed signals
AM29 AH9 D18 A24 P30
VCCP72 VCCP164 VSS28 VSS112 VSS197 14mils spacing to high speed signals
M25 J29 AN2 AK27 V3
VCCP73 VCCP165 VRDSEL VSS29 VSS113 R115 VSS198 max. 1200mils
M26 J11 AK16 AK28 P29
VCCP74 VCCP166 VSS30 VSS114 1K VSS199 IMPSEL
L8 K25 AK20 B20 AF16 F6
VCCP75 VCCP167 VSS31 VSS115 +/-5% VSS200 RSVD26
U25 P8 AM27 AM20 AE10
VCCP76 VCCP168 VSS32 VSS116 r0402h4 VSS201 HCOMP6
Y8 K23 AM1 H26 AF13 Y3
VCCP77 VCCP169 VSS33 VSS117 Dummy VSS202 RSVD28 HCOMP7
AJ12 AL19 AL13 B17 H6 AE3
VCCP78 VCCP170 VSS34 VSS118 VSS203 RSVD29
AD27 AM8 AL17 H25 A18
*
VCCP79 VCCP171 VSS35 VSS119 VSS204 R205 51 Ohm IMPSEL
U23 T26 C19 H24 A2 E7
VCCP80 VCCP172 VSS36 VSS120 VSS205 RSVD31 HCOMP8 +/-5% r0402h4
M23 N28 E28 AA3 E2 B13
AG29 AH12 AH7 AA7 D9 D14
N27 AL22 AK30 H23 C4 E6
AM22 AN15 D24 AA6 A6 D1
U28 AJ8 H10 D6 E5
VCCP85 VCCP177 VSS125 VSS210 RSVD36
K28 U26
VCCP86 VCCP178
U8 AJ19 Socket-IntelPrescottCPU Socket-IntelPrescottCPU
VCCP87 VCCP179
AK18 T27
VCCP88 VCCP180
AD8 AK8
VCCP89 VCCP181
A K24 AN12 A
VCCP90 VCCP182
AH28 AG9
VCCP91 VCCP183
AH21 N26
VCCP92 VCCP184
Socket-IntelPrescottCPU FOXCONN PCEG

Title
LGA775-2
Custom G31M04 A

5 4 3 2 1

14 HAJ[35..3]
5
HAJ3
HAJ4
J42
HA3#
U1MCH
U12B
HD0#
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R40 HDJ0
HDJ1
HDJ[63..0]
4
HDJ[63..0] 14
3
QQ:453100829 2
U12E
1
Placed both Resistors close to GMCH

Within 750 mils
L39 P41 W=4 mils, S=10 mils from GMCH to connector
HAJ5 J40 HA4# HD1# R41 HDJ2
**
HAJ6 HA5# HD2# HDJ3 U1MCH BSEL0 HSYNC_P R139 39 +/-1%
L37 N40 G20 C15
HA6# HD3# U12A BSEL0 HSYNC HSYNC 24
HAJ7 L36 R42 HDJ4 BSEL1 J20 D15 VSYNC_P R140 39 +/-1%
HA7# HD4# BSEL1 VSYNC VSYNC 24
HAJ8 K42 M39 HDJ5 EXP_RXP0 F15 D11 EXP_TXP0 BSEL2 J18 Modify by Steven 051707 Apply 0402 or not
HA8# HD5# 23 EXP_RXP0 EXP_RXP0 EXP_TXP0 EXP_TXP0 23 BSEL2
HAJ9 N32 N41 HDJ6 EXP_RXN0 G15 D12 EXP_TXN0 TP16 TP_ALLZTEST K20 B18
HA9# HD6# 23 EXP_RXN0 EXP_RXN0* EXP_TXN0* EXP_TXN0 23 ALLZTEST RED RED 24
HAJ10 N34 N42 HDJ7 EXP_RXP1 K15 B11 EXP_TXP1 F20 C19
HA10# HD7# 23 EXP_RXP1 EXP_RXP1 EXP_TXP1 EXP_TXP1 23 XORTEST GREEN GREEN 24
HAJ11 M38 L41 HDJ8 EXP_RXN1 J15 A10 EXP_TXN1 G18 B20
FSB
HA11# HD8# 23 EXP_RXN1 EXP_RXN1* EXP_TXN1* EXP_TXN1 23 RESERVED_24 BLUE BLUE 24
HAJ12 N37 J39 HDJ9 EXP_RXP2 F12 C10 EXP_TXP2 GMCH_EXP_SLR E18 C18 R152 R153 R151
HA12# HD9# 23 EXP_RXP2 EXP_RXP2 EXP_TXP2 EXP_TXP2 23 EXP_SLR RED#
HAJ13 M36 L42 HDJ10 EXP_RXN2 E12 D9 EXP_TXN2 K17 D19 150 150 150
HA13# HD10# 23 EXP_RXN2 EXP_RXN2* EXP_TXN2* EXP_TXN2 23 RESERVED_25 GREEN# * * *
VGA
HAJ14 R34 J41 HDJ11 EXP_RXP3 J12 B9 EXP_TXP3 GMCH_EXP_EN_HDR J17 D20 +/ -1% +/ -1% +/ -1%
D HA14# HD11# 23 EXP_RXP3 EXP_RXP3 EXP_TXP3 EXP_TXP3 23 EXP_EN BLUE# D
HAJ15 N35 K41 HDJ12 EXP_RXN3 H12 B7 EXP_TXN3 H18 r0402h4 r0402h4 r0402h4
HA15# HD12# 23 EXP_RXN3 EXP_RXN3* EXP_TXN3* EXP_TXN3 23 RESERVED
HAJ16 N38 G40 HDJ13 EXP_RXP4 J11 D7 EXP_TXP4 L13 DDCA_DATA
HA16# HD13# 23 EXP_RXP4 EXP_RXP4 EXP_TXP4 EXP_TXP4 23 DDC_DATA DDCA_DATA 24
HAJ17 U37 F41 HDJ14 EXP_RXN4 H11 D6 EXP_TXN4 L17 M13 DDCA_CLK
HA17# HD14# 23 EXP_RXN4 EXP_RXN4* EXP_TXN4* EXP_TXN4 23 RESERVED_1 DDC_CLK DDCA_CLK 24
HAJ18 N39 F42 HDJ15 EXP_RXP5 F7 B5 EXP_TXP5 N17 Placed close to
HA18# HD15# 23 EXP_RXP5 EXP_RXP5 EXP_TXP5 EXP_TXP5 23 RESERVED_2
HAJ19 R37 C42 HDJ16 EXP_RXN5 E7 B6 EXP_TXN5 N18 A20 REFSET GMCH within
HA19# HD16# 23 EXP_RXN5 EXP_RXN5* EXP_TXN5* EXP_TXN5 23 RESERVED_3 REFSET
HAJ20 P42 D41 HDJ17 EXP_RXP6 E5 B3 EXP_TXP6 N15 300 mils
HA20# HD17# 23 EXP_RXP6 EXP_RXP6 EXP_TXP6 EXP_TXP6 23 RESERVED_4
HAJ21 R39 F38 HDJ18 EXP_RXN6 F6 B4 EXP_TXN6 M20 C14 CK_96M_P_GMCH
HA21# HD18# 23 EXP_RXN6 EXP_RXN6* EXP_TXN6* EXP_TXN6 23 RESERVED_5 DREFCLKP CK_96M_P_GMCH 8
HAJ22 V36 G37 HDJ19 EXP_RXP7 C2 F2 EXP_TXP7 L15 D13 CK_96M_N_GMCH
HA22# HD19# 23 EXP_RXP7 EXP_RXP7 EXP_TXP7 EXP_TXP7 23 RESERVED_6 DREFCLKN CK_96M_N_GMCH 8
HAJ23 R38 E42 HDJ20 EXP_RXN7 D2 E2 EXP_TXN7 Controller Link Routing L18 L12
HA23# HD20# 23 EXP_RXN7 EXP_RXN7* EXP_TXN7* EXP_TXN7 23 RESERVED_7 VCC 1D25V_MCH
HAJ24 U36 E39 HDJ21 EXP_RXP8 G6 F4 EXP_TXP8 1. width=4 mils, Spacing=7 mils M18 M11
PCIE
HA24# HD21# 23 EXP_RXP8 EXP_RXP8 EXP_TXP8 EXP_TXP8 23 RESERVED_8 VSS
HAJ25 U33 E37 HDJ22 EXP_RXN8 G5 G4 EXP_TXN8 2. CL_CLK and CL_DATA should be length
HA25# HD22# 23 EXP_RXN8 EXP_RXN8* EXP_TXN8* EXP_TXN8 23
HAJ26 R35 C39 HDJ23 EXP_RXP9 L9 J4 EXP_TXP9 matched to within 100 mils
HA26# HD23# 23 EXP_RXP9 EXP_RXP9 EXP_TXP9 EXP_TXP9 23
HAJ27 V33 B39 HDJ24 EXP_RXN9 L8 K3 EXP_TXN9
HA27# HD24# 23 EXP_RXN9 EXP_RXN9* EXP_TXN9* EXP_TXN9 23
HAJ28 V35 G33 HDJ25 EXP_RXP10 M8 L2 EXP_TXP10 TP19 AD12 F13 TP_MCH_F13
HA28# HD25# 23 EXP_RXP10 EXP_RXP10 EXP_TXP10 EXP_TXP10 23 CL_DATA RESERVED_001 TP20
HAJ29 Y34 A37 HDJ26 EXP_RXN10 M9 K1 EXP_TXN10 TP18 AD13 F17
HA29# HD26# 23 EXP_RXN10 EXP_RXN10* EXP_TXN10* EXP_TXN10 23 CL_CLK RESERVED_23
HAJ30 V42 F33 HDJ27 EXP_RXP11 M4 N2 EXP_TXP11 CL_VREF_MCH AM5 A14 TP_MCH_A14
23 EXP_RXP11 EXP_TXP11 23 TP22
MISC
HAJ31 V38 HA30# HD27# E35 HDJ28 EXP_RXN11 L4 EXP_RXP11 EXP_TXP11 M2 EXP_TXN11 PLTRSTJ R199 1.65KOhm CL_RST AA12 CL_VREF RESERVED_26 AM18 ICH_PLTRSTJ
HA31# HD28# 23 EXP_RXN11 EXP_RXN11* EXP_TXN11* EXP_TXN11 23 CL_RST# RSTIN# PLTRSTJ 25,29,35
HAJ32 Y36 K32 HDJ29 EXP_RXP12 M5 P3 EXP_TXP12 +/-1% r0402h4 AM15 AM17 PWRGD_3V
EXP_TXP12 23 PWRGD_3V 25,35
*
HAJ33 HA32# HD29# HDJ30 23 EXP_RXP12 EXP_RXN12 EXP_RXP12 EXP_TXP12 EXP_TXN12 R197 1K CL_PWROK PWROK ICH_SYNCJ
Y38 H32 M6 N4 J13
HA33# HD30# 23 EXP_RXN12 EXP_RXN12* EXP_TXN12* EXP_TXN12 23 ICH_SYNC# ICH_SYNCJ 25
HAJ34 Y39 B34 HDJ31 EXP_RXP13 R9 R2 EXP_TXP13 +/-1% r0402h4
HA34# HD31# 23 EXP_RXP13 EXP_RXP13 EXP_TXP13 EXP_TXP13 23
HAJ35 AA37 J31 HDJ32 EXP_RXN13 R10 P1 EXP_TXN13 A42 TP_MCH_DET_N
HA35# HD32# 23 EXP_RXN13 EXP_RXN13* EXP_TXN13* EXP_TXN13 23 NC TP23
F32 HDJ33 EXP_RXP14 T4 U2 EXP_TXP14 PWRGD_3V
HD33# 23 EXP_RXP14 EXP_RXP14 EXP_TXP14 EXP_TXP14 23
M31 HDJ34 EXP_RXN14 R4 T2 EXP_TXN14 AA10
14 HREQJ[4..0] HD34# 23 EXP_RXN14 EXP_RXN14* EXP_TXN14* EXP_TXN14 23 RESERVED_9
HREQJ0 F40 E31 HDJ35 EXP_RXP15 R6 V3 EXP_TXP15 AA9 BC43 TP_MCH_CGC_1
HREQ0# HD35# 23 EXP_RXP15 EXP_RXP15 EXP_TXP15 EXP_TXP15 23 RESERVED_10 TEST0 TP24
HREQJ1 L35 K31 HDJ36 EXP_RXN15 R7 U4 EXP_TXN15 AA11 BC1 TP_MCH_CGC_2
HREQ1# HD36# 23 EXP_RXN15 EXP_RXN15* EXP_TXN15* EXP_TXN15 23 RESERVED_11 TEST1 TP26
HREQJ2 L38 G31 HDJ37 Y12 A43 TP_MCH_CGC_3
HREQ2# HD37# RESERVED_12 TEST2 TP25
HREQJ3 G43 K29 HDJ38 DMI_RXP0 W2 V7 C2590.1uF 16V, X7R, +/-10% DMI_TXP0
DMI_TXP0 25
********
HREQJ4 J37 HREQ3# HD38# F31 HDJ39 25 DMI_RXP0 DMI_RXN0 V1 DMI_RXP0 DMI_TXP0 V6 C2580.1uF 16V, X7R, +/-10% DMI_TXN0 U30
HREQ4# HD39# 25 DMI_RXN0 DMI_RXN0* DMI_TXN0* DMI_TXN0 25 RESERVED_13
J29 HDJ40 DMI_RXP1 Y8 W4 C2480.1uF 16V, X7R, +/-10% DMI_TXP1 U31 N20
HD40# 25 DMI_RXP1 DMI_RXP1 DMI_TXP1 DMI_TXP1 25 RESERVED_14 NC_1
M34 F29 HDJ41 DMI_RXN1 Y9 Y4 C2530.1uF 16V, X7R, +/-10% DMI_TXN1 R29 BC42
14 HADSTBJ0 HADSTB0# HD41# 25 DMI_RXN1 DMI_RXN1* DMI_TXN1* DMI_TXN1 25 RESERVED_15 NC_2
DMI
U34 L27 HDJ42 DMI_RXP2 AA7 AC8 C2610.1uF 16V, X7R, +/-10% DMI_TXP2 R30 BC2
14 HADSTBJ1 HADSTB1# HD42# 25 DMI_RXP2 DMI_RXP2 DMI_TXP2 DMI_TXP2 25 RESERVED_16 NC_3
K27 HDJ43 DMI_RXN2 AA6 AC9 C2660.1uF 16V, X7R, +/-10% DMI_TXN2 BB43
HD43# 25 DMI_RXN2 DMI_RXN2* DMI_TXN2* DMI_TXN2 25 NC_4
L40 H26 HDJ44 DMI_RXP3 AB3 Y2 C2570.1uF 16V, X7R, +/-10% DMI_TXP3 U12 BB1
14 HDSTBPJ0 HDSTBP0# HD44# 25 DMI_RXP3 DMI_RXP3 DMI_TXP3 DMI_TXP3 25 RESERVED_17 NC_5
M43 L26 HDJ45 DMI_RXN3 AA4 AA2 C2640.1uF 16V, X7R, +/-10% DMI_TXN3 U11 B43
14 HDSTBNJ0 HDSTBN0# HD45# 25 DMI_RXN3 DMI_RXN3* DMI_TXN3* DMI_TXN3 25 RESERVED_18 NC_6
HDBIJ0 M40 J26 HDJ46 R12 B42 3D3V_SYS
14 HDBIJ0 HDINV0# HD46# RESERVED_19 NC_7
G35 M26 HDJ47 R13 B2
14 HDSTBPJ1 HDSTBP1# HD47# RESERVED_20 NC_8
H33 C33 HDJ48 CK_PE_100M_P_GMCH B12 R178 5 OF 7
14 HDSTBNJ1 HDSTBN1# HD48# 8 CK_PE_100M_P_GMCH GCLKP
C HDBIJ1 J33 C35 HDJ49 CK_PE_100M_N_GMCH B13 AC11 GMCH_EXP_COMP 24.9 C
14 HDBIJ1 HDINV1# LE82G31 HD49# 8 CK_PE_100M_N_GMCH GCLKN* EXP_COMPO 1D25V_MCH
G27 E41 HDJ50 AC12 +/-1%
14 HDSTBPJ2 HDSTBP2# HD50# HDJ51 EXP_COMPI
14 HDSTBNJ2 H27 B41 G17 LE82G31
HDBIJ2 G29 HDSTBN2# HD51# D42 HDJ52 23 SDVO_CTRLDATA
E17 SDVO_CTRLDATA width 10 mils, spacing 6 mils at breakout
14 HDBIJ2
*
HDINV2# HD52# HDJ53 23 SDVO_CTRLCLK SDVO_CTRLCLK 2 OF 7 bga1226_1h25 ICH_SYNCJ R148 1K
B38 C40 10 mils after that
14 HDSTBPJ3 HDSTBP3# HD53# HDJ54 Del R934,R935 0Ohm RES +/-5% r0402h4
D38 D35 LE82G31
14 HDSTBNJ3 HDBIJ3 HDSTBN3# HD54# HDJ55
14 HDBIJ3 E33 B40
HDINV3# HD55# HDJ56 bga1226_1h25 R200,R201,R205,R208,R209,R210 USE 0 OHM FOR 946PL.
C38
HD56# HDJ57 DUMMY R192,R194.
W40 D37
*
14 HADSJ HADS# HD57# HDJ58 PWRGD_3V
Y40 B33 R323 10K
14 HTRDYJ HTRDY# HD58# HDJ59 +/-5% Dummy
W41 D33
14 HDRDYJ
T43 HDRDY# HD59# C34 HDJ60
14 HDEFERJ HDEFER# HD60# HDJ61
Y43 B35
14 HITMJ
U42 HHITM# HD61# A32 HDJ62 1D25V_MCH
14 HITJ HHIT# HD62# HDJ63
V41 D32
14 HLOCKJ HLOCK# HD63#
AA42
****
14 HBR0J HBREQ0# HSWING DMI_RXP0
W42 B25 R163 4.7K +/-5%
14 HBNRJ HBNR# HSWING HRCOMP R150 1.3K REFSET
G39 D23
14 HBPRIJ HBPRI# HRCOMP HSCOMP DMI_RXP1 R171 4.7K +/-5% +/-1%
14 HDBSYJ
U40 C25
U41 HDBSY# HSCOMP D25 HSCOMPJ
14 HRSJ0 HRS0# HSCOMP# MCH_GTLREF DMI_RXP2 R172 4.7K +/-5%
AA41 D24
14 HRSJ1
U39 HRS1# HDVREF B24 placed close to GMCH within 500 mils
14 HRSJ2 HRS2# HACCVREF DMI_RXP3 R175 4.7K +/-5% 4 mils width
C31 R32 CK_200M_P_GMCH 8
14 HCPURSTJ HCPURST# HCLKP U32 6 mils spacing to static signals
HCLKN CK_200M_N_GMCH 8
12 mils spacing to toppling signals
1 OF 7
bga1226_1h25
FSB_VTT FSB_VTT COMP SIGNAL TERMINATION

*
R136 R138 49.9 HSCOMPJ

* 301 Resistor and Capacitor +/-1% r0402h4 C186
+/-1% next to each other. 2.7pF
B
* 50V, NPO, +/-0.25pF B
Dummy
*
R145 49.9 HSWING
*
+/-1% r0402h4 FSBSEL0 R401 10K BSEL0
*
R137 49.9 HSCOMP +/-5% 1D25V_MCH
*R135
100 Ohm
*
C178
10nF
+/-1% r0402h4
*
C185
2.7pF
+/-1% 25V, X7R, +/-10% 50V, NPO, +/-0.25pF FSB_VTT
Dummy
23 GMCH_EXP_EN_HDR
GMCH_EXP_EN_HDR *R194
1K
HSWING voltage should be 0.25*FSB_VTT +/-1%
10 mils width, 10 mils spacing R404 r0402h4
max. 3 inches long * 470 CL_VREF_MCH
4 mils width, 6 mils spacing in the breakout FSBSEL0 +/-5% JP1(P1 & P2)
8 FSBSEL0
4 mils width, 14 mils spacing after the breakout
max. 750 mils
JP1
*R196
392
*
C288
0.1uF
0.349V
routed on a single layer and matched within 50mils FSBSEL1 3 +/-1% 16V, Y5V, +80%/-20%
*
8 FSBSEL1 3 R402 10K BSEL1 r0402h4
2
HRCOMP R154 2 +/-5% FSBSEL1
1 Place close to VREF Pin
16.5 Ohm +/-1% FSBSEL2 1 Jumper
8 FSBSEL2
Reserved
Header_1X3
10 mils width, 7 mils spacing min. 4 mils width
max. 500 mils 10 mils spacing
*
GMCH_EXP_SLR
5 on 5 mils in breakout, max 250 mils 1D25V_MCH R132 1K 5 mils min. for max. of 300 mils in breakout
+/-5% r0402h4 JP2(P1 & P2)
ATX: 1 JP2
BTX: 0 3
*
3 2 R403 10K BSEL2
2 +/-5%FSBSEL2
1
1
FSB_VTT Jumper
Not used for CoreTM2 Duo and Wolfdale with G31 Chipset Header_1X3 Reserved
Del or not in G31
*
*R134 R131
100 Ohm +/-5%
+/-1%
0
MCH_GTLREF_CPU 14
*
A R144 MCH_GTLREF A
C171 10
* 1uF *R130
200 +/-1%
*
C187
220pF
+/-1% 50V, NPO, +/-5%
10V, Y5V, +80%/-20%
GTLREF voltage should be 0.63*VTT = 0.75V FOXCONN PCEG

12 mils width, 15 mils spacing
divider should be within 1.5" of the GTLREF pin Title
220pF caps should be placed near MCH pin BearLake-GMCH-1
place series resistor as close to divider
Resistor and Capacitor next to each other
C G31M04 A

5 4 3 2 1

19,20 M_MAA_A[14..0]
5
M_MAA_A0
M_MAA_A1
www.sp860.com
BA31
U12C
SMA_A0
U1MCH
4
SDQS_A0
AU4 M_DQS_A0
M_DQS_AJ0
M_DQS_A[7..0] 20
M_DQS_AJ[7..0] 20
3
QQ:453100829
21,22 M_MAA_B[14..0] M_MAA_B0
M_MAA_B1
M_MAA_B2
2
BB17
AY17
U12D
SMA_B0
SMA_B1
U1MCH
SDQS_B0
SDQS_B0#
AV6
AU5
M_DQS_B0
M_DQS_BJ0
M_DQM_B0
1
M_DQS_B[7..0] 22
M_DQS_BJ[7..0] 22
M_DQM_B[7..0] 22
BB25 AR3 M_DQM_A[7..0] 20 BA17 AR7 M_DATA_B[63..0] 22
M_MAA_A2 BA26 SMA_A1 SDQS_A0# AR2 M_DQM_A0 M_MAA_B3 BC16 SMA_B2 SDM_B0
SMA_A2 SDM_A0 M_DATA_A[63..0] 20 SMA_B3
M_MAA_A3 BA25 M_MAA_B4 AW15 AN7 M_DATA_B0
M_MAA_A4 SMA_A3 M_DATA_A0 M_MAA_B5 SMA_B4 SDQ_B0 M_DATA_B1
AY25 AR5 BA15 AN8
M_MAA_A5 SMA_A4 SDQ_A0 M_DATA_A1 M_MAA_B6 SMA_B5 SDQ_B1 M_DATA_B2
BA23 AR4 BB15 AW5
AY24 AV3 BA14 AW7
AY23 AV2 AY15 AN5
BB23 AP3 BB14 AN6
BA22 AP2 AW18 AN9
AY33 AU1 BB13 AU7
M_MAA_A11 SMA_A10 SDQ_A6 M_DATA_A7 M_MAA_B12 SMA_B11 SDQ_B7
D BB22 AV4 BA13 M_DQS_B[7..0] 22 D
M_MAA_A12 SMA_A11 SDQ_A7 M_MAA_B13 SMA_B12 M_DQS_B1
AW21 M_DQS_A[7..0] 20 AY29 AR12 M_DQS_BJ[7..0] 22
M_MAA_A13 AY38 SMA_A12 BB3 M_DQS_A1 M_MAA_B14 AY13 SMA_B13 SDQS_B1 AP12 M_DQS_BJ1
SMA_A13 SDQS_A1 M_DQS_AJ[7..0] 20 SMA_B14 SDQS_B1# M_DQM_B[7..0] 22
M_MAA_A14 BA21 BA4 M_DQS_AJ1 AW9 M_DQM_B1
SMA_A14 SDQS_A1# M_DQM_A[7..0] 20 SDM_B1 M_DATA_B[63..0] 22
BA2 M_DQM_A1 BA27
SDM_A1 M_DATA_A[63..0] 20 21,22 M_WE_BJ SWE_B#
BB34 AW29 AT11 M_DATA_B8
19,20 M_WE_AJ SWE_A# M_DATA_A8 21,22 M_CAS_BJ SCAS_B# SDQ_B8 M_DATA_B9
AY35 AY2 AW26 AU11
19,20 M_CAS_AJ SCAS_A# SDQ_A8 M_DATA_A9 21,22 M_RAS_BJ SRAS_B# SDQ_B9 M_DATA_B10
BB33 AY3 AP13
19,20 M_RAS_AJ SRAS_A# SDQ_A9 BB5 M_DATA_A10 21,22 M_BS_B[2..0] M_BS_B0 AY19 SDQ_B10 AR13 M_DATA_B11
M_BS_A0 SDQ_A10 M_DATA_A11 M_BS_B1 SBS_B0 SDQ_B11 M_DATA_B12
BA33 AY6 BA18 AR11
M_BS_A1 SBS_A0 SDQ_A11 M_DATA_A12 M_BS_B2 SBS_B1 SDQ_B12 M_DATA_B13
AW32 AW2 BC12 AU9
M_BS_A2 SBS_A1 SDQ_A12 M_DATA_A13 SBS_B2 SDQ_B13 M_DATA_B14
BB21 AW3 AV12
SBS_A2 SDQ_A13 BA5 M_DATA_A14 BB27 SDQ_B14 AU12 M_DATA_B15
19,20 M_BS_A[2..0] SDQ_A14 M_DATA_A15 21,22 M_SCS_B0J SCS_B0# SDQ_B15
AW35 BB4 BB30 M_DQS_B[7..0] 22
19,20 M_SCS_A0J SCS_A0# SDQ_A15 21,22 M_SCS_B1J SCS_B1# M_DQS_B2
BA35 M_DQS_A[7..0] 20 AY27 AP15 M_DQS_BJ[7..0] 22
19,20 M_SCS_A1J
BA34 SCS_A1# BB9 M_DQS_A2 AY31 SCS_B2# SDQS_B2 AR15 M_DQS_BJ2
SCS_A2# SDQS_A2 M_DQS_AJ[7..0] 20 SCS_B3# SDQS_B2# M_DQM_B[7..0] 22
BB38 BA9 M_DQS_AJ2 AW13 M_DQM_B2
SCS_A3# SDQS_A2# M_DQM_A[7..0] 20 21,22 M_SCKE_B[1..0] SDM_B2 M_DATA_B[63..0] 22
AY9 M_DQM_A2 M_SCKE_B0 AY12
19,20 M_SCKE_A[1..0] SDM_A2 M_DATA_A[63..0] 20 SCKE_B0
M_SCKE_A0 BC20 M_SCKE_B1 AW12 AU15 M_DATA_B16
M_SCKE_A1 SCKE_A0 M_DATA_A16 SCKE_B1 SDQ_B16 M_DATA_B17
AY20 AY7 BB11 AV13
SCKE_A1 SDQ_A16 M_DATA_A17 SCKE_B2 SDQ_B17 M_DATA_B18
AY21 BC7 BA11 AU17
SCKE_A2 SDQ_A17 M_DATA_A18 21,22 M_ODT_B[1..0] M_ODT_B0 SCKE_B3 SDQ_B18 M_DATA_B19
BA19 AW11 BA29 AT17
SCKE_A3 SDQ_A18 M_DATA_A19 M_ODT_B1 SODT_B0 SDQ_B19 M_DATA_B20
AY11 BA30 AU13
19,20 M_ODT_A[1..0] M_ODT_A0 SDQ_A19 M_DATA_A20 SODT_B1 SDQ_B20 M_DATA_B21
AY37 BB6 BB29 AM13
M_ODT_A1 SODT_A0 SDQ_A20 M_DATA_A21 SODT_B2 SDQ_B21 M_DATA_B22
BA38 BA6 BB31 AV15
SODT_A1 SDQ_A21 M_DATA_A22 SODT_B3 SDQ_B22 M_DATA_B23
BB35 BA10 AW17
SODT_A2 SDQ_A22 M_DATA_A23 SDQ_B23
BA39 BB10 AV31 M_DQS_B[7..0] 22
SODT_A3 SDQ_A23 22 CK_M_200M_P_DDR0_B SCLK_B0 M_DQS_B3
M_DQS_A[7..0] 20 AW31 AT24 M_DQS_BJ[7..0] 22
AU31 AT20 M_DQS_A3 22 CK_M_200M_N_DDR0_B
AU27 SCLK_B0# SDQS_B3 AU26 M_DQS_BJ3
20 CK_M_200M_P_DDR0_A SCLK_A0 SDQS_A3 M_DQS_AJ[7..0] 20 22 CK_M_200M_P_DDR1_B SCLK_B1 SDQS_B3# M_DQM_B[7..0] 22
AR31 AU18 M_DQS_AJ3 AT27 AP23 M_DQM_B3
20 CK_M_200M_N_DDR0_A SCLK_A0# SDQS_A3# M_DQM_A[7..0] 20 22 CK_M_200M_N_DDR1_B SCLK_B1# SDM_B3 M_DATA_B[63..0] 22
AP27 AN18 M_DQM_A3 AV32
20 CK_M_200M_P_DDR1_A SCLK_A1 SDM_A3 M_DATA_A[63..0] 20 22 CK_M_200M_P_DDR2_B SCLK_B2
AN27 AT32 AV24 M_DATA_B24
20 CK_M_200M_N_DDR1_A SCLK_A1# M_DATA_A24 22 CK_M_200M_N_DDR2_B SCLK_B2# SDQ_B24 M_DATA_B25
AV33 AT18 AU29 AT23
20 CK_M_200M_P_DDR2_A SCLK_A2 SDQ_A24 M_DATA_A25 SCLK_B3 SDQ_B25 M_DATA_B26
AW33 AR18 AR29 AT26
20 CK_M_200M_N_DDR2_A SCLK_A2# SDQ_A25 M_DATA_A26 SCLK_B3# SDQ_B26 M_DATA_B27
AP29 AU21 AV29 AP26
AP31 SCLK_A3 SDQ_A26 AT21 M_DATA_A27 AW27 SCLK_B4 SDQ_B27 AU23 M_DATA_B28
SCLK_A3# SDQ_A27 M_DATA_A28 SCLK_B4# SDQ_B28 M_DATA_B29
AM26 AP17 AN33 AW23
SCLK_A4 SDQ_A28 M_DATA_A29 SCLK_B5 SDQ_B29 M_DATA_B30
AM27 AN17 AP32 AR24
C AT33 SCLK_A4# SDQ_A29 AP20 M_DATA_A30 SCLK_B5# SDQ_B30 AN26 M_DATA_B31 C
SCLK_A5 SDQ_A30 M_DATA_A31 SDQ_B31
AU33 AV20
SCLK_A5# SDQ_A31 M_DQS_B[7..0] 22
AW39 M_DQS_B4
M_DQS_A[7..0] 20 SDQS_B4 M_DQS_BJ[7..0] 22
AR41 M_DQS_A4 AU39 M_DQS_BJ4
SDQS_A4 M_DQS_AJ[7..0] 20 SDQS_B4# M_DQM_B[7..0] 22
AR40 M_DQS_AJ4 AU37 M_DQM_B4
SDQS_A4# M_DQM_A[7..0] 20 SDM_B4 M_DATA_B[63..0] 22
AU43 M_DQM_A4
SDM_A4 M_DATA_A[63..0] 20
AW37 M_DATA_B32
M_DATA_A32 SDQ_B32 M_DATA_B33
AV42 AV38
SDQ_A32 M_DATA_A33 SDQ_B33 M_DATA_B34
AU40 BB2 AN36
SDQ_A33 M_DATA_A34 RESERVED_1 SDQ_B34 M_DATA_B35
AP42 AW42 AN37
AN39 AN32 AU35
SDQ_A35 AV40 M_DATA_A36 AM31 RESERVED_3 SDQ_B36 AR35 M_DATA_B37
AV41 AG32 AN35
SDQ_A37 AR42 M_DATA_A38 AF32 RESERVED_5 SDQ_B38 AR37 M_DATA_B39
SDQ_A38 M_DATA_A39 TP_MCH_AP21 RESERVED_6 SDQ_B39
AP41 AP21
SDQ_A39 TP51 SM_SLEWIN0 M_DQS_B[7..0] 22
TP_MCH_AA39 AA39 AL35 M_DQS_B5
M_DQS_A[7..0] 20 TP52 SM_SLEWIN1 SDQS_B5 M_DQS_BJ[7..0] 22
AL41 M_DQS_A5 AL34 M_DQS_BJ5
SDQS_A5 M_DQS_AJ[7..0] 20 SDQS_B5# M_DQM_B[7..0] 22
AL40 M_DQS_AJ5 AM37 M_DQM_B5
SDQS_A5# M_DQM_A[7..0] 20 SDM_B5 M_DATA_B[63..0] 22
AM43 M_DQM_A5
AM35 M_DATA_B40
M_DATA_A40 SDQ_B40 M_DATA_B41
AN41 AM38
SDQ_A40 AM39 M_DATA_A41 SDQ_B41 AJ34 M_DATA_B42
AK42 AL38
SDQ_A42 AK41 M_DATA_A43 SDQ_B43 AR39 M_DATA_B44
AN40 AM34
AN42 AL37
SDQ_A45 AL42 M_DATA_A46 SDQ_B46 AL32 M_DATA_B47
SDQ_A46 M_DATA_A47 SDQ_B47
AL39
SDQ_A47 M_DQS_B[7..0] 22
AG35 M_DQS_B6
AG42 M_DQS_A6 AG36 M_DQS_BJ6
SDQS_A6
SDQS_A6#
AG41 M_DQS_AJ6
M_DQM_A6
M_DQS_AJ[7..0] 20
M_DQM_A[7..0] 20
DDR_1 SDQS_B6#
SDM_B6
AG39 M_DQM_B6
M_DQM_B[7..0] 22
M_DATA_B[63..0] 22
AG40
AG38 M_DATA_B48
AJ40 M_DATA_A48 SDQ_B48 AJ38 M_DATA_B49
AH43 AF35
AF39 AF33
AE40 AJ37
SDQ_A51 AJ42 M_DATA_A52 SDQ_B52 AJ35 M_DATA_B53
B SDQ_A52 SDQ_B53 B
AJ41 M_DATA_A53 TP_MCH_AM21 AM21 AG33 M_DATA_B54
SDQ_A53 TP53 RESERVED_7 SDQ_B54
AF41 M_DATA_A54 AF34 M_DATA_B55
SDQ_A54 M_DATA_A55 DDR_GMCH_VREF SDQ_B55
AF42 AM6 M_DQS_B[7..0] 22
SDQ_A55 SVREF M_DQS_B7
AC36
AC42 M_DQS_A7 AC37 M_DQS_BJ7
DDR_0 SDQS_A7
SDQS_A7#
AC41 M_DQS_AJ7
M_DQS_AJ[7..0] 20
M_DQM_A[7..0] 20
SDQS_B7#
SDM_B7
AD38 M_DQM_B7
M_DQM_B[7..0] 22
M_DATA_B[63..0] 22
AC40 M_DQM_A7
AD36 M_DATA_B56
TP_MCH_AN21 AN21 AD40 M_DATA_A56 SRCOMP0 AN2 SDQ_B56 AC33 M_DATA_B57
TP54 RESERVED SDQ_A56 SRCOMP0 SDQ_B57
AD43 M_DATA_A57 SRCOMP1 AN3 AA34 M_DATA_B58
SDQ_A57 M_DATA_A58 SRCOMP2 SRCOMP1 SDQ_B58 M_DATA_B59
AB41 BB40 AA36
SDQ_A58 M_DATA_A59 SRCOMP3 SRCOMP2 SDQ_B59 M_DATA_B60
AA40 BA40 AD34
SDQ_A59 M_DATA_A60 DDR2 Compensation Group Signals SMRCOMPVOL SRCOMP3 SDQ_B60 M_DATA_B61
AE42 AM8 AF38
SDQ_A60 AE41 M_DATA_A61 SMRCOMPVOH AM10 SMRCOMPVOL SDQ_B61 AC34 M_DATA_B62
SDQ_A61 M_DATA_A62 SMRCOMPVOH SDQ_B62 M_DATA_B63
AC39 BB19 AA33
SDQ_A62 M_DATA_A63 R187 20 SRCOMP0 RESERVED SDQ_B63
AB42
SDQ_A63 +/-1% 4 OF 7
3 OF 7
1D8V_STR LE82G31 bga1226_1h25

LE82G31 bga1226_1h25
R181 20 SRCOMP1
C281 +/-1%
0.1uF
* 16V, Y5V, +80%/-20%
1D8V_STR 1D8V_STR 1D8V_STR
R221 20 SRCOMP2
+/-1% 1D8V_STR
C302 C297
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% *R180
1K 1D8V_STR
Dummy
+/-1%
r0402h4 R202 20 SRCOMP3
*R191
1K
+/-1%
SMRCOMPVOH +/-1% r0402h4
C279 DDR_GMCH_VREF
A
*R185
3.01K * 10nF
25V, X7R, +/-10%
A
+/-1%
r0402h4
*R195
1K
+/-1% *
C287
0.1uF
16V, Y5V, +80%/-20%
SMRCOMPVOL r0402h4
*R189
1K C275
+/-1% 10nF 5 mils width, 10 mils spacing, max 500 mils length for breakout region
r0402h4 * 25V, X7R, +/-10% Place CAP./RES. within 1" of GMCH package.
1D8V_STR: 10 mils width/10 mils spacing.
width 10 mils, spacing 10 mils
5 mils width/spacing minimum for max. of 300 mils FOXCONN PCEG
SMRCOMPVOH: 0.8 *VCCSM in GMCH break-out area
SMRCOMPVOL: 0.2 *VCCSM Placed close to GMCH pin Title
BearLake-GMCH-2
C G31M04 A

5 4 3 2 1

UI1_1
8
7
8
D 7
5
2
1 A
2
1
U12_1
FOXCONN
www.sp860.com D
5
4
1D25V_MCH
AJ12
AJ11
AJ10
3
VCC_1
VCC_2
U12F
VCC_81
VCC_172
VCC_173
VCC_174
VCC_82
AG25
AG24
AG23
AG22
AG21
AG20
1D25V_MCH
QQ:453100829 2
BC37
BC32
BC28
BC24
BC10
VSS_1
VSS_2
VSS_3
VSS_4
U12G
VSS_181
VSS_182
VSS_183
VSS_184
AF5
AF3
AF2
AF1
AD42
1
B 5C 6 AJ9 VCC_3 VCC_83 AG19 BC5 VSS_5 VSS_185 AD39

6 VCC_4 VCC_84 VSS_6 VSS_186
3 AJ8 AG18 BB7 AD37
4 B 3 Heatsink AJ7 VCC_5 VCC_85 AG17 AY41 VSS_7 VSS_187 AD35
4 AJ6 VCC_6 VCC_86 AG15 AY4 VSS_8 VSS_188 AD33
VCC_7 VCC_87 VSS_9 VSS_189
Heatsink AJ5 AG14 AW43 AD25
AJ4 VCC_8 VCC_88 AF26 AW41 VSS_10 VSS_190 AD23
AJ3 AF25 AW1 AD21
CLIP1N AJ2 AF24 AV37 AD19
CLIP2S CLIP4S 1 AH4 AV35 AC38
VCC_12 VSS_14 VSS_194
1 1 AH2 AF22 AV27 AC35
GND
POWER
2 AH1 AF20 AV23 AC24
2 2 AG13 AF18 AV21 AC22
Clip_2P VCC_15 VCC_95 VSS_17 VSS_197
AG12 AF17 AV17 AC20
D VCC_16 VCC_96 VSS_18 VSS_198 D
Clip_2P Clip_2P AG11 AF15 AV11 AC10
This is for ICH7 heatsink hook. For GMCH heatsink hook AG10
VCC_18 VCC_98
AF14 AV9
VSS_20 VSS_200
AC7
AG9 AE27 AV7 AC5
CLIP3N VCC_19 VCC_99 VSS_21 VSS_201
AG8 AE26 AU42 AB43
1 AG7 VCC_20 VCC_100 AE25 AU38 VSS_22 VSS_202 AB25
AG6 VCC_21 VCC_101 AE23 AU32 VSS_23 VSS_203 AB23
2 AG5 AE21 AU24 AB21
AG4 VCC_23 VCC_103 AE19 AU20 VSS_25 VSS_205 AB19
Clip_2P VCC_24 VCC_104 VSS_26 VSS_206
AG3 AE17 AU6 AB2
AG2 VCC_25 VCC_105 AD27 AU2 VSS_27 VSS_207 AB1
AF13 AD26 AT31 AA38
AF12 AD18 AT29 AA35
AF11 VCC_28 VCC_108 AD17 AT15 VSS_30 VSS_210 AA24
AD24 AD15 AT13 AA22
AD22 VCC_30 VCC_110 AD14 AT12 VSS_32 VSS_212 AA20
1D25V_MCH AD20 VCC_31 VCC_111 AC27 AR38 VSS_33 VSS_213 AA8
AC25 AC26 AR33 AA5
AC23 VCC_80 VCC_113 AC17 AR32 VSS_35 VSS_215 Y42
1D25V_MCHPCIE VCC_34 VCC_114 VSS_36 VSS_216
L27 AC21 AC15 AR27 Y37
0 AC19 VCC_35 VCC_115 AC14 AR26 VSS_37 VSS_217 Y35
C272 C268 EC48 1D25V_MCH AC13 AB27 AR23 Y33
1

* 10uF
* 0.1uF
16V, Y5V, +80%/-20%
* 220uF
6.3V, +/-20%
AC6
AB24 VCC_38 VCC_118
AB26
AB18
AR21
AR20 VSS_40 VSS_220
Y25
Y23
10V, Y5V, +80%/-20%

10uF C172
AB22 AB17 AR17 Y21
2
1
* AB20
AA25 VCC_41
VCC_42
VCC_121
VCC_122
AA27
AA26
AR9
AR6 VSS_43
VSS_44
VSS_223
VSS_224
Y19
Y10
AA23 AA17 AP43 Y7
2
AA21 VCC_43 VCC_123 AA15 AP24 VSS_45 VSS_225 Y5
AA19 AA14 AP18 Y1
AA13 VCC_45 VCC_125 Y27 AP1 VSS_47 VSS_227 W3
1D25V_MCH AA3 VCC_46 VCC_126 Y26 AN38 VSS_48 VSS_228 V43
Y24 Y18 AN31 V39
Y22 VCC_48 VCC_128 Y17 AN29 VSS_50 VSS_230 V37
Y20 Y15 AN24 V34
Y13 VCC_50 VCC_130 Y14 AN23 VSS_52 VSS_232 V32
Place in 1D25V_MCH_CL plane Y6 VCC_51 VCC_131 W27 AN20 VSS_53 VSS_233 V11
(less than 100 mils from the package) V13 W26 AN15 V8
V12 W25 AN13 V5
V10 W23 AN12 V2
V9 W21 AN11 U38
*
L22 270nH VCCA_HPLL U13 VCC_56 VCC_136 W19 AN4 VSS_58 VSS_238 U35
+/-20% C176 VCC_57 VCC_137 VSS_59 VSS_239
U10 W18 AM42 U8
1

* 2.2uF
6.3V, Y5V, +80%/-20%
U9
U6
VCC_59
VCC_60
VCC_139
VCC_140
W17
V27
AM40
AM36
VSS_61
VSS_62
VSS_241
VSS_242
U7
U5
U3 V26 AM33 T42
2
N12 VCC_61 VCC_141 V25 AM29 VSS_63 VSS_243 T1

N11 V24 AM24 R36
N9 VCC_63 VCC_143 V23 AM23 VSS_65 VSS_245 R33
1D8V_STR Connect ground sides of caps with traces to GND balls N8 V22 AM20 R31
*
L20 2.2uH VCCA_MPLL (less than 100 mils from the package) N6 VCC_65 VCC_145 V21 AM11 VSS_67 VSS_247 R11
C +/-20% VCC_66 VCC_146 VSS_68 VSS_248 C
N3 V20 AM9 R8
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%

R129 1 L6 V19 AM7 R5
+/-5% J6 V18 AM4 R3
C306
C305
C304 J3 V17 AM2 P43

1

C170
* * * J2 V15 AM1 P30
1

R128 1
+/-5% * 10uF
10V, Y5V, +80%/-20%
G2
F11
VCC_72 VCC_152
V14
U26
AL36
AL33
VSS_74 VSS_254
P21
P18
2.2uF
2.2uF
2.2uF
2
F9 VCC_73 VCC_153 U25 AK43 VSS_75 VSS_255 P17

2

D4 U24 AJ39 P2
1D25V_MCH C13 VCC_75 VCC_155 U23 AJ36 VSS_77 VSS_257 N36
C9 VCC_76 VCC_156 U22 AJ33 VSS_78 VSS_258 N33
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%

C309
C437
C303
1D25V_MCH P20 U21 AH42 N31

1

* * * VCC_159
VCC_160
U20
U19
AG37
AG34
VSS_81
VSS_82
VSS_261
VSS_262
N27
N21
L0805 1uH Y11 U18 AF43 N13
2.2uF
2.2uF
2.2uF
2
VCCA_EXPPLL VCC_CL_PLL VCC_79 VCC_161 VSS_83 VSS_263

L21 1 2 R141 1 GMCH Memory Decoupling Y32 U17 AF37 N10
+/-10% +/-5% C179 C192 VCCA_EXPPLL VCC_CL_PLL VCC_162 VSS_84 VSS_264
B15 U15 AF36 N7
1
VCCA_HPLL VCCA_EXPPLL VCC_163 VSS_85 VSS_265

R142 1 * 10uF
10V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20% * Dummy C23
V31
VCCA_HPLL
RESERVED_002
VCC_164
VCC_165
U14
R20
AF10
AF9
VSS_86
VSS_87
VSS_266
VSS_267
N5
M42
+/-5% VCCA_MPLL A24 R18 AF8 M37
2
VCCA_DPLLA A22 VCCA_MPLL VCC_166 R17 AF7 VSS_88 VSS_268 M35

3D3V_SYS VCCA_DPLLB VCCA_DPLLA VCC_167 VSS_89 VSS_269
C22 R15 AF6 M33
VCCA_DPLLB VCC_168 R14 M27 VSS_90 VSS_270 BC41
1D25V_MCH VCC_169 VSS_91 VSS_271
P15 M21 BC3
B17 VCC_170 P14 M17 VSS_92 VSS_272 BA1
VCC3_3 VCC_171 VSS_93 VSS_273
L0805 10uH FSB_VTT 1D25V_MCH M15 AY40
VSS_94 VSS_274
L18 1 2 VCCA_DPLLA M10 AF23
VSS_95 VSS_275
+/-20% EC40 C206 C204 P29 AL26 M7 AF21
VTT_1 VCC_CL_1 VSS_96 VSS_276
* 220uF
* 0.1uF
* 0.1uF P27
VTT_2 VCC_CL_2
AL24 M1
VSS_97 VSS_277
AF19
10V, Y5V, +80%/-20%
10uF C276
6.3V, +/-20% 16V, Y5V, +80%/-20% C143 16V, Y5V, +80%/-20% P26 AL23 L33 AE24
1

10uF
10V, Y5V, +80%/-20% * * P24
P23
VTT_4
VTT_5
VCC_CL_4
VCC_CL_5
AL21
AL20
L32
L31
VSS_99
VSS_100
VSS_279
VSS_280
AE22
AE20
L19 L0805 10uH Dummy N29 AL18 L29 AE18
2
VCCA_DPLLB VTT_6 VCC_CL_6 VSS_101 VSS_281

1 2 N26 AL17 L21 AC18
EC39 C205 N24 AL15 L20 AA18
+/-20% * 220uF
6.3V, +/-20% * 0.1uF
16V, Y5V, +80%/-20%
N23
M29
VTT_9 VCC_CL_9
AK30
AK29
L11
L7
VSS_104 VSS_284
W24
W22
M24 VTT_10 VCC_CL_10 AK27 L5 VSS_105 VSS_285 W20
Place in the PCI-E power plane VTT_11 VCC_CL_11 VSS_106 VSS_286
M23 AJ31 L3 R21
1D8V_STR (less than 100 mils from the package) L24 VTT_12 VCC_CL_12 AG31 K43 VSS_107 VSS_287 E1
Intel DG: 220uF L23 VTT_13 VCC_CL_13 AF31 K26 VSS_108 VSS_288 C43
K24 AD32 K21 C1
K23 VTT_15 VCC_CL_15 AC32 K18 VSS_110 VSS_290 A41
J24 AA32 K13 A5
J23 VTT_17 VCC_CL_17 AJ30 K12 VSS_112 VSS_292 A3
H24 VTT_18 VCC_CL_18 AJ29 K2 VSS_113 VSS_293
VTT_19 VCC_CL_19 VSS_114
H23 AJ27 J38
FSB_VTT G26 VTT_20 VCC_CL_20 AG30 J35 VSS_115
R147 Need to Check Change to Dummy VTT_21 VCC_CL_21 VSS_116
G24 AG29 J32
*
L23 10 VCCDQ_CRT G23 VTT_22 VCC_CL_22 AG27 J27 VSS_117

B +/-5% r0805h6 VTT_23 VCC_CL_23 VSS_118 B
F26 AG26 J21
2.2uF C182
2.2uF C159
2.2uF C188
1 F24 AF30 J9
1

6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
*
C177
1uF
+/-5%
* * * F23
E29
VTT_26
VTT_27
VCC_CL_26
VCC_CL_27
AF29
AF27
J7
J5
VSS_121
VSS_122
10V, Y5V, +80%/-20% E27 AD30 H31
2
Reserved E26 VTT_28 VCC_CL_28 AD29 H29 VSS_123

E23 AC30 H21
Dummy D29 VTT_30 VCC_CL_30 AC29 H20 VSS_125
Dummy VTT_31 VCC_CL_31 VSS_126
D28 AL12 H17
D27 VTT_32 VCC_CL_32 AL11 H15 VSS_127
C30 VTT_33 VCC_CL_33 AL10 H13 VSS_128
Place in FSB_VTT plane as close to the GMCH as possible VTT_34 VCC_CL_34 VSS_129
C29 AL9 G42
L0805 10uH (less than 100 mils from the package) C27 AL8 G38
L40 1 2 VCCD_CRT B30 AL7 G32
+/-20% B29 AL6 G21
C175 C190 B28 AL5 G13
* 4.7uF
6.3V, X5R, +/-10% * 0.1uF
16V, Y5V, +80%/-20%
B27
A30 VTT_40
VTT_41
VCC_CL_40
VCC_CL_41
AL4
AL3
G12
G11 VSS_135
VSS_136
Reserved A28 AL2 G9
R27 VTT_42 VCC_CL_42 AK26 G7 VSS_137
5V_SYS 1D8V_STR R26 VTT_43 VCC_CL_43 AK24 G1 VSS_138
U9 AME8800 VTT_44 VCC_CL_44 VSS_139
R24 AK23 F37
3 2 VCCA_DAC R23 VTT_45 VCC_CL_45 AK21 F35 VSS_140
V_IN V_OUT VTT_46 VCC_CL_46 VSS_141
BC39 AK20 F27
VCCSM_1 VCC_CL_47 VSS_142
GND
BC34 AK18 F21

1

3D3V_SYS * C144 * C145
BC30
BC26
VCCSM_3
VCCSM_4
VCC_CL_49
VCC_CL_50
AK17
AK15
F18
F3
VSS_144
VSS_145
3D3V_SYS 1uF Dummy 1uF BC22 AK3 E43
2
Near the FB20 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20% VCCSM_5 VCC_CL_51 VSS_146
BC18 AK2 E32
Dummy Dummy BC14 VCCSM_6 VCC_CL_52 AK1 E24 VSS_147
*
FB20 BB39 AJ13 E21

+/-5% VCCSM_8 VCC_CL_54 VSS_149
FB L0603 600 Ohm BB37 AD31 E20
C142 C403 1 BB32 AC31 E15
* 0.1uF
16V, X7R, +/-10%
* 10nF
25V, X7R, +/-10% VCCA_EXP VCCA_DAC
BB28
BB26
VCCSM_11
VCCSM_12
VCC_CL_57
VCC_CL_58
AA31
Y31
E13
E11
VSS_152
VSS_153
Dummy Dummy BB24 AJ26 E9
R146 BB20 AJ24 E3
C184
C194 BB18 AJ23 D40

1

* * 0.1uF
16V, Y5V, +80%/-20%
BB16
BB12 VCCSM_16
VCCSM_17
VCC_CL_62
VCC_CL_63
AJ21
AJ20
D31
D21 VSS_157
VSS_158
1uF
Modify by Steven 051707 AY32 AJ18 D17

2

10V, Y5V, +80%/-20%
Near the NB Dummy AW24 AJ17 D3

Modify by Steven 051707 AW20 VCCSM_19 VCC_CL_65 AJ15 C26 VSS_160
AV26 AJ14 C11
AV18 VCCSM_21 VCC_CL_67 AA30 C6 VSS_162
1D25V_MCHPCIE AD11 VCCSM_22 VCC_CL_68 AA29 C5 VSS_163
VCC_EXP_1 VCC_CL_69 VSS_164
AD10 Y30 C4
AD9 Y29 B37
VCC_EXP_3 VCC_CL_71 1D8V_STR VSS_166
AD8 V30 B32
AD7 VCC_EXP_4 VCC_CL_72 V29 B31 VSS_167
A AD6 VCC_EXP_5 VCC_CL_73 U29 B26 VSS_168 A
AD5 U27 B23
2
AD4 VCC_EXP_7 VCC_CL_75 AL13 L29 B22 VSS_170

AD2 AK14 L0805 1uH B19
AD1 AL29 B14
AC4 AL27 B10
VCC_EXP_11 VCC_CL_79 +/-10% VSS_174
1D25V_MCH 1D25V_MCH 1D25V_MCH AC3 A39
VCC_EXP_12 VSS_175
AC2 A34
1
VCC_EXP_13 VSS_176
AE4 BB41 A26
VCC_EXP_14 VCC_SMCLK_1 VSS_177
AE3 BA42 A18
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

10uF C122
10uF C291
10uF C117
10uF C129
1uF C229
1uF C220
1uF C213
1uF C249
C127 C130 C123 AE2 AY42 C295 A12

1

10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10uF
10V, Y5V, +80%/-20% * * * * * * 10uF
10V, Y5V, +80%/-20% * * * * * 10uF
10V, Y5V, +80%/-20%
VCCA_DAC C17
B16 VCCA_DAC_17
VCCA_DAC_18
VCC_SMCLK_4
VCC_SMCLK_5
BB42
BA43 * 0.1uF
16V, Y5V, +80%/-20%
R201
1
R222
1
A7
VSS_180 7 OF 7
Dummy Dummy VCCA_EXP A16
2
VCCD_CRT C21 VCCA_EXP

VCCDQ_CRT B21 VCCD_CRT AL31 +/-5% +/-5% LE82G31 bga1226_1h25
D16
VCCDQ_CRT RESERVED_1
AJ32 FOXCONN PCEG
1
Dummy VSS_1 RESERVED_2

Dummy
Don't use 1.8, use 1.5v.
6 OF 7 * C310
10uF Title
BearLake-GMCH-3
2
Dummy Dummy Place in 1D25V_MCH plane as close to GMCH as possible 10V, Y5V, +80%/-20%
LE82G31 bga1226_1h25 Size Document Number Rev
Custom G31M04 A

5 4 3 2 1

5
www.sp860.com 4 3
QQ:453100829 2 1
VTT_DDR M_ODT_A[1..0] 17,20
D M_SCKE_A[1..0] 17,20 D
M_BS_A[2..0] 17,20
R287 33 +/-5% M_MAA_A2
M_MAA_A[14..0] 17,20
R284 33 +/-5% M_MAA_A13
RN38
*1 2 M_RAS_AJ 17,20
VTT_DDR
3 4 M_WE_AJ 17,20 Need to Check Change to Dummy Need to Check Change to Dummy
5 6 M_CAS_AJ 17,20 1D8V_STR
7 8
33
C426
C375
C381
C380
C384
+/-5%
C451
C399
C377
C379
C396
C450
C449
RN34
*1 2
M_MAA_A14
M_BS_A2 * * * * *
3 4
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
5
7
6
8
M_MAA_A12
M_MAA_A11 * * * * * * *
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
33
+/-5%
VTT_DDR
C C
RN35
*1 2
M_MAA_A9
M_MAA_A7 Reserved Reserved
3 4 M_MAA_A8
5 6 M_MAA_A5 Reserved Reserved
7 8
33
+/-5%
Channel A VTT_0.9V high-frequency decoupling caps.
RN36
Place as close to termination resistors as possible
*1 2
M_MAA_A6
M_MAA_A4
3 4 M_MAA_A3
5 6 M_MAA_A1
7 8 VTT_DDR
33
+/-5%
RN37
*1 2
M_MAA_A0
M_BS_A1
3 4 M_MAA_A10
5 6 M_BS_A0
7 8
33
+/-5% C442 C389
1
B * 4.7uF
6.3V, X5R, +/-10% * 4.7uF
6.3V, X5R, +/-10%
B
VTT_DDR
2
R285 43 Ohm
R286 43 Ohm M_SCKE_A1
M_SCKE_A0
VTT_DDR
Channel A VTT_0.9V Mid Range decoupling caps.
R288
R290
43 Ohm
43 Ohm
Placed in termination Island
M_SCS_A0J 17,20
R289 43 Ohm
M_ODT_A0 17,20
M_SCS_A1J 17,20
R283 43 Ohm
M_ODT_A1 17,20
A A
FOXCONN PCEG
Title
DDR2 Channel A Termination
Custom G31M04 A

5 4 3 2 1

5
www.sp860.com
2
5
8
11
DIMM1
VSS
VSS
VSS
VSS
4
NC_1
NC/TEST
NC_2
68
102
19 M_ODT_A[1..0] 17,19
3
QQ:453100829 2 1
14
17 VSS 77 M_ODT_A1
VSS ODT1 M_ODT_A0
20 195
VSS ODT0
23
VSS
26
VSS
29
VSS
32 42
VSS CB<0>
35 43
VSS CB<1>
38 48
VSS CB<2>
41 49
VSS CB<3> 1D8V_STR
D 44 161 D
VSS CB<4>
47 162
1D8V_STR 50 VSS CB<5> 167
VSS CB<6>
65 168
VSS CB<7>
66
79 VSS C432
EC53 EC52 VSS 100pF C404 C436 C406 C407 C433
* 1000uF * 1000uF
82
85
VSS
VSS M_DQS_AJ[7..0] 17
* 50V, NPO, +/-5% * 0.1uF * *
0.1uF 0.1uF * *
0.1uF 0.1uF
6.3V, +/-20% 6.3V, +/-20% 88
VSS M_DQS_A0 For EMI
91 7
VSS DQS<0> Dummy
94 6
VSS DQS#<0> M_DQS_AJ0
97
100 VSS 16 M_DQS_A1 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
VSS DQS<1> 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
103 15
Place between Ch A DIMM II 106
109 VSS 28 M_DQS_A2
and Ch B DIMM 1 112
VSS DQS<2>
27
115 VSS DQS#<2> M_DQS_AJ2
VSS M_DQS_A3
118 37
VSS DQS<3>
121 36
124
VSS M_DQS_A4
127 84
1D8V_STR VSS DQS<4>
130 83
133
VSS M_DQS_A5
136 93
VSS DQS<5>
139 92
EC38 VSS DQS#<5> M_DQS_AJ5
142
VSS
* 1000uF
6.3V, +/-20%
145
148 VSS DQS<6>
105
104
M_DQS_A6 1D8V_STR
151
VSS M_DQS_A7
154 114
157 VSS DQS<7> 113
Place between GMCH and DIMM VSS DQS#<7>
160 M_DQS_AJ7
VSS M_DQS_A[7..0] 17
163
166
VSS
VSS
DQS<8>
DQS#<8>
46
45 *R291
1K
169 +/-1%
VSS M_DQM_A0 r0402h4
198 125
VSS DM0/DQS9
201 126
C 204 VSS NC/DQS9# C
1D8V_STR VSS M_DQM_A1 SMVREF_A
207 134
VSS DM1/DQS10 SMVREF_A 22
210 135
213 VSS NC/DQS10#
VSS M_DQM_A2
216
VSS DM2/DQS11
146
*R292 C387 C386
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
1K
219
VSS NC/DQS11#
147
* 0.1uF
* 0.1uF
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
222 +/-1% 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%

VSS
C430
225 155 M_DQM_A3 r0402h4

VSS DM3/DQS12
C398
C352
228 156
VSS NC/DQS12# Dummy
231
VSS M_DQM_A4
* * * 1D8V_STR
234
237 VSS
VSS
DM4/DQS13
NC/DQS13#
202
203
10V, Y5V, +80%/-20%
51
VDDQ
1uF
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
56 211 M_DQM_A5
VDDQ DM5/DQS14
1uF
1uF
62 212 close to DIMM pin

VDDQ NC/DQS14# Width 10 mils minimum, Spacing 10 mils minimum.
72
75 VDDQ 223 M_DQM_A6
VDDQ DM6/DQS15
78 224
VDDQ NC/DQS15#
191
194 VDDQ 232 M_DQM_A7
VDDQ DM7/DQS16
181 233
175 VDDQ NC/DQS16#
VDDQ M_DQM_A[7..0] 17
170 164
53 VDDQ DM8/DQS17 165
VDD NC/DQS17# 1D8V_STR
59
VDD M_DATA_A[63..0] 17
64 3 M_DATA_A0
197 VDD DQ<0> 4 M_DATA_A1
VDD DQ<1> M_DATA_A2
69 9
Channel A DIMM 1 1.8V high-frequency decoupling caps. VDD DQ<2> M_DATA_A3
172 10
place as close to DIMM power pins as possible VDD DQ<3> M_DATA_A4
187 122
VDD DQ<4> M_DATA_A5
184 123
VDD DQ<5>
C441
C355
C167
C191
178 128 M_DATA_A6
VDD DQ<6> M_DATA_A7
189 129
67 VDD DQ<7> 12 M_DATA_A8
VDD DQ<8> M_DATA_A9
DQ<9>
DQ<10>
13
21 M_DATA_A10 * * * *
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
18 22 M_DATA_A11
3D3V_SYS 55 RC1 DQ<11> 131 M_DATA_A12
B RC0 DQ<12> B
238 132 M_DATA_A13
SMVREF_A VDDSPD DQ<13> M_DATA_A14
1 140
8,22,29,36 SMB_CLK_MAIN VREF DQ<14> M_DATA_A15
120 141
SCL DQ<15> M_DATA_A16
119 24
8,22,29,36 SMB_DATA_MAIN SDA DQ<16> M_DATA_A17
25
DQ<17> M_DATA_A18
101 30
SA2 DQ<18> M_DATA_A19
240 31
SA1 DQ<19> M_DATA_A20
239 143
SA2 SA1 SA0 SA0 DQ<20> 144 M_DATA_A21
DQ<21> M_DATA_A22
0 0 0 190 149
17,19 M_BS_A[2..0] M_BS_A1 BA1 DQ<22> M_DATA_A23
71 150
M_BS_A0 BA0 DQ<23> M_DATA_A24 Channel A DIMM II 1.8V high-frequency decoupling caps.
33
DQ<24> M_DATA_A25
34 place as close to DIMM power pins as possible
17,19 M_SCKE_A[1..0] M_SCKE_A1 171 DQ<25> 39 M_DATA_A26
M_SCKE_A0 CKE1 DQ<26> M_DATA_A27
52 40
CKE0 DQ<27> M_DATA_A28
152
DQ<28> M_DATA_A29
153
DQ<29> M_DATA_A30
158
DQ<30> M_DATA_A31
76 159
17,19 M_SCS_A1J S1# DQ<31> M_DATA_A32
193 80
17,19 M_SCS_A0J S0# DQ<32> M_DATA_A33
81
221 DQ<33> 86 M_DATA_A34
17 CK_M_200M_N_DDR2_A CK2#/RFU DQ<34> M_DATA_A35
220 87
17 CK_M_200M_P_DDR2_A CK2/RFU DQ<35> M_DATA_A36
138 199
17 CK_M_200M_N_DDR1_A CK1#/RFU DQ<36> M_DATA_A37
137 200
17 CK_M_200M_P_DDR1_A CK1/RFU DQ<37> M_DATA_A38
186 205
17 CK_M_200M_N_DDR0_A 185 CK0# DQ<38> 206 M_DATA_A39
17 CK_M_200M_P_DDR0_A CK0 DQ<39> M_DATA_A40
89
17,19 M_MAA_A[14..0] M_MAA_A0 DQ<40> M_DATA_A41
188 90
M_MAA_A1 A0 DQ<41> M_DATA_A42
183 95
63 96
182 208
61 209
60 214
180 215
M_MAA_A7 58 A6 DQ<47> 98 M_DATA_A48
179 99
A M_MAA_A9 A8 DQ<49> M_DATA_A50 A
177 107
70 108
M_MAA_A11 57 A10/AP DQ<51> 217 M_DATA_A52
176 218
196 226
174 227
173 A14 DQ<55> 110 M_DATA_A56
17,19 M_BS_A[2..0] M_BS_A2 A15 DQ<56> M_DATA_A57
54 111
A16/BA2 DQ<57> M_DATA_A58
116
DQ<58> M_DATA_A59
117
17,19 M_CAS_AJ
74
192 CAS#
DQ<59>
DQ<60>
229
230
M_DATA_A60
M_DATA_A61
FOXCONN PCEG
17,19 M_RAS_AJ
73 RAS# DQ<61> 235 M_DATA_A62 Title
17,19 M_WE_AJ WE# DQ<62> M_DATA_A63
236 Index Page
DQ<63>
DDR II
C G31M04 A

5 4 3 2 1

5
www.sp860.com 4 3
M_SCKE_B[1..0] 17,22
QQ:453100829 2 1
M_BS_B[2..0] 17,22
M_MAA_B[14..0] 17,22
M_ODT_B[1..0] 17,22
D D
VTT_DDR
VTT_DDR R318 33 +/-5% M_MAA_B2
R313 33 +/-5% M_MAA_B13
R317 43 Ohm
R316 43 Ohm M_SCKE_B1 RN42
M_SCKE_B0
*1 2 M_RAS_BJ
M_WE_BJ
17,22
17,22
3 4
5 6 M_CAS_BJ 17,22
7 8
33
+/-5%
VTT_DDR RN43
R311 43 Ohm
*1 2
M_BS_B2
M_MAA_B12
R312 43 Ohm 3 4 M_MAA_B14
M_SCS_B0J 17,22 5 6
R314 43 Ohm M_MAA_B11
M_ODT_B0 17,22 7 8
M_SCS_B1J 17,22
R315 43 Ohm 33
+/-5%
C
M_ODT_B1 17,22 C
RN44
*1 2
M_MAA_B7
M_MAA_B9
3 4 M_MAA_B8
5 6 M_MAA_B6
7 8
33
+/-5%
RN45
*1 2
M_MAA_B5
M_MAA_B4
3 4 M_MAA_B3
5 6 M_MAA_B1
7 8
33
+/-5%
RN41
*1 2
M_MAA_B0
M_MAA_B10
3 4 M_BS_B1
5 6 M_BS_B0
7 8
33
+/-5%
B B
VTT_DDR Need to Check Change to Dummy

VTT_DDR Need to Check Change to Dummy 1D8V_STR
C448
C447
C397
C383
C452
C385
C446
C395
C378
C428
C382
C427
C429 C392
* * * * * * * * * * * *
1
4.7uF 4.7uF
* *
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
16V, Y5V, +80%/-20%
0.1uF
6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
2
VTT_DDR
A A
Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Channel B VTT_0.9V Mid Range decoupling caps. Channel B VTT_0.9V high-frequency decoupling caps.
Placed in termination Island Place as close to termination resistors as possible
FOXCONN PCEG
Title
Index Page
C G31M04 A

5 4 3 2 1

5
www.sp860.com
2
5
8
11
14
DIMM2
VSS
VSS
VSS
VSS
VSS
4
NC_1
NC/TEST
NC_2
68
102
19
M_ODT_B1
M_ODT_B[1..0] 17,21
3
QQ:453100829
2 1
17 77
20 VSS ODT1 195 M_ODT_B0
VSS ODT0
23
VSS
26
VSS
29
VSS
32 42
VSS CB<0>
35 43
VSS CB<1>
38 48
VSS CB<2>
41 49
VSS CB<3>
44 161
VSS CB<4>
D 47 162 D
VSS CB<5>
50 167
65 VSS CB<6> 168
VSS CB<7>
66
VSS
79
82 VSS
VSS
85 M_DQS_BJ[7..0] 17
VSS
88
91 VSS 7 M_DQS_B0
VSS DQS<0>
94 6
VSS DQS#<0> M_DQS_BJ0
97
VSS M_DQS_B1
100 16
103 VSS DQS<1> 15
106
VSS M_DQS_B2
109 28
112 VSS DQS<2> 27
115
118 VSS 37 M_DQS_B3
VSS DQS<3>
121 36
124
VSS M_DQS_B4
127 84
VSS DQS<4>
130 83
133
1D8V_STR VSS M_DQS_B5
136 93
VSS DQS<5>
139 92
142
VSS M_DQS_B6
145 105
VSS DQS<6>
148 104
VSS DQS#<6>
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
151 M_DQS_BJ6
VSS M_DQS_B7
154 114
VSS DQS<7>
C390
C440
C353
C405
157 113
160 VSS DQS#<7> M_DQS_BJ7
VSS M_DQS_B[7..0] 17
163 46
VSS DQS<8>
* * * * 166
169
VSS
VSS
DQS#<8>
45
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
198 125 M_DQM_B0

VSS DM0/DQS9
1uF
1uF
1uF
1uF
201 126
VSS NC/DQS9#
204
C 207 VSS 134 M_DQM_B1 1D8V_STR C
VSS DM1/DQS10
210 135
VSS NC/DQS10#
213
216 VSS 146 M_DQM_B2
VSS DM2/DQS11
219 147
VSS NC/DQS11# C438 C374 C434
222
VSS M_DQM_B3
225
228
VSS
VSS
DM3/DQS12
NC/DQS12#
155
156 * 0.1uF
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20%
231
VSS M_DQM_B4
234 202
1D8V_STR VSS DM4/DQS13
237 203
Channel B DIMM1 1.8V high-frequency decoupling caps. 51 VSS NC/DQS13#
place as close to DIMM power pins as possible VDDQ M_DQM_B5
56 211
VDDQ NC/DQS14#
72
VDDQ M_DQM_B6
75 223
VDDQ NC/DQS15#
191
VDDQ M_DQM_B7
194 232
VDDQ NC/DQS16#
175 M_DQM_B[7..0] 17
170 VDDQ 164
VDDQ DM8/DQS17
53 165
59 VDD NC/DQS17#
VDD M_DATA_B[63..0] 17
64 3 M_DATA_B0
VDD DQ<0> M_DATA_B1
197 4
69 VDD DQ<1> 9 M_DATA_B2
VDD DQ<2> M_DATA_B3
172 10
VDD DQ<3> M_DATA_B4 1D8V_STR
187 122
VDD DQ<4> M_DATA_B5
184 123
VDD DQ<5> M_DATA_B6
178 128
VDD DQ<6> M_DATA_B7
189 129
VDD DQ<7>
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603
67 12 M_DATA_B8
VDD DQ<8> 13 M_DATA_B9
DQ<9>
C402
C431
C354
C401
21 M_DATA_B10
DQ<10> M_DATA_B11
18 22
3D3V_SYS RC1 DQ<11> M_DATA_B12
55 131
RC0 DQ<12> M_DATA_B13
B 238
1
VDDSPD
VREF
DQ<13>
DQ<14>
132
140 M_DATA_B14 * * * * B
20 SMVREF_A
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

120 141 M_DATA_B15
SCL DQ<15>
1uF
1uF
1uF
1uF
8,20,29,36 SMB_CLK_MAIN 119 24 M_DATA_B16
8,20,29,36 SMB_DATA_MAIN SDA DQ<16> M_DATA_B17
25
DQ<17> M_DATA_B18
101 30
SA2 DQ<18> M_DATA_B19
240 31
SA1 DQ<19> M_DATA_B20
239 143
SA2 SA1 SA0 SA0 DQ<20> M_DATA_B21
144
0 1 0 190 DQ<21> 149 M_DATA_B22
17,21 M_BS_B[2..0] M_BS_B1 BA1 DQ<22> M_DATA_B23
71 150
M_BS_B0 BA0 DQ<23> M_DATA_B24
33
DQ<24> M_DATA_B25
34
17,21 M_SCKE_B[1..0] M_SCKE_B1 DQ<25> M_DATA_B26
171 39
M_SCKE_B0 52 CKE1 DQ<26> 40 M_DATA_B27
CKE0 DQ<27> M_DATA_B28
152
DQ<28> M_DATA_B29
153
DQ<29> M_DATA_B30 Channel B DIMM II 1.8V high-frequency decoupling caps.
158
DQ<30> M_DATA_B31 place as close to DIMM power pins as possible
76 159
17,21 M_SCS_B1J S1# DQ<31> M_DATA_B32
193 80
17,21 M_SCS_B0J S0# DQ<32> M_DATA_B33
81
DQ<33> M_DATA_B34
221 86
17 CK_M_200M_N_DDR2_B 220 CK2#/RFU DQ<34> 87 M_DATA_B35
17 CK_M_200M_P_DDR2_B CK2/RFU DQ<35> M_DATA_B36
138 199
17 CK_M_200M_N_DDR1_B CK1#/RFU DQ<36> M_DATA_B37
137 200
17 CK_M_200M_P_DDR1_B CK1/RFU DQ<37> M_DATA_B38
186 205
17 CK_M_200M_N_DDR0_B CK0# DQ<38> M_DATA_B39
185 206
17 CK_M_200M_P_DDR0_B CK0 DQ<39> 89 M_DATA_B40
17,21 M_MAA_B[14..0] M_MAA_B0 DQ<40> M_DATA_B41
188 90
M_MAA_B1 A0 DQ<41> M_DATA_B42
183 95
63 96
182 208
61 209
60 214
180 215
58 98
M_MAA_B8 179 A7 DQ<48> 99 M_DATA_B49
177 107
A M_MAA_B10 A9 DQ<50> M_DATA_B51 A
70 108
M_MAA_B11 A10/AP DQ<51> M_DATA_B52
57 217
M_MAA_B12 176 A11 DQ<52> 218 M_DATA_B53
196 226
174 227
A14 DQ<55> M_DATA_B56
173 110
17,21 M_BS_B[2..0] M_BS_B2 54 A15 DQ<56> 111 M_DATA_B57
A16/BA2 DQ<57> M_DATA_B58
116
DQ<58> M_DATA_B59
117
DQ<59> M_DATA_B60
74 229
17,21 M_CAS_BJ
17,21 M_RAS_BJ
192
CAS#
RAS#
DQ<60>
DQ<61>
230 M_DATA_B61 FOXCONN PCEG
73 235 M_DATA_B62
17,21 M_WE_BJ WE# DQ<62> 236 M_DATA_B63 Title
DQ<63>
Index Page
DDR II Size Document Number Rev
C G31M04 A

5 4 3 2 1

5
www.sp860.com 4 3
QQ:453100829 2 1
D D
3D3V_SB 3D3V_SYS 12V_SYS 12V_SYS 3D3V_SYS 12V_SYS 3D3V_SYS 3D3V_SB
PCI-E1_16X C157 C66
1
C109
B1
12V PRSNT1#
A1 * 0.1uF * 0.1uF
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20%
B2 A2
2
12V 12V 25V, X7R, +/-10%
B3 A3
B4 RSVD1 12V A4
GND GND
B5 A5
25,30,31,36 SMB_CLK_RESUME SMCLK JTAG2
B6 A6
25,30,31,36 SMB_DATA_RESUME SMDAT JTAG3
B7 A7
GND JTAG4
B8 A8
3.3V JTAG5
B9 A9
JTAG1 3.3V
B10 A10
WAKEJ 3.3VAUX 3.3V ICH_G_PLTRSTJ
B11 A11 ICH_G_PLTRSTJ 30,35
25,30 WAKEJ WAKE# PWRGD
All AC Coupling caps. should be placed within 250 mils of the connector KEY 12V_SYS 3D3V_SYS 12V_SYS
B12 A12
RSVD2 GND CK_PE_100M_P_16PORT
B13 A13
GND REFCLK+ CK_PE_100M_P_16PORT 8
EXP_TXP0_C B14 A14 CK_PE_100M_N_16PORT EC26 EC28 EC41
16 EXP_TXP0 CK_PE_100M_N_16PORT 8
*
HSOP0 REFCLK-
C151 0.1uF 16V, X7R, +/-10%
16 EXP_TXN0
EXP_TXN0_C B15 A15 * 470uF * 1000uF * 470uF
*
C152 0.1uF 16V, X7R, +/-10% HSON0 GND 16V, +/-20% 6.3V, +/-20% 16V, +/-20%
B16 A16
SDVO_CTRLCLK GND HSIP0 EXP_RXP0 16 Reserved
16 SDVO_CTRLCLK B17 A17
PRSNT2_B17# HSIN0 EXP_RXN0 16
B18 A18
GND GND
EXP_TXP1_C B19 A19

16 EXP_TXP1
*
C C162 0.1uF 16V, X7R, +/-10% EXP_TXN1_C B20 HSOP1 RSVD3 A20 C
16 EXP_TXN1
*
C161 0.1uF 16V, X7R, +/-10% HSON1 GND
B21 A21
GND HSIP1 EXP_RXP1 16
B22 A22
EXP_TXP2_C B23 GND HSIN1 A23 EXP_RXN1 16
16 EXP_TXP2
*
C169 0.1uF 16V, X7R, +/-10% EXP_TXN2_C HSOP2 GND

B24 A24
16 EXP_TXN2
*
C168 0.1uF 16V, X7R, +/-10% HSON2 GND
B25 A25
B26 A26
EXP_TXP3_C GND HSIN2 EXP_RXN2 16
B27 A27
16 EXP_TXP3
*
C174 0.1uF 16V, X7R, +/-10% EXP_TXN3_C HSOP3 GND

16 EXP_TXN3 B28 A28
*
C173 0.1uF 16V, X7R, +/-10% HSON3 GND
B29 A29
B30 A30
SDVO_CTRLDATA B31 RSVD4 HSIN3 A31 EXP_RXN3 16
16 SDVO_CTRLDATA PRSNT2_B31# GND
B32 A32
GND RSVD5
B33 A33
16 EXP_TXP4
*
C181 0.1uF 16V, X7R, +/-10% HSOP4 RSVD

16 EXP_TXN4 B34 A34
*
C180 0.1uF 16V, X7R, +/-10% B35 HSON4 GND A35
B36 A36
GND HSIN4 EXP_RXN4 16
16 EXP_TXP5 B37 A37
*
C193 0.1uF 16V, X7R, +/-10% B38 HSOP5 GND A38

16 EXP_TXN5
*
C189 0.1uF 16V, X7R, +/-10% HSON5 GND
B39 A39
B40 GND HSIP5 A40 EXP_RXP5 16
16 EXP_TXP6 B41 A41
*

16 EXP_TXN6
*
C200 0.1uF 16V, X7R, +/-10% HSON6 GND
B43 A43
B44 A44
16 EXP_TXP7 B45 A45
*
C214 0.1uF 16V, X7R, +/-10% HSOP7 GND

B46 A46
16 EXP_TXN7
* HSON7 GND
C212 0.1uF 16V, X7R, +/-10% B47 A47
16 GMCH_EXP_EN_HDR B48 A48
B49 A49
GND GND
16 EXP_TXP8 B50 A50

*
C218 0.1uF 16V, X7R, +/-10% HSOP8 RSVD6

16 EXP_TXN8
B51 A51
*
C219 0.1uF 16V, X7R, +/-10% HSON8 GND

B52 A52 EXP_RXP8 16
GND HSIP8
B53 A53
B54 GND HSIN8 A54 EXP_RXN8 16
B 16 EXP_TXP9 B
*
C225 0.1uF 16V, X7R, +/-10% HSOP9 GND

16 EXP_TXN9 B55 A55
*
C230 0.1uF 16V, X7R, +/-10% HSON9 GND

B56 A56
B57 A57
B58 A58
16 EXP_TXP10
*
C235 0.1uF 16V, X7R, +/-10% HSOP10 GND

16 EXP_TXN10 B59 A59
*
C233 0.1uF 16V, X7R, +/-10% HSON10 GND

B60 A60
B61 A61
16 EXP_TXP11 B62 A62
*

16 EXP_TXN11
*
C236 0.1uF 16V, X7R, +/-10% HSON11 GND

B64 A64
B65 A65 EXP_RXN11 16
GND HSIN11
*
C242 0.1uF 16V, X7R, +/-10% HSOP12 GND

*

B69 A69
*
C265 0.1uF 16V, X7R, +/-10% HSOP13 GND

B71 A71
16 EXP_TXN13
*
C260 0.1uF 16V, X7R, +/-10% HSON13 GND

B72 A72
B73 A73
16 EXP_TXP14
B74 A74
*
C270 0.1uF 16V, X7R, +/-10% HSOP14 GND

*

B77 A77
16 EXP_TXP15
B78 A78
*
C278 0.1uF 16V, X7R, +/-10% HSOP15 GND

*
C277 0.1uF 16V, X7R, +/-10% HSON15 GND

B80 A80
B81 GND HSIP15 A81 EXP_RXP15 16
B82 A82
RSVD7 GND
Slot-PCIE-16X
All AC Coupling caps. should be placed within 250 mils of the connector
A A
FOXCONN PCEG
Title
Index Page
C G31M04 A

5 4 3 2 1

5
www.sp860.com 4 3
QQ:453100829 2 1
D D
L8 L3
RED 5V_SYS
16 RED
*
5V_SYS 5V_SYS 82nH@100MHz L0603 0.1uH
*
C26 R33 C22 C5
C61 C113 1 2
3D3V_SYS * 3.3pF * 150
* 22pF
* 10pF F1
50V, NPO, +/-0.25pF+/ -1% 50V, NPO, +/-5% 50V, NPO, +/-5%
* 0.1uF
16V, Y5V, +80%/-20%
* 0.1uF
16V, Y5V, +80%/-20% D5
r0402h4
Fuse 1.5A
BAV99
Dummy
L9 L4
L_RED
EMI cap. for RGB layer change GREEN L_GREEN
16 GREEN
*
L_BLUE
82nH@100MHz L0603 0.1uH
C30 R35 C23 C6
*
3
3.3pF 150 22pF 10pF VGA
1 2 3D3V_SYS
* 50V, NPO, +/-0.25pF+/ -1% * 50V, NPO, +/-5% * 50V, NPO, +/-5% 5V_DDCA_CLK 15 SCL GND 5
RGB routing r0402h4 5V_DDCA_DATA 10 GND
C 14 VSYNC ID0 4 C
1. from GMCH to the first 150 ohm resistor: 7.5 mils(min. 6 mils spacing ) D6
9 NC
2. from the first 150 ohm res. to the second 150 ohm resistor: 4 mils BAV99 13 HSYNC B 3
3. from the second 150 ohm resistor to connector: 4 mils 8 GND
12 SDA G 2
4. spacing minimum 6 mils, 30 mils spacing is recommended 7 GND
16V, Y5V, +80%/-20%

5. R,G,B should be length matched to 700 mils, max. length is 8400 mils 11 ID1 R 1
C44 6 GND
6. R,G,B signals should be ground referenced L10 L5 * 0.1uF VGA
BLUE DZ11AA1-HW7-4F
16
17
16 BLUE
*
82nH@100MHz L0603 0.1uH
C42 R37 C24 C7
*
3
3.3pF 150 22pF 10pF
3D3V_SYS 5V_SYS 1 2 3D3V_SYS

* 50V, NPO, +/-0.25pF+/ -1% * 50V, NPO, +/-5% * 50V, NPO, +/-5%
r0402h4
D10
BAV99
RN8
2
4
6
8
2.2K
+/-5% The 150 Ohm resistors near VGA connector and
* 13
5
7
minimizing length to filter. The filters to VGA

connector maximum distance 800 mils.
3D3V_SYS
VSYNC_S
HSYNC_S
B B
D14
BAV99
1 2
5V_SYS
G
DDCA_CLK S D R21 +/-1% 5V_DDCA_CLK

16 DDCA_CLK
100 Ohm
G
Q4
*
DDCA_DATA 2N7002-7-F S D R22 +/-1%5V_DDCA_DATA

16 DDCA_DATA
100 Ohm
3
Q2
1 2 5V_SYS
2N7002-7-F
D9
BAV99
16 VSYNC
VSYNC R24
+/-5% * 0
Reserved
VSYNC_S
3
C4
*
R40
+/-5%
0
Dummy
R25
+/-5%
0
Reserved
1 2
3D3V_SYS * 10pF
50V, NPO, +/-5%
D3 Dummy
BAV99
A A
For EMI For EMI

C15,C26 Near by the connector
*
Place between VGA port and USB port Place between VGA port and Parallel port HSYNC R23 0 HSYNC_S
16 HSYNC
+/-5% Reserved
3
C3
10pF
1 2 3D3V_SYS * 50V, NPO, +/-5% FOXCONN PCEG
D2 Dummy Title
BAV99
Index Page
C G31M04 A

5 4 3 2 1

5
www.sp860.com 4 3
QQ:453100829 2
GPIO[39:36,23:21,19,7:0]: default as inputs and should be

pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to
VccSus3_3 if unused.
1
double check unused GPIO

pins
UI1F SIO PME change to GPIO8

UI1C
ICH7
ICH7
D 29,35 L_AD[3..0] D
Need to Checked
DMI_TXN0 V26 DMI0RXN USBP0N F1 USBP0N AA5 LDRQ1*/GPIO23 GPIO0/BM_BUSY* AB18 ICH7_GPIO0
16 DMI_TXN0 USBN0 38
16 DMI_TXP0
DMI_TXP0 V25 DMI0RXP USBP0P F2 USBP0P
USBP0 38
L_AD0 AA6 LAD0 GPIO6 AC21 ICH7_GPIO6
DMI_RXN0 C347 0.1uF 16V, X7R, +/-10% U28 DMI0TXN USBP1N G4 USBP1N L_AD1 AB5 LAD1 GPIO7 AC18 ICH7_GPIO7
** ** ** **
16 DMI_RXN0 USBN1 28
LPC
DMI_RXP0 C349 0.1uF 16V, X7R, +/-10% DMI_RXP0_ICH U27 DMI0TXP USBP1P G3 USBP1P L_AD2 AC4 LAD2 GPIO8 E21 L_PMEJ
16 DMI_RXP0 USBP1 28 L_PMEJ 35
16 DMI_TXN1
DMI_TXN1 Y26 DMI1RXN USBP2N H1 USBP2N
USBN2 38
L_AD3 Y6 LAD3 GPIO9 E20 ICH7_GPIO9
P66DET 26
DMI_TXP1 Y25 DMI1RXP USBP2P H2 USBP2P AC3 LDRQ0* GPIO10 A20 ICH7_GPIO10
16 DMI_TXP1 USBP2 38 35 L_DRQ0J
DMI_RXN1 C356 0.1uF 16V, X7R, +/-10% W28 DMI1TXN USBP3N J4 USBP3N AB3 LFRAME* GPIO12 F19 LAN_PMEJ
16 DMI_RXN1 USBN3 28 29,35 L_FRAMEJ LAN_PMEJ 32
DMI
DMI_RXP1 C359 0.1uF 16V, X7R, +/-10% DMI_RXP1_ICH W27 DMI1TXP USBP3P J3 USBP3P GPIO13 E19 ICH7_GPIO13
**
16 DMI_RXP1 USBP3 28
16 DMI_TXN2
DMI_TXN2 AB26 DMI2RXN USBP4N K1 USBP4N
USBN4 38 33 ICH_BCLK
R274 33 +/-5% r0402h4 U1 ACZ_BCLK GPIO14 R4 ICH7_GPIO14
DMI_TXP2 AB25 DMI2RXP USBP4P K2 USBP4P R267 33 +/-5% r0402h4 R5 ACZ_RST* GPIO15 E22 ICH7_GPIO15
16 DMI_TXP2 USBP4 38 33 ICH_RSTJ
AUDIO
DMI_RXN2 C365 0.1uF 16V, X7R, +/-10% AA28 DMI2TXN USBP5N L4 USBP5N T2 ACZ_SDI_0 GPIO16/DPRSLPVR AC22 Need to Checked
16 DMI_RXN2 USBN5 32
16 DMI_RXP2
DMI_RXP2 C363 0.1uF 16V, X7R, +/-10% DMI_RXP2_ICHAA27 DMI2TXP USBP5P L5 USBP5P
USBP5 32
T3 ACZ_SDI_1 GPIO18/STPPCI* AC20 ICH7_GPIO18
DMI_TXN3 AD25 DMI3RXN USBP6N M1 USBP6N T1 ACZ_SDI_2 GPIO20/STPCPU* AF21
16 DMI_TXN3
**
DMI_TXP3 USBP6P USBN6 38 33 ICH_SDIN2 PWR_LED 9
16 DMI_TXP3
AD24 DMI3RXP USBP6P M2 R273 33 +/-5% r0402h4 T4 ACZ_SDOUT GPIO24 R3
*
USBP6 38 33 ICH_SDOUT
16 DMI_RXN3
DMI_RXN3 C369 0.1uF 16V, X7R, +/-10% AC28 DMI3TXN USBP7N N4 USBP7N
USBN7 32 33 ICH_SYNC
R270 33 +/-5% r0402h4 R6 ACZ_SYNC GPIO25 D20 R240 1K
DMI_RXP3 C370 0.1uF 16V, X7R, +/-10% DMI_RXP3_ICHAC27 DMI3TXP USBP7P N3 USBP7P AC1 CLK14 EL_RSVD/GPIO26 A21 +/-5% r0402h4 Reserved
16 DMI_RXP3 USBP7 32 8 CK_14M_ICH
USB
EL_STATE0/GPIO27 B21
W1 EE_CS EL_STATE1/GPIO28 E23
EPROM
30 HSI_N0
F26 PERN_1 OC0* D3 W3 EE_DIN GPIO32/CLKRUN* AG18
30 HSI_P0
F25 PERP_1 OC1* C4 Y2 EE_DOUT GPIO33/AZ_DOCK_EN* AC19 Board_ID0 29
HSO_N0_SLOT C328 0.1uF 16V, X7R, +/-10% E28 PETN_1 OC2* D5 ICH_BCLK Y1 EE_SHCLK GPIO34/AZ_DOCK_RST* U2
30 HSO_N0_SLOT Board_ID1 29
** **
USB_OCJ_FRONT 38
30 HSO_P0_SLOT
HSO_P0_SLOT C330 0.1uF 16V, X7R, +/-10% E27 PETP_1 OC3* D4 GPIO35 AD21
H26 PERN_2 OC4* E5 V3 LAN_CLK GPIO38 AD20 ICH7_GPIO38
32 HSI_N2_LAN Board_ID2 29Need
H25 PERP_2 OC5*/GPIO29 C3 C351 U3 LAN_RSTSYNC GPIO39 AE20 BIOS_WPJ to Checked
32 HSI_P2_LAN
*
C338 0.1uF 16V, X7R, +/-10% HSO_N2 PETN_2 OC6*/GPIO30 22pF R239 ICH_LAN_RSTJ LAN_RST* CPUPWRGD_GPIO49
32 HSO_N2_LAN
32 HSO_P2_LAN
C339 0.1uF 16V, X7R, +/-10% HSO_P2
G28
G27 PETP_2 OC7*/GPIO31
A2
B3
USB_OCJ_BACK 32
* 50V, NPO, +/-5% 10K +/-5% r0402h4
C19
U5 LAN_RXD0
AG24 CPU_PWRG 14
K26 PERN_3 V4 LAN_RXD1 THRM* AF20 ICH_THRM_UP
LAN
ICH_VRMPWRGD_UP ICH_THRM_UP 14,35
K25 PERP_3 T5 LAN_RXD2 VRMPWRGD AD22
MISC
J28 PETN_3 USBRBIAS D1 USBRBIAS_ICH R261 22.6 U7 LAN_TXD0 MCH_SYNC* AH20
ICH_SYNCJ 16
J27 PETP_3 USBRBIAS* D2 V6 LAN_TXD1 PWRBTN* C23
PCI-EXPRESS
Dummy ICH_RIJ_PU PWRBTNJ 35
M26 PERN_4 V7 LAN_TXD2 RI* A28
M25 PERP_4 SUS_STAT* A27 LPCPDJ LPCPDJ 29
L28 PETN_4 ICH_RTCX1 AB1 RTCX1 SUSCLK C20 TP_SUSCLK VCCRTC
RTC
TP55
L27 PETP_4 CLK48 B2 CK_48M_ICH ICH_RTCX2 AB2 RTCX2 SYS_RST* A22
CK_48M_ICH 8 ICH_SYS_RSTJ 8,9,14
P26 PERN_5 26 RTCRSTJ
RTCRSTJ AA3 RTCRST* PLTRST* C26 PLTRSTJ
PLTRSTJ 16,29,35
P25 PERP_5 WAKE* F20 WAKEJ
C SMB_ALERT_PU INTRUDERJ WAKEJ 23,30 C
N28 PETN_5 USBRBIAS connection B23 SMBALERT*/GPIO11 INTRUDER* Y5 R281
N27 PETP_5 5 mils width, length no longer than 500 mils
23,30,31,36 SMB_CLK_RESUME
C22 SMBCLK PWROK AA4
PWRGD_3V 16,35
390K
T25 PERN_6 Trace tied together close to pins. B22 SMBDATA RSMRST* Y4 NB_RSMRSTJ +/-5%
23,30,31,36 SMB_DATA_RESUME SMALERT_ICH INTVRMEN
T24 PERP_6 A26 LINKALERT* INTVRMEN W4
SMB
R28 PETN_6 SMLINK0 B25 SMLINK0 SPKR A19 SPKR
SPKR 9
1D5V_PE_ICH R27 PETP_6 SMLINK1 A25 SMLINK1 check pull-up resistor
SLP_S3* B24
SLP_S3J 35
R252 24.9 DMI_COMP_ICH C25 DMI_ZCOMP ICH_SPI_MOSI P5 SPI_MOSI SLP_S4* D23
SLP_S4J 13
+/-1% DMI_IRCOMP ICH_SPI_MISO SPI_MISO SLP_S5*
SPI
D25 P2 F22 TP66
ICH_SPI_CSJ P6 SPI_CS*
DMI compensation CK_PE_100M_N_ICH AE28 DMI_CLKN ICH_SPI_CLK R2 SPI_CLK TP0/BATLOW* C21 ICH_BATLOW_PU
8 CK_PE_100M_N_ICH
5 mils width, 7 mils spacing CK_PE_100M_P_ICH AE27 DMI_CLKP 2 of 6 SPI_ARB P1 SPI_ARB TP1/DPRSTP* AF24 TP_ICH7_AF24
8 CK_PE_100M_P_ICH TP56 TP57
Place the resistor within 500 mils of ICH7 TP2/DPSLP* AH25 TP_ICH7_AH25
TP59
bga652h26_ich7 TP3 TP_ICH7_F21
1 ? 4 of 6 F21 TP58
bga652h26_ich7
1 ?
*
R279 +/-5% RSMRSTJ
RSMRSTJ 35
*
8,10,14 VRMPWRGD R309 0 Dummy ICH_VRMPWRGD_UP 0 @CLONE
+/-5% r0402h4
C418
3D3V_SYS R299 3D3V_SB
*
1
100KOhm R399 3D3V_SB 3D3V_SB
3D3V_SB +/-1% * Need Check??
*R388 22K 1
1uF
10V, Y5V, +80%/-20%
RN29 3D3V_SB r0402h4 4.7K +/-5% R277
*
2
U15 U17
*
1 2 ICH7_GPIO14 Dummy +/-5% r0402h4 22K R392 +/-5%
5
1
5
1
3 4 SMALERT_ICH r0402h4 @TF +/-5% 0 @CLONE
RN39 6 SMLINK0
ICH7_GPIO7
ICH_VRMPWRGD_UP *
1 2
5
7 8 SMLINK1 *R243
8.2K
+/-5%
@CLONE
2
#R388#R399
2 4 2 4 E C NB_RSMRSTJ
3 4 Q85
ICH_THRM_UP 10K r0402h4 C367 @TF @TF MMBT3906
ICH7_GPIO6
5
7
6
8 +/-5%
* 1uF @TF *R278
10K
B
3
3
8p4r0603h7 ICH_RIJ_PU @TF +/-5%
10K 10V, Y5V, +80%/-20% @TF
+/-5% 3D3V_SB
R406
B
RN28 B
*
*
ICH7_GPIO0 R296 10K +/-5%
*
1
3
2 L_PMEJ
4 ICH7_GPIO15
3D3V_SB
5 6 SMB_ALERT_PU
1
VCCRTC 4.7K
7 8 ICH_BATLOW_PU
+/-5%
10K @TF 3
*
+/-5% INTRUDERJ R280 1M
8p4r0603h7 +/-5% r0402h4 D44
BAV99
A 2
3D3V_SB 3D3V_SB @TF
RN27
Chassis Intruder Header

*
1
3
2 ICH7_GPIO10
4 LAN_PMEJ
D46
1N4148W
5 6 WAKEJ @TF
7 8 ICH7_GPIO13
C
* *
INTR ICH7_GPIO9 R241 10K +/-5%

INTRUDERJ 10K r0402h4 Dummy
1
2 +/-5%
LPCPDJ
*R405
2.2K
8p4r0603h7 R242 10K +/-5% +/-5%
Header_1X2 Use 3D3V_SYS or not r0402h4 Dummy U16_1 @TF
Steven Sun Update 2007.03.28 3D3V_SYS
W25X40VDAIZ
*R297
4.7K
Use 3D3V_SYS or not +/-5%
3D3V_SB W25X40VDAIZ r0402h4
Dummy ICH7_GPIO18
C
ICH_RTCX2
*
7
5
3
1 *
R310 1K B Q35
10,14 VID_SELECT MMBT3904_NL
ICH_RTCX1 close to ICH7 RN40 Use 3D3V_SYS or not r0402h4 +/-5%
10K Dummy Dummy
E
3D3V_SB
+/-5%
*
R282 10M
+/-5%
8
6
4
2
A A
X3 XTAL-32.768kHz X3_1 16V, Y5V, +80%/-20%
2 1 3D3V_SB C417 0.1uF *R329
10K
*
+/-5%
Need to Apply C368 C371 U16 Reserved
4
12pF 12pF ICH_SPI_CSJ r0402h4

* * 8 1
*
50V, NPO, +/-5% 50V, NPO, +/-5% Crystal Retainer ICH_SPI_HOLDJ 7 VCC CS 2 SPI_MISO R304 47 ICH_SPI_MISO
**
ICH_SPI_CLK R265 47 +/-5% r0402h4 SPI_CLK HOLD DO +/-5% r0402h4 BIOS_WPJ

6 3
ICH_SPI_MOSI R266 47 +/-5% r0402h4 SPI_MOSI CLK WP
5 4
DIO GND
This clip is for ICH7
32.768Khz Crystal clip. close to ICH7 within 100 mils Socket
FOXCONN PCEG
Assume Capastor CL value is 12.5 Title
SPI Population Options Index Page
C G31M04 A

5 4 3 2 1

5
www.sp860.com 4 3
QQ:453100829 2 1
UI1B 1
3D3V_SYS
ICH7 SATA_TXP0 C471 10nF 25V, X7R, +/-10% SATA_TXP0_C 2
** **
SATA_TXN0 C475 10nF 25V, X7R, +/-10% SATA_TXN0_C 3 8
PIDE_D0 AB15 DD0 SATA0RXN AF3 SATA_RXN0 4 SATA_1
PIDE_D1 AE14 DD1 SATA0RXP AE3 SATA_RXP0 SATA_RXN0 C488 10nF 25V, X7R, +/-10% SATA_RXN0_C 5 9 CONN_SATA
PIDE_D2 AG13 DD2 SATA0TXN AG2 SATA_TXN0 SATA_RXP0 C491 10nF 25V, X7R, +/-10% SATA_RXP0_C 6
PIDE_D3 DD3 SATA0TXP SATA_TXP0
D
PIDE_D4
AF13
AD14 DD4 RSVD/SATA1RXN
RSVD/SATA1RXP
AH2
AE5 SATA_RXN1
7
*R366
8.2K *R365
4.7K
D
PIDE_D5 AC13 DD5 AD5 SATA_RXP1 1 +/-5% +/-5%

PIDE_D6 AD12 DD6 RSVD/SATA1TXN AG4 SATA_TXN1 SATA_TXP1 C472 10nF 25V, X7R, +/-10% SATA_TXP1_C 2 r0402h4 r0402h4
** **
PIDE_D7 AC12 DD7 RSVD/SATA1TXP AH4 SATA_TXP1 SATA_TXN1 C476 10nF 25V, X7R, +/-10% SATA_TXN1_C 3 8 SATA_3
PIDE_D8 AE12 DD8 SATA2RXN AF7 SATA_RXN2 4 CONN_SATA
SATA
PIDE_D9 AF12 DD9 SATA2RXP AE7 SATA_RXP2 SATA_RXN1 C480 10nF 25V, X7R, +/-10% SATA_RXN1_C 5 9
PIDE_D10 AB13 DD10 SATA2TXN AG6 SATA_TXN2 SATA_RXP1 C485 10nF 25V, X7R, +/-10% SATA_RXP1_C 6 PIDE
PIDE_D11 AC14 DD11 SATA2TXP AH6 SATA_TXP2 7 P_IDERSTJ 1 2
PIDE_D12 AF14 DD12 IDE RSVD/SATA3RXN AD9 SATA_RXN3 PIDE_D7 3 4 PIDE_D8
PIDE_D13 AH13 DD13 RSVD/SATA3RXP AE9 SATA_RXP3 PIDE_D6 5 6 PIDE_D9
PIDE_D14 AH14 DD14 RSVD/SATA3TXN AG8 SATA_TXN3 PIDE_D5 7 8 PIDE_D10
PIDE_D15 AC15 DD15 RSVD/SATA3TXP AH8 SATA_TXP3 PIDE_D4 9 10 PIDE_D11
SATACLKN AF1 CK_SATA_100M_N_ICH PIDE_D3 11 12 PIDE_D12
CK_SATA_100M_N_ICH 8
PIDE_DAKJ AF16 DDACK* SATACLKP AE1 CK_SATA_100M_P_ICH PIDE_D2 13 14 PIDE_D13
CK_SATA_100M_P_ICH 8
PIDE_DREQ AE15 DDREQ PIDE_D1 15 16 PIDE_D14
PIDE_IORJ AF15 DIOR* PIDE_D0 17 18 PIDE_D15
PIDE_IOWJ AH15 DIOW* SATARBIASN AH10 SATARBIAS_ICH R300 24.9 19
PIDE_RDY PIDE_DREQ X
AG16 IORDY SATARBIASP AG10 SATARBIAS connection 21 22
AF18 SATA_LED 5 mils width, length no longer than 500 mils PIDE_IOWJ 23 24 Cable detection
SATALED*
PIDE_A0 AH17 DA0 Trace tied together close to pins. PIDE_IORJ 25 26 high: 40-conductor cable(ATA 33)
PIDE_A1 AE17 DA1 GPIO21/SATA0GP AF19 R295 10K PIDE_RDY 27 28 low: 80-conductor cable(ATA 66/100)
3D3V_SYS
*
PIDE_A2 AF17 DA2 GPIO19/SATA1GP AH18 +/-5% r0402h4 PIDE_DAKJ 29 30
GPIO36/SATA2GP AH19 IRQ14 31 32
PIDE_CS1J AE16 DCS1* GPIO37/SATA3GP AE19 PIDE_A1 33 34
PIDE_CS3J PIDE_A0 PIDE_A2 P66DET 25
AD16 DCS3* 35 36
A20GATE AE22 A20GATE 35
PIDE_CS1J 37 38 PIDE_CS3J ?
A20M* AH28 A20MJ 14
PIDE_LED 39 40
IRQ14 AH16 IDEIRQ CPUSLP* AG27 TESTHI_13 14
IGNNE* C481
INIT3_3V*
AG22
AG21
IGNNEJ 14
SATA_TXP2 C479 10nF 25V, X7R, +/-10% SATA_TXP2_C
1
2
Header_2X20_20
* 47nF *R367
10K
** **
HOST
INIT* AF22 SATA_TXN2 C484 10nF 25V, X7R, +/-10% SATA_TXN2_C 3 8 SATA_2 16V,X7R,+/-10% +/-5%
INITJ 14
INTR AF25
INTR 14
4 CONN_SATA HDD1 r0402h4
FERR* AG26 FERRJ
FERRJ 14
SATA_RXN2 C490 10nF 25V, X7R, +/-10% SATA_RXN2_C 5 9 Dummy
NMI AH24 SATA_RXP2 C493 10nF 25V, X7R, +/-10% SATA_RXP2_C 6
NMI 14
RCIN* AG23
KBRSTJ 35
7
SERIRQ AH21 SERIRQ 29,35
SMI* AF23 SMIJ 14 1
C STPCLK* AH22 SATA_TXP3 C470 10nF 25V, X7R, +/-10% SATA_TXP3_C 2 C
STPCLKJ 14
** **
3 of 6 THERMTRIP* AF26 THERMTRIPJ
THERMTRIPJ 14
SATA_TXN3 C474 10nF 25V, X7R, +/-10% SATA_TXN3_C 3 8 SATA_4 IDE data lines should be matched to strobes(IORJ, RDY)within +/- 250 mils,
4 CONN_SATA strobes should be matched to their complement within +/- 10 mils
SATA_RXN3 C489 10nF 25V, X7R, +/-10% SATA_RXN3_C 5 9
bga652h26_ich7 1 ? SATA_RXP3 C492 10nF 25V, X7R, +/-10% SATA_RXP3_C 6
Reserved
7
*
R387 33 P_IDERSTJ
35 IDE_RSTJ +/-5% r0402h4
C511
placed near IDE connector 0.1uF
3D3V_SB * 16V, Y5V, +80%/-20%
VCCRTC Dummy
FSB_VTT D25
1 width 20 mils
3
VBAT 2
3D3V_SYS
*
R302 62 THERMTRIPJ
B
+/-5% r0402h4 BAT54C *R319
20K
+/-1%
B
C183 R345 R344

* *
*
R301 62 FERRJ R143 1uF 10K 10K

+/-5% r0402h4 1K * 10V, Y5V, +80%/-20% +/-5% +/-5%
+/-1% RTCRSTJ r0402h4 r0402h4
C423
1
Place at ICH7 end of route 1uF
C419 * 10V, Y5V, +80%/-20% PIDE_LED
+
1uF BAT1
* 2 1
D38
10V, Y5V, +80%/-20% 3

Dummy Battery Holder HDD_LEDJ 9
2
-
SATA_LED
BAT54A
BAT1_1
LITHIUM BATT
CR2032
Battery
Clear CMOS CLR_CMOS:2-3
For battery cell.
CLR_CMOS CLR_CMOS CMOS
1
1
2
25 RTCRSTJ 2
A 3 Clear (1-2) A
3 Jumper
Header_1X3 Normal (2-3) Default Reserved
FOXCONN PCEG
Title
Index Page
C G31M04 A

5 4 3 2 1

5
UI1A
ICH7
www.sp860.com AD[31..0]
4
1D5V_CORE
UI1D
ICH7
3
QQ:453100829 REF5V
1D5V_CORE
2
E4
AG11
C27
R14
VSS
VSS
VSS
VSS
UI1E
ICH7
1
VSS
VSS
VSS
VSS
A4
A23
B1
B8
AD[31..0] 31
R15 VSS VSS B11
A1 VCC1_5_A R16 VSS VSS B14
PAR E10 PAR AD0 E18 AD0 AB10 VCC1_5_A V5REF AD17 R17 VSS VSS B17
31 PAR
DEVSELJ A12 DEVSEL* AD1 C18 AD1 AB17 VCC1_5_A V5REF G10 R18 VSS VSS B20
31 DEVSELJ
1
A9 PCICLK AD2 A16 AD2 AB7 VCC1_5_A REF5V_SUS T6 VSS VSS B26
8 CK_33M_ICH
B18 PCIRST* AD3 F18 AD3 AB8 VCC1_5_A V5REF_SUS F6 VCCRTC L36 T12 VSS VSS B28
31 IRDYJ
IRDYJ A7 IRDY* AD4 E16 AD4 AB9 VCC1_5_A L0805 10uH T13 VSS VSS C2
PMEJ B19 PME* AD5 A18 AD5 AC10 VCC1_5_A VCCRTC W5 1D5V_CORE T14 VSS VSS C6
31
31
PMEJ
SERRJ
SERRJ
STOPJ
B10
F15
SERR*
STOP*
PCI AD6
AD7
E17
A17
AD6
AD7
AC17
AC6
VCC1_5_A
VCC1_5_A VCCUSBPLL C1
+/-20% T15
T16
VSS
VSS
VSS
VSS
D10
D13
31 STOPJ
2
LOCKJ E11 PLOCK* AD8 A15 AD8 3D3V_SYS 3D3V_SYS AC7 VCC1_5_A T17 VSS VSS D18
31 LOCKJ
TRDYJ F14 TRDY* AD9 C14 AD9 AC8 VCC1_5_A VCCSATAPLL AD2 U4 VSS VSS D21
31 TRDYJ
D PERRJ C9 PERR* AD10 E14 AD10 AD10 VCC1_5_A U12 VSS VSS D24 D
31 PERRJ
FRAMEJ F16 FRAME* AD11 D14 AD11 C321 C388 AD6 VCC1_5_A VCCDMIPLL AG28 VCCDMIPLL 1D05V_SYS C421 C394 U13 VSS VSS E1
31 FRAMEJ
1
AD12 AD12 0.1uF 0.1uF 10uF 0.1uF
31 GNT0J E7 GNT0* AD13
B12
C13 AD13 * * AE10
AE6
VCC1_5_A
VCC1_5_A VCC1_05 L11 * 10V, Y5V, +80%/-20% * Near AD2 U14
U15
VSS
VSS
VSS
VSS
E2
E8
31 GNT1J D16 GNT1* AD14 G15 AD14 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% AF10 VCC1_5_A VCC1_05 L12 16V, Y5V, +80%/-20% U16 VSS VSS E15
2
D17 GNT2* AD15 G13 AD15 AF5 VCC1_5_A VCC1_05 L14 U17 VSS VSS F3
F13 GNT3* AD16 E12 AD16 AF6 VCC1_5_A VCC1_05 L16 U24 VSS VSS F4
A14 GNT4*/GPIO48 AD17 C11 AD17 AF9 VCC1_5_A VCC1_05 L17 U25 VSS VSS F5
GNT5J D8 GNT5*/GPIO17 AD18 D11 AD18 AG5 VCC1_5_A VCC1_05 L18 U26 VSS VSS F12
AD19 A11 AD19 AG9 VCC1_5_A VCC1_05 M11 V2 VSS VSS F27
D7 REQ0* AD20 A10 AD20 AH5 VCC1_5_A VCC1_05 M18 V13 VSS VSS F28
31 PREQ0J
C16 REQ1* AD21 F11 AD21 AH9 VCC1_5_A VCC1_05 P11 V15 VSS VSS G1
31 PREQ1J
31 PREQ2J C17 REQ2* AD22 F10 AD22 F17 VCC1_5_A VCC1_05 P18 V24 VSS VSS G5
31 PREQ3J E13 REQ3* AD23 E9 AD23 G17 VCC1_5_A VCC1_05 T11 V27 VSS VSS G2
31 PREQ4J A13 REQ4*/GPIO22 AD24 D9 AD24 H6 VCC1_5_A VCC1_05 T18 V28 VSS VSS G6
C8 GPIO1/REQ5* AD25 B9 AD25 H7 VCC1_5_A VCC1_05 U11 W6 VSS VSS G9
31 PREQ5J
AD26 A8 AD26 J6 VCC1_5_A VCC1_05 U18 W24 VSS VSS G14
A3 PIRQA* AD27 A6 AD27 J7 VCC1_5_A VCC1_05 V11 W25 VSS VSS G18
31 INTAJ
31 INTBJ B4 PIRQB* AD28 C7 AD28 1D5V_PE_ICH T7 VCC1_5_A VCC1_05 V12 W26 VSS VSS G21
31 INTCJ C5 PIRQC* AD29 B6 AD29 VCC1_05 V14 Y3 VSS VSS G24
31 INTDJ B5 PIRQD* AD30 E6 AD30 D26 VCC1_5_B VCC1_05 V16 Y24 VSS VSS G25
G8 GPIO2/PIRQE* AD31 D6 AD31 D27 VCC1_5_B VCC1_05 V17 Y27 VSS VSS G26
31 INTEJ
31 INTFJ F7 GPIO3/PIRQF* D28 VCC1_5_B VCC1_05 V18 Y28 VSS VSS H3
F8 GPIO4/PIRQG* C/BE0* B15 CBEJ0 E24 VCC1_5_B 1D5V_CORE AA1 VSS VSS H4
31 INTGJ CBEJ0 31
G7 C/BE1* C12 CBEJ1 E25 VCC1_5_B FSB_VTT AA24 VSS VSS H5
31 INTHJ GPIO5/PIRQH* CBEJ1 31
C/BE2* D12 CBEJ2 E26 VCC1_5_B V_CPU_IO AE23 AA25 VSS VSS H24
1 of 6 C/BE3* C15 CBEJ3 CBEJ2 31 F23 VCC1_5_B V_CPU_IO AE26 AA26 VSS VSS H27
POWER
CBEJ3 31 3D3V_SYS C255 C334
F24 VCC1_5_B V_CPU_IO AH26 AB4 VSS VSS H28
G22 VCC1_5_B 0.1uF 0.1uF AB6 VSS VSS J1
1
bga652h26_ich7 G23 VCC1_5_B VCC3_3 A5 AB11 VSS VSS J2
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

VCC1_5_B VCC3_3
GNT5J GNT4J BOOT
H22
H23 VCC1_5_B VCC3_3
AA7
AB12 * * AB14
AB16
VSS
VSS
VSS
VSS
J5
J24
0 1 SPI J22 VCC1_5_B VCC3_3 AB20 AB19 VSS VSS J25
1 0 PCI J23 VCC1_5_B VCC3_3 AC16 AB21 VSS VSS J26
1 1 LPC 1D5V_CORE K22 VCC1_5_B VCC3_3 AD13 AB24 VSS VSS K24
VCCDMIPLL LRC Filter K23 VCC1_5_B VCC3_3 AD18 AB27 VSS VSS K27
L22 VCC1_5_B VCC3_3 AG12 AB28 VSS VSS K28
*
GNT5J R237 1K L23 VCC1_5_B VCC3_3 AG15 AC2 VSS VSS L13
+/-5% r0402h4 Reserved M22 VCC1_5_B VCC3_3 AG19 Dummy Dummy AC5 VSS VSS L15
L0805 1uH M23 VCC1_5_B VCC3_3 AH11 AC9 VSS VSS L24
L35 1 2 VCCDMIPLL N22 VCC1_5_B VCC3_3 B13 AC11 VSS VSS L25
+/-10% N23 VCC1_5_B VCC3_3 B16 AD1 VSS VSS L26
C420 C408 P22 VCC1_5_B VCC3_3 B27 AD3 VSS VSS M3
1
extra one 47uF(backside) in DG0.7
Rated at least 100mA
* 10uF
10V, Y5V, +80%/-20% * 10nF P23
R22
VCC1_5_B
VCC1_5_B
VCC3_3
VCC3_3
B7
C10
AD4
AD7
VSS
VSS
VSS
VSS
M4
M5
C Dummy 25V, X7R, +/-10% R23 VCC1_5_B VCC3_3 D15 AD8 VSS VSS M12 C
2
R24 VCC1_5_B VCC3_3 F9 AD11 VSS VSS M13
R25 VCC1_5_B VCC3_3 G11 AD15 VSS VSS M14
R26 VCC1_5_B VCC3_3 G12 AD19 VSS VSS M15
1D05V_SYS 1D5V_CORE T22 VCC1_5_B VCC3_3 G16 AD23 VSS VSS M16
T23 VCC1_5_B VCC3_3 U6 3D3V_SB AE2 VSS VSS M17
Place LRC near pin AG28 T26 VCC1_5_B VCCSUS3_3 A24 AE4 VSS VSS M24
T27 VCC1_5_B VCCSUS3_3 C24 AE8 VSS VSS M27
C299 T28 VCC1_5_B VCCSUS3_3 D19 AE11 VSS VSS M28
C342 C343 C298 0.1uF 1D5V_CORE U22 VCC1_5_B VCCSUS3_3 D22 AE13 VSS VSS N1
0.1uF 1uF 0.1uF
* * * * U23 VCC1_5_B VCCSUS3_3 E3 AE18 VSS VSS N2
10V, X5R, +/-10%
Dummy V22 VCC1_5_B VCCSUS3_3 G19 AE21 VSS VSS N5

16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
Dummy VCC1_5_B VCCSUS3_3 VSS VSS

VCC1_5_B LC Filter V23
W22 VCC1_5_B VCCSUS3_3
K3
K4
AE24
AE25 VSS VSS
N6
N11
L33 0 W23 VCC1_5_B VCCSUS3_3 K5 AF2 VSS VSS N12
Y22 VCC1_5_B VCCSUS3_3 K6 AF4 VSS VSS N13
Near D28, T28,and AD28 Y23 VCC1_5_B VCCSUS3_3 L1 AF8 VSS VSS N14
L34 0 1D5V_PE_ICH AA22 VCC1_5_B VCCSUS3_3 L2 AF11 VSS VSS N15
C372 C373 C346 C345 AA23 VCC1_5_B VCCSUS3_3 L3 AF27 VSS VSS N16
EC56 0.1uF 0.1uF 0.1uF 0.1uF C376 AB22 VCC1_5_B VCCSUS3_3 L6 AF28 VSS VSS N17
1
ICH7 Core decoupling caps. * 100uF
16V, +/-20% * * * * * 10uF AB23
AC23
VCC1_5_B
VCC1_5_B
VCCSUS3_3
VCCSUS3_3
L7
M6
AG1
AG3
VSS
VSS
VSS
VSS
N18
N24
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
Dummy AC24 VCC1_5_B VCCSUS3_3 M7 AG7 VSS VSS N25

2
AC25 VCC1_5_B VCCSUS3_3 N7 AG14 VSS VSS N26

AC26 VCC1_5_B VCCSUS3_3 P7 AG17 VSS VSS P12
AD26 VCC1_5_B VCCSUS3_3 R7 AG20 VSS VSS P13
Dummy Dummy AD27 VCC1_5_B VCCSUS3_3 V1 AG25 VSS VSS P14
AD28 VCC1_5_B VCCSUS3_3 V5 AH1 VSS VSS P15
VCCSUS3_3 W2 AH3 VSS VSS P3
1D5V_CORE 1D5V_PE_ICH 3D3V_SYS VCCSUS3_3 W7 VSS P4
VSS P16
Place LC near pin D28 VCCSUS1_05 AA2 TP_ICH7_AA2 AH7 VSS VSS P17
TP_ICH7_C28 TP61
C256 C322 VCCSUS1_05 C28 AH23 VSS VSS P24
TP_ICH7_G20 TP63
0.1uF C327 0.1uF VCCSUS1_05 G20 AH27 VSS VSS P27
TP_ICH7_K7 TP62
* Dummy 0.1uF
Reserved * 16V, Y5V, +80%/-20%
VCCSUS1_05 K7
TP_ICH7_Y7 TP65 VSS P28
16V, Y5V, +80%/-20% * 5V_SB 3D3V_SB 5 of 6 VCCSUS1_05 Y7

TP64
AH12 VSS VSS
VSS
R1
R11
16V, Y5V, +80%/-20% REF5V_SUS VSS R12
C515 bga652h26_ich7 VSS R13
0.1uF 1 ? 6 of 6
A
Place near B27

* R233 D30 * 16V, Y5V, +80%/-20% bga652h26_ich7
10 1N4148W Dummy
Place near D28 REF5V_SUS 3D3V_SB
+/-1%
C
B PCI-E decoupling caps. C315 REF5V_SUS Please Bottom near Pin

B
0.1uF F6 within 40mil

* 16V, Y5V, +80%/-20%
C358
0.1uF
place cap. near pin F6 * 16V, Y5V, +80%/-20%

within 40 mils REF5V
C516
1D5V_CORE 1D5V_CORE 0.1uF
V5REF_SUS / 3D3V_SB Power Sequencing
* 16V, Y5V, +80%/-20% Place near V1
C336 C337 Dummy
0.1uF
* 10nF
* Reserved 25V, X7R, +/-10%
LAN decoupling caps. VCCRTC
16V, Y5V, +80%/-20% Reserved Please Bottom near Pin FSB_VTT FSB_VTT
double check in new CRB or DG G10 within 40mil
Place near A1 Place near C1 C393 C391 C364 C435 C366

0.1uF 0.1uF
C400
0.1uF 0.1uF
* 1uF
10V, Y5V, +80%/-20%
* * * *
1
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

5V_SYS 3D3V_SYS
3D3V_SB * 4.7uF
6.3V, X5R, +/-10%
3D3V_SYS
A
2
R305 D37 1D5V_CORE 1D5V_CORE Dummy
3D3V_SB 1K 1N4148W
Need to Check Change to Dummy
+/-1%
16V, Y5V, +80%/-20%
C361
C
C344 C457 C414 C416 0.1uF Place near W5

0.1uF 0.1uF C341 0.1uF 1uF
* * * 10nF REF5V
REF5V
* * 10V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% Near AE23 and AE26 Place near AH26
Reserved Reserved C415 16V, Y5V, +80%/-20% Reserved
16V, Y5V, +80%/-20% 25V, X7R, +/-10% 0.1uF Reserved
RTC decoupling caps.
* 16V, Y5V, +80%/-20%
CPU decoupling caps.
Place near AH5 Place near AH9 Place near U6
place cap. near pin AD17/G10
Near L1 and K3 within 40 mils
Place near E3
V5REF / 3D3V_SYS Power Sequencing
Audio decoupling caps. 3D3V_SYS
3D3V_SYS 1D5V_CORE
A USB decoupling caps. A
3D3V_SYS 3D3V_SYS
C519
VCCDMIPLL C413 C424 0.1uF C323 C311 C317 C319
* 0.1uF
* 0.1uF
* 16V, Y5V, +80%/-20%
*
0.1uF
*
0.1uF
*
0.1uF
*
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% C412 Dummy Dummy
16V, Y5V, +80%/-20%

C409 0.1uF Please Bottom
10nF
* * 16V, Y5V, +80%/-20%
near Pin AB12
within 40mil
25V, X7R, +/-10% Place near AH11 Place near AD2
Dummy
FOXCONN PCEG
Place near AG28
Place near AG15/AB12 Place near A5, B7, C10 Title
Index Page
DMI decoupling caps. SATA decoupling caps. PCI decoupling caps. Size Document Number Rev
IDE decoupling caps. Custom G31M04 A

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Rear Dual USB Connector

D D
SVCC2
C34 EC19
* 0.1uF * 470uF
16V, +/-20%
16V, Y5V, +80%/-20%
Reserved
C C
L7 Dummy
1 4
2 3 USB USBN3 USBP3

Common Choke 90 Ohm_2L
3
1
USBN3 R26 0 Reserved V0
2 1 2 SVCC2 1 2 SVCC2
25 USBN3 USBP3 R27 0 Reserved -D0 5 6 7 8
3
25 USBP3 +D0
4
G0 D8 D1
5 BAV99 BAV99
USBN0 R11 0 Reserved V1 1 2 3 4 Reserved Reserved
6
25 USBN0 USBP0 R13 0 Reserved -D1 USBP0 USBN0
7
25 USBP0 +D1
8
CG1
CG2
CG3
CG4
G1
3
1 2 SVCC2 1 2 SVCC2
L1 Dummy CONN-USBx2
9
10
11
12
1 4 Reserved
D4 D11
2 3 BAV99 BAV99
Reserved Reserved
Common Choke 90 Ohm_2L
B B
A A
FOXCONN PCEG
Title
REAR USB
Custom G31M04 A

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MH4 MH3 MH1 MH5 MH6 MH2

Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole
3D3V_SYS
6
5
6
5
6
5
6
5
6
5
6
5
D TPM D
7 4 7 4 7 4 7 4 7 4 7 4
1 2 8 3 8 3 8 3 8 3 8 3 8 3
8 CK_33M_TPM LCLK GND
9 2 9 2 9 2 9 2 9 2 9 2
3
1
25,35 L_FRAMEJ LFRAMEn KEY
5 6 CP19 X_COPPER mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8 mh40x80_8

16,25,35 PLTRSTJ LRESETn NC_3 SMB_DATA_MAIN 8,20,22,36
L_AD3 7 8 L_AD2
25,35 L_AD3 LAD3 LAD2 L_AD2 25,35
9 10 L_AD1
VDD LAD1 L_AD1 25,35
L_AD0 11 12
25,35 L_AD0 LAD0 GND 3D3V_SYS
13 14
NC_1 NC_4
15 16
NC_2 SERIRQ SERIRQ 26,35
17
GND CLKRUNin
18 *R306
1K *R271
1K *R308
1K
+/-5% +/-5% +/-5%
19 20 CP20 X_COPPER r0402h4 r0402h4 r0402h4
25 LPCPDJ LPCPDn NC_5 SMB_CLK_MAIN 8,20,22,36 Reserved Reserved @3JACK
Header_2X10_4 (TPM)
@TF
Board_ID2 Board_ID2 25
Board_ID1 Board_ID1 25
Board_ID0
C Need check? Board_ID0 25 C
*R298
1K *R269
1K *R307
1K
+/-5% +/-5% +/-5%
r0402h4 r0402h4 r0402h4
Dummy Dummy @6JACK
12V_SYS
3D3V_SYS 3D3V_SYS
3D3V_SYS T3 T4
1 1
2 2
B T1 T1 B
C133
* C320 C455 * 10nF

25V, X7R, +/-10%
4.7uF
Dummy * 10nF
25V, X7R, +/-10%
Dummy
Dummy
12V_SYS
T1 T2 FD1 FD2 FD3 FD4

1 1 FMARK FMARK FMARK FMARK
2 2 FD40 FD40 FD40 FD40
T1 T1
1
A A
FOXCONN PCEG
Title
FWH
Custom G31M04 A

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D D
3D3V_SB 3D3V_SYS 12V_SYS

12V_SYS 3D3V_SYS
12V_SYS 3D3V_SYS 3D3V_SB
C131 C135
PCI-E1_1X 0.1uF 0.1uF
1
B1
B2
12V
12V
PRSNT1#
12V
A1
A2
* C114
0.1uF * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
C B3 A3 C
2
RSVD_1 12V 25V, X7R, +/-10%
B4 A4
GND GND
B5 A5
23,25,31,36 SMB_CLK_RESUME SMCLK JTAG2
B6 A6
23,25,31,36 SMB_DATA_RESUME SMDAT JTAG3
B7 A7
GND JTAG4
B8 A8
3.3V JTAG5
B9 A9
JTAG1 3.3V
B10 A10
3.3VAUX 3.3V
B11 A11
23,25 WAKEJ WAKE# PWRGD ICH_G_PLTRSTJ 23,35 3D3V_SB
KEY
B12 A12 EC35

RSVD_2 GND
B13
B14
GND REFCLK+
A13
A14
CK_PE_100M_P_1PORT_2 8 * 470uF
16V, +/-20%
25 HSO_P0_SLOT HSOP0 REFCLK- CK_PE_100M_N_1PORT_2 8
B15 A15
25 HSO_N0_SLOT HSON0 GND
B16 A16
GND HSIP0 HSI_P0 25
B17 A17
PRSNT2# HSIN0 HSI_N0 25
B18 A18
GND GND
Slot_PCI-X1
PCI-E x1 Slot 2
B B
A A
FOXCONN PCEG
Title
PCI Express x1 Slot
Custom G31M04 A

5 4 3 2 1

5
-12V_SYS 5V_SYS
www.sp860.com
3D3V_SYS
4
3D3V_SYS
5V_SYS
12V_SYS
3
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-12V_SYS 5V_SYS
3D3V_SYS
2
3D3V_SYS
5V_SYS
12V_SYS
1
Note: 20-24 mils PCI1 Note: 20-24 mils PCI2

B1 A1 B1 A1
-12V TRST# -12V TRST#
B2 A2 B2 A2
TCK +12V TCK +12V
B3 A3 B3 A3
GND1 TMS GND1 TMS
B4 A4 B4 A4
TDO TDI TDO TDI
B5 A5 B5 A5
+5V1 +5V2 INTBJ +5V1 +5V2 INTCJ
B6 A6 INTBJ 27 B6 A6 INTCJ 27
INTCJ +5V3 INTA# INTDJ INTDJ +5V3 INTA# INTAJ
27 INTCJ B7 A7 INTDJ 27 27 INTDJ B7 A7 INTAJ 27
INTAJ INTB# INTC# INTBJ INTB# INTC#
27 INTAJ B8 A8 27 INTBJ B8 A8
INTD# +5V4 3D3V_SB INTD# +5V4 3D3V_SB
D B9 A9 B9 A9 D
PRSNT1# RSV1 PRSNT1# RSV1
B10 A10 B10 A10
B11 RSV2 +5V5 A11 B11 RSV2 +5V5 A11
PRSNT2# RSV3 PRSNT2# RSV3
B12 A12 B12 A12
GND2 GND3 GND2 GND3
B13 A13 B13 A13
B14 GND4 GND5 A14 B14 GND4 GND5 A14
RSV4 SB3V RSV4 SB3V
B15 A15 PCIRSTJ 35 B15 A15 PCIRSTJ 35
GND6 RESET# GND6 RESET#
8 CK_33M_PCI1 B16 A16 8 CK_33M_PCI2 B16 A16
B17 CLK +5V6 A17 B17 CLK +5V6 A17
GND7 GNT# GNT0J 27 GND7 GNT# GNT1J 27
PREQ0J B18 A18 PREQ1J B18 A18
REQ# GND8 REQ# GND8
B19 A19 PMEJ 27 B19 A19 PMEJ 27
AD31 +5V7 PCI_PME# AD30 AD31 +5V7 PCI_PME# AD30
B20 A20 B20 A20
AD29 B21 AD(31) AD(30) A21 AD29 B21 AD(31) AD(30) A21
AD(29) +3.3V1 AD28 AD(29) +3.3V1 AD28
B22 A22 B22 A22
AD27 GND9 AD(28) AD26 AD27 GND9 AD(28) AD26
B23 A23 B23 A23
AD25 B24 AD(27) AD(26) A24 AD25 B24 AD(27) AD(26) A24
AD(25) GND10 AD24 AD(25) GND10 AD24
B25 A25 B25 A25
CBEJ3 B26 +3.3V2 AD(24) A26 IDSEL0 CBEJ3 B26 +3.3V2 AD(24) A26 IDSEL3
27 CBEJ3 C/BE#(3) IDSEL 27 CBEJ3 C/BE#(3) IDSEL
AD23 B27 A27 AD23 B27 A27
AD(23) +3.3V3 AD22 AD(23) +3.3V3 AD22
B28 A28 B28 A28
AD21 GND11 AD(22) AD20 AD21 GND11 AD(22) AD20
B29 A29 B29 A29
AD19 AD(21) AD(20) AD19 AD(21) AD(20)
B30 A30 B30 A30
B31 A31 B31 A31
AD17 +3.3V4 AD(18) AD16 AD17 +3.3V4 AD(18) AD16
B32 A32 B32 A32
AD(17) AD(16) AD(17) AD(16)
B33 A33 B33 A33
C/BE#(2) +3.3V5 FRAMEJ C/BE#(2) +3.3V5 FRAMEJ
27 CBEJ2 B34 A34 FRAMEJ 27 27 CBEJ2 B34 A34 FRAMEJ 27
IRDYJ GND13 FRAME# IRDYJ GND13 FRAME#
27 IRDYJ B35 A35 27 IRDYJ B35 A35
IRDY# GND14 TRDYJ IRDY# GND14 TRDYJ
B36 A36 TRDYJ 27 B36 A36 TRDYJ 27
DEVSELJ B37 +3.3V6 TRDY# A37 DEVSELJ B37 +3.3V6 TRDY# A37
27 DEVSELJ DEVSEL# GND15 27 DEVSELJ DEVSEL# GND15
B38 A38 STOPJ B38 A38 STOPJ
GND16 STOP# STOPJ 27 GND16 STOP# STOPJ 27
LOCKJ B39 A39 LOCKJ B39 A39
27 LOCKJ LOCK# +3.3V7 27 LOCKJ LOCK# +3.3V7
PERRJ B40 A40 PSCLK PERRJ B40 A40 PSCLK
27 PERRJ PERR# SDONE PSDATA 27 PERRJ PERR# SDONE PSDATA
B41 A41 B41 A41
SERRJ +3.3V8 SBO# SERRJ +3.3V8 SBO#
27 SERRJ B42 A42 27 SERRJ B42 A42
SERR# GND17 PAR SERR# GND17 PAR
B43 A43 PAR 27 B43 A43 PAR 27
CBEJ1 B44 +3.3V9 PAR A44 AD15 CBEJ1 B44 +3.3V9 PAR A44 AD15
27 CBEJ1 AD14 C/BE#(1) AD(15) 27 CBEJ1 AD14 C/BE#(1) AD(15)
B45 A45 B45 A45
AD(14) +3.3V10 AD13 AD(14) +3.3V10 AD13
B46 A46 B46 A46
C AD12 B47 GND18 AD(13) A47 AD11 AD12 B47 GND18 AD(13) A47 AD11 C
AD10 AD(12) AD(11) AD10 AD(12) AD(11)
B48 A48 B48 A48
B49 A49 B49 A49
GND20 AD(9) GND20 AD(9)
AD8 B52 A52 CBEJ0 AD8 B52 A52 CBEJ0

AD(8) C/BE#(0) CBEJ0 27 AD(8) C/BE#(0) CBEJ0 27
AD7 B53 A53 AD7 B53 A53
AD(7) +3.3V11 AD6 AD(7) +3.3V11 AD6
B54 A54 B54 A54
AD5 +3.3V12 AD(6) AD4 AD5 +3.3V12 AD(6) AD4
B55 A55 B55 A55
AD3 AD(5) AD(4) AD3 AD(5) AD(4)
B56 A56 B56 A56
B57 A57 B57 A57
AD1 B58 GND22 AD(2) A58 AD0 AD1 B58 GND22 AD(2) A58 AD0
AD(1) AD(0) AD(1) AD(0)
B59 A59 B59 A59
ACK64J B60 +5V8 +5V9 A60 REQ64_1J ACK64J B60 +5V8 +5V9 A60 REQ64_2J
ACK64# REQ64# ACK64# REQ64#
B61 A61 B61 A61
+5V10 +5V11 +5V10 +5V11
B62 A62 B62 A62
+5V12 +5V13 +5V12 +5V13
Slot,PCI CONN Slot,PCI CONN
AD[31..0] AD[31..0]
AD[31..0] 27 AD[31..0] 27
IDSEL0 R133 330 AD18

+-5%
5V_SYS 3D3V_SYS -12V_SYS

IDSEL3 R126 330 AD17
+-5%
B
C90 C232 B
CP15
0.1uF EC43 0.1uF
2
*
EC27
470uF * 16V, Y5V, +80%/-20%
* 1000uF
6.3V, +/-20% * 16V, Y5V, +80%/-20%
* C100
PSCLK 2 1 SMB_CLK_RESUME 23,25,30,36
16V, +/-20% 0.1uF Del R351,R352
1
X_COPPER
CP16
25V, X7R, +/-10% PSDATA 2 1 SMB_DATA_RESUME 23,25,30,36
X_COPPER
5V_SYS
3D3V_SYS
RN20
*1
RN14
INTBJ
INTBJ 27
*1 2 REQ64_2J
2 INTCJ 3 4 ACK64J
3 4 INTCJ 27 5 6
INTDJ REQ64_1J
5 6 INTDJ 27 7 8
INTAJ
7 8 INTAJ 27
2.7K
8.2K +/-5%
+/-5%
RN30
*1 2 PREQ1J
PREQ2J
27
27
PCI Slot
3 4 3D3V_SYS
5 6 PREQ3J 27
7 8 PREQ0J 27
RN19
8.2K
+/-5%
*1 2
STOPJ
LOCKJ
RN26 3 4 PERRJ
5 6
* 13 2
4
INTGJ
INTHJ
INTGJ
INTHJ
27
27
1394a
7 8
SERRJ
A INTFJ IT8211 8.2K A

5 6 INTFJ 27
INTEJ +/-5%
7 8 INTEJ 27
8.2K
+/-5% RN18
Reserved
* 13 2
FRAMEJ
IRDYJ
**
R238 8.2K +/-5% r0402h4 4 TRDYJ

PREQ4J 27 5 6
R236 8.2K +/-5% r0402h4 DEVSELJ
PREQ5J 27 7 8
8.2K FOXCONN PCEG
+/-5%
Title
PCI Slot
C
G31M04 A

5 4 3 2 1

5
3D3V_SB
www.sp860.com U26
4
U25 U82
RTL8111B-VC-GR
3
QQ:453100829 VDD33
AVDDL
2
EECS 1
U2
8
1
VDD33
VDD33
C20
1
EESK CS VCC
* R2 RTL8101E-GR RTL8111C-GR
* C514 2 7
* 0.1uF
E
0 10uF EEDI/AUX 3 SK DC 6
DI ORG
10V, Y5V, +80%/-20%

+/-5% B Q1 EEDO 4 5 16V, Y5V, +80%/-20%
2
@8111C BCP69T1G DO GND Reserved
R7
@8101E @8111C @8111B @8111B AT93C46DN-SH-T
*
@8111B R30
C
4
L6
*
0 VDD33
*
@8111C +/-5%
0 GVDD 4.7uH dummy
+/-5% Near to pin 200mil
* Dummy C16 C17 Width >40mil
2KOhm R28 0.1uF 1uF CTRL18 L2 0
* *
VDD33
AVDDL
AVDDH
XTAL2
XTAL1
+/-5%
DVDD
GVDD
#R389#R390
+/-1% 16V, X7R, +/-10% 10V, Y5V, +80%/-20%
DVDD
DVDD
LED0
LED1
LED2
LED3
@8111B @8111B @8101E C94 C64 C65 C38 EEDI/AUX R34 3.6K +/-1% 33VAUX
CTRL15
D 3D3V_SB D
*R389 *R390 r0805h6
* *
0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
RSET
1
2.49K 2KOhm C29 C2
*
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

+/-1% +/-1% 10uF 10uF
C12
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

r0402h4 r0402h4 EGND R68 +/-5% VDD33
2
@8111C/8111B @8101E U4 XTAL1 Reserved
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
*
0 r0805h6
1
RSET
VDD15E
VDD33D
VDD15D
65
VCTRL15
NC22
CKTAL2
CKTAL1
NC21
LED0
LED1
LED2
LED3
NC20
NC19
NC18
1
33pF C139 C513
+/-5% X6
XTAL-25MHz
* 10uF * 10uF
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

CTRL18 1 48 EESK
2
VCTRL18 EESK C11
AVDDH 2 47 EEDI/AUX Reserved Reserved
2
MDI0+ 3 AVDD33 EEDI/AUX 46 VDD33 XTAL2
*
MDI0- MDIP0 VDD33C EEDO
4 45
AVDDL MDIN0 EEDO EECS 3D3V_SYS
5 44
AVDD18A EECS 33pF
RTL8101E
MDI1+ 6 43 DVDD
MDI1- MDIP1 VDD15C +/-5% @8111B @8111B
7 42 R49
AVDDL 8 MDIN1 NC17 41 DVDD
MDI2+
MDI2-
9
AVDD18B
NC1
NC16
NC15
40 *1K+/-5% FB15 +/-5%
10 39 3D3V_SB VDD33
AVDDL NC2 NC14 DVDD r0402h4 AVDDL L15
11 38 AVDDL
MDI3+ NC3 NC13 VDD33 0 0
12 37
MDI3- NC4 VDD33B R46
13 36 1 2+/-1% +/-5% r0805h6 C37 C62
NC5 ISOLATEB
1
AVDDL 15K Reserved @8111C C93 C92 0.1uF 0.1uF
DVDD
14
15
NC6 NC12
35
34 r0805h6 VDD33 * * 10uF 10uF * *
LANWAKEB
REFCLK_N
REFCLK_P
VDD15A NC11
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

VDD33 16 33 R54 0 DVDD Dummy
EVDD18A
EVDD18B
2
VDD33A NC10
PERSTB
VDD15B
*
EGNDA
EGNDB
+/-5%
E
HSON
HSOP
MDI0+
MDI1+
@8101E/8111B
HSIN
HSIP
MDI0-
MDI1-
NC7
NC8
NC9
B Q3
BCP69T1G
#U26#U25#U82 @8111B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
*R32 *R36 *R39 *R43
C
4
49.9 49.9 49.9 49.9 CTRL15 L11 DVDD
+/-1% +/-1% +/-1% +/-1% 0
EVDD18
EVDD18
DVDD
r0402h4 r0402h4 r0402h4 r0402h4 +/-5% C74 C40 C46 C25 C86 C18 AVDDH FB2 +/-5%
DVDD
AVDDH VDD33
EGND
@8101E @8101E @8101E @8101E @8101E 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
25 LAN_PMEJ * * * * * *
1
r0805h6 C45 0
*
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

35 ICH_LAN_PLTRSTJ
C33 C39
* C14 10uF r0805h6
10V, Y5V, +80%/-20%

C 0.1uF 0.1uF 10uF C
* *
2
10V, Y5V, +80%/-20%
16V, X7R, +/-10% 16V, X7R, +/-10% C19
2
25 HSO_P2_LAN
0.1uF
25 HSO_N2_LAN
C85 0.1uF 16V, X7R, +/-10%
HSI_N2_LAN 25
@8101E @8101E *
**
16V, Y5V, +80%/-20%

C84 0.1uF 16V, X7R, +/-10%
HSI_P2_LAN 25
EGND
REFCLK- Reserved Reserved Reserved

CK_PE_100M_N_LAN 8
@8101E/8111B
REFCLK+ @8101E
CK_PE_100M_P_LAN 8
AVDDL R69 +/-5%

AVDDL EVDD18
0 #FB23#R391
3D3V_SB R3 CTRL15 r0805h6
0 C82 C83
+/-5% C10 R391 FB23 0.1uF 0.1uF
* *
1
@8111C C1 C8 0.1uF
U3
* * * 0 FB 100 Ohm
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%

MDI0+ 1 8 MDI0+ r0805h6 10uF 10uF
1 8 +/-5% +/-25%
10V, Y5V, +80%/-20%
10V, Y5V, +80%/-20%

@8111C
2
MDI0- MDI0- @8111B @8101E/8111C
2 7
2 7 r0805h6 0805h11
MDI1+ 3 6 MDI1+ AVDDL
3 6
MDI1- 4 5 MDI1-
4 5 R31
SLVU2.8-4.TBT 0
@TF +/-5% @8111C @8111C
@8101E
U6
MDI2+ 1 8 MDI2+ USBPW1357_1(P1 & P2)
1 8 USBPW1357_1
C49 C48
MDI2- MDI2- 0.1uF 470pF
2
2 7
7
* 50V, X7R, +/-10% * 3
2
3
2
5V_SB
MDI3+ 3 6 MDI3+ 16V, Y5V, +80%/-20% 3D3V_SB 1
B
MDI3- 4
3
4
6
5
5 MDI3-
Reserved @8101E
BACK PANEL ( LAN + 2 USB Connector ) Jumper
1
Header_1X3
5V_SYS
B
Reserved
SLVU2.8-4.TBT
@TF R60 R59 F3
150 150 Fuse 2.6A
*
+/-5% +/-5% fs1813h13
LED1 D17 C A SVCC2
1N4148W Reserved C76 @8111C/8111B Reserved
470pF
50V, X7R, +/-10% * NIC_USB
*
LED2 D16 C A Dummy
25 USB_OCJ_BACK
1N4148W @8101E
27 SVCC2 1 R58
*
LED3 R70 0 22 28 C79 R57 47K

YLW_LED
+/-5% @8111C/8111B L12 Dummy 0.1uF 56K +/-5%

21 29
*
USB-2
USB-1
30 1 4 +/-5% r0402h4
16V, Y5V, +80%/-20% r0402h4
2 3 2
9 1
MDI0+ 10 5 Common Choke 90 Ohm_2L
MDI0- 11
RJ45-MJ2
MDI1+ 12 2 R65 0 Reserved USBN5

MDI1- R67 0 Reserved USBN7 USBN5 25 USBN5 USBP5
13 6
MDI2+ USBN7 25
14
3
AVDDL MDI2- 15 3 R64 0 Reserved USBP5
MDI3+ R66 0 Reserved USBP7 USBP5 25
16 7 1 2 SVCC2 1 2 SVCC2
MDI3- USBP7 25
17
*
R61 0 18 4 L13 Dummy

D12 D13
+/-5% Dummy C77 8 1 4
BAV99 BAV99
*R62 0.1uF
GRN_LED
0
+/-5% * 16V, Y5V, +80%/-20% 20 23
2 3
USBP7 USBN7
Reserved Dummy 19 24 Common Choke 90 Ohm_2L
3
25
26 1 2 SVCC2 1 2 SVCC2
C80
A CONN-USBx2_RJ45 * 0.1uF D19 D18 A
BAV99 BAV99
3D3V_SB R63 150 +/-5% #NIC_USB1#NIC_USB2 16V, Y5V, +80%/-20%
LED0
NIC_USB1 NIC_USB2
C78 JFM24U13-21U5-4F RU1-250ARWGF

FOXCONN PCEG
470pF Title
* 50V, X7R, +/-10%
Index Page
Dummy Size Document Number Rev
CONN-USBx2_RJ45
@8101E CONN-USBx2_RJ45
C G31M04 A
@8111C/8111B Date: Wednesday, September 12, 2007 Sheet 32 of 39

5 4 3 2 1

5
www.sp860.com 4 3
QQ:453100829 2 1
**
MIC1_VREFO R20 2.2K +/-5% L_IR_A M_R_A
33 MIC1_VREFO RN9
L_OR_A M_L_A
33 MIC1_VREFO_R
MIC1_VREFO_R R19 2.2K +/-5%
2 1 * LFE_M
SURR_R_M
CEN_C
SURRBACK_L_C
L_OL_A
SURR_R_C
4 3 CEN_M LFE_C L_IL_A
6 5 SURR_L_M SURR_L_C SURRBACK_R_C
**
EC5 100uF R8 75 +/-5% FB9 FB L0603 600 Ohm M_R_A 8 7 C51 C52 C50 C13 C59 C60 C58 C57 C55 C53 C56 C54
* AUDIO
**
33 MIC1_R 150pF 150pF 150pF 150pF 150pF 150pF 150pF 150pF 150pF 150pF 150pF 150pF
MIC-IN 22K
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%

EC1 100uF R5 75 +/-5% FB8 FB L0603 600 Ohm M_L_A
*
1
33 MIC1_L +/-5%
AUDIO
GND_AUDIO
Reserved * * * * * * * * * * * *
D D
2
LINE-IN
**
EC3 100uF R1 75 +/-5% FB11 FB L0603 600 Ohm L_IR_A R38 +/-5% r0402h4 SURRBACK_L_M
33 LINE1_R
** * 2
22K
1
Reserved
EC4 100uF R10 75 +/-5% FB7 FB L0603 600 Ohm L_IL_A
33 LINE1_L * R56
2 +/-5%
1 r0402h4 SURRBACK_R_M
22K Reserved @6JACK @6JACK @6JACK @6JACK
@6JACK @6JACK
*
RN1 GND_AUDIO GND_AUDIO
1
3
5
7
22K
+/-5%
******
2
4
6
8
Reserved EC22 @6JACKR78 75 SURR_L_M FB13 @6JACK FB L0603 600 Ohm SURR_L_C
*
******
33 SURR_L 100uF @6JACK +/-5%
EC23 @6JACKR76 75 SURR_R_M FB5 @6JACK FB L0603 600 Ohm SURR_R_C
33 SURR_R 100uF @6JACK +/-5% *
EC16 @6JACKR73 75 CEN_M FB1 @6JACK FB L0603 600 Ohm CEN_C
33 CEN 100uF @6JACK +/-5% *
GND_AUDIO EC17 @6JACKR75 75 LFE_M FB4 @6JACK FB L0603 600 Ohm LFE_C
33 LFE 100uF @6JACK +/-5% *
EC11 @6JACKR41 75 SURRBACK_L_M FB12 @6JACK FB L0603 600 Ohm SURRBACK_L_C
33 SURRBACK_L 100uF @6JACK +/-5% *
EC12 @6JACKR55 75 SURRBACK_R_M FB14 @6JACK FB L0603 600 Ohm SURRBACK_R_C
*
* *
EC2 AUD_FIO_R R6 75 +/-5% FB10 FB L0603 600 Ohm L_OR_A 33 SURRBACK_R 100uF @6JACK +/-5%
* AUDIO
* *
33 LINE_OUT_R 100uF
33 LINE_OUT_L
EC6 AUD_FIO_L R14 75 +/-5% FB6
* FB L0603 600 Ohm L_OL_A Front_OUT
100uF
C 1 1 C
R15 R4
22K 22K
+/-5% +/-5%
r0402h4 r0402h4 AUDIO1A CONN-JACK AUDIO1D CONN-JACK GND_AUDIO 1 AUDIOA audio
2 Reserved 2 Reserved @6JACK @6JACK M_R_A 5
M_S_A 4
3
33 MIC1_JD M_L_A 2
GND_AUDIO AUDIO1B CONN-JACK AUDIO1E CONN-JACK GND_AUDIO #AUDIO1#AUDIO2
@6JACK @6JACK GND_AUDIO 21 AUDIOB audio 26
SPDIF_OUT L_OR_A 25
5V_SYS 1 L_OS_A 24
1 GND_AUDIO
23
SPDIF_OUT AUDIO1C CONN-JACK AUDIO1F CONN-JACK 33 F_JD L_OL_A
3 22
33 SPDIF_OUT 3 @6JACK @6JACK GND_AUDIO #AUDIO1#AUDIO2
4
C165 4
GND_AUDIO 31 AUDIOC audio 36
* 22pF
50V, NPO, +/-5%
Header_1X4_K2 L_IR_A
L_IS_A
35
34
Dummy 33
AUDIO2 INSULATOR 33 L1_JD L_IL_A GND_AUDIO
32
For EMI GND_AUDIO #AUDIO1#AUDIO2
Silk Screen
AUDIO
D22 GND_AUDIO 41 AUDIOD audio
SURRBACK_R_C 45
2 SURRBACK_GND 44
B 33 MIC2_VREFO 3 43 B
33 SURRBACK_JD SURRBACK_L_C
1 42
GND_AUDIO #AUDIO1#AUDIO2
GND_AUDIO 51 AUDIOE audio
BAT54A LFE_C
2 55
3 CEN_GND 54
33 LINE2_VREFO
1 53
33 CEN_JD CEN_C 52
D21 GND_AUDIO #AUDIO1#AUDIO2
BAT54A RN10 3D3V_SYS 61 AUDIOF audio
2
4
6
8
GND_AUDIO
4.7K SURR_R_C 65
+/-5% SURR_GND 64
* 13
5
7
63
33 SURR_JD
*R50
10K
CONN-JACK
@3JACK GND_AUDIO
SURR_L_C 62
#AUDIO1#AUDIO2
+/-5%
****
EC7 100uF +/-20% R87 75 +/-5% F_AUDIO Dummy
***
****
33 MIC2_L C32 1uF 10V, X5R, +/-10% c0603h9 R409 1K +/-1% CD_IN
1 2 GND_AUDIO 33 CD_L
***
EC8 100uF +/-20% R86 75 +/-5% 3 4 1
33 MIC2_R FIO_PRESENCEJ 33
5 6 C28 1uF 10V, X5R, +/-10% c0603h9 R410 1K +/-1% 2
MIC2_JD 33 33 CD_GND
EC9 100uF +/-20% R85 75 +/-5% 7 3
33 AUX_R X
9 10 C21 1uF 10V, X5R, +/-10% c0603h9 R411 1K +/-1% 4
LINE2_JD 33 33 CD_R
EC10 100uF +/-20% R84 75 +/-5%
33 AUX_L Header_2X5_K8 Header_1X5
Reserved
*
for ALC880 RN13

1
3
5
7
A 22K A
+/-5%
2
4
6
8
FOXCONN PCEG
Title
Index Page
GND_AUDIO GND_AUDIO Size Document Number Rev
Custom G31M04 A

5 4 3 2 1

5
www.sp860.com 4 3
QQ:453100829 2 1
*
TMPIN2 R379 10K SIOVREF
+/-1% r0402h4
80 Ohm@100MHz
C503 5V_SYS 0603h10
0.1uF RT2 Reserved
16V, Y5V, +80%/-20% * T 10K 5V_SYS
FB22
5V_SB
+/-1% Note:
* C443 *Place CAPs close to pin 67, trace minimum 12 mils
0.1uF
Place near pin4, 35, 99 * 16V, Y5V, +80%/-20% *
C498
10uF C500 EC67
GNDA * 0.1uF
10V, Y5V, +80%/-20%
* * 100uF
D
System Temperature Monitor +/-20%
D
Place between SIO and PCI-E x16
Printer
35
99
67
4
5V_SYS 5V_SYS U21
COM A
VCC
VCC
VCC
VCCH
C118 C444 FAN half speed PD[7..0]
PD[7..0] 37
0.1uF 0.1uF PD7
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
37
37
DCDAJ
RIAJ
118
119
DCD1#
RI1#
PD7
PD6
116
115 PD6
120 114 PD5
37 CTSAJ CTS1# PD5
121 113 PD4
CP3 37 DTRAJ DTR1#/JP1 PD4
Parallel Port
122 112 PD3
37 RTSAJ RTS1#/JP2 PD3
TMPIN1 123 111 PD2
THERMDA 14 37 DSRAJ DSR1# PD2 PD1
For EMI 124 110
Serial Port 1/2

37 SOUTA SOUT1/JP3 PD1
C504 CP4 X_COPPER 125 109 PD0
THERMDC 14 37 SINA SIN1 PD0
3.3nF DCDBJ
* 16V, NPO, +/-5% X_COPPER
37
37
DCDBJ
RIBJ
RIBJ
126
127
DCD2#
RI2#
STB#
AFD#
108
107
STBJ
AFDJ
37
37
THERMDA/THERMDC CTSBJ 128 106
37 CTSBJ CTS2# ERR# ERRJ 37
GNDA 1. width=10 mils, spacing=10 mils. DTRBJ 1 105
37 DTRBJ DTR2#/JP4 INIT# INIT 37
2. route the lines in parallel RTSBJ 2 104
37 RTSBJ RTS2# SLIN# SLINJ 37
GNDA DSRBJ 3 103
CPU Temperature Monitor 37
37
DSRBJ
SOUTB
SOUTB 5
DSR2#
SOUT2
ACK#
BUSY
102
ACKJ
BUSY
37
37
CIRTX
CIRTX 36
SINB CIRRX
37 SINB
6
SIN2 IT8718F-S/GX-L PE
101
100
PE 37 CIRRX 36
COM B SLCT SLCT 37
Power-on Control
PVID5 20
Update by ITE Gary 0202 PVID4 21
JSBB2/GP27
79
PVID3 JSBB1/GP26 GP40 R377 10K +/-5% Need to checked
22 78 5V_SB
JSBCY/GP25 PWROK2/GP41
*
PVID2 23 77 r0402h4
JSBCX/GP24 GP53 SIO_GP41_DDR_VOL_5 13
Gameport/MIDI
24 76
5V_SYS 14,25 ICH_THRM_UP JSAB2/GP23 PSON#/GP42 PS_ONJ 9
5V_SYS 13 SIO_GP10_DDR_VOL_3 25 75
JSAB1/GP22 PANSWH#/GP43 PBTNJ_SIO 9
PVID1 26 72 PWRON
JSACY/GP21 PWRON#GP44 PWRBTNJ 25
Need to check PVID0 27 71 SLP_S3J
JSACX/GP20 PSIN/GP45 SLP_S3J 25
RN47 PVID6 28
MIDI_OUT/GP17
*R338 FLOPPY 29
*
9 SIO_BEEP MIDI_IN/GP16
C 2.2K
*
1 2 TK00J 1 2 30 CIRTX R325 10K +/-5% 5V_SYS
C
*
1 2 RESETCON#/CIRTX/GP15
MISC.
+/-5% 3 4 WPTJ 4 Need to check 85 CIRRX R378 0 +/-5% r0402h4
X 4 RSMRST#/CIRRX/GP55 RSMRSTJ 25
r0402h4 5 6 RDATAJ 5 6 DENSELJ 51 66 r0402h4 @CLONE
5 6 DENSEL# IRTX/GP47 IRTX 36
Dummy 7 8 DSKCHGJ 7 8 INDEXJ 63 70
7 8 INDEX# IRRX/GP46 IRRX 36
9 10 MOTEAJ 52 68 CASEOPENJ
RTSBJ 150 +/-5% 9 10 MTRA# COPEN#
11 12 14 PECI 55
11 12 DRVAJ DRVB# Need to checked
13 14 54
13 14 DRVA# PCIRSTJ
15 16 53 84 PCIRSTJ 31
Floppy I/F
15 16 MTRB#/THRMO# PCIRST4#/SCRPRES#/GP10
SCR I/F
17 18 DIRJ 57 34
17 18 STEPJ DIR# PCIRST3#/SCRCLK/GP11 ICH_G_PLTRSTJ 23,30
19 20 58 33 ICH_LAN_PLTRSTJ 32
*
FSB_VTT INDEXJ 19 20 WDATAJ STEP# PCIRST2#/SCRIO/GP12 R322 10K
21 22 56 32 3D3V_SYS
23 21 22 24 WGATEJ 60 WDATA# PWROK1/SCRPFET#/GP13 31 IDE_RSTJ +/-5% r0402h4
23 24 WGATE# PCIRST1#/SCRRST/GP14 IDE_RSTJ 26
R363 25 26 TK00J 62
25 26 TRK0# PWRGD_3V 16,25
150 27 28 WPTJ 64 98 VIN0
**
+/-5% 27 28 RDATAJ WPT# VIN0 VIN1 R355 10K +/-5% Reserved
29 30 61 97 5V_SYS
29 30 SIDE1J RDATA# VIN1 VIN2
31 32 59 96
33 31 32 34 DSKCHGJ 65 HDSEL# VIN2 95 R356 0
33 34 DSKCHG# VIN3/ATXPG PWRG_ATX 9,13
CP18 94 VIN4 +/-5% r0402h4 Reserved
Header_2X17_3 FDD VIN4 VID7
93
VIN5
Hardware Monitoring
X_COPPER VIDVCC 36 92 VID6
16,25,29 PLTRSTJ LPCPD# VIN6 VIN7
37 91
38 LRESET# VIN7 90 SIOVREF
25 L_DRQ0J LDRQ# VREF TMPIN1 C505
39 89
26,29 SERIRQ SERIRQ TMPIN1 TMPIN2 1uF
VIDVCC 25,29 L_FRAMEJ L_AD0
40
41
LFRAME#
LAD0
TMPIN2
TMPIN3
88
87 *
L_AD1 42 12 Need to checked
L_AD2 43 LAD1 FAN_CTL3/GP36 11
LAD2 FAN_TAC3/GP37 FANIN3 36
L_AD3 44 10 Place cap close to pin90, and
LPC I/F
LAD3 FAN_CTL2/GP51 FANOUT2 36
CK_33M_SIO 47 9 GNDA
8 CK_33M_SIO PCICLK FAN_TAC2/GP52 FANIN2 36 Do Not remove it.
PVID7 48 8
CK_48M_SIO CLKRUN#/GP50/PCIRST5# FAN_CTL1 FANOUT1 36
49 7
8 CK_48M_SIO CLKIN FAN_TAC1 VID0 FANIN1 36
25 L_PMEJ 73 19
for KB/MOUSE wake PME#/GP54 VID0/GP30 VID1
18
VID1/GP31 17 VID2
5V_SYS VID2/GP32 VID3
26 KBRSTJ
45 16
KRST# VID3/GP33
RESET OPEN DRAIN 26 A20GATE 46 14 VID4
*
GA20 VID4/GP34 VID5 CASEOPENJ R375 1M +/-5%
80 13
B
Voltage Monitor select "high" 36
36
KBDATA
KBCLK
81 KDAT
KCLK
VID5/GP35 r0402h4
VCCRTC
B
R330
KB/MS
82
Del CP21 Reserved R359 * 2.2K
36
36
MSDATA
MSCLK 83
MDAT
MCLK VBAT
69 VBAT L_AD[3..0]
Steven Sun Update 2007.03.28 +/-5% C502
GNDD
GNDD
GNDD
GNDD
GNDA
VCCP 1D8V_STR 3D3V_SYS 12V_SYS 1uF 25,29 L_AD[3..0]
Dummy * 10V, Y5V, +80%/-20% L_AD3
L_AD2
DTRBJ RTSAJ L_AD1
15
50
74
117
86
R382 Place cap close to pin 69 L_AD0
*R384 *R385 *R386 * 30K R331 R342
10K
+/-1%
10K
+/-1%
10K
+/-1%
+/-1%
r0402h4
* 680
+/-5%
* 680
+/-5%
*
FB21 80 Ohm@100MHz
r0402h4 r0402h4 r0402h4 r0402h4 r0402h4 0603h10 Reserved
Reserved Reserved Reserved Reserved Reserved
****
VIN0 R376 4.7K +/-5% SLP_S3J
VIN1 r0402h4
VIN2 Power On Strapping Options GNDA R321 1K ICH_LAN_PLTRSTJ
+/-5% r0402h4 Reserved
*
VIN4 R326 680 +/-5%SOUTB Symbol value Description R109 1K PCIRSTJ

r0402h4 +/-5% r0402h4 Reserved
1 Disabled. 3D3V_SYS R320 1K ICH_G_PLTRSTJ
JP1 VTT_OUT_RIGHT +/-5% r0402h4 Reserved
*
R332 680 +/-5%RTSBJ

Pin 121 Flashseg1_EN 0 Flash I/F Address Segment 1 (FFF8_0000h~FFFF_FFFFh, RN22 RN46
Reserved
000E_0000h~000F_FFFFh) is enabled 10
10
PVID7
PVID6
PVID7
PVID6 * 13 2
4
*
1
3
2
4
SERIRQ
KBRSTJ
JP2 1 Disable VID output pins 10 PVID5
PVID5
5 6
5 6 A20GATE
Dummy
Pin 122 VIDO_EN 10 PVID4
PVID4
7 8
7 8
Dummy
C509
Dummy
C508
C507
0.1uF
Reserved
C506
0 Enable VID output pins 680 +/-5% 8p4r0603h7 10K
0.1uF 0.1uF
* R381 0.1uF Use for chip 1 when two IT8718F exit in the same system. Chip is selected +/-5%
16V, Y5V, +80%/-20%
* * 10K
* JP3 1 in conjunction with "Global Configuration Register - Index 22, bit 7
RN21 Modify for Steven 090407
*
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
* +/-1% R343 8.2K +/-5%

A20GATE
Pin 124 CHIP_SEL PVID3
*1
* *
10 PVID3 2
r0402h4 r0402h4 Dummy Use for chip 0 when two IT8718F exit in the same system. Chip is selected 10 PVID2
PVID2
3 4
R380 4.7K +/-5% VIN7
0 in conjunction with "Global Configuration Register - Index 22, bit 7 10 PVID1
PVID1
PVID0 5 6
Reserved r0402h4
10 PVID0 7 8
The output buffers of PCIRST1#, PCIRST2#, PCIRST3# and 5V_SYS
R324 4.7K +/-5% IDE_RSTJ
GNDA
JP4 BUF_SEL 1 PCIRST4# are open-drain.
680 +/-5%
8p4r0603h7
r0402h4
A GNDA GNDA GNDA GNDA Pin 1 0 The output buffers are push-pull. A
Change to analog GND or not

11 The default value of EC Index 15h / 16h / 17h is 00h VID0
14 VID0
5V_SYS JP5:JP7 10 The default value of EC Index 15h / 16h / 17h is 20h 14 VID1
VID1
Pin 2 & 46 FAN_CTL_SEL 14 VID2

VID2
01 The default value of EC Index 15h / 16h / 17h is 40h 14 VID3
VID3
VID4
14 VID4
R351 4.7K +/-5% DTRAJ
00 The default value of EC Index 15h / 16h / 17h is 60h 14 VID5
VID5
*
r0402h4 VID6
JP6 1 The threshold voltage of VID is 2.0 / 0.8V
14
14
VID6
VID7
VID7 FOXCONN PCEG
Pin 5 VID_ISEL Title
0 The threshold voltage of VID is 0.8 / 0.4V
Super I/O ITE8712F/IX
JP7 1 Disable WDT to reset PWROK Size Document Number Rev
WDT_EN
Pin 46 0 Enable WDT to reset PWROK C G31M04 A

5 4 3 2 1

5
5V_SB
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5V_AUDIO
A
D15 12V_SYS Jack Detect
SD103AW
*
FB16 SENSE_A R45 39.2K +/-1% r0402h4
C
SURR_JD 34
D U7 L78L05N @6JACK D
D20 C A Reserved
1
OUT IN
3
* 1N4148W R48 5.1KOhm +/-1% r0402h4
F_JD 34
C98 300 Ohm@100MHz
GND
C75
* 10uF 0805h11
* *
1
* 4.7uF
Dummy *
16V, Y5V,+80%~-20%
Dummy
R44 10K +/-1% r0402h4
L1_JD 34
2
EC14
2
100uF R74 R47 20K +/-1% r0402h4

MIC1_JD 34
10
+/-5%
Dummy
GND_AUDIO
5V_SB GND_AUDIO Filtering Power Noise(Improve

background noise caused by MIC-boost)
Jack Detect
EC65 SENSE_B R17 5.1KOhm +/-1% r0402h4
SURRBACK_JD 34
* 470uF
16V, +/-20%
@6JACK
* * *
R16 10K +/-1% r0402h4
CEN_JD 34
3D3V_SYS 5V_AUDIO @6JACK
R12 20K +/-1% r0402h4

MIC2_JD 34
ICH_BCLK
C68 C88 C67 C69 C15 C27 R9 39.2K +/-1% r0402h4
LINE2_JD 34
1
C * 0.1uF
* 4.7uF
Dummy * 0.1uF
* 0.1uF
* 0.1uF
Dummy * 0.1uF C
Dummy Dummy
2
GND_AUDIO All of JD resistors should be placed as
25
38
1
9
U1
close as possible to Codec.
DVdd1
DVdd2
AVdd1
AVdd2
3
GPIO1
34 FIO_PRESENCEJ 2
GPIO0
11
ALC662-GR 35
25 ICH_RSTJ RESET# FRONT_L LINE_OUT_L 34
6 36 LINE_OUT_R 34
25 ICH_BCLK BCLK FRONT_R
10 37
*
*
25 ICH_SYNC R51 22 +/-5% r0402h4 SYNC LINE1-VREFO-R R18 10K +/-1% r0402h4 @883
8 33 5V_AUDIO
25 ICH_SDIN2 SDATA_IN DCVOL SENSE_B
5 34
25 ICH_SDOUT SDATA_OUT Sense B (JD2)
39
*
SURR-OUT-L SURR_L 34
40 R29 20K +/-1% r0402h4
*
R53 10K +/-5% r0402h4 Dummy C70 1uF 10V, X5R, +/-10% Dummy JDREF (or NC)
9 BEEP_PC 12 41 SURR_R 34
*
SENSE_A PC_BEEP SURR-OUT-R

13
Sense A (JD1) CEN-OUT
43 CEN 34 Near to Codec
R52
AUX_L 14 44 GND_AUDIO
34 AUX_L LINE2-L LFE-OUT LFE 34
C71 AUX_R 15 45 SURRBACK_L
34 AUX_R LINE2-R SIDESURR-L SURRBACK_L 34
* 100pF
34
34
MIC2_L
MIC2_R
MIC2_L_16
MIC2_R_17
16
17
MIC2-L
MIC2-R
SIDESURR-R
46 SURRBACK_R
SURRBACK_R 34
B Dummy 18 28 MIC1_VREFO B
34 CD_L CD_L MIC1-VREFO-L MIC1_VREFO 34
1K+/-1% Dummy
19 27 C9 1 2 10uF GND_AUDIO
*
34 CD_GND CD_GND VREF
20 29
34 CD_R CD_R LINE1-VREFO
21 30 MIC2_VREFO 34
34 MIC1_L MIC1-L MIC2-VREFO
22 31 LINE2_VREFO 34
34 MIC1_R MIC1-R LINE2-VREFO
23 32 MIC1_VREFO_R 34
34 LINE1_L LINE_L MIC1-VREFO-R
24
34 LINE1_R LINE_R
DVss1
DVss2
AVss1
AVss2
47
SPDIFI(EAPD)
48
34 SPDIF_OUT SPDIFO
GND_AUDIO #U23#U24 ALC662-GR
4
7
26
42
Add CD-IN Eric
CP32
C91 0.1uF
*
Dummy 16V, Y5V, +80%/-20% U23 U24

X_COPPER
GND_AUDIO
C35 0.1uF
ALC888-GR
CP12 ALC662-GR
* * * *
Dummy 16V, Y5V, +80%/-20%
C132 0.1uF
Dummy 16V, Y5V, +80%/-20% For EMI X_COPPER
A A
C63 0.1uF
Dummy 16V, Y5V, +80%/-20% ALC662-GR ALC888-GR
@662 @888
C36 0.1uF
Dummy 16V, Y5V, +80%/-20% FOXCONN PCEG
GND_AUDIO Title
GND_AUDIO AUDIO 655/861

Custom
G31M04 A

5 4 3 2 1

5
SM Bus Bridge
www.sp860.com 4 3
QQ:453100829 5V_SYS
2
Peak fan current draw: 1.5A
Average fan current draw: 1.1A
Fan start-up current draw: 2.2A
Fan start-up current draw maximum duration: 1.0 second
Fan header voltage: 12V +/- 10%
1
*R259
4.7K
+/-5%
r0402h4
R260
35 FANOUT2
100 +/-1%
If use SUIO power good 3D3V_SYS
D D
12V_SYS
function, dummy Q7,Q6,Q8 R293 2.7K +/-5% SMB_DATA_MAIN
pop R25,R18 R294 2.7K +/-5% SMB_CLK_MAIN
12V_SYS
Near the Memory
CP9
C
D32
8,20,22,29 SMB_DATA_MAIN SMB_DATA_RESUME 23,25,30,31
R264 1N4148W
X_COPPER
CPU_FAN
* 4.7K Reserved
+/-5%
for Clock Generator/DIMMs/TPM/Clock Buffer 2FAN2_2
A
for PCI-E x16/ICH7/LAN/PCI/PCI-E x1/Riser Card/New Card +12V 4FAN2_4
CMD R263
1
*
GND 3FAN2_3 27KOhm
CP10 ? TACH C340 +/-5%
FANIN2 35
Max. output current = 3A EC54 47pF
8,20,22,29 SMB_CLK_MAIN SMB_CLK_RESUME 23,25,30,31
* 100uF Header_1X4 FAN4P * 50V, NPO, +/-5%
2
R262
X_COPPER CPU FAN 16V, +/-20%
Dummy
22K
+/-5%
C C
5V_SYS
5V_SB
C99
0.1uF
16V, Y5V, +80%/-20% *
Dummy IR/CIR 1 5V_SYS
1 2
4 3 5V_SYS
X CIRRX 35 IRRX
35 IRRX 5 6 4 GND
7 8 CIRTX 35 5 IRTX
35 IRTX 9 X
*R383
4.7K
Header_2X5_K3K10 +/-5%
#IR#IR/CIR1 r0402h4 R374
C473 C494
35 FANOUT1
* 470pF
* 470pF
50V, X7R, 50V,
+/-10%
X7R, +/-10% IR/CIR CONNECTOR IR
1
IR/CIR1
100 +/-1%
Dummy Dummy
Need check whether follow up 3
X
12V_SYS
TF spec?? 4
5 X
Header_1X5_K2 Header_2X5_K3K10
@CLONE @TF
12V_SYS
D42
C
R370 1N4148W
SYS_FAN * 4.7K Reserved
KB/MS_PW 2FAN1_2 +/-5%
+12V
4FAN1_4
3 CMD 1 R372
5V_SB
A
B B
*
3 5V_SB GND
2 3FAN1_3 27KOhm
FANIN1 35
2 TACH +/-5%
1 5V_SYS
1 C96 EC64 C495 2
Header_1X3 F2 * 0.1uF
Dummy
* 100uFHeader_1X4 FAN4P
16V, +/-20% * 47pF
50V, NPO, +/-5%
R373
22K
Fuse 1.5A Dummy +/-5%
KB/MS_PW(P1 & P2) Max. output current = 3A
System FAN
*
Jumper
8
6
4
2
Reserved
RN2 FB3 KB/MS
4.7K 300 Ohm@100MHz
*
+/-5%
*
16
7
5
3
1
13 12V_SYS
12V_SYS
CP5 X_COPPER CLK_NET03 5 11
35 KBCLK
3 9 EC25
CP6 X_COPPER 1 7 * 100uF D23
C
35 KBDATA CP23
2 17 16V, +/-20% R98 1N4148W
4 8 Dummy * 4.7K Dummy
6 10 +/-5%
12 X_COPPER Header_1X3 Dummy
14 R102
CP25
*
3 27KOhm
FANIN3 35
15 2 +/-5% 2
UP DOWN C125 Dummy R105
1
47pF 22K
PWR_NET02
PS2X2 X_COPPER
CP26 NB_FAN
* 50V, NPO, +/-5% +/-5%
Dummy
CP21 X_COPPER CLK_NET02 Dummy Dummy 1
35 MSCLK
A CP22 X_COPPER X_COPPER A
35 MSDATA
CP27
C41
0.1uF
* * X_COPPER
CP28
NB FAN
16V, Y5V, +80%/-20%
50V, NPO, +/-10%
180pF
CN3 X_COPPER FOXCONN PCEG
Title
Keyboard / Mouse / Fan
KB\MS Size
C
Document Number
G31M04
Rev
A

5 4 3 2 1

5
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QQ:453100829 2
5V_SYS
1
U18
5V_SYS 20 1 12V_SYS
VCC +12V
16 5 NRTSB -12V_SYS 5V_SYS 12V_SYS
A
35 RTSBJ DA1 DY1
16V, Y5V, +80%/-20%

C445 0.1uF
15 6 NDTRB C43
35 DTRBJ DA2 DY2 NSOUTB D7 0.1uF
13
DA3 DY3
8
*
1
35 SOUTB NRIB 16V, Y5V, +80%/-20%
35
35
RIBJ
CTSBJ
19
18
RY1
RY2
RA1
RA2
2
3 NCTSB * C410 * * C422
1N4148W
17 4 NDSRB 0.1uF 0.1uF Reserved
C
1
2
35 DSRBJ RY3 RA3 NSINB
14 7
35 SINB RY4 RA4 NDCDB RN3
D 12 9 D
35 DCDBJ RY5 RA9 25V, X7R, +/-10% 25V, X7R, +/-10%
11
GND -12V
10 -12V_SYS @TF @TF * 13 2
4
STB1-
AFD1-
@TF INIT1-
GD75232 5 6 SLIN1-
@TF 7 8
RS232 Drivers and Receivers 2.7K
+/-5%
placed near GD75232 RN7
PD[7..0]
35 PD[7..0]
*1 RN5
*
1
3
2
4
ACK-
BUSY
PD0 2 33 PE
5 6
PD1 3 4 +/-5% SLCT
7 8
PD2 5 6 8p4r0603h7
PD3 7 8 10K
PD4 +/-5%
*
PD5
PD6
*1 2 33
RN6 R42
+/-5%
10K
r0402h4
ERR-
PD7 3 4 +/-5%
5 6 8p4r0603h7
COM2
NDCDB NSINB 7 8
1 2
NSOUTB 3 4 NDTRB
5 6 NDSRB
NRTSB 7 8 NCTSB
NRIB 9
Header_2X5_K10
@TF
35 STBJ *1 2 33
RN4 STB1-
AFD1-
35 AFDJ 3 4 +/-5% INIT1-
35 INIT 5 6 8p4r0603h7 SLIN1-
NDTRB NRTSB 35 SLINJ 7 8
NSINB NDSRB
PRT
NSOUTB NCTSB
STB1- 1
NDCDB NRIB AFD1- 14
P_D0 2
C
* * ERR- 15 C
50V, NPO, +/-10% 50V, NPO, +/-10% 35 ERRJ P_D1 3
180pF 180pF INIT1- 16
CN9 CN8 P_D2 4
@TF @TF SLIN1- 17
P_D3 5
18
placed near header P_D4 6
placed near header 19
P_D5 7 28
20 27
COM 2 Header P_D6
P_D7
8
21
26
9
22
ACK- 10
35 ACKJ
23
BUSY 11
35 BUSY
24
PE 12
35 PE
25
SLCT 13
5V_SYS 35 SLCT
C512 CONN-D-SUB
0.1uF CN5
* 16V, Y5V, +80%/-20% CN4 CN7 CN6 220pF
Dummy 220pF 220pF 220pF 50V, NPO, +/-10%
50V, NPO, +/-10% 50V, NPO, +/-10% 50V, NPO, +/-10% 8P4C0603h12
For EMI * 8P4C0603h12 * 8P4C0603h12 * 8P4C0603h12 *
U5 -12V_SYS 5V_SYS 12V_SYS

B B
5V_SYS 20 1 12V_SYS
VCC +12V C72
2
NRTSA 0.1uF C31

35 RTSAJ
16
DA1 DY1
5
* *
16V, Y5V, +80%/-20%
35 DTRAJ
15
DA2 DY2
6 NDTRA * C47 0.1uF
13 8 NSOUTA 0.1uF Reserved
1
35 SOUTA DA3 DY3 NRIA 25V, X7R, +/-10%

19 2
35 RIAJ RY1 RA1 NCTSA
18 3
35 CTSAJ RY2 RA2 NDSRA 25V, X7R, +/-10%
17 4
35 DSRAJ RY3 RA3 NSINA
14 7
35 SINA RY4 RA4 NDCDA
12 9
35 DCDAJ RY5 RA9
11 10 -12V_SYS
GND -12V
GD75232
placed near GD75232
RS232 Drivers and Receivers
COM1
PRT PORT
11
NDCDA 1
NDSRA 6
NSINA 2
NRTSA 7
NSOUTA 3
NCTSA 8
NDTRA 4
NRIA 9
* * 5
50V, NPO, +/-10% 50V, NPO, +/-10% 10
180pF 180pF
CN2 CN1
Reserved Reserved CONN-COM PORT
Update by Steven 053107

A A
COM 1
placed near connector
Ring
FOXCONN PCEG
Title
Serial / Parallel
C
G31M04 A

5 4 3 2 1

5
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USBPW0246_1(P1 & P2)
4 3
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USBPW0246_1
3 5V_SB 5V_SYS 5V_SYS
3
2
2
1 5V_SYS
Jumper 1 C73 C326
D
Reserved
Header_1X3 * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% D
F4
FUSB_PWR Fuse 2.6A
*
fs1813h13
EC51 C332
*
* 470uF
16V, +/-20% * 0.1uF R257
+/-5%
10K Reserved
r0402h4
USB_OCJ_FRONT 25
USBN1 USBP1
16V, Y5V, +80%/-20%
3
1
R258 C333 1 2 FUSB_PWR 1 2 FUSB_PWR
FOR EMI ISSUE 15K
+/-1% * 0.1uF
D28 D27
16V, Y5V, +80%/-20%
2 BAV99 BAV99
USBN2 USBP2
3
F_USB1 1 2 1 2
FUSB_PWR FUSB_PWR
1 2
USBN1 R212 0 Reserved 3 4 R229 0 Reserved USBN2
25 USBN1 USBN2 25 D29 D31
C USBP1 R225 0 Reserved 5 6 R234 0 Reserved USBP2 C
25 USBP1 USBP2 25 BAV99 BAV99
C307 C314 7 8 C324 C318
1
L28 Dummy
4
* 6.8pF
+/-0.5pF* 6.8pF
+/-0.5pF
X 10
* 6.8pF
+/-0.5pF * 6.8pF
+/-0.5pF 1
L30 Dummy
4
Dummy Dummy Header_2X5_K9 Dummy Dummy
2 3 2 3
Common Choke 90 Ohm_2L Common Choke 90 Ohm_2L
USB Front Header II
FUSB_PWR
5V_SYS
C331 C148
* 0.1uF
* 0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
FOR EMI ISSUE
B B
USBN4 USBP4
3
F_USB2
1 2 1 2 FUSB_PWR 1 2 FUSB_PWR
USBN4 R268 0 Reserved 3 4 R275 0 Reserved USBN6
25 USBN4 USBP4 R272 0 Reserved R276 0 Reserved USBP6 USBN6 25
5 6
25 USBP4 C348 C350 C360 C357 USBP6 25 D34 D33
7 8
BAV99 BAV99
1
L31 Dummy
4
* 6.8pF
*
+/-0.5pF
6.8pF
+/-0.5pF
X 10
* 6.8pF
*
+/-0.5pF
6.8pF
+/-0.5pF 1
L32 Dummy
4
Dummy Dummy Header_2X5_K9 Dummy Dummy USBN6 USBP6
2 3 2 3
3
Common Choke 90 Ohm_2L Common Choke 90 Ohm_2L 1 2 FUSB_PWR 1 2 FUSB_PWR
USB Front Header 1
D35 D36
BAV99 BAV99
A A
FOXCONN PCEG
Title
Serial / Parallel
Custom G31M04 A

5 4 3 2 1

5
www.sp860.com 4
1. Change Lan RTL8111B colay RTL8101E to RTL8111C colay RTL8101E

3
QQ:453100829
2 1
2. Change Audio ALC888 colay ALC883 to ALC662 colay ALC888

3. Reserved Memory ratio schematic for over clock.
4. Del R108,C139,Q22,Q20,R107 and then connect VRMPWGD directly for VRD11.
5. Add R371,C501 for power button debounce circuit.
6. Reserved U15,U17 for TF spec.
7. Reserved TPM Header for TF spec.
D
8. Reserved U3,U6 for TF spec. D
9. Add R8,R1,R5,R10,R6,R14,R87,R86,R85,R84,R78,R76,R73,R75,R41,R55 for Audio ESD

10. Reserved CIR function for TF spec.
11. Reserved NB FAN.
12. Reserved C307,C314,C324,C318,C348,C350,C360,C357 for TF Front Panel
13. Change R335 to 91ohm,R337 to 115ohm for Memory Power
14. Remove R338 and stuff R332 for FAN half speed when Power on.
15. Reserved R46 for realtek's suggestion
16. Reserved U9,C144,C145 for VCCA_DAC
17. Add RT8111B SCH
18. Del EC72,EC55,EC54,EC73 for placement issue
19. Reserved R40,R25 For EMI
21. Add C16,C17 For RTL8111B LAN Chip EMI
22. Add FB22 For ITE suggestion
23. Reserved C497 for Front Panel ESD
24. Del Power V15SFR SCH
25. Add R208,R220 for further CPU
26. Reserved R321,R109,R320 for PCI RST
27. Disconnect SLP_S4 with CLK Gen
28. Change C368,C371 from 18pF to 12pF
29. Change F_AUDIO Pin7 connect to Audio_GND directly and connect Pin6,Pin10 to codec through the resistor.
C After Gerber Out: C
30. Reserved C506

31. Change R363 size from 0402 to 0603
32. Change R111 to 33ohm 1%
33. Add R400 100ohm 1%
34. Dummy Q24 C146
35. Reserved R94 In 8KS2H SKU
36. Reserved R114,C147,R110,Q23,Q26
37. Change R116,R118 to 10K 1%
38. Change C160 to 1uF 0603
39. Reserved Q39
40. Del CP2
41. Del EC29
42. Reserved R356
43. Change PCIe_16x slot to 2EG48211-S7Y-4F
44. Del EC65,EC66
45. Add EC68
46. Change L25,L38 to 630307400-176-G
47. Reserved C451,C396,C375,C381,C430,C441,C355,C436,C447,C448,C397,C385,C446,C427,C405,C401,C395,C353,C390
48. Del RN17
49. Add R401,R402,R403 10K 5%
B
50. Add JP1,JP2, JP1(P1&P2),JP2(P1&P2) B
51. Add R404 470ohm
52. Add EC69
53. Del EC46,EC47
54. Change L26,L37 to APL1108P-2R5L
55. Change C5,C6,C7 to 10pf
56. Change L8,L9,L10 to GL1608082NJT
57. Reserved C38,C65
58. Change CP14 to L40 10uH
59. Change L23 to 10uH
60. Add C139,C513,C514 10uF
61. Add EC65
62. Del CP24
63. Add R25 for EMC
64. Add R409,R410,R411 for Audio codec ESD protection
65. Change EC55 to 680uF
66. Change L23 From 10uH Inductor to 10ohm Resistor
A A
FOXCONN PCEG
Title
CHANGE LIST
C G31M04 A

5 4 3 2 1

G31M04 Schematic Foxconn Precision Co. Inc.: Fab.A Data: 2007/6/15 Page Index

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5

Foxconn Precision Co. Inc.

06. Power Sequence 30. PCIE1X

15. LGA775 -2 39. changlist B

16. Broadwater -GMCH -1

Date: Wednesday, September 12, 2007 Sheet 1 of 41

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Cedar Mill, Presler ,

PCI Express x 16 Channel A DDR2

GMCH DDR2 667/800 Channel B DDR2

USB2.0 Port 3 SATA Connector 2

USB2.0 Port 4 SPI Flash SATA Connector 3

Date: Wednesday, September 12, 2007 Sheet 2 of 39

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Front Panel PWROK ACZ_RST#

RSMRST circuit FOXCONN PCEG

Date: Wednesday, September 12, 2007 Sheet 3 of 39

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MCH 200/266/333 MHz Diff Pair

PCI Express/DMI 100 MHz Diff Pair

TPM 33 MHz TPM

SIO 33 MHz Super I/O

SATA 100 MHz Diff Pair

Date: Wednesday, September 12, 2007 Sheet 4 of 39

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3.3V Super I/O

ATX P/S 3.3V

1.2V FSB 5VSB

GMCH 1.25 V Vcore (Core Logic) PCI Express X16

Nineveh GbE Lan

1.8V ANALOG 418.2mA BJT

Date: Wednesday, September 12, 2007 Sheet 5 of 39

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+3D3V_DUAL +3D3V_SYS +3D3V_SYS +3D3V_DUAL

+5V_SYS +5V_DUAL +5V_DUAL +5V_SYS

+3D3V_SYS +3D3V_DUAL +3D3V_DUAL +3D3V_SYS

+1D8V_STR +1D8V_STR +1D8V_STR +1D8V_STR

Date: Wednesday, September 12, 2007 Sheet 6 of 39

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Date: Wednesday, September 12, 2007 Sheet 7 of 39

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25V, X7R, +/-10%

16V, Y5V, +80%/-20%

CP8 X_COPPER 3D3V_CLK

25V, X7R, +/-10%

25V, X7R, +/-10%

25V, X7R, +/-10%

25V, X7R, +/-10%

25V, X7R, +/-10%

CK_33M_TPM R94 33 +/-5% @TF ICS_FSBSEL1 10 *Freerun/PCICLK1_2x GND 55 X2

R1014.7K +/-5% r0402h4 *SEL24_48#/24_48Mhz CPUT_LR0 200M_N_CPU

50V, NPO, +/-5%

ICS_FSBSEL0 R1002.2K +/-5% r0402h4 FSBSEL0

CK_33M_SIO ICS_FSBSEL2 R95 2.2K +/-5% r0402h4 FSBSEL2

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

C126 C124 C110 C104 C116 C115

Date: Wednesday, September 12, 2007 Sheet 8 of 39

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C454 C510 C462 C461