Spartan-3A/3AN Starter Kit Board Schematic

(Annotated)
21-AUG-2007

For additional information …

www.xilinx.com/s3astarter

See UG334: Spartan-3A/3AN Starter Kit User Guide for further information on each board feature
Hirose FX2 100-pin Expansion Connector
Connectorless Debugging Port Landing Pads
Six-pin Accesory Headers

Connectorless
Debugging Port

ADC
Inputs
FX2 Expansion
Connector
DAC
Outputs Six-pin
Accessory
Headers

DAC Analog Outputs

ADC Analog Inputs

TM

Spartan-3A/3AN Starter Kit Board

FX2 Expansion Connector, 6-pin Headers

 SPI PROM select jumpers
RS-232 serial ports

NOTE: See schematic Page 13 for details.

Clock Input/Output SMA connector

PS/2 Mouse/Keyboard connector

RS-232 12-bit VGA port

Primary DATA
DCE DTE
VGA Audio jack
Secondary DATA
PS/2

Primary CLK
Secondary CLK
SPI select
The PS/2 connector has primary and secondary connections to jumper
the FPGA. The secondary connections are available by
attaching an external Y-splitter cable.

Stereo Audio mini jack

Clock SMA
TM

Spartan-3A/3AN Starter Kit Board

RS-232, VGA, Audio ports, SMA connector

 LAN8700 10/100 Ethernet PHY

RJ-45 Connector

LAN8700 10/100 Ethernet PHY

TM
RJ-45 Connector

www.smsc.com/main/catalog/lan8700.html Spartan-3A/3AN Starter Kit Board

10/100 Ethernet PHY, magnetics

 FPGA core
supply
(1.2V)

FPGA I/O
Bank 0 Banks 0, 1, 2
(3.3V)

Bank 1
FPGA

Bank 2
I2 C Interface FPGA auxiliary
supply
(3.3V)

Embedded
USB / JTAG
Programmer
(1.8V)

Bank 3
FPGA

DDR2 SDRAM
Termination
(0.9V)

DDR2 SDRAM
Device, FPGA
I/O Bank 3
(1.8V)
DAC Reference
Voltage
(3.3V)
I2 C Interface

Wall power adapter

input
DDR2 SDRAM
Voltage Ref.
Power switch (0.9V)

Voltage
TM
regulators

Spartan-3A/3AN Starter Kit Board

www.national.com/pf/LP/LP3906.html
Voltage regulators
 JTAG Header

FPGA Configuration Control

Platform
Flash
PROM

Platform Flash Enable

(Jumper J46)

SUSPEND
slide switch

PROG_B
jumper

PROG_B DONE
pushbutton LED

Platform Flash Enable Jumper

(Jumper J46)
DONE DONE DONE
CE CE CE
PROM PROM PROM
GND GND GND
FPGA Mode Select jumper J46 J46 J46
(Jumper J26)
DISABLE Enable Enable
only during Always
Platform Flash PROM configuration
Second 4 Mbit
Platform Flash Enable Jumper Platform Flash PROM
Master Serial JTAG (Jumper J46) is not mounted
JTAG Header
M0 Also enable M0
Platform Flash
M1 PROM using M1
SUSPEND switch
M2 Jumper J46 M2 TM

J26 J26 PROG_B pushbutton

Disable Platform Flash PROM DONE LED
by removing Jumper J46
Master SPI Master BPI (Spartan-3AN only)
Master Internal SPI
Spartan-3A/3AN Starter Kit Board
M0 M0 M0
M1 M1 M1
Configuration, Mode pins, Platform Flash PROM
M2 M2 M2
SUSPEND pin, JTAG header
J26 J26 J26
 FPGA: XC3S700A/AN-4FGG484C(E FPGA: XC3S700A/AN-4FGG484C(ES)

Bank 0

Bank 1
FPGA FPGA

TM

Spartan-3A/3AN Starter Kit Board

CLK_50MHZ CLK_AUX
FPGA I/O Bank 0 and Bank 1, Clock Oscillators
50 MHz Oscillator Auxiliary Oscillator Socket
FPGA: XC3S700A/AN-4FGG484C(ES) FPGA: XC3S700A/AN-4FGG484C(ES)

FPGA I/O Bank 3

is dedicated to the
DDR2 SDRAM
interface

interface
Bank 3

FPGA FPGA

Bank 2

AWAKE
LED

TM

Spartan-3A/AN Starter Kit Board

FPGA I/O Bank 2 and Bank 3

 TM

Spartan-3A/3AN Starter Kit Board

FPGA Power Supply Decoupling

 Programmable Gain Amplifier (AMP)
Analog-to-Digital Converter (ADC) LTC6912-1, two-channel, serial
LTC1407-1, two-channel, 12-bit resolution, serial www.linear.com/pc/productDetail.do?navId=H0,C1,C1154,C1009,C1121,P7596
www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1158,P2484

Thevenin termination to improve

Digital-to-Analog Converter (DAC) the signal integrity on these
LTC2624, four-channel, 12-bit resolution, serial high-fanout signals.
www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1005,C1156,P2048

ADC, DAC,
pre-amplifier

(3.3V)

(nominally 3.3V) Analog

headers
(see sheet 2)

TM
The DAC_REF_CD voltage is programmable via the
I2C control interface on the LP3906 voltage regulator
designated as IC18 on sheet 5. At power-up, this
reference voltage is 3.3V.

Spartan-3A/3AN Starter Kit Board

ADC, DAC, and Pre-amplifier

www.linear.com
 DESIGN NOTE: The Revision C board has an inductor in this
location. Shorting across this location improves high-frequency
0Ω DDR2 SDRAM interface performance.
The Revision D board uses a 0Ω resistor.

DDR2 SDRAM device

Termination network
Connects to FPGA
I/O Bank 3

32Mx16 DDR2 SDRAM

The DDR2 SDRAM interface has specific pin assignment

and layout requirements to support the Xilinx Memory
Interface Generator (MIG) software. See the “DDR SDRAM”
chapter in UG334: Spartan-3A/3AN Starter Kit User Guide.

0Ω
TM

DESIGN NOTE: The Revision C board has an inductor in this Spartan-3A/3AN Starter Kit Board
location. Shorting across this location improves high-frequency
DDR2 SDRAM interface performance.
The Revision D board uses a 0Ω resistor. 32Mx16 DDR2 SDRAM
 DONE
CE
To configure from parallel NOR
PROM Flash, remove Jumper J46 to
GND disable the Platform Flash PROM
J46

STMicroelectronics
M29DW323DT
32 Mbit, x8/x16
parallel NOR Flash

M0
To configure from parallel NOR
M1 Flash, set the FPGA mode select
M2 pins using Jumper J46 as shown
J26

TM

Spartan-3A/3AN Starter Kit Board

www.st.com/stonline/products/families/memories/fl_nor_emb/fl_m29dw.htm M29DW323DT x8/x16 Parallel NOR Flash

 Jumper J1 defines which SPI Flash is used for
SPI mode configuration and which is available
Atmel AT45DB161D 16 Mbit serial DataFlash®PROM using a second SPI slave select signal.
NOTE: Jumper J1 appears on schematic Page 3.
J1 J1

www.atmel.com/products/DataFlash/

Configure From: Atmel STMicro

Atmel Select Signal: SPI_SS_B ALT_SS_B
STMicro Select Signal: ALT_SS_B SPI_SS_B

Atmel DataFlash
STMicro SPI Flash

Platform Flash Jumper

(Jumper J46)
SPI Flash
DONE
select jumpers
CE
PROM (Jumper J1)
GND
J46

Remove Jumper J46

to configure FPGA
from SPI Flash PROM

STMicroelectronics M25P16 16 Mbit SPI serial Flash PROM

Mode Select Jumpers

(Jumper J26)

M0
M1
www.st.com/stonline/products/families/memories/fl_ser/index.htm
M2
J26
Master SPI Mode
M[2:0]=<0:0:1>

TM

Spartan-3A/3AN Starter Kit Board

The Spartan-3A Starter Kit board supports multiple pad landings for each SPI Flash architecture. STMicro SPI serial Flash, Atmel serial DataFlash
However, only one STMicro and one Atmel PROM are mounted on the board.
 Eight discrete LEDs
Four pushbutton switches

Four slide switches

Four pushbutton switches
surround rotary knob

Rotary knob switch with pushbutton switch

Rotary pushbutton switch

16x2 character LCD
Four slide switches
Eight discrete LEDs

TM

Spartan-3A/3AN Starter Kit Board

16-character by 2-line LCD display
Slide switches, Rotary knob, Character LCD,
Pushbutton switches, discrete LEDs
 TM

Spartan-3A/3AN Starter Kit Board

The DDR2 SDRAM interface has specific pin assignment DDR2 SDRAM Termination Network (1 of 2)
and layout requirements to support the Xilinx Memory
Interface Generator (MIG) software. See the “DDR SDRAM”
chapter in UG334: Spartan-3A/3AN Starter Kit User Guide.
The DDR2 SDRAM interface has specific pin assignment
and layout requirements to support the Xilinx Memory
Interface Generator (MIG) software. See the “DDR SDRAM”
chapter in UG334: Spartan-3A/3AN Starter Kit User Guide.

TM

Spartan-3A/3AN Starter Kit Board

DDR2 SDRAM Termination Network (2 of 2)

 Bank 0

FPGA FPGA

Bank 2

Pairs of pins on the Transmit Receive

header form potential 2x17 stake pin header 2x17 stake pin header
differential I/O pairs.
Optionally, each pin
can be a single-ended
I/O pin.
Each individual
differential I/O pair
is routed with matched
100-ohm impedance.

The receive clock differential

pair feeds the GCLK6 and
GCLK7 global clock inputs,
which in turn connect to the
top, right DCM labeled
DCM_X2Y3

If using differential inputs, set the DIFF_TERM=TRUE constraint.

There are no external termination resistors provided on the board.
INST <I/O_BUFFER_INSTANTIATION_NAME> DIFF_TERM = “TRUE” ;

Recieve stake pins

Transmit stake pins

TM

Spartan-3A/3AN Starter Kit Board

Differential I/O Headers