ADS Tutorial PDF

Advanced RF Designs using ADS-Part II
Agilent Technologies
Anurag Nigam
(Senior Designer, NatTel Microsystems)
Workshop Outline & Details
An Introduction
This is a second part of workshop on Advanced RF Designs using ADS. Pre-requisite of this workshop is working knowledge of ADS and Microwave basics.
Workshop lays the foundation of sound design techniques by describing principle of operation of various sub-circuits in a transceiver. Participants walk through
real world designs of various sub-circuits.
The whole presentation spans over a period of 3 days. The designs are pre-designed by the trainer using ADS Demo Kits for reference. All hands-on exercises
are repeated in the workshop along with the participants. The details of the topics as a follows-
Day1
Tutorial 1 Exercise 2
Transmitter and Receiver overview in ADS using System Level ACPR Simulations using Envelope Simulator
Components Tutorial 3
Transmitter and Receiver Specifications RF Board and Module Technology
Exercise 1a Electromagnetic Simulations using Momentum
Transmitter Simulation to analyze spurs and design for specified Exercise 3a
spurious level Losses in Transmission lines on boards
Exercise 1b Exercise 3b
Transmitter Simulation to analyze Cascaded Gain and Gain Microstrip Lines and Coplanar Waveguide design on RF Board
Compression Tutorial 4
Exercise 1c Brief overview of microwave filters.
Transmitter IM3 simulations Exercise 4
Exercise 1d A band pass filter design using filter designer in ADS
Receiver Simulation to analyze cascaded noise figure and signal to Tutorial 5
noise ratio PLL from system perspective
Modulation Schemes used in modern communication systems and Effects of Phase Noise on system performance
system considerations. Tutorial 5 (continued)
ADS sources and test benches to generate and analyze linearity of PLL architectures and operation
transmitter for various modulation schemes.
© Copyright 2009 Agilent Technologies 2

Workshop Details
Day 4
Tutorial 6 Tutorial 11
System Level Mixer representation Mixer Simulations across frequency and power- Introduces methods to
Specifications of a Mixer simulate the mixer across frequency and power. Introduces conversion gain,
Role of Mixer in up-conversion & down-conversion phase and gain imbalance of a mixer and one 1-dB compression of a mixer
Mixer Topologies Exercise 9
Tutorial 7 Across frequency & across RF power simulation of mixer
Introduction to SMT components- method to model SMT capacitors and
inductors for use in mixer design & simulations.
Tutorial 8
Introduces Gilbert Cell Mixers and its types, design of FET and BJT
Mixers
Exercise 6
Gilbert Cell Input Stage Design- Single Ended to Differential Interface
Tutorial 9
FET Gilbert Cell Mixer Design Equations
Exercise 7
Gilbert Cell Mixer Design & Simulations
Tutorial 10
Introduction to Quadrature Mixer- Detailed Operation of Quadrature mixer
& its sub-circuits. Mixer Specifications for sample design.
Exercise 8a
Design of Input Hybrid of a Quadrature Mixer and simulation of Gain and
Phase Balance
Exercise 8b
Design of Input and Output Bias Decoupling Circuits
Exercise 8c
Design of Output Open Circuited Stub
Exercise 8d
Matching of Active Devices in a Quadrature Mixer

Workshop Details
Day 5
Exercise 13
Tutorial 12 Inter-stage design and two stage amplifier simulations
Introduction to Power Amplifiers- Introduces Power Amplifiers and their Tutorial 15
electrical characteristics, differentiates power amplifier specifications in a Introduction to Load-pull set-up for Power Amplifiers- introduces load-pull
TDD and FDD system, Classes of Power Amplifiers stands (Maury)
Introduction to switching amplifiers- High efficiency class E amplifier Set-up and simulate load-pull on a two stage PA
operation and design Exercise 15
Exercise 10 Two Tone Characterization of PA
Design a Class E Power Amplifier using ideal components Exercise 16
Tutorial 14 ACPR Characterization of PA
Two stage Amplifier Topology- Introduces two stage power amplifier Exercise 17
topology, discusses DC biasing of a device, details methods for small % EVM Characterization of PA
signal matching an active device, introduces concept of stability,
introduces bias decoupling using SMT Components. Thermal instabilities
are discussed followed by description of techniques to improve them.
Exercise 11a
Design & simulate bias decoupling on board
Exercise 11b
Simulate DC Characteristics of a device
Exercise 11c
Stabilization of Partially Stable devices, Small Signal Tune of Driver
Stage and Power Stage.
Exercise 12
Simulate single stage amplifier and design large signal match for
amplifier ensuring stability and desired compression point

Transmitter & Receiver Overview
Tutorial 1: Introduction to Modern Transceivers
Modern Communication Systems
Communication systems can be “Analog” or “Digital”. Analog Systems are not spectrally
Communication Systems
efficient and there are no error correcting algorithms. The number of subscribers in an
analog system are less. Switching of calls in progress is not possible in analog systems.
Due to these reasons analog communication systems are used only for fixed point to
point low data rate links.
Digital Analog The need of today is high data rate, high subscriber, mobile connectivity in harsh
environments. This has been possible due to digital communication systems. Figure
below shows the expectations from a modern communications systems.
Figure 1: Types of communication systems
Figure below shows typical architecture Spectral
Microwave
of a modern communication system. All Efficiency Robust Channel
the digital processing up to final serial to Characteristics
parallel conversion (symbol generation)
is done by Digital Baseband Processor.
Antenna Power
IQ Generation and Demodulation is done
by ADC/DAC & IQ Modulator. Frequency
up/down conversion and channel
Expectations from Modern Equipment/
selection is done by Transceiver. Power
Communication Systems Device Size
MMIC
amplification and Noise improvement is Radio

done by Radio Front-end. Radiation & Front-end
Reception is done by antenna. Communication
Analog Range
Digital Mixed Signal
Data Throughput
Digital Level of Rate
RFIC
ADC/DAC Integration
Baseband Transceiver
IQ Modulator
Processor
Figure 2: Typical Communication System Architecture Figure 3: Expectations from modern communication system

Operation of Typical Transmitter
Figure shows Typical Transmitter for Modern Communication System. Transmitter Antenna
converts digital signal to RF. Receiver works in a similar fashion but in reverse
order i.e. it converts RF into digital data.
t BPF
I t
t Switch /
Sin Circulator
VCO/ PLL PA
RF
IF
I IF Amp LO
1110 1001 1000 1011
Cos
1101 0001 0000 0111
Serial-to
-Parallel
VCO
0100
1011
Q
Q
1111 0011 0010 0110
1 t
1010 1100 0101 0100
0
1
1
0
1
0
0 Figure 4: Flow of signal in a typical transmitter t

Duplex Systems
Communication systems can be “Simplex” i.e. communication can take place only in one direction at one time or can be “Duplex” i.e. communication takes
place both ways at same time. Duplex systems are preferable in voice communication systems. Data communication can be duplex but may be asymmetric
i.e. data channel is broadband while acknowledgement channel is narrow band. Video broadcast is an example of simplex system. Local Area Network
(LNA) is an example of duplex system.
In Time Division Duplex (TDD) systems, Transmit and Receive Packet Bursts take place in different
time slots.
RF in
PA Preamble Preamble
Transmit Data Packets Receive Data Packets

t
SPDT In Frequency Division Duplex (FDD) systems, Transmission and Reception takes place in different
switch frequency bands.
RF out
LNA
Figure 5: Radio Front-end for Time Division Duplex
Transmit Band Receive Band f
RF in
PA
Circulator
RF out
LNA
Figure 6: Radio Front-end for Frequency Division Duplex

Dual Conversion Transceiver Architecture
Agilent Technologies Transmitter inputs IQ signals and
modulates IF tone and its quadrature
component with them. The sum of the
+ quadrature components modulates RF
I_ carrier. Receiver does the reverse.
90º In the figure you can easily distinguish

RF Mixer
between Transceiver and Radio Front-
+ end. Filters have not been shown in
Q_ the figure but are essential off-chip
Antenna
components of a Radio.
PA
Channel 0º Transceivers have two well known
Selection
VCO/PLL VCO/PLL
architectures. Figure shows a dual
conversion transceiver. Architecture
+ SPDT uses three mixers in transmit and
I _ switch three mixers in receive chain.
RF Mixer BALUN LNA Transmitter

90º
Two mixers at the input modulate IF
+ quadrature components with I and Q
Q _ signals. The modulated outputs are
summed and modulate the RF. RF
Figure 7: Dual Conversion Transceiver output is amplified by a Power
Amplifier. Amplified output from the
Power Amplifier is radiated by the
antenna into space.
Receiver
Antenna picks up weak signals from space and passes them to the Low Noise Amplifier. Function of the Low Noise Amplifier is to amplify the weak signals
without adding much of its own noise. A BALUN converts single ended output of the LNA into differential signal. Mixer down converts the signals at RF to IF.
Signals at IF are further down converted by two mixers to I and Q components by mixing them with quadrature IF components.

Direct Conversion Transceiver Architecture
+ Figure shows direct conversion architecture of a transceiver. Its

I_ operation is same as that of a dual conversion transceiver with
only one difference that there is a single conversion.
90º Transmitter
The two input mixers modulate RF and its quadrature component
+
directly with I and Q signals from the baseband. The outputs are
Q_
Antenna summed and amplified by a Power Amplifier. The amplified RF
PA output is radiated into space by an antenna.
Channel 0º
Selection
VCO/PLL Receiver
Antenna picks up weak signals from the space and pass them on
+ SPDT to Low Noise Amplifier. Low Noise Amplifier amplifies the signals.
I _ switch RF output from the LNA is converted into differential signal by a
BALUN. Differential RF signal is mixed with RF and its quadrature
component to recover I and Q signal components.
BALUN LNA
90º
Merits and De-merits
+
Direct Conversion Transceivers use lesser components than Dual
Q _ Conversion Transceivers use. The architecture uses less number
of filters. The drawbacks of such a transceiver are slightly
Figure 8: Direct Conversion Transceiver degraded performance, DC coupling between stages, lower
reverse isolation in RF Path, and lower isolation between LO and
RF leading to self demodulation of LO and wandering DC
problems.
PLL at high frequency requires high-end CMOS Technology

(0.18um or below), high speed small swing digital design with
level shifters, and higher power consumption.

Transceiver Specifications
Various specifications of a Transceiver are shown in the figure. Two or more requirements can be inter-
dependent leading to iterative nature of Transceiver Design.
Output Power
Linearity Transmitter
Function of a transmitter is to transmit Modulated RF Carrier into space with minimum distortion and
sufficient power to reach the receiver under worst channel considerations.
Bandwidth- System bandwidth is the requirement placed by data rates. Choice of Bandwidth affects
Transmitter Cascaded receiver sensitivity.
Gain
Output Power- Maximum output power from a transmitter depends on receiver sensitivity, maximum
distance between transmitter and receiver, and nature of channel (Path Loss & Attenuation). In case
antenna is isotropic, power drops with square of distance. This is referred to as Path Loss.
Spur Levels
Various attenuations and antenna losses have to be taken into
    4R  account to compute the power received by the receiver. This power
2
Stability LP =   = −20 log10  

System  4R     has to higher than sensitivity of the receiver.
Cascaded
Bandwidth
Pout _ max = L p + Lattenuation + Lantenna _ loss + Sensitivit y
Noise Figure
Linearity Linearity- Non-linearity affects communication system in two ways. It causes Inter-symbol interference
due to AM-AM & AM-PM conversion. This affects Bit Error Rate of the system. Out-band emissions due to
non-linearity cause inter-channel interference.
Spur Levels- Inter-modulation frequency components and harmonics are referred to as spurs. Their power
Receiver SFDR level is expressed relative to carrier power (dBc). Spurs cause inter-channel interference and affect Noise
Figure of the receiver. Spurs grow with transmitter power and limit the maximum power that transmitter can
transmit.
Sensitivity Stability- Spurs can also be result of oscillations in Gain Stages. In-band as well as out-band stability
across all supply voltages, power, and temperature of every circuit has to be assured.
Selectivity
Figure 9: Transceiver Specifications

Transceiver Specifications
Receiver
Function of a receiver is to respond to weakest signals in the desired band and produce output with certain
Output Power acceptable bit error rate (BER). Another characteristics of a receiver is to reject undesired bands.
Linearity
Sensitivity- Ability of a receiver to detect weakest signals in the desired band and faithfully reproduce the
signal of interest at an acceptable BER is called Sensitivity. It can be expressed in dBm or uV.
e = k .f .T .(S N )det .NFT .Z 0 (V)

Transmitter Cascaded
Gain Here the terms refer to commonly known quantities.
Noise Figure- Its is the ratio of the gain offered by a stage to Noise to the gain offered to Signal
expressed in dB. In case it is specified as a pure number then it is called Noise Factor. Terms in the noise
Spur Levels figure can be rearranged to define Noise Figure as the ratio of Signal to Noise Ratio at the input of the
receiver to Signal to Noise Ratio at the output of the receiver. In case various stages are cascaded, the
Stability overall Noise Figure is mathematically given by-
System
Bandwidth NF2 − 1 NF3 − 1 NF4 − 1 G1 , G2 , G3 , G4 ,
Cascaded NFT = NF1 + + + + .... NF1 NF2 NF3 NF4
Noise Figure G1 G1G2 G1G2G3
Linearity
NF refers to Noise Factor. Figure 11: Cascaded Stages
This Noise Factor does not include contribution from image, harmonics, and inter-mod products. The
effects of reverse Isolation in RF Path, RF to LO Isolation of the mixer and leakage are also not included in
this expression.
Receiver SFDR
Selectivity- Ability of a receiver to reject out of the band frequencies like image, harmonics & Inter-
modulation products. Noise around these components increases Noise Figure of the system.
SFDR- Spurious Free Dynamic Range is the ratio of maximum input power a receiver can tolerate without
Sensitivity sufficient distortion to the minimum power a receiver can detect. Third Order Intercept Input Power is
considered as maximum input power.
Selectivity
Figure 10: Transceiver Specifications

Spectral Analysis of Transmitter
Exercise 1a & 1c:
Design of Transmitter with certain Spur Level & Compression Characteristics
Transmitter Overview
BPF_Chebyshev BPF_Chebyshev
BPF1 BPF2
Var VAR Fcenter =RFfreq Fcenter =RFfreq
Eqn
VAR1 BWpass =30 MHz BWpass =30 MHz
IFfreq = 70 MHz Ripple=0.2 dB Ripple=0.2 dB
LOfreq =766.5 MHz BWstop =IFfreq BWstop =IFfreq
RFfreq =IFfreq+LOfreq Astop =24 dB Astop =24 dB
IL =0.4 dB IL =0.4 dB
P_1Tone Amplifier2
MixerWithLO Amplifier2
PORT1 DriverStg
MIX1 PwrStg Term
Z =50 Ohm S21=dbpolar(16,0)
ZRef =50 Ohm S21=dbpolar(12,0) Term2
P =polar(dbmtow(0),0) S11=dbpolar(-10,0) S11=dbpolar(-10,0)
DesiredIF =RF plus LO Num =2
Freq =IFfreq S22=dbpolar(-10,180) S22=dbpolar(-10,180)
ConvGain =dbpolar(6.5,0) Z =50 Ohm
NF =15 dB S12=0 S12=0
SOI =27 SOI=50 SOI=58
TOI =20 TOI=40 TOI=48
LO_Freq =LOfreq
Figure 12: Complete Transmitter RF Section in ADS

Setting Up ADS Schematic
We will set up a new project for Transmitter Design and Analysis. From ADS Main Window choose “File> New Project…” to create a new project. Name the
new project as “TransceiverAnalysis”.
Creating New Project in ADS Components to Use
For this simulation we are going to
use “MixerIMT2” data based model
from “System-Data Models” Palette.
Various inputs are ConvGain =6.5 dB,

NF=8dB, IMT_File = “C:\...\circuit\
templates\dbl1.imt”
Creating New Schematic Sources to Use

From “Sources-Freq Domain” palette we
Use “New Schematic Window” Button use “P_1Tone” for this simulation.
from title bar to open a new schematic.
Use “File> Save Design” to name the

schematic as “UpConversion.dsn”.

Transmitter Specifications
Design Inputs Linear Output Power, System Bandwidth & Spur Level
Gain 31 dB Design inputs are listed on the left. Maximum power to be radiated by the antenna is computed
Maximum distance to receiver 30 km below. All the spurs are expected to be 50 dB below the carrier. System Bandwidth is 30 MHz.
Crest Factor 3 dB
Space Attenuation 0.04 dB/km Choice of IF
Transmit Antenna Loss 0 dB The nearest component to the RF is LO Frequency. For receiver requirements, the frequency
Receive Antenna Loss 0 dB midway between RF and LO frequency referred to as Half IF poses serious constraints on
Worst S/N for detector 13 dB receiver performance and has to be outside Receiver Bandwidth. IF filter has to offer sufficient
Channel Bandwidth 1.25 MHz attenuation to half IF. If we choose IF to be slightly higher than 2 times the Bandwidth, his will
Noise Figure 5.4 dB place half IF sufficiently away from the RF.
SFDR of Receiver 105 dB
System Impedance 50 Ω Let us assume the IF to be 70 MHz. For RF to be 836.5 MHz and IF to be 70 MHz, LO
Spurs at peak power -50 dBc frequency is 766.5 MHz. The lower and upper band edges are 821.5 MHz and 851.5 MHz. The
Radio frequency 836.5 MHz half IF is 801.5 MHz i.e. 20 MHz away from lower band edge. If you choose higher IF
System Bandwidth 30 MHz frequency a better Noise Figure can be achieved.
Approximate Requirements from transmitter
Data Based Mixer Model
Receiver sensitivity
e = k .BW .T .(S / N )det .NFT .Z 0 Figure shows the location of the file that
models the Mixer. Double Click “dbl1.imt”
= 1.38 10 − 23 1.25 106  298 19.9  3.46  50 to view its contents in Notepad.
= 4.21V = −94.5dBm To start with we will choose input IF power
Linear Output Power at Antenna to the mixer to be -10 dBm and LO power
c 3 108 to be 0 dBm. Set these numbers in the file
= = = 0.3586m and save it.
f 836.5 106
( )
L p = 20 log10 4 30 103 0.3586 = 120.4dB
Lta = Lra = 0dB
Pout _ max = e + L p + Lta + Lra + As  R = −94.49 + 120.4 + 0.04  30 = 27.14dBm

Components for ADS Schematic
Add a HB Controller to the Insert a “Var” Component & write equations

Schematic and set the
frequencies and order as
shown
Name output node “Vout”

Name the probe “Iout”
Write the equation for Pout
Create an ADS Schematic as shown in

the figure. Various components used are
shown in the figure.
Add IF and LO input sources as

“P_1Tone” components from “Sources-
Freq Domain” Palette.
Set the frequency and power for the

sources as shown in the figure.
Figure 13: ADS setup for Up Conversion using a file based Mixer Model

Analyzing the Simulation Results
Hit simulate button. Data display window opens automatically. Add a rectangular plot to the display
window. Add “Pout_S” to the rectangular plot. Write an equation in the display window as shown in the
figure to compute spur levels in dBc. Add a table. Add “SpurdB”, Mix(1), Mix(2), and “Pout_S” to the table.
Figure 14: Output of the mixer
Analysis & Conclusion

1 & -1 component refers to LO-IF component (image) That is undesirable and has to be suppressed
by a BPF. 1 & 0 component refers to LO component that depends on RF to LO isolation. 1 & 1
component refers to RF that is desired. The spurs are symmetric as the data based model of mixer
models it. Note that the conversion gain of the mixer is 6.5 dB as specified, IF input is -10 dBm and
RF output is -10dBm + 6.5 dB = -3.5 dBm.

BPF for Transmitter Chain
Add a new schematic to the project named “FilterTest”. Create a circuit as
shown in the figure. Specify Filter characteristics as shown in the figure. Define
variables using “Var” component. Set the S-Parameter simulation controller as
shown in the figure.
Hit Simulate. Data Display Window opens automatically. Add a rectangular plot
to the data display. Add S21 to the plot. Write the equations as shown in the
figure. Add a table. Double click the filter and use help to know its
characteristics.
Figure shows response of the Chebyshev BPF. It has a bandwidth of 30 MHz.
The stop band attenuation at stop band frequency is better than specified.
Band edges have insertion loss of 1 dB.
Figure 15: S-Parameter Simulation of Chebyshev

Band Pass Filter
Figure 16: S-Parameter Response of Band

Pass Filter

Mixer with Compression Characteristics
Agilent Technologies Non-Linear Mixer Models in ADS
Non-linear models for Mixer are available in
“System-Amps & Mixers” palette. We use
Besides Data Based Mixer Model, there are three more mixer models available in
“MixerWithLO” Model.
ADS that show compression characteristics. Out of these three only
“MixerWithLO” model can be used in Budget Analysis. We are going to use this
ZRef = 50 ohm, TOI = 18 dBm,
mixer model in transmitter design.
DesiredIF = RF plus LO, SOI = 25 dBm,
Create the schematic as shown in the figure. Specify variables using “VAR” ConvGain = dbpolar(6.5,0) LO_freq = LOfreq
Component as shown in the figure. Set up HB Simulation as shown in the figure. NF = 15 dB
Write the equations

for computing IM
Components. Save
the schematic as
“TOIandSOI.dsn” . In
case you do not
wish to write the
equations copy the
schematic from
Workshop CD. Refer
to the instructor for
doing so.
Figure 17: Non-Linear Mixer Simulations to demonstrate TOI and SOI of a Mixer

Two Tone Simulation of Mixer
Source of Mix Components & their Gains
Pout = g1 ( A1Cos(1t ) + A2Cos(2t ))

+ g 2 ( A1Cos(1t ) + A2Cos(2t ))
2
Second Order Mixing generates f 2 − f1 = 1MHz and f 2 + f1 = 141MHz components
that grow with twice the gain in dB with power.
+ g 3 ( A1Cos(1t ) + A2Cos(2t ))
3
Third Order Mixing generates 2 f 2 − f1 = 72MHz and 2 f1 + f 2 = 69MHz components
that grow with thrice the gain in dB with power
IM3 Lower IM3 Upper

2*f2-f1=72 MHz Figure shows the definition of Third
2*f1-f2=69 MHz
Order Intercept (TOI) and Second
IFfreq IFfreq+1MHz Order Intercept (SOI) for a non-linear
SOI response.
70MHz 71MHz
(f1) (f2)
TOI
LOfreq =766.5 MHz
Psat
Pout (dBm)
IM3 Lower IM3 Upper

835.5 MHz 838.5 MHz
836.5 MHz 837.5 MHz Pin (dBm)

(f1) (f2) Figure 18: TOI & SOI of a Non-Linear Stage

Copy the data display “TOIandSOI.dds” from the workshop

CD. Refer to the instructor to understand the compression
characteristics of the mixer. Also observe the spectral
growth as the marker 2 is moved up to higher output
powers. View Gain Compression of the mixer.
Figure shows TOI and SOI of the mixer. IM3 components
are 48 dB below the tones. Half dB input compression
occurs at -3.7 dBm input power.
Figure 19: Response of the mixer to two tone input across input power

Complete Transmitter
Agilent Technologies By rule of thumb TOI of PA is 16 dB better than 1 dB compression point. SOI is usually 10
dB better than TOI.
Linear Output Power @ antenna 27 dBm. TOI of PA 48 dBm. Gain Margin 2dB
Crest Factor 3 dB. SOI of PA 58 dBm. Gain PA + Driver 28 dB
System Margin 1dB. Gain of Transmitter 31 dB. PA Gain 12 dB
1 dB compression point @ antenna 31 dBm. Mixer Gain 6.5 dB Driver Gain 16 dB
1 dB compression point of PA 31.4dBm. Losses in filters 0.8 dB.
P -1dB of Driver 19.4 dB

Margin 3 dB
TOI of Driver 39 dBm
SOI of Driver 50 dBm
Save “TOIandSOI.dsn” as
“TransmitterTOIandSOI.dsn”.
Add “Amplifier2” from “System-

Amps & Mixers” Palette to the
Transmitter Chain as shown in the
figure. Add the BPF designed
earlier as shown in figure.
Figure 20: ADS Schematic to analyze compression characteristics of transmitter

Save data display “TOIandSOI.dds” as IM3 @ peak

“TransmitterTOIandSOI.dds”. Hit simulate. Linear Power

Figure shows that Transmitter delivers
31.7 dBm at the antenna with 1 dB Gain
compression. At the linear power of 27
dBm at the antenna the IM3 components
are -37 dBc.
Po @ -1 dB
Compression
Figure 21: Response of the transmitter to

two tone input across input power

Spurious Analysis
Save “TransmitterTOIandSOI.dsn” as “TransmitterSpurLevel.dsn”. Replace input power source with

“P_1Tone”. Set the Power to 0 dBm and Frequency to “IFfreq”.
Set “IFfreq” and “LOfreq” in the HB Controller to be the simulation frequencies with order 3.
Delete all the equations in “Meas1” except “Pout_S”. Hit Simulate.
Plot “Pout_S” in a rectangular plot as shown in the figure. Figure shows that all the spurs at peak
power are below -147dBm.
Figure 23: Spectral Response of the

Transmitter at peak output power
Figure 22: ADS Schematic to simulate spurious response of the transmitter

Cascaded Gain and Compression
Exercise 1b:
Budget Analysis of Transmitter Chain
Schematic for Budget Analysis
Save “TransmitterSpurLevel.dsn” as “TransmitterCascadedGain.dsn”. Add a variable “IFpwr” to the variable component “Var1”. Specify “IFpwr” as power in
“P_1Tone” Source. Remove HB Controller and add a Budget Controller from “Simulation-Budget”.
Figure 24: ADS Schematic to simulate Cascaded Gain and Cascaded Gain Compression

Budget Controller
Enable Non-Linear
Analysis
Set Maximum Power
Add Measurements
Specify Channel BW
Choose Display Options
Figure 25: Budget Simulation Controller Setup

Hit Simulate. Results are automatically displayed.
Figure 26: Cascaded Gain and Gain Compression

Click tab “Measurement Table” at the bottom of the data display window to view results in
tabulated form. Click Tab “Measurement Plots” at the bottom of the data display window to
view the results in form of plots.
Table and plots show that at 0 dBm input power, the transmitter is 0.527 dB compressed.
The individual component contribution to the compression is as follows
Mixer is 0.397 dB Compressed

Driver is 0.13 dB Compressed
Output stage is not Compressed
Small Signal Gain is 32.871 dB. At peak power, the Transmitter Gain is 32.344 dB
Figure 27: Cascaded Gain and Gain Compression

Receiver Sensitivity & Noise Figure
Exercise 1d:
Receiver Design & Analysis
Receiver Overview
Var BPF_Chebyshev Amplifier2 BPF_Chebyshev BPF_Chebyshev

VAR
Eqn BPF1 LNA BPF2 BPF3
VAR1
Fcenter =RFfreq S21=dbpolar(14,0) Fcenter =IFfreq Fcenter =IFfreq
IFfreq = 70 MHz
BWpass =30 MHz S11=dbpolar(-10,0) BWpass =CHBW BWpass =CHBW
LOfreq =766.5 MHz
Ripple=0.2 dB S22=dbpolar(-10,180) Ripple=0.2 dB Ripple=0.2 dB
RFfreq =IFfreq+LOfreq
BWstop =IFfreq S12=dbpolar(-28,180) BWstop =10 MHz BWstop =10 MHz
CHBW =1.25 MHz
Astop =24 dB NF=0.8 dB Astop =10 dB Astop =10 dB
RFpwr =-30
MaxRej =60 dB SOI=42 MaxRej =60 dB MaxRej =60 dB
IL =0.4 dB TOI=32 IL =0.4 dB IL =0.4 dB
MixerWithLO Amplifier2
MIX1 IFAmp
Term
ZRef =50 Ohm S21=dbpolar(16,0)
P_1Tone Term2
DesiredIF =RF minus LO S11=dbpolar(-10,0)
PORT1 Num =2
ConvGain =dbpolar(2,0) S22=dbpolar(-10,180)
Z =50 Ohm Z =50 Ohm
SP11=dbpolar(-10,0) S12=dbpolar(-28,180)
P =polar(dbmtow(RFpwr),0)
SP22=dbpolar(-10,180) NF=10 dB
Freq =RFfreq
NF =8 dB SOI=54
SOI =42 TOI=44
TOI =32
LO_Freq =LOfreq
Figure 28: Complete Receiver RF Section in ADS

Receiver Specifications
Approximate Requirements from receiver
Design Inputs Receiver sensitivity Input TOI at Antenna Input 1 dB Compression
Point at Antenna
e = k .BW .T .(S / N )det .NFT .Z 0
Gain 28 dB
Worst S/N for detector 13 dB TOI input = e + SFDR P1dBinput = TOI input − 16dB
Channel Bandwidth 1.25 MHz
= 1.38 10 1.25 10  298 19.9  3.46  50 = −94.5dBm + 110dB
− 23 6
= 15.5dBm − 16dB
Noise Figure 5.4 dB
SFDR of Receiver 105 dB = 4.21V = −94.5dBm = 15.5dBm = −0.5dBm
System Impedance 50 Ω
Spurs at peak power -50 dBc First BPF in the design should be same as final BPF of Transmitter. First design the stages with Gain and TOI/SOI
Radio frequency 836.5 MHz inputs so as to achieve gain of 28 dB and input 1 dB compression point of 0dBm. With few iterations you can get the
System Bandwidth 30 MHz following design that can be good start point for final receiver design. Save the schematic as “DwnConversion.dsn”.
You can copy the

schematic and the data
display file from the
Workshop CD.
Figure 29: ADS Schematic for Receiver using System Components

The simulation setup uses “Pout_S=10*log10(0.5*real (Vout*conj ( Iout.i )))” to compute the output power. Write this equation using Measurement Equation
Component. Add the variables to the schematic using “VAR” Component.
“IFfreq=70 MHz”, “LOfreq=766.5 MHz”, “RFfreq=IFfreq+LOfreq”, “CHBW=1.25 MHz”, “RFpwr=-30”
Add the HB Controller and set the simulation frequencies as “RFfreq” & “LOfreq” with order 3. Hit Simulate. Repeat simulations with “RFpwr=0dBm”.
Figure 30: Response of the receiver to RFpwr=-30 dBm Figure 31: Response of the receiver to RFpwr=0 dBm
Figure on the left indicates that at -30 dBm input power, Receiver Gain is 29.2 dB & Spur Level is -155.7 dBc. Figure on the right indicates that at 0 dBm
input power, Receiver Gain is 28.6 dB i.e. receiver is 0.6 dB compressed & Spur Level is -94.6dBc. Thus initial design meets the Spur Level and Input 1 dB
Compression Point Specifications.

Budget Analysis
Agilent Technologies Copy the circuit and the variables on to a new schematic and name it “ReceiverCascadedNF.dsn”.
Add a Budget Controller to the Schematic. Set the Budget Controller as shown below.
Enable Non-Linear Analysis

such as Gain Compression
Limit Maximum
Input Power
Add Noise
Measurements
Set Channel BW for
Noise Computation
Format output
in rows
Enable Auto-format display
Figure 32: Budget Controller settings for receiver simulations

Cascaded Noise Figure
Hit simulate. Data Display window displays the results automatically. Double Click the table in “Measurement Tables” Page and format it as graph. Reduce
the “RFpwr” to a point that S/N ratio at the output across channel bandwidth reduces to 13 dB. Note this power. You can copy “ReceiverCascadedNF.dsn”
from the Workshop CD.
Figure 33: ADS Schematic to simulate Cascaded Noise Figure of the Receiver and Signal to Noise Ratio at the detector input


Figure shows that -95 dBm input power results in minimum S/N ratio at the detector input that can be detected. Thus the lowest power at the antenna that
can be detected is -95 dBm. Noise Figure of the receiver is 4.48 dB. This Noise Figure does not take into account the noise from harmonic distortion
(under compression), the noise due to leakage and the noise due to inter-modulation products. Noise Figure is a strong function of reverse isolation of
cascaded components, and mixer LO to IF isolation.
Figure 34: Receiver performance with lowest detectable input power

Input TOI of the Receiver
Change the “max. component input power (dBm)” in Budget controller to “40 _dBm”. Add “InTOI_dBm” to the “Selected Measurements” List in the Budget
Controller under “Measurements” Tab. Perform Budget Simulations.
Table under “Measurement Tables” Tab of the Data Display window shows that at the input of “BPF1” i.e. antenna input, the input TOI is 11 dBm. From the
previous results the weakest power at the antenna that can be detected in -95 dBm. Hence the Spurious Free Dynamic Range (SFDR) of the receiver is
106 dBm. To further improve the SFDR introduce a variable Gain LNA with better dynamic range or use a better detector.
Figure 35: Receiver Performance simulated though Budget Analysis in ADS
We have successfully designed RF section of a Radio Transceiver to transmit & receive over a distance of 30 km. The radio has system Bandwidth of 30 MHz
and Channel Bandwidth of 1.25 MHz.

Modern Communication Systems
Tutorial 2: Introduction to various modulation techniques
Theory of Modulation
A pure sinusoidal wave, referred to as carrier, has three characteristics namely- Amplitude, Frequency & Phase. The data can be analog or digital. Digital
data does not directly modulate the carrier because the modulating signal has to be bandwidth limited and it would not be spectrally efficient for data bits to
directly modulate the carrier.
Depending on the carrier characteristics that is modulated the form of modulation can be amplitude modulation in case carrier Amplitude is modulated or
frequency modulation in case carrier Frequency is modulated or phase modulation in case carrier Phase is modulated. Any of these forms of modulation
result in sidebands when viewed in frequency domain.
For these basic forms of modulations various Modulators are

available in ADS under “System- Mod / Demod” palette. For
Pure Sinusoidal demodulation the corresponding demodulators are also
Wave Carrier
AC Cos (C t + C )
available.
More than one of the characteristics of sinusoidal carrier can

be modulated to achieve higher data rates. The data bit
stream can be divided into symbols of two or more bits. These
Amplitude Modulation Phase Modulation symbols can be represented by unique carrier phase and
amplitude. Thus the phasor diagram of the carrier can be
Frequency Modulation divided into bins with each bin representing a symbol. This
from of modulation is called QAM.
Figure 36: Basic Forms of Modulation
Thus QAM 16 has 16 bins in carrier Phasor Diagram, QAM 32
has 32 bins, QAM 64 has 64 bins and so on.
These forms of modulation and many more have been

standardized by IEEE. Most commonly known are NADC,
PDC, IS95, WCDMA 3GPP, EDGE, CDMA 2000 etc.
Figure 37: Basic Modulators & Demodulators

Envelope Simulations
Time Domain simulation involving modulated signals requires time step decided by carrier frequency while the total duration of simulation is decided by bit
rate or symbol rate. This results in large simulation time at small time steps. This problem is solved through envelope simulations. Time stepping in
Envelope simulations is decided by symbol rate and samples per symbol. The total duration of simulation is decided by number of symbols and symbol
rate. RF carrier frequency is specified as in Harmonic Balance Simulations.
Typical Envelope Simulation Controller settings for a π/4-DQPSK (Differential Phase Shift Keying)
system are shown in the figure. For more complex standards like IS95 and WCDMA, symbol rate
and bit rate have to be known. Various signal sources are available for complex modulation
schemes in ADS.
Var VAR
Eqn
VAR1
IFfreq = 70 MHz
LOfreq =766.5 MHz
RFfreq =IFfreq+LOfreq
CHBW =1.25 MHz
RFpwr =-30 DSP Based Sources are
Bit_rate =48.6 KHz Ptolemy Designs for the
Sym_rate =Bit_rate/2 Source.
Syms =100
SamPerSym =10
Tstep =1/(Sym_rate*SamPerSym)
Tstop =Syms/Sym_rate
Figure 38: Envelope Simulation Controller Settings
Figure 39: Modulated Signal Sources in ADS

Linearity Characterization
Due to Non-Linearity in a circuit or a system various near band (out-band) components are generated example inter-modulation products for two tone inputs.
In a multi-tone scenario whole spectrum appears adjacent to the channel. This is referred to as “Spectral Growth”. The power in adjacent channel (integrated
across complete adjacent channel) compared to power in channel of interest is referred to as “Adjacent Channel Power Ratio” (ACPR). Thus the two
adjacent channels (higher & lower in frequency) have ACPR_upper and ACPR_lower. The emission in next upper and lower channels compared to power in
channel of interest is referred to as “Alternate Channel Leakage Ratio” (ACLR).
Linearity Can also be expressed in terms of demodulated symbols. For QAM we have discussed that there are bins for each symbol. Due to non-linearity of
the system, the demodulated symbols have certain phase and amplitude error of carrier. This vector error expressed as percentage of carrier phasor is
known as “Percentage Error Vector Magnitude” of “%EVM”. Error Vector Magnitude (EVM) can also be expressed in dB.
Carrier phase and magnitude varies EVM

due to non-linearity in a system i.e.
phase imbalance and gain imbalance
ACPR & ACLR Definition
offered to I & Q signals results in
Error as shown in the figure.
ACPR_upper
ACLR_upper
I I
There is an upper limit on these

specifications based on tolerable System’s Q Q
S/N at transmitted peak power (i.e.
Transmitter Chain under compression)
Figure 40: ACPR & ACLR for a Non-Linear System
Transmitted Constellation Received Constellation

Figure 41: Error Vector Magnitude for a Non-Linear System

ACPR Measurements for Transmitter
Exercise 2:
ACPR Simulations using Envelope Simulator
Simulation Setup Overview
Figure shows the transmitter designed earlier, with input as modulated IF. “PI4DQPSK_ModTuned” from “System-Mod/Demod” palette is
used as modulator. Data input to the modulator is from PN Sequence Generator. Measurement equations are written to compute channel
power and ACPR.
Meas MeasEqn
Eqn
Meas1
MainChannelPower = 10*log10(channel_power_vr(mix(Vout,{1,1}),50,{-15 KHz, 15 KHz},”Kaiser”))+30
ACP_Transmitter = acpr_vr(mix(Vout,{1,1}),50,{-15 KHz, 15 KHz}, {-45 KHz, -15 KHz}, {15 KHz, 45 KHz}" Kaiser”)
Var VAR
Eqn VAR1
IFfreq = 70 MHz
ENVELOPE
LOfreq =766.5 MHz BPF_RaisedCos
RFfreq =IFfreq+LOfreq BPF3 BPF_Chebyshev Envelope BPF_Chebyshev
IFpwr =-4.9 Alpha =0.25 BPF1 Env1 BPF2
Bit_rate =48.6 KHz Fcenter =IFfreq Fcenter =RFfreq Freq[1] =LOfreq Fcenter =RFfreq
PI4DQPSK_ModTuned
Sym_rate =Bit_rate/2 SymbolRate =Sym_rate BWpass =30 MHz Freq[2] =IFfreq BWpass =30 MHz
MOD1
Syms =100 DelaySymbols =Filt_DelaySyms Ripple=0.2 dB Order[1] =3 Ripple=0.2 dB
Fnom =IFfreq
SamPerSym =10 Exponent =0.5 BWstop =IFfreq Order[2] =1 BWstop =IFfreq
Rout =50 Ohm
Tstep =1/(Sym_rate*SamPerSym) DutyCycle =100 Astop =24 dB Stop =Tstop Astop =24 dB
SymbolRate =Sym_rate
Tstop =Syms/Sym_rate SincE =yes IL =0.4 dB Step =Tstep IL =0.4 dB
Delay = 50 nsec
Filt_DelaySyms =10
Videal Vin Vout
P_1Tone VtLFSR_DT MixerWithLO Amplifier2 Amplifier2

PORT1 SRC1 MIX1 DriverStg PwrStg
Vlow = -1 V ZRef =50 Ohm S21=dbpolar(16,0) S21=dbpolar(12,0) Term
Z =50 Ohm
Vlow = 1 V DesiredIF =RF plus LO S11=dbpolar(-10,0) S11=dbpolar(-10,0) Term2
P =polar(dbmtow(IFpwr),0)
Rate = Bit_rate ConvGain =dbpolar(6.5,0) S22=dbpolar(-10,180) S22=dbpolar(-10,180) Num =2
Freq =IFfreq
Delay = 0 nsec NF =15 dB S12=0 S12=0 Z =50 Ohm
DT
Taps = 6538 SOI =27 SOI=50 SOI=58
Seed = 27 TOI =20 TOI=40 TOI=48
Rout =1 Ohm LO_Freq =LOfreq
Figure 42: Transmitter with π/4 DQPSK modulated IF Input

Transmitter ACPR Simulations
Copy transmitter circuit from “TransmitterTOIandSOI.dsn”
to a new schematic and name it “TransmitterACPR.dsn”.
Add the variables as shown in the figure. Add Envelope
Controller and set the frequencies & order. Specify stop
and step time. Replace the input by a source circuit as Left Shift Register with series Raised Cosine Filters provide
shown in the figure. Name the nodes as in figure. Add feedback from various taps sharp cutoff, FIR in nature,
measurement equations for Channel Power and ACPR. (6538) and a starting seed is a Alpha specifies excess BW,
PN Sequence Source. Delay has to be adjusted
PI4DQPSK_ModTuned
is available in “System-
Mod/Demod” Palette
Figure 43: ADS Schematic to perform Envelope Simulations on Transmitter with π/4 DQPSK modulated IF Input

Hit Simulate. In the data display window add rectangular plots showing power spectrum (in dBm) at Vout node and Vin node. Note that the desired
component of Vout is at index 4 and that of Vin is at index 1. Add polar plots for Videal, Vin and Vout. The desired indexes are 1, 1, 4 respectively. Add a
table to display main channel power, lower and upper ACPR.

Adjust the IFpwr to -4.9 dBm such that the output power is 27 dBm. Observe that ACPR is better than -40dBc.
Figure 44: Output (Red) and Input (Blue) Power Spectrums. ACPR better than -40 dBc at desired output power of 27 dBm

RF Board Technology
Tutorial 3a: Introduction to Microwave Theory & Application of RF Boards
Applications of RF Boards
Applications
• Radio Frequency Boards are used for interconnecting components (Integrate Circuits (ICs), System in package (SIP) modules and daughter boards).
• RF Boards are used for evaluation of ICs, SIP Modules etc
• RF Boards are used as carriers for ICs in a Module.
Characteristics of RF Boards
• Electrical Characteristics of a board are

• Dielectric Constant that decides velocity of propagation of Electromagnetic (EM) Wave
• Loss Tangent that decides dielectric loss of a board
• Dielectric Material (Substrate) Height that decides dielectric and radiation losses and via insertion loss
• Metal (conductor) Thickness that decides conductor loss
• Variation of dielectric constant across frequency that decides signal dispersion
• Dielectric breakdown that decides power handling capacity of transmission lines
• Physical Characteristics
• Temperature Coefficient of Expansion that decides suitability of board for plastic modules
• Peel-off strength of metal that decides suitability of board for harsh environment
• Flexibility of board that decides suitability of board for moving parts ( flip screens of laptops and mobile phones)

Structure of Substrates
Single Layer Boards (Laminates)
Figure below shows a panel of single layer board. Boards are available in standard substrate heights and of standard panel size from vendors like Rogers.
Key Specifications of a Board are-

W
Substrate Height (H)- 4/10/20/60 mil
Panel Size (L x W)- 5” x 8”
Metal Thickness- ¼ Oz or ½ Oz or 1 Oz Copper
Metal 2- Copper i.e. 0.67 mil or 1.34 mil or 2.68 mil
L
plated with gold Relative Dielectric Constant ( r )- 2.2 – 6.6
Loss Tangent ( tan  )- 0.001 – 0.03
Dielectric Metal Conductivity ( )- 4.1 x 107 S / m
(Laminate/Substrate)
Metal 1- Copper
plated with gold
H
Figure 45: Single Layer Laminate
Multi-Layer Boards (Laminates)
Figure left shows Multilayer Board. The connectivity between metal structures on
two layers is through Vias.
Figure 46: Multi-Layer Laminate

Via Connectivity
Via and its types
Figure 47: Via connecting two metal traces Figure 48: Plated through Via Figure 49: Filled Via
Vias are used for connecting two metal traces on different metal layers. The height of the via is same as that of the substrate. Via Inductance depends on the
height of the via. So thicker the substrate higher the via inductance. In high frequency designs this inductance may be intolerable. Hence thinner substrates are
used. Vias are of two types- a) Plated through Vias & b) Filled Vias. Plated through Vias have higher inductance compared to Filled Vias.
Typical Parameters
Via Diameter
Drill Diameter Smallest Drill Dia. – 10 mil
Drill Location
Smallest Via Dia. – 4 mil
Via Location for EM Sim. Min. Via loc. from edge – 4 mil
Min. separation
between traces – 4 mil
Min. Separation between Traces
Figure 50: Typical laminate via dimensions

Board Material
Laminates (Board Material) are available from various vendors. The most widely known vendor for laminates is Rogers. The most commonly used laminates are
mentioned below.
RT Duroid 5870/ 5880 Glass micro fiber reinforced Poly Tetra Fluoro Ethylene
5870 ( r = 2.3) & 5880 ( r = 2.2)
tan  = 0.001
Suitable for high frequency application
Thermal Coefficient of Expansion not very well matched to that of copper
RT Duroid 6002/ 6202/6006/6010LM Ceramic reinforced PTFE

6002 & 6202 ( r = 2.94) & 6006 ( r = 6.15) & 6010LM ( r = 10.2)
tan   0.001
Suitable for high frequency application
Thermal Coefficient of Expansion very well matched to that of copper
Thermally very stable
TMM 3/ 4/ 5/ 6/ 10/ 10i Thermostat Ceramic Loaded Plastic
TMM 3 ( r = 3.27) & TMM 4 ( r = 4.5) & TMM 6 ( r = 6.0) & TMM 10 ( r = 9.2) & TMM 10i ( r = 9.8)
tan   0.001
Well suited for microstrip patch antennas, for space application and are good replacement for Alumina
There are other laminates suited for high frequency applications. Please refers to Rogers website.

Electromagnetic (EM) Simulations
Numerical Methods are used for simulating Electric and Magnetic Fields in a charge free medium. Field Solution results in determination of voltage and current at
various points in a passive structure. This is an exact way of determining parasitics of a structure.
Numerical Methods
For Electromagnetics
For structures much For structures comparable to or

larger than Wavelength, smaller than Wavelength,
Computation for Scattering Computation of fields
Optical Techniques Field Solution
PTD- Physical Theory GO- Geometric

of Diffraction PO- Physical Optics Matrix Techniques Time Domain Techniques
Optics
GTD- General Theory

UTD- Universal
of Diffraction
Theory of Diffraction
FEM / FVM- Finite MoM – Method of FDTD – Finite Difference
Element/Volume Method Moment Time Domain Method
Figure 51: Various Methods for full field simulations

EM Solver Choice
Finite Element Method Finite Difference Time

Method of Moment
Finite Volume Method Domain Method
Features Features Features

• Requires computation of substrate dependent • Based on specialized form of Garlekin’s • Based on finite differences in time and space
Green Functions Method domain in quadrature
• Not easy to parallelize • It is a method of residues • Time stepping and space stepping of EM
• Has a limit on size of structures • Not very accurate at high frequencies Waves
• 2.5 D Simulator- Solves E and H Fields in thin • Not easy to Parallelize • Easy to Parallelize
sheets • 3D Simulator- Solves E and H Fields in • Has no limit on size of structures
• Frequency domain technique volumes • Time domain technique
• Has limit on size of structures
Applications • Frequency domain technique Applications
• Good for planar structures, 2D structures in • Good for 3D structures, uses cubical and
form of thin sheets or thin bent sheets Applications hexagonal cells
• Not good for 3D structures, models z-currents • Good for 3D structures, uses tetrahedral mesh • Good for simulating Vias, bond wires,
and fields & does not compute them and dynamic meshing packages and sockets
• Not exact for Vias, bond wires and volumes • Good for simulating Vias, bond wires, • Encloses structures in Perfectly matched
• Computes Far Filed patterns from packages and sockets layers, does not have to choose large volume
transformation from near field patters • Computes Far Filed patterns from enclosing
transformation from near field patters • Not good for mix of large and small features
like thin sheets and large volumes
• Can do multi-wavelength structures

EM Solvers from Agilent
Examples
MOMENTUM Method of Moment based EM Solver, suitable for planar structures like
passives on boards and on ICs
EMDS Finite Volume Method based EM Solver, suitable for IC Packages,

Module Packages and Enclosures
AMDS Finite Difference Time Domain Method based EM Solver, suitable for
IC Packages, Module Packages, Enclosures, multi-wavelength large
structures etc.

Generic Packages
Air Cavity Package (ACP)

Quad-Flat No Lead (QFN)
Quad-Flat Package (QFP)
Ceramic Flat Pack (CFP)
System in Package (SIP)

Generic Packages
Ball Grid Array (BGA)
Fine Pitch Ball Grid Array (FBGA)
Ceramic Pin Grid Array (CPGA)
Flipchip Package (FP)

Microwave & RF Components
Tutorial 3b: An overview of Microwave Theory & EM Wave Propagation
Point Form of Maxwell’s Equations
Maxwell’s Equations
Relationships between gradient of electric and magnetic field vectors in space at any point is space to charge, current and their time gradients at any
point of time is given by various laws contributed by Faraday, Ampere, Gauss, Lenz, Coulomb, Volta and others. These were compiled into the final form by
James Clerk Maxwell and came to be known as Maxwell’s Equations.
For the Maxwell’s Equations to hold true the field vectors (electric and magnetic) should be single valued, continuous, bounded and their derivatives
should be continuous in the medium. Special case applies at media interface where charge and current can be abrupt referred to as boundary conditions.
Point Form
Differential form of Maxwell’s Equation referred to as point form is as follows
→ where
→ →B →  V Is electric charge density (Q/m3)
 E = − MS − E Is electric field intensity (V/m)
t  M Is magnetic charge density (W/m3)
→
→ →
→ → D
→ H Is magnetic field intensity (A/m)
M S Is impressed magnetic current
  H = JS +  E+ →
t D Is electric flux density (Q/m2 ) →
→ J S Is impressed electric current
. D =  V →
B Is magnetic flux density (W/m2) →
→  E Is electric current due conductivity
→
. B =  M M S Is magnetic current density ( V/m2) →
D
→ Is magnetic displacement current
J S Is electric current density (A/m2) t
→
B
Is electric displacement current
t
Source of Electric Field
Types of Electric Field in Space
a) Static Electric Field- Electric Field that does not change with time
b) Dynamic Electric Field- Electric Field that changes with time
Static Charges as a Source of Static Electric Field
+
Governing Maxwell’s Equation

.D = V Source of Electric Field is electric charges. Electric Lines of Force
initiate at positive charges and terminate at negative charges
Static Electric Field (E)
-
Static Charges Relation of Electric Field to Potential

Figure 52: Static Field from Static Charges E = −V
Such an arrangement of static charges has no mechanism to generate magnetic field and hence incapable of setting up Electromagnetic Waves. For
Electromagnetic waves to exist, there must be time varying Electric and Magnetic Fields

Time Varying Electric Field
Time Varying Electric Field (or Electric Current) as a Source of Loops of
+
Magnetic Field
H Source of Loops of Magnetic Field is time varying Electric Field or Electric Current
Density
E
  
EM Waves   H = J + D t
_ In the present set-up of fixed charges in space, there is time harmonic to the
charges, capable of setting of time varying Electric Field which sets up Magnetic
E
field. The electric current density is zero. This is equivalent to voltage standing
H
waves on a resonant length wire.
t1 Figure 53: Time harmonic of charges sets up TEM Waves

time
+ _
H E
E
H
_ EM Waves +
EM Waves
E E
H H
t3
t2
time time

Time Varying Magnetic Field
open end Time Varying Magnetic Field (or Magnetic Current) as a Source of Loops of
H Electric Field
Source of Loops of Electric Field is time varying Magnetic Field or Magnetic Current
E Density
I
L

  
  E = − M S − B t
open end I
H In the present set-up of standing wave current on a wire, there is time harmonic of
E current, capable of setting of time varying Magnetic Field which sets up Electric Field.
The magnetic current density is zero.
t1
time Figure 54: Time harmonic of standing wave Electric Current sets up TEM Waves
open end open end
E E
H I H
I L
L
open end I open end I

H H
E E t3
t2
time time

Dielectric Material Properties
Medium Properties (Constitutive Relations)

Electric and Magnetic Flux Density Vectors are related to Electric and Magnetic Field Intensity Vectors using a set of medium dependent constants.
These relations are referred to as Constitutive Relations. These constants are direction independent in case of Isotropic Materials and direction dependent in
case of Anisotropic Materials. In case these constants are field strength dependent the medium is Non-Linear else Linear. These constants are Constant of
Permittivity (affecting Electric Flux Density) and Constant of Permeability (affecting Magnetic Flux Density) within the medium. In case these parameters are
function of frequency then the medium is Dispersive else Non-Dispersive.
Insulators & Polar & Anisotropic Anisotropic Isotropic

Semiconductors
D X   XX  XY  XZ  E X  D X   XX 0 0  E X  →
D = E
→
D  =   YY  YZ  . E Y  D  =  0  YY 0  . E Y 
Dielectric  Y   YX  Y 
DZ   ZX  ZY  ZZ  E Z  DZ   0 0  ZZ  E Z 
B X   XX  XY  XZ  HX  B X   XX 0 0  HX  → →
Magnetic B  =   YY  YZ  . HY  B  =  0  YY 0  . HY 

B = H
 Y   YX  Y 
B Z   ZX  ZY  ZZ  HZ  B Z   0 0  ZZ  HZ 
The above two constitutive relations hold true in case of insulators that have dipoles and no free charges. These dipoles align when static field is applied to the
medium and oscillate when the applied field has time harmonic relation.
In case of conductors that have free electric charges (no dipoles), a constitutive relation know as Ohm’s Law is applicable.
→ → Free Magnetic charges do not exist, hence no equivalent of Ohms’ Law for magnetic materials
Conductors J = E

Material Properties and Losses
Electric Polarization
→
Electric Field applied to the dielectric causes dipoles to align as per the applied→field. For charge neutrality there is a polarization vector ( D ) in the
direction of the applied field as shown in the figure. This increases the Electric Flux Density (P ) in the medium
where
→ → →
0 Is the dielectric constant of free-
D = 0 E+ P
space (8.854e-12) F/m
+ + + + + + + → →
- -
P =  0 E (1 + ) = r Is the relative dielectric
P E Dipoles → → → → → →
 D =  0 E +  0 E =  0 (1 +  ) E =  0 r E =  E
+ + constant. It is a pure
- - - - - - - complex number
Figure 55: Source of Dielectric Loss in a substrate.

Dielectric Loss  = '− j "
The imaginary part of dielectric constant takes into account the loss due to damping of oscillating dipoles when alternating electric field is applied across the
→
dielectric. Substituting into the Maxwell Curl Equation and assuming
JS = 0
→ → → → → →
  H =  E+ j('− j" )E =  E+ j' E+ " E Ratio of real to imaginary part gives the loss tangent. Loss Tangent is a measure of total loss (dielectric and
conductive) in the medium compared to stored reactive power.
Loss Tangent
 + "
tan( ) =
'
Magnetic Polarization and Loss → → → → → → → →

It is similar to Electric Polarization. B =  0 H+ P =  0 H+  0 H =  0 (1 +  )H =  0r H =  H Magnetic Loss has similar mechanism as that for dielectric loss.

Microstrip Line
Microstrip Line
W Microstrip Line
Microstrip line as shown in the figure consists of a metal transmission line separated from
an electrically large ground plane by dielectric material.
Important Points to note
H There are two medium- air and substrate- in which fields exist. Propagation Velocity in air
Dielectric is different from that in substrate. This distorts TEM Mode and results in ‘Quasi-TEM’
d
E Mode of propagation.
Ground Plane
Figure 56: Electric and Magnetic Fields for a Microstrip Line
The difference in relative dielectric constants of air and substrate results in

a) Electric Lines of Flux fringe at the edges.
b) Current density at the edges increases compared to that in the center of the line.
If W/h is large
a) Fringing reduces.
b) Field Intensity is high within the substrate causing increase in current density at the line-substrate interface
In case air and substrate are replaced by dielectric material of slightly lower relative dielectric constant completely surrounding the Microstrip Line such that
Electric Flux Density is the same, the dielectric constant is called Effective Dielectric Constant.
Quasi-static analysis of a microstrip line results in very close approximation of its electrical properties. Effective Dielectric Constant is used in all the
calculations
Metal thickness contributes to fringing of the Electric Lines of Flux as well at the Microstrip edges

Microstrip Line Design Trade-offs
Microstrip Formulae by I.J. Bahl, K.C.Gupta, R.Garg, and D.K. Trivedi
W- Width of the Microstrip Line Effective Dielectric Constant Characteristic Impedance

d- Dielectric thickness    60  8 W d 
 r - Relative Dielectric Constant r + 1  r − 1  12   ln +  for W d = 1
e = + . 1 1+
W   e  W d 4  
 e- Effective Dielectric Constant 2  2  Z0 =  
 d 120 
 for W d  1 
Velocity  e W d + 1.393 + 0.667 ln(W d + 1.444 ) 
 
1
vp =
00e
Eeff
Figure 57: Effective Dielectric Constant, Phase Velocity & Characteristic Impedance for microstrip line

Microstrip Line Attenuation- Dielectric Loss
Figure 58: Dielectric Loss of a Microstrip Line
 00 r (e − 1) tan 

d = x 10-3 Np/mm
2 e (r − 1)
Figure shows−3the attenuation due to dielectric

loss ( e − d .10 ) per unit length in mm as function
of width of the microstrip line in mm for different
relative dielectric constants, dielectric thickness,
loss tangent, frequency and conductivity
 conductor = 2 x 10 6 S
Observations
• As dielectric constant increases, the flux density
within the substrate increases leading to higher
dielectric loss
• As the line width increase fringing in free-space

reduces and the flux density within the substrate
increases leading to higher dielectric loss
• As frequency increases dielectric loss increases
• As the substrate height increases, fringing in free-

space increases and the flux density within the
substrate reduces leading to lower dielectric loss
• As the loss tangent reduces the dielectric loss

reduces

Microstrip Line Attenuation- Conductor Loss
Figure 59: Conductor Loss of a Microstrip Line
0 2
c = x 10-3 Np/mm
Z0 W
Figure shows the attenuation due to conductor loss

−3
( e− d .10 ) per unit length in mm as function of
width of the microstrip line in mm for different
conductivity, dielectric thickness, dielectric
constant, frequency and loss tangent tan() = 0.02
Observations
• As dielectric constant increases, the flux density

within the substrate increases reducing the effective
conductor cross section area and increasing the
conductor loss
• As the line width increase fringing in free-space
reduces and the flux density within the substrate
increases. It increases the effective conductor cross
section area and reduces the conductor loss
• As frequency increases skin depth reduces and
conductor loss increases
• As the substrate height increases, fringing in free-
space increases and the flux density within the
substrate reduces. It increases the effective conductor
cross section area and reduces the conductor loss
• As the conductivity is increased the conductor loss
reduces

Losses in RF Boards
Exercise 3a:
Losses in Transmission Lines on RF Boards
Open Study File
Step1: Create project named “IntroductionLayout_prj”

Step2: Copy Design File named “Dielectric_ConductorLoss.dsn” from “IntroductionLayout_prj” on Workshop CD & open it
Figure 60: Path to the desired design file

Simulation
Step3: All the microstrip equations are written as measurement equations. Hit “Tuning” to start simulations
Figure 61: ADS Setup to study Microstrip Line Characteristics using Tuning

Analysis Data Display
Step4: Various Sliders indicated Material Properties and Microstrip Line Dimensions. Move them to see their effect
Phase Velocity Vs
Characteristic Impedance
Dielectric and Conductor

Losses Vs Characteristic Imp.
Phase Velocity in m/s
Losses in
dB
Line Dimensions in mil

Figure 62: Data Display Window and Tuners to analyze Microstrip Line Characteristics

50 Ω Lines on RF Board
Exercise 3b:
Microstrip Lines & Coplanar Waveguide design on RF Board
Microstrip Line Design @ 6GHz
Step1: Open “LineCalc” Program from Start> All Programs> Advanced Design System 2008> ADS Tools> LineCalc
Design Aim: Design a 50 Ohm Microstrip Line on FR4 Substrate with an electrical length of λ/4 at 6 GHz
Step2: Enter the design form as below
Substrate Parameters
 r = 4.3 Design
r = 1 Outputs
H = 10mil
Hu = 
T = 0.67mil
 = 4.1107 S / m
tan  = 0.02
Design
Outputs
Component Parameters
Freq = 6GHz Design
Inputs
Figure 63: Synthesized dimensions of 50 Ω microstrip line, λ/4 @ 6 GHz

Substrate Definition
Step3: Open a New Layout from ADS Main Window using “New Layout Window” Button.
Save the new layout as “MicrostripLine.dsn”
Step4: Define substrate using “Momentum> Substrate> Create/Modify…”
Figure 64: Define Substrate Layers under “Substrate Layers” Tab

Metallization
Step5: Map Layout Layers as Metal Layers

and define their properties
BrdVia is mapped as VIA with following

properties
Metal0 and Metal1 have same properties and are

mapped as “STRIP” shown
Figure 65: Metal Layers and their definition

Save Substrate Definition
Step6: Save Substrate Definition for reuse in later designs using “Momentum>
Substrate> Save As…”. Name the file as “FR4Sub.slm”
Figure 66: Save Substrate Definition in a file

Microstrip Line Layout
Step7: Layout the structure shown
in figure using the techniques for
drawing discussed earlier. Make
sure dimensions are proper and line
is aligned to the center of the ground
plane.
Use “EMDS> 3D EM Preview” to

view the structure in 3D
274.3 mil
18.7 mil
418.7 mil
Figure 67: Microstrip Line Layout and 3D Preview

Setup for Simulations
Add Ports
Port are added where the characteristics of a passive circuit are sought. Port have to be on the same metal layer as the
Layout the circuit structure.
Step 8: Add Port 1 and Port 2 on Metal1 Layer to the centre of two Microstrip Line edges. Enable “Midpoint Snap” for
ease of port placement.
Add Ports
Declare Port Type
Pre-Compute
Substrate
Choose Metal Layer for ports
Setup Mesh
Frequency
Pre-Compute
Mesh
Setup Frequency
Plan & Simulate
Figure 68: Flow for EM Simulations Figure 69: Ports on Metal 1 at Microstrip Line edges

Port Alignments and Application
Step 9: Add Port 3 and Port 4 on Metal0 Layer to the centre of two Ground Plane edges. Use “Rotate By Increment” button from Menu Bar for rotating
the port in steps till it aligns as show in figure.
Step 10: Use “Momentum> Port Editor…” to define
ports. Port 3 is “Ground Reference” associated to Port1
and Port 4 to Port2
Figure 71: Ports at the center of two edges of ground plane on Metal 0
Use “Midpoint Snap” and “Rotate By Increment”

Figure 70: Access to Port Editor
to properly place the ports

Port Types using Port Editor
Declare Port Type as below
Select the port to

be defined
Choose the nearest Port
Figure 72: Ground Reference Ports in association to other Ports

Pre-Compute Substrate
Step 11: Use “Momentum> > Substrate> Precompute…” to define frequency for substrate computation and perform Green Functions computation for the
substrate
Figure 73: Pre-Compute Green Functions for substrate in defined frequency range

Mesh Setup
Step 12: Use “Momentum> Mesh> Setup…” to define mesh

properties. Set the “Mesh Frequency”
Figure 74: Set the mesh frequency

Setup Frequency for Simulation and Simulate
Step 13: Use “Momentum> Simulation>

S-parameters…” to define simulation
frequency and simulate.
Choose Sweep Type as Single
Set the frequency
Add it to Frequency Plan
Hit “Simulate” to perform simulations
Figure 75: Simulation Setup

Data Display
Step 14: As soon as simulation completes Data Display opens with following results. Place a marker on S11. It shows that the design is off. Instead of
expected impedance of 50 Ohm, it is 73 Ohms. To correct the design, widen the microstrip line to 25.1 mil and re-simulate the circuit.
Figure 76: Simulation Results

Correction and Re-Simulation
Step 15: Corrected Microstrip Line Width results in 50 Ohm line as shown by the simulation results. Use “Momentum> Post-Processing> Visualization…” to
view currents.
Figure 77: Improved Simulation Results

Design CPWG using LineCalc
Design Aim: Design

a 50 Ohm Coplanar
Waveguide Line on
FR4 Substrate with
an electrical length of
λ/4 at 6 GHz
Step 16: Use Line
Calc to design the line
as shown in figure
Step 17: Open a

New Schematic from
ADS Main Window.
Save the new design
as “CPWGLine.dsn”.
Figure 78: CPWG Design using LineCalc

CPWG Layout
Step 18: Open FR4 Substrate saved earlier using “Momentum> Substrate> Open…”. Click “No” to “Open a supplied substrate?” Choose “FR4Sub.slm”.
Step 19: Layout the CPWG Structure as shown in the figure. Add Port 1 and Port 2 to the line on Metal 1 and 3 and 4 to ground on Metal 0. Define Port 3
and 4 as Ground Reference Ports with respect to Port 1 and Port 2 respectively.
4 mil from edge

5 mil gap
14 mil
420 mil
293 mil
Figure 79: 50 Ohm CPWG Layout

EM Simulation Response
Step 20: EM Simulation response shows that line is slightly off in impedance. Increase the width of line and re-simulate.
Figure 80: EM Simulation Response of CPWG Line

Corrected CPWG Line
Step 21: Increase the width of the line to 17 mil without affecting other dimensions and re-simulate the line.
Figure 81: EM Simulation Response of corrected CPWG Line

Microwave Filters
Tutorial 4: A brief overview of microwave filters
An Introduction to filters
Filters are two port networks that provide frequency selective impedance matching between two ports. A filter response has two distinct regions namely-
pass band and stop band. Magnitude and Phase response of a filter depends on the placement of poles and zeros in complex frequency plain.
Characteristics of a Filter
Filters are two port passive networks i.e. S11 + S 21 = 1
2 2
General Transfer Function
S 21 ( j ) =
2 1
1 +  Fn2 ( )
2
A general transfer function represented by S21(s)=N(s) / D(s) in complex plane s=σ+jω has zeros (i.e. where function takes on zero value) and poles
(i.e. where function takes on infinite value or singularities). In the complex plane x-axis represents ω=0 i.e. frequency independent network and y-axis
represents σ=0 i.e. lossless network. σ can take on negative values only i.e. left half of complex s plane as filters are passive. Filters are thus always
stable. ε in the general transfer function represents ripple amplitude and is modulated by frequency dependent function Fn2 ( ). This response in a low
pass response. Thus the base design of a filter is low pass. High pass, band pass and band stop filters are obtained by certain transformation.
Insertion Loss Based on magnitude & phase response (depends on Fn2 ( )) filters can be of following types
 
IL _ dB( ) = 10 log10 
1  a) Butterworth (Maximally Flat Amplitude in pass and stop band) Filters
 S ( j ) 2 
 21  b) Chebyshev ( Equal-ripple Amplitude in pass band, Maximally Flat Amplitude in stop band) Filters
Return Loss c) Elliptic ( Equal-ripple Amplitude in pass and stop band) Filters
(
RL _ dB( ) = 10 log10 1 − S 21 ( j )
2
) d) Gaussian ( Maximally Flat Group Delay) Filters
e) All Pass ( Unity Amplitude only Phase Response ) Filters
Phase Response
21 _ rad ( ) = phase(S21 ( j )) Butterworth and Chebyshev are all pole filters with equal spaced poles on circle or eclipse in left half of
Complex s plane. Filter choice depends on filter characteristics desired. In case of broad band systems
Group Delay Group Delay response of chosen filter may have to be equalized using All Pass networks.
− d21
 21 _ sec( ) =
d

Filter Design Flow
In ADS, Filter Design Flow is automated using Filter Design Guide. To demonstrate a
Choose a generic design flow we will design an elliptic band pass filter for WIFI 802.11 b / g
Filter Type applications with following specifications
Filter Characteristics
Pass Band Frequency 2.4 – 2.6 GHz

Choose Filter Pass Band Insertion Loss 1.9 dB
Order Stop Band Attenuation
@ 2100 MHz <18 dB
@ 1980 MHz <20 dB
@ 836 MHz <35 dB
Frequency Mapping @ 3700 MHz <20 dB
Step 1: Create a new project named “BPFDesign”. Create

“FilterSynthesis.dsn” Schematic.
Impedance Scaling
Filter Design Guide
Filter Transformation A component from “Filter DG – All”

palette has to be placed on to the
schematic to specify the type of filter.
“Design Guide > Filter” opens a Wizard
Richard’s to design and simulate the filter.
Transformation
Design Guides are circuit synthesis and simulation wizards that
Figure 83: Various Design Guides in ADS
Figure 82: Filter Design Flow assist a designer to design circuits and perform fast
simulations.

Microwave Filter Design
Exercise 4:
Band pass Filter Design using Filter Design Guide
Band pass Filter Design
Step 2: From “Filter DC – All” palette place “Band-pass Lumped Element Step 3: Use “DesignGuide > Filter” to perform filter design. Choose
Filter Smart Component” on to the schematic. Click “Ok” to the information. “Filter Control Window…” to open “Filter DesignGuide” Wizard.
Figure 84: Band-pass Lumped Element Filter Smart Component
Figure 85: Access to Filter Control Window

Using Filter Assistant
Step 4: In Filter
DesignGuide under Filter
Assistant tab, set the
inputs
Fp1= 2.4
Fp2=2.6
Fs2=3.6 Filter Pass band Ripple
Fs1=1.9
Units=GHz
Filter stop band edge
Ap =0.3 dB attenuation
As = 18 dB
First Element: Parallel
Response Type: Elliptic
Hit Design to synthesize

the filter.
Filter order is computed
automatically.
We will not use other tabs
in the Filter DesignGuide Filter Frequency
for now. Response
Figure 86: Filter Design

using Filter Assistant

Filter Simulations
Step 5: Create S Parameter Simulation setup in ADS to simulate the designed filter
Step 6: Plot S21 and S11. Note that RL is better than 10 dB in pass band
and all attenuation characteristics are met.
Figure 87: ADS Setup for S-Parameter Simulation of the designed filter
A More detailed design is beyond the scope of this workshop.
Figure 88: ADS Setup for S-Parameter Simulation of the designed filter

Phase Locked Loop from System Perspective
Tutorial 5: A brief introduction to Phase Locked Loops
Basics of Frequency Synthesis
In coherent Communication Systems, a stable frequency source is required. A controllable source of frequency is required to select a channel in the
band of operation. This is achieved through a frequency synthesizer.
A frequency synthesizer generates one or more spectrally pure and stable frequencies using a very stable frequency reference source. Besides, VCO
performance criteria of Spectral Purity, Thermal Stability and Low VCO Wideband Noise, the others criteria are fast frequency acquisition time, and
high steady state frequency accuracy. The design constraints are low power, low supply voltage and small die size.
Spectral Purity
Single tone is desired in communication systems with no other spectral components. This is not feasible due to device noise and voltage and current
perturbations in resonant circuits. If frequency perturbation is discrete set of frequencies then spurs or side bands appear. Spurs are measured in dBc.
In case such variations are random in nature then skirts appear around the tone. The spectral purity is measured in terms of spectral power per Hz at
certain offset from the carrier expressed in dBc/Hz. This is referred to as Phase Noise.
V(t ) = V0Sin (2f 0 t ) Represents Pure Sinusoidal Signal
Vp (t ) = (V0 + v(t ))Sin (2f 0 t + (t )) Represents Signal with Amplitude and Phase Noise
Through amplitude limiting the effect of amplitude modulation by noise can be removed.
Vp (t ) = V0Sin (2f 0 t + (t )) Represents Signal with Phase Noise Only

Nature of Phase Noise
(t ) = .Sin (2f m t ) + (t )

where
   2 Random Phase Variation causes skirts around the pure tone as well as the spurs in spectra
Spurs or Side-bands

Basics of Frequency Synthesis
Ignoring the random phase noise component-

Vp (t ) = V0Sin (2f 0 t + .Sin (2f m t )) = V0Sin (2f 0 t )Cos (.Sin (2f m t )) + V0 Cos (2f 0 t )Sin (.Sin (2f m t ))
V  V 
Vp (t ) = V0Sin (2f 0 t ) + V0 Cos(2f 0 t ).Sin (2f m t ) = V0Sin (2f 0 t ) + 0 Sin (2(f 0 + f m )) − 0 Sin (2(f 0 − f m ))
2 2
Spurs at offset of (f m ) = −20 log10  2 

  
VCO
-60 -30dB/Dec
PLL
PN (dBc/Hz)
-90
-120 -20dB/Dec
1K 10K 100K 1M 10M

freq
Figure 89: Typical Nature of SSB Phase Noise of a VCO and a PLL
In-band Phase Noise of PLL is as good as that of the reference while

Out-band Phase Noise is same as that of a VCO

Introduction to PLL
Phase locked loop is a feedback control system used to stabilize the frequency of a Voltage Controlled Oscillator in a communication transceiver or a digital
clock. A random variation in time period of VCO output tone viewed in time domain appears as a Jitter and in frequency domain as skirts around the tone of
interest. This can be due to device noises in VCO Circuit. The other issues can be drift of frequency with temperature or ageing of the circuits. PLL is used to
stabilize the frequency of a VCO. PLL is also used for channel selection in a transceiver.
Block Diagram of a PLL
f ref Vcontrol
LF f out
PFD CP
Xtal
VCO
Div by N
On-board Pierce Oscillator
PLL
Figure 90: Phase Locked Loop with reference frequency generator

Operation of PLL
Output frequency from the voltage controlled oscillator is divided by an integer by “Divide by N” Counter. The divided frequency is compared with the
reference frequency from the external source by “Phase Frequency Detector” (PFD). Output of the PFD turns on/off current source and sink current to the
Charge Pump (CP). PFD does this by comparing leading edges of waveform from reference and that from “Divide by N” Counter. If the leading edge of
reference frequency is before that of divided frequency then pull up is activated else pull down is activated. Thus the output of charge pump increases if
divided frequency is less than that of reference and decreases if divided frequency is more than that of reference. Output of Charge Pump is filtered by a
loop filter (LF) and controls the control voltage of the VCO. In steady state- f out = Nf ref
Demerits of Integer N PLL
• High Resolution results in narrow loop bandwidth and larger locking

f ref Vcontrol time.
LF f out
PFD CP • Spurs at reference frequency and its harmonics are at low offsets
from the desired frequency. Their suppression is difficult.
VCO
• Large Divide-by ratio increases phase noise associated with the
reference signal, the PFD, the CP and the frequency divider by
20.log(N) dB.
Div by N
• As visible from the PN nature across offset frequencies in the
previous slide, the VCO phase noise at low frequency offsets is not
PLL sufficiently suppressed.
Figure 91: PLL Operation

Phase Noise & System Performance
Exercise 5:
A Demo Simulation to show effect of Phase Noise on EVM of the system
Effects of Phase Noise on Transceiver Performance
Copy project “EffectsofPhaseNoise_prj” from workshop

CD into your ADS working directory. Open
“a_QPSK_Sys.dsn”. Locate “QPSK Demodulator” and its
LO Source. Edit the phase noise expression of the
source to be good as shown in the figure and hit
simulate. Adjust filter delay to get clear constellations.
Low Phase Noise results in

Low % EVM
Figure 92: Good phase noise of LO Source does not degrade % EVM of the demodulated signal

Effects of Phase Noise on Transceiver Performance
Edit the phase noise expression of the LO tone to be bad

as shown in the figure and hit simulate. Adjust filter delay
to get clear constellations.
High Phase Noise results in

High % EVM
Figure 93: Effect of bad phase noise of LO Source on % EVM of the demodulated signal

Types of Frequency Synthesizers
Besides Integer N PLL, the other types of commonly used PLL are Fractional N PLL.
Frequency Fractional-N PLL-FS
Synthesizers The divide by ratio in a fractional N synthesizer is a fraction and hence large frequency
reference can be used. This results in large loop bandwidth, small locking time, and better
Direct Indirect phase noise at low offsets. Fixed pattern for dual or multi modulus divider results in low
Synthesis Synthesis frequency spurs that reside inside loop bandwidth and are difficult to suppress.
Direct Analog PLL-FS Blocks f ref

PLL DLL f out
FS PFD CP/LF VCO
 N 
Direct Digital   (Dual Modulus counter)
FS Integer N Fractional N  N +1 
CLK  N  CLK
P (Programmable Counter) P  
Dual Multi  N +1 
Modulus Modulus
 S (Programmable Swallow Counter)
M
CLK
Rest of the blocks are same as those Programmable
Figure 94: Types of Frequency Synthesizers of Integer N PLL Count P
S
Programmable
Count S
Summary of Operation Figure 95: Dual Modulus Fractional N PLL
Let us assume all the counters are down counters and all the latches are negative edge triggered. VCO output is clock for dual modulus counter. For S
counts, this counter divides by N+1 and for the remaining P-S counts, the counter divides by N. The counts in P and S choose the channel in the
frequency band. Both counters are down counters. Till S in not reset M can be active and cause Dual Modulo counter to count N+1 pulses. As soon as S
is reset M changes state and Dual Modulo counter counts N pulses. Both S and P are loaded with counts when P resets. The reset Pulse from P is PN+S
division of VCO output and is compared to reference frequency. The duty cycle does not matter as long as all the counters and PFD are edge triggered.
f out
f ref =
S(N + 1) + (P − S)N
f out = S(N + 1) + (P − S)Nf ref = S + PNf ref

Dual Modulus PLL Design
Design Example for a Dual Modulus Randomized Fractional N PLL

PLL Topology of Choice
Demerits of Fixed N/(N+1)
Fixed N/(N+1) fractional divider causes spurs within the loop bandwidth. Spurs appear at a
f ref f out
XTAL /D very low offset frequency and are difficult to suppress. For such a PLL to be useful for
PFD CP/LF VCO communication purposes various methods can be adopted. One of the method is to
CLK randomize the fraction using a topology shown in the figure. We will see block by block
Randomizer  N  CLK performance of the components and response of the complete PLL at various channels in
 
T  N +1  the WLAN band.
Comparator P-S R M Various Channels in WLAN band
Logic Logic Channel Mix with 2.8 GHz (16) P-S (17) S
2412 MHz 388 MHz 20 4
CLK
Programmable T 2417 MHz 383 MHz 8 15
Count P-S
S 2422 MHz 377 MHz 13 18
R 2427 MHz 373 MHz 18 5
Programmable
2432 MHz 368 MHz 23 0
Count S
Figure 96: Dual Modulus Fractional N PLL Block Diagram 2437 MHz 363 MHz 11 11
2442 MHz 358 MHz 16 6
2447 MHz 353 MHz 21 1
2452 MHz 348 MHz 9 12

PLL Components PLL Constants 2457 MHz 343 MHz 14 7
The topology uses N = 16 2462 MHz 338 MHz 19 2
• three Programmable Counters,
• a PN Sequence Generator, f XTAL = 25MHz 2467 MHz 333 MHz 7 13
• a Phase & Frequency Detector,
D = 25 2472 MHz 328 MHz 12 8
• a Charge Pump
• a Second Order Loop Filter, and f ref = 1MHz 2477 MHz 323 MHz 17 3
• a VCO 2482 MHz 318 MHz 5 14
2487 MHz 313 MHz 10 9
PLL Topology © Copyright 2009 Agilent Technologies 106

Programmable Counters
PN Sequence Generator
PN Sequence Generator generates random one and zero bit stream. Output of this PN Sequence Generator generates
• control bit (M) for N/(N+1) Divider,
• Toggle signal for P-S Counter and S Counter, if residue count in both these counters is not zero.
In case residue count is zero in P-S counter and residue count is not zero in S counter, M is held to one till S counts down to zero. In case
residue count is zero in S counter and residue count is not zero in P-S counter M is held to zero till P-S counts down to zero.
Count Reload on 22nd
Down Edge
N/N+1
16 Counts 17 Counts 16 Counts 17 Counts

V out
M
time (sec)
Figure 97: Performance of the N/(N+1) divider with
Randomized Control Bit
Steady State statistics for PLL locked to 363 MHz
P-S=11
S=11
P=22
16 x 11+17 x 11=363
Freq=363 MHz/363= 1MHz
Selected Channel is 2437 MHz

PFD, Charge Pump & Loop Filter
Figure 98: State Diagram for PFD Design
Vdiv  Vref 
Vdiv  P up =0 P up =0 P up =1 Vref 
P dn =1 P dn =0 P dn =0
Vref  Vdiv 
Second Order Loop Filter Design

K VCO = 2(125)MHz
f ref = 1MHz
TS = 40u sec Figure 99: Phase & Frequency Detector Response
4 P up
fC =  100KHz
Ts P dn
To make sure the stability of the loop

f
f C  ref
10
Choosing
f C = 91KHz
Vcntl
I CP .R.K VCO C
C = 2f C = Z = 1.3992V
Figure 100: (up) Second Order Loop Filter
2N 3
2C N 1
or R = C1 = = 269pf
I CP K VCO Z R Figure 101: (left) Charge Pump and Loop Filter
N = 400 p 2 = 3C time (sec) Response in time domain
I CP = 100A
C2 =
1
= 32pf f out = f 0 + Vcntlx K VCO = (188 + 125 x 1.3992)MHz = 363MHz
R = 18.3KHz p 2 R

Mixer from System Perspective
Tutorial 6: Mixers in Modern Communication Systems
Specifications of a Mixer
Introduction
Mixers are active or passive circuits used to translate the frequency of the signal . In case a mixer scales up the frequency it is called an up-conversion
mixer and in case it down scales the frequency it is called a down-conversion mixer.
Specifications of a Mixer
Various important specifications of a mixer that affect transceiver performance are
Conversion Gain: It is the ratio of power at the output of the mixer to that at the input of the mixer expressed in dB. Conversion Gain affects the over all
gain of the transmitter or receiver chain. In most of the active mixers Conversion Gain trades-off with peak linear input power.
Peak Linear Input Power: Maximum input power to a mixer up to which Conversion Gain does not show appreciable compression. It can be expressed as
Input Power at 1 dB compression point.
Input Third Order Intercept (TOI_input): It is the input power at which third order inter-mod product gain and linear conversion gain matches.
RF-to-LO Isolation: It is important for a down conversion mixer. It is the isolation in dB between RF and LO ports of a mixer. It affects receiver noise figure,
sensitivity and dynamic range and in case of active mixer the DC operation point of the mixer. RF-to-LO isolation is good in quadrature mixers and relatively
poor in Gilbert Cell mixers.
Reverse Isolation: It is important for a down conversion mixer. It is the isolation in dB between input and output of a mixer. It affects receiver noise figure,
sensitivity and dynamic range.
Gain Compression: It is the characteristics of a mixer as its conversion gain drops with increasing input power. It can be due to limitation of the input or of
the output voltage/current swings.
Gain Imbalance: In case of differential output from a mixer, it is the difference in gain between inverted and non-inverted outputs.
Phase Imbalance: in case of differential output from a mixer, it is the difference in phase between inverted and non-inverted outputs.

Mixer in Perspective- Up-conversion
A fu S I Sin ( IF t +  fu (t ))
S I Sin( IF t +  fu (t )) 
M
SI =  A In e − j(In t +  In ( t ))  
A fu  
A fu Sin ( IF t +  fu (t )) + SQ Cos( IF t +  fu (t ))
n =0
 
1 2
LO1 PLL
A fuCos ( IF t +  fu (t )) LPF or BPF can be used

M
− j(Qn t + Qn ( t )) Asu Cos(LOt + su (t ))
SQ =  A Qn e
n =0 LO2 PLL
A fu S Q Cos ( IF t +  fu (t ))
Image Component rejected by
final ceramic BPF
1
2
  
sin (IF + LO )t +  fu (t ) + su (t ) − sin (LO − IF )t + su (t ) −  fu (t ) 
A fu Asu APAS I

+
A fu Asu APASQ
2
  
cos (IF + LO )t +  fu (t ) + su (t ) + cos (LO − IF )t + su (t ) −  fu (t )  
2
A fu Asu APA
2
S I   
sin ( IF +  LO )t +  fu (t ) + su (t ) + SQ cos ( IF +  LO )t +  fu (t ) + su (t ) 
Figure 102: Role of Mixers in first and
second up-conversion

Mixer in Perspective- Down-conversion
A fu Asu APA ALNA A fd

4
S I    
sin ( IF )t +  fu (t ) + su (t ) −  fd (t ) + SQ cos ( IF )t +  fu (t ) + su (t ) −  fd (t ) 
A fu Asu APA ALNA A fd Asd
SI
8
Asd Sin ( IF t + sd (t ))

1
LO4 PLL
Asd Cos(IF t + sd (t ))

LPF
A fd Cos ( LOt +  fd (t ))
LO3 PLL
A fu Asu APA ALNA A fd Asd
SQ
8
1
A fu Asu APA ALNA
2
S I   
sin ( IF +  LO )t +  fu (t ) + su (t ) + SQ cos (IF +  LO )t +  fu (t ) + su (t )  
Figure 103: Role of Mixers in first and

second down-conversion

Mixer Topologies
Mixers can be of various types. Few of them are-

• Single Diode Mixer
• Balanced Diode Mixer
• FET Gilbert Cell Mixer
• HBT Gilbert Cell Mixer
• Quadrature Mixer
Diodes can be used in square law region to provide mixing. Single

diode used for mixing is an unbalanced mixer while two diodes
can be used to result in balanced mixer.
Mixers can have balanced input and balanced output. RF and LO

inputs can be differential and output can be differential as well.
Such mixers are called dual balanced mixers. One example of Figure 104: BJT Gilbert Cell Mixer Figure 105: FET Gilbert Cell Mixer
such a mixer is a Gilbert cell mixer. Gilbert cells can be CMOS Vcc
implemented using FETs or BJTs. Dual Gate FETs can also be Bipolar Vcc
used as single device mixers. 3
2
Single ended to differential conversion is done using BALUN. 7
Gilbert Cell requires two such BALUN for RF and LO inputs. IF1
4 6
Quadrature Mixer does not require single ended to differential
conversion as they have single ended RF and LO input and RF 5 4
differential output.
IF2
6
LO 1 3
5
(1) Hybrid (2) RF Bias Decoupling (3) IF Bias Decoupling (4) RF 2

Reflection Stub (5) RF Input Match (6) IF Output Match (7) Bias
Circuit Figure 106: Quadrature Mixer

Introduction to SMT Components
Tutorial 7: Surface Mount Components for Mixer Design
SMT Component Modeling
We will design an MIC Quadrature Mixer on a four metal FR4 board. We will use SiGe HBT Devices, Johanson Capacitors and Coilcraft Inductors.
Let us look into modeling of Johanson Capacitors. Johanson provides software for modeling capacitors. Install the software from the workshop CD
and launch the program.
Figure 107: Launch the modeling software from the ‘Start’ Menu

SMT Capacitor Modeling
Choice of
Capacitor
Capacitor Size and

Pad Dimensions
SPICE Model for

Capacitor. Rp should
be removed as it alters
circuit DC conditions Figure 108: Software Wizard to Model 0402 Capacitor. SPICE Model of a 10 pF Capacitor

SMT Inductor Modeling
0402CS Series RVAR = k * f

Part number R1 R2 C(pF) L(nH) k H
0402CS-1N0 2 0.001 0.2 1.3 6.00E-06 104000 where f is the frequency in Hz
0402CS-2N0 2 0.001 0.1 2.2 9.80E-06 68000
0402CS-2N2 1 0.01 0.2 2.2 8.00E-06 86500
0402CS-3N3 2 0.001 0.09 3.4 1.20E-05 54000
0402CS-3N6 2 0.001 0.1 3.6 1.30E-05 50000
0402CS-3N9 2 0.001 0.05 3.9 1.30E-05 51000
0402CS-5N1 2 0.001 0.05 5.1 1.70E-05 39500
0402CS-5N6 2 0.001 0.05 5.6 1.75E-05 38000
0402CS-6N2 2 0.001 0.05 6.3 2.20E-05 30500
0402CS-7N5 2 0.001 0.05 7.5 2.60E-05 26000
0402CS-8N2 2 0.001 0.12 8.4 2.70E-05 23500
0402CS-9N0 2 0.001 0.08 8.9 2.80E-05 23300
0402CS-10N 2 0.001 0.08 10.1 3.10E-05 21500
0402CS-11N 2 0.001 0.09 10.8 3.50E-05 18600
0402CS-12N 2 0.001 0.09 12 3.90E-05 16700
0402CS-15N 2 0.001 0.1 15 5.10E-05 12900
0402CS-19N 2 0.001 0.1 18 6.00E-05 11000
0402CS-23N 3 0.001 0.1 1 22 7.00E-05 9000
0402CS-27N 4 0.001 0.1 26 8.00E-05 7700
0402CS-36N 5 0.001 0.1 36 1.20E-04 5200
0402CS-40N 7 0.001 0.11 40 1.30E-04 4600
Figure 109: SPICE Models for Coilcraft 0402 Surface Mount Inductors SPICE Model for 0402
SMT Inductors
Passives used in mixer design like inductors and capacitors should be
modeled or their “s2p” (touchtone) files should be used in simulations. These
details are available for various Coilcraft Inductors in “Coilcraft” folder on
workshop CD.

Introduction to Gilbert Cell Mixers
Tutorial 8: BJT and FET Gilbert Cell Mixer Operation & Design
Gilbert Cell Multiplier as Mixer
Left figure shows emitter coupled pair, right figure shows source
coupled pair. Difference of current in two legs is directly proportional to
the differential input voltage in a linear fashion in certain input voltage
range. Three such pairs constitute a four quadrant multiplier popularly
known as Gilbert Cell.
Figure 111: Emitter Coupled Pair Figure 112: Source Coupled Pair
Left figure shows basic Gilbert Cell Multiplier. Differential output current
depends on multiplication of two differential input voltages. Placing a
resistive load results in differential output voltage proportional to product of
two differential input voltages.
Figure 110: BJT & MOSFET Gilbert Cell

Gilbert Cell Operation- Emitter Coupled Pair
Vi1 − Vbe1 + Vbe 2 − Vi 2 = 0 or Vi = Vbe1 − Vbe 2 (a) I out = I 7 − I8 = (I 3 + I 5 ) − (I 4 + I 6 ) = (I 3 − I 4 ) − (I 6 − I 5 )

I  I   Vy   V   V 
Vi = VT ln  c1  − VT ln  c 2  I out = I1 tanh −  − I 2 tanh − y  = (I1 − I 2 ) tanh − y 
 Is   Is   2VT   2VT   2VT 
I   V   Vy 
Vi = VT ln  c1  I out = I tail tanh − x  tanh − 
 Ic2 
Vi
 2VT   2VT 
I c1
= e VT also − (I c1 + I c 2 ) = I tail (b) Assuming Vx  2VT and Vy  2VT
Ic2
I tail
I tail I tail I out = Vx Vy
− Ic2 = Vi
and − I c1 = Vi 4VT
2
−
1+ e VT
1+ e VT
I tail R c
I c = I c1 − I c 2 = − I c 2 − (− I c1 ) Vo = R c I out = 2
Vx Vy
4VT
 
  Note that as long as transistors in the pair are matched, the
 1 1  product is independent of the transistor sizes
I c = I tail  − 
 Vi
  V
− i 

 1 + e
VT  1 + e VT 
   
   
  − Vi Vi

  e 2 VT − e 2 VT 
 
I c = I tail   V   = I tanh − Vi 

  − 2 Vi Vi

tail  2V
   T 
 e T
+ e 2 VT
(a) Emitter Coupled Pair
 
 
(b) BJT Gilbert Cell

Gilbert Cell Operation- Source Coupled Pair
 n C ox  W  (a)
Assuming all NMOS transistors to same size
k=   Vi = Vi1 − Vi 2
2 L I out = I 7 − I8 = (I3 + I5 ) − (I 4 + I 6 ) = (I3 − I 4 ) − (I 6 − I5 )
 I
2
 2
V 2I1 2I 2
2
I out = kVy  − Vy − − Vy 
2
I d1 = k  tail − i + i 
V
 2k 4 2  k k 
 
2   I 
2
 
2 
 1 Vi 
2 2
I out = kVy   tail − x + x  − V 2 −  tail − x − x  − V 2 
2 V V I V V
I d1 = k 
I tail Vi
− +  k y 
2   k 2 
y
 2 k 2 2 . 2   
2

2

 (b)
2
k  I tail Vi
2
V   I 2
V   I 2
V 
Assu min g  tail − x + x   Vy and  tail − x − x   Vy
V V
I d1 = − + i 
2 k 2 2   k 2 2   k 2 2 
  
Similarly
2 I out = 2kVy Vx
k I V 
2
I d 2 =  tail − i − i 
V
Vo = R d I out = 2kR d Vy Vx
2 k 2 2 

If top 2 pairs are same size and bottom pair is different size
I d = I d1 − I d 2
 
k I V 
( )
2 2
k 2  I tail Vx Vx  k 2  I tail Vx Vx 
2
I d =  2 tail − i  2Vi
2 2
I out 
= k1Vy  − + − Vy −
2
− −
2
− Vy 
2 k 2  k1  k 2 2  k1  k 2 2 
    2   2  
 2I tail 2  I out = 2k1k 2 Vy Vx
I d = kVi  − Vi 
 k 
(a) Source Coupled Pair
(b) NMOS Gilbert Cell

Basic Trade-off Theory for Gilbert Cell Multiplier
A multiplier can provide mixing with very low harmonic content which is also desirable for first down conversion. For multiplication, all three source-
coupled pairs are maintained to operate in linear region. At the expense of conversion gain, this arrangement is desirable for good linearity. If either
of the two signals or both are large enough to force either of the pairs or all into non-linear region, multiplication takes place not only between two
signals but also their harmonics.
For high conversion gain, LO Signal can be large to force the top two pairs out of the linear region without affecting the linearity of the mixer as long
as the lower RF Source coupled pair is linear and there is a harmonic LPF at the output of the mixer. Beyond certain LO level, increasing LO
strength does not affect the conversion gain, because inner and outer transistors in the top two pairs are steering current. In case of high LO level
and high RF level, the odd harmonics at the output of the mixer have to be terminated properly specially when the RF Filtering near the LO
frequency at the antenna is not sufficient.
The design parameters of interest are Conversion Gain and Linearity. Both will be decided by the RF input pair. For this source-coupled pair these
specifications translate to Trans-linear Gain and Input Voltage Range of Source Coupled Pair.
Trans-Linear Gain Input Voltage Range
GT = =
(
 (I d ) 2. I tail − kVi
2
)  Vi |G T =0 = 
I tail
= 2Vov
Vi 2.I tail k
− Vi
2
k
G T _ peak = G T |Vi =0 = 2I tail k

Transfer Characteristics of Transconductance Cell
Effects of W/L on performance of Source Coupled Pair Effects of W/L on performance of Source Coupled Pair
2.5 2.5
Itail = 2.5 mA Itail = 2.5 mA
2
1.5 2
Id1(mA),Id2(mA)--->
Id1-Id2(mA)--->
0.5 1.5
-0.5 1
-1
Vov =0.84V Vov =0.84V
-1.5 0.5
-2
Vov =0.42V Vov =0.42V
-2.5 0
-1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5
Vi(V)---> Vi(V)--->
2Vov
Figure 113: Differential Output Current Vs Input Voltage for Figure 114: Drain Current Vs Input Voltage for different FET Sizes
different FET Sizes
As is visible maximum input voltage range is achieved at the cost of low gain. Trans-linear gain of 0dB (1) causes maximum input voltage range of  2Vov.

Trans-linear Gain and Input Voltage Range
Agilent Technologies Input Voltage Range & Vov Vs W/L
Trans-Linear Gain Vs W/L
12 1.2
Trans-Linear Gain Input Range
Itail =2.5 mA 1.1 Itail =2.5 mA Over Drive
11
1
10
0.9
9
Vi im(V)& Vov(V)--->
0.8
Gt(mA/V)--->
8
0.7
7
0.6
l
6
0.5
5
0.4
4 0.3
3 0.2
0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350
W/L---> W/L--->
Figure 115: Gain Vs Device Size Figure 116: Input Voltage Range Vs
Device Size
Figure 117: Gain Vs Device Size &

Tail Current

System Considerations & Mixer Specifications
Designing for Pin@-1dB=0dBm at antenna & Receiver NF=8.8 dB
LNA
Pin=0dBm
Ceramic BPF BALUN
SPDT
Differential
Output to Mixer
Single Ended Input

to BALUN Mixer
Gain -1dB -2.8dB -0.6dB +12dB -3.5dB on each line
Power -1dBm -3.8dBm -4.4dB +7.6dB +4.1dB on each line
Figure 118: Power level calculation at the Mixer Input Design Mixer for super-heterodyne receiver with following
specifications
In a 50 Ω system 7.6 dBm corresponds to r.m.s voltage given by
• Conversion Gain (Gc) >-1 dB
 4.1
 • Input Return Loss @ RF & LO Ports <-10 dB
Vrms = 10 10
10 −3 .50 = 0.3585V • Noise Figure < 21 dB
  • Pin @ -1 dB Compression 7.6 dBm
• RF Frequency Band 2.4 – 2.5 GHz
V p − p = 2 2V rms= 1V = v x • LO Frequency 2.1 GHz
• LO 7.6dBm

Single Ended to Differential Interface
Exercise 6:
BALUN Operation and Design as Input Stage to Gilbert Cell
Single-ended to Differential Conversion- BALUN
Agilent Technologies BALUN RF BALUN LO
f 0 = 2.45GHz f 0 = 2.1GHz
Design BALUN using lumped components as shown in the figure. BALUN should Z0 Z0
operate over frequency band of 2.4 – 2.5 GHz for RF Input. VCO will be differential. For L= = 4.6nH L= = 5.36nH
2f 0 2f 0
simulation purposes we use single ended source. For LO operating at 2.1 GHz, design
another BALUN. Setup the circuit in ADS and perform S-Parameter Simulations 1 1
C= = 0.9 pF C= = 1 pF
2 2f 0 Z 0 2 2f 0 Z 0
Figure 119: Narrowband BALUN

using Lumped Components
Figure 120: S-Parameter Setup to

simulate the response of BALUN

RF BALUN Response
Plot the response of RF BALUN as shown below. Figure shows that the designed BALUN is matched at all the three ports, generates differential
signal at the output with good gain and phase balance. Repeat the same for LO BALUN. Create RF and LO BALUN Components.
Figure 121: S-Parameter response of the RF BALUN

Gilbert Cell RF & LO Input Interface
Mixer input is capacitive while BALUN needs 50Ω termination. This is implemented as shown in the figure at BALUN output. Notice the RF Common Mode
Voltage applied to the output. Similarly LO Common Mode Voltage is applied to the LO devices.
Figure 122: RF interface and Common Mode Voltage Bias
RF Common Mode Voltage = 1.55V. Output is loaded with gate-to-source capacitance of

the RF Source Coupled Pair. The result is as calculated.
Figure 123: RF Input to Mixer

FET Gilbert Cell Mixer Design Equations
Tutorial 9: FET Gilbert Cell Mixer Design as per specifications
Gilbert Cell Design for Large Input Range
Design Assumptions
The design trades-off conversion gain for linear input range and large
output voltage swing.
Vdd = 3.6V
Pdiss = 9mW
 nCox = 180 10−6 A V 2
 p Cox = 90 10−6 A V 2
K rdsn = 3 107 V m
K rdsp = 1.7 107 V m
Tail Current & Tail Device Design

Pdiss 9 10−3
I tail = = = 2.5mA
Figure 124: FET Gilbert Cell Vdd 3.6
Vov 3 = 5% of Vdd = 0.18V
5 10−3
(W L )7 = 2 I bias
= = 857
 nCoxVov2 3 180 10−6  (0.18)2
L7 = 0.5m W7 = 428.6m

Gilbert Cell Design for Large Input Range
RF Transistor Sizing Load Resistor Sizing

vx = 1 Assuming that output can swing by 1V across the load
vx 1 resistor. The quiescent voltage at the output should be at
Vov 2 = = = 0.7071V least
2 2
Voq = Vdd − 1 = 2.6V
(W L )1, 2 = 2(I tail 22 ) = 2  2.5 10−6 = 28
−3
Providing 10% of DC Supply as head room

 nCoxVov 2 180 10
Voq = 2.6 − 0.36 = 2.24V
L1, 2 = 0.5m
Assuming ¼ the tail current causes 1 V swing
W1, 2 = 14m Thus-
 nCox  W  Rd = 4 I tail = 1.6K

k2 =   = 0.0025 A V
2
2 L Conversion Gain, Input Common Mode Voltages

LO Transistor Sizing
k 2 I tail Rd
vy = 1 Gc = = 1 = 0dB
2 2
vy 1
Vov1 = = = 0.7071V VCMLO = Voq − 2Vov1 + Vov1 + Vt = 2.6V
2 2
VCMRF = Vov3 + Vov 2 + Vt = 1.55V
(W L )1, 2 = 2(I tail 42 ) = 2.5 10 −6 = 14
−3
 nCoxVov 2 180 10

L1, 2 = 0.5m
W1, 2 = 7 m
 nCox  W 
k2 =   = 0.00125 A V
2
2  
L

Gilbert Cell Mixer Design & Simulations
Exercise 7:
Step by step procedure to design & simulate a Gilbert Cell
Gilbert Cell Core- RF Trans-linear Cell
Set-up DC Simulations to simulate RF Trans-linear Cell response to the input voltage. Response shows input voltage range to be 1V peak-to-peak. Similar
response is expected from LO Trans-linear Cells.
Figure 125: DC Simulation of RF Trans-linear Cell

Gilbert Cell Mixer Core
With the help of the instructor put together the following circuit for Gilbert Cell Core and perform HB Simulations. Optimize the performance of the mixer core
V_DC sigehp_pbdtres
Vdc = 3.6 V sigehp_pbdtres r= 1.6 KOhm
Vo1 r= 1.6 KOhm Vo2
0.4 pf 0.1 Ohm 0.1 Ohm 0.4 pf
LO_Pwr =7.6
RF_Pwr =7.6 50 Ohm
RFfreq = 2.45 GHz V_DC sigehp_nfetx sigehp_nfetx sigehp_nfetx sigehp_nfetx
LOfreq = 2.10 GHz Vdc = VCMLO V wp = 14 um wp = 14 um wp = 14 um wp = 14 um
l = 0.5 um l = 0.5 um l = 0.5 um l = 0.5 um
VCMRF = 1.55 V nf = 1 nf = 1 nf = 1 nf = 1
VCMLO = 2.6 V m=1 m=1 m=1 m=1
P_1Tone
Z = 50 Ohm BALUNComp_LO
P = polar(dbmtow(LO_Pwr),0)
Freq = LOfreq 50 Ohm 2 nH
2 nH
50 Ohm
V_DC sigehp_nfetx
Vdc = VCMLO V wp = 6 um
I_DC l = 0.5 um
V_DC Idc = 320 uA nf = 2
Vrf m=1 Freq[1] = RFfreq
Vdc = VCMRF V
Freq[2] = LOfreq
Order[1] = 13
P_1Tone Order[2] = 13
Z = 50 Ohm BALUNComp_RF
P = polar(dbmtow(RF_Pwr),0)
Freq = RFfreq sigehp_nfetx sigehp_nfetx
wp = 19 um wp = 20 um 4 pf
l = 0.5 um l = 0.5 um
V_DC 50 Ohm nf = 2 nf = 19
Vdc = VCMRF V m=1 m=1
Figure 126: Gilbert Cell Mixer Core in ADS

HB Controller Settings
Set the HB Controller for Noise using

the options under “Noise” Tab as
shown in the figure. Under Noise Tab
check “Nonlinear noise” option. Click
“Noise (1)” and “Noise (2)” to set the
noise simulation frequency and node
names. Hit Simulate.
Change the data set name. Sweep

“RF_Pwr” in HB Controller. Simulate.
Figure 127: HB Controller settings for

Noise Simulations

Gilbert Cell Mixer Performance
Refer to the instructor for details
Sweep the RF Power and plot the following characteristics of the designed Gilbert Cell.
7 dB
Figure 128: HB Simulation Results of the Optimized Gilbert Cell Mixer

Introduction to Quadrature Mixer
Tutorial 10: Operation of Quadrature Mixer & its sub-circuits
Quadrature Mixer Operation
Signal Flow through a Quadrature Mixer
2
 (
Vout1 = ARF Cos  RF t + RF − 90 ) VIF1
VRF = ARF Cos(RF t + RF ) ( )
LPF
+ ALOCos  LOt + LO − 180 
VLO = ALOCos(LOt + LO ) (

Vout 2 = ALOCos  LOt + LO − 90 )
  2
 (
+ ARF Cos  RF t + RF − 180 ) LPF
VIF 2
Figure 129: Equation Based Modeling of Quadrature Mixer
Signal at the output of a Quadrature Mixer

Balanced Differential Output
ARF + ALO + ARF ALO Sin( IF t + RF − LO )

1 1
VIF1 =
2 2
2 2
The baseband signal around DC is a common mode input to the
= ARF + ALO − ARF ALO Sin( IF t + RF − LO )
1 2 1 2 subsequent differential stages. Hence, it does not show up at the
VIF 2
2 2 differential output.

Quadrature Mixer Sub-Circuits
Bipolar Vcc
Mixer CMOS Vcc
3
90˚ Hybrid 1
2
50 Ω λ/4 Transmission Line 7
IF1
RF 4 6
36 Ω λ/4 Transmission Line
5 4
4.7-5.4 GHz Bias De-Coupling 2
IF2
LO 6
200-700 MHz Bias De-Coupling 3
1 5 3
4.7 GHz Reflection Stub 4 2
4.7-5.4 GHz Input Match 5 Figure 130: Mixer Sub-circuits
Quadrature Mixer is suitable for receivers as it has a very good RF-to-LO Isolation. The mixer can
200-700 MHz Output Match 6 be implemented using two transistors and few SMT components on a RF board. Various sub-
circuits of the mixer are shown in the figure and listed on left. We will design these sub circuits.
Then we will integrate them to design the mixer. Finally we will perform across frequency and
across power simulations of the final mixer.
Bandgap/PTAT/CTAT Bias 7

Circuit Concepts
Dual Gate FETs have been used in the past for mixers at high frequencies. Issue with such mixers is RF-to-LO isolation. Leakage of RF into Local
Oscillator affects Spectral Purity of the Mixer and degrades its IF output in terms of linearity. Leakage of LO to RF can reradiate back into space through
the antenna.
To avoid these effects, a 90˚ Hybrid is used at the input of the Mixer. As proposed in Principle of operation, 90˚ & 180˚ delays are expected at the ports
2 and 3, respectively for RF while same is expected for LO at the ports 3 and 2, respectively. Isolation is expected between ports 1 & 4.
CMOS Vcc We design 90˚ Hybrid at the input of the mixer

Bipolar Vcc operating at 5.1 GHz. 5.1 GHz is the center between
3 LO and RF.
2
7
IF1
RF 4 6
1 2
5 4
4 3 IF2
LO 6
1 5 3
Figure 131: 90˚ Hybrid at the input of the Mixer

Circuit Concepts
Input matching to the bipolar devices should be a broadband matching covering complete frequency band from 4.7 GHz to 5.4 GHz.
Input planes, as shown in the figure, should be matched at RF band and fully miss-matched at IF band. Series Capacitors miss-match at IF band and
couple at RF band.
Matching Planes
CMOS Vcc
Bipolar Vcc
3
2
7
IF1
RF 4 6
5 4
IF2
LO 6
1 5 3
Figure 132: Input Match to the bipolar devices

Circuit Concepts
Output match to the bipolar devices has large bandwidth. It has to be a low pass circuit to reject the higher order mix components. Output Match also has to
reflect 4.7 – 5.4 GHz band by creating a short. Open Circuited Stub marked as 4 in the figure does the same.
Output Match, marked 6 in the figure, can be a single pole match and still be broadband due to low parasitics of the bipolar devices.
CMOS Vcc
Bipolar Vcc
3
2
7
IF1
RF 4 6
5 4
IF2
LO 6
1 5 3
Figure 133: Output Match to the bipolar devices

Circuit Concepts
4.7 – 5.4 GHz Bias Decoupling, shown as 2, is a broadband bias decoupling. Large 0402 SMT Inductor and small 0402 capacitor can be used to achieve
broadband bias de-coupling on the board. We instead use a 0402 SMT resistor and a 0402 by-pass capacitor for broadband bias decoupling. Trance of
lines and bondwires are modeled for accuracy.
200 – 700 MHz Bias Decoupling, shown as 3, is a broadband bias decoupling. Large 0402 SMT Components on board are used to achieve bias
decoupling.
CMOS Vcc
Bipolar Vcc
3
2
7
IF1
RF 4 6
0.2-0.7 GHz Bias De-Coupling
5 4
4.7-5.4 GHz Bias De-Coupling IF2

LO 6
1 5 3
Figure 134: 4.7-5.4 GHz and 200-700 MHz Bias De-coupling Circuits

Ideal Hybrid Design
λ/4 Electrical Length Use microstrip line elements in Genesys to design a Hybrid as shown in figure.
1 2
Z 0 = 50 2   36  Establishing Impedances Establishing Power
λ/4 Electrical Length

Consider for analysis that power is put in port 1 and 4 as
Even and Odd Modes with amplitudes +-1/2. Figures 16 0 j 1 0
Z 0 = 50  Z 0 = 50  and 17 show circuit for Even and Odd Modes. The  
1  j 0 0 1
superimposition will show that power is put only in port 1 S  = −
while port 4 is matched to characteristic impedance. For 2 1 0 0 j 
simplicity all impedances and terminations are  
4 3
normalized.
0 1 j 0
Z 0 = 50 2   36 
Figure 135: Ideal 90˚Hybrid Design
1+ j λ/4 1 1− j λ/4 1
|| − j = 1 1 || − j = || j = 1 1 || j =
2 1+ j 2 1− j
1 2 1 2
+1/2 +1/2
1 λ/8 1 λ/8 1
1 1 1
1 1 1 1
+1/2 1 2 -1/2 1 2
1 1
Figure 136: Even Mode Impedances Figure 137: Odd Mode Impedances

Mixer Specifications
Design a Quadrature Mixer on FR4 board using SiGe HBT devices and SMT Components with following specifications
• RF Frequency Band 4.9-5.4 GHz
• LO Frequency 4.7 GHz
• Conversion Gain >0 dB
• Output Phase Imbalance <3 degrees
• Output Gain Imbalance <0.5 dB
• RF Input Match <-10 dB
• LO Match <-10 dB

Input Hybrid of Quadrature Mixer
Exercise 8a:
Design of the Input Hybrid Stage of the Quadrature Mixer
ADS Schematic for Ideal Hybrid Simulation
Create ADS Schematic for Ideal Hybrid simulation as shown in the figure. Perform S-Parameter Simulations to determine the performance of the design.
Figure 138: ADS Schematic for 90˚ Hybrid

Simulation Response of Ideal Hybrid
Plot S(1,4) & S(4,1) i.e. the RF & LO Isolation. Plot S(2,1) & S(3,1) Magnitude in dB. This represents power division in half (-3dB). Plot Phase[S(3,1)]-
Phase[S(2,1)]. This represents quadrature output.
Figure 139: S-Parameter Response of the designed 90˚ Hybrid

Input / Output Bias Decoupling for Active Device
Exercise 8b & 8c:
RF Decoupling design for active device at its input and output
Bias Decoupling
4.7-5.4 GHz bias decoupling is implemented using a 0402 SMT 4 KΩ

resistor and a bypass capacitor. 200-700 MHz decoupling is implemented
using 0402 SMT components on the board. We use Johanson capacitors
and Coilcraft inductors.
Use the modeling techniques illustrated earlier to model SMT capacitors

and inductors.
Generate SPICE Models as
shown in the figure. Setup IF Bias
De-coupling circuit and perform S-
Parameter Simulations from DC to
700 MHz.
Figure 140: IF Bias Decoupling Circuit

IF Bias Decoupling Response
Plot S21 on a rectangular graph and S11 and S22 on a Smith Chart. Create a symbol for IF Bias Decoupling Circuit for use in further simulation. S21
shows good bias de-coupling for the IF band from 200 MHz to 700 MHz
Figure 141: IF Bias Decoupling Circuit Response

Output Short Circuited Stub Design & Simulations
Use a quarter wave line as open circuited stub. To terminate the end effects a large resistor is chosen for termination on open circuit side. Setup S-
Parameter Simulations as shown in the figure and plot the response
Figure 142: Open Circuit Stub used at the output of the mixer
Figure 143: Response of the OC Stub

Active Device Matching
Exercise 8d:
Matching of the Active Device at its input and output
Mixer Active Circuit Design
Setup the circuit as shown in the figure using SiGe HBT, pre-designed sub-circuits and lumbered components. Match the input at 4.7-5.4 GHz using
a high pass match and match the output at 200-700 MHz using a low pass match. Add Stability circle components. Perform S-Parameter Simulations
followed by input and output tuning to 50 Ω. Use High Frequency Feedbacks to stabilize the circuit across the frequency band.
SC Stub
Bias Decoupling
High Freq.
Feedback IF Bias Decoupling
Substrate
Contact
Output Match
Source
Input Match Degeneration
Figure 144: Mixer active circuit matching (small signal)

Active Circuit Small Signal Matching
Plot the S-Parameters of the tuned active circuit as shown in the figure. Notice that the input is tuned to RF while output is tuned to IF.
Figure 145: Small Signal Tuned Active Circuit for the Mixer

Mixer Integration, Optimization, & Simulations
Tutorial 11: Mixer is integrated and optimized for performance
Mixer Circuit
Interface two active mixer circuits to the output of the hybrid as shown in the figure. Enable tuning on matching components, feedback and bias.
Generate component of the mixer shown in the figure.
VoutPlus
RFin
LOin
VoutMinus
Tuned Circuit
Components & Bias
Figure 146: Quadrature Mixer Cell

Mixer Simulations
We will perform across frequency HB Simulations of the Mixer at a fixed input RF Power of -5
Figure 147: HB Controller settings for mixer simulations dBm. LO Power is fixed at 1.5 dBm. All these parameters can be optimized. We will observe
across band performance of the mixer in terms of Output Power, Conversion Gain, Gain
Imbalance and Phase Imbalance. Our frequency band of interest is 4.9 GHz to 5.4 GHz.
We will perform across RF

Power Simulation of the
mixer and determine its -1
dB Compression Point.
Gain Imbalance and

Phase Imbalance are also
functions of RF power. For
across power simulation
we use mid-band RF
frequency 5.15 GHz

Mixer Characterization
Exercise 9:
Across frequency & across RF power simulation of mixer
Mixer Simulations Across RF Frequency & Tuning
Set up the HB simulations for the mixer as shown in the figure. Add the measurement equations to measure power of mix components. For
optimization of Conversion Gain and Output Phase imbalance, use Tune. Reduce device sizes and supply current to optimize Conversion Gain &
output phase balance. Refer to the instructor for details.
Figure 148: HB Simulation Setup to tune the performance of mixer across frequency

Optimized Mixer Performance Across RF Frequency
Plot Conversion Gain, Differential Output Power, Phase Imbalance and Gain Imbalance across the RF frequency. Refer to the instructor for further details.
Figure 149: Across Frequency Performance of the Quadrature Mixer

Mixer Simulations Across RF Power
Make the changes to the sweep variables as shown below to simulate the performance of the mixer across the RF Power. Refer to the instructor for
further details.
Figure 150: HB Simulation Setup to simulate performance of the Quadrature Mixer across RF Power

Mixer Performance Across RF Power
Plot Conversion Gain, Differential Output Power, Phase Imbalance and Gain Imbalance across the RF Power. Refer to the instructor for further details.
Figure 151: Across RF Power Performance of the Quadrature Mixer

Introduction to Power Amplifiers
Tutorial 12: Power Amplifiers, their electrical characteristics, applications & types
Introduction to Power Amplifiers
Tutorial Topics:
a) Concept of Power Amplification

b) Classes of Power Amplifiers (PA) and Comparison
c) PA Performance Parameters
We will discuss in detail the requirement of Power Amplification in a wireless communication system, examples of wireless communication
systems, various classes of power amplifiers, their distinguishing features and applications, various performance parameters of a power amplifier
and their significance in the design.
Power Amplifiers are part of Radio Front-Ends. Power Amplifiers can be Monolithic Microwave Integrated Circuits (MMIC) or Microwave
Integrated Circuits (MIC).
MMIC PAs are 50Ω matched circuits on a single die. MMIC PAs can be packaged in generic plastic or ceramic packages, need few off-chip or no
off-chip components and can be integrated easily on board.
MIC PAs are tuned on a RF board or a ceramic carrier/ laminate or a custom module laminate.
Some distinguishing features of a PA are-
a) Highest power consuming circuits in a radio
b) Occupy largest area on die or on board
c) Provide highest power at the output with modest gains and hence reverse isolation on board/ package is important
d) Dissipate largest amount of heat and hence design for thermal stability is important

Concept of Power Amplification
Examples Long haul
Downlink
Uplink
Figure 152: Example of Wireless Communication System (Mobile Phones)
Various examples of wireless communication systems are-
• Mobile Communication System- GSM, PCS, DCS, Cellular, WCDMA (UMTS)

• Wireless LAN- WiFi (IEEE 802.11a/b/g)
• Wireless MAN- WiMAX (IEEE 802.16 a /b /c /d /e), LMDS
• Personal Communications- Bluetooth, WUSB, Fire Wire
• Industrial Communications- ZigBee (IEEE 802.15.4)
• Satellite Communications
• Extra Terrestrial Communications

Power Amplification in Full Duplex Systems
Types of Full Duplex Communication

Orange represents transmit frequency
Blue represents receive frequency
Power Amplifier Power Amplifier
Antenna
Antenna
Circulator Circulator
Low Noise Amplifier Low Noise Amplifier
Figure 153: Frequency Division Duplex
Power Amplifier
Power Amplifier
Antenna Antenna
BPF BPF
Switch Switch

Blue represents transmit & receive frequency
Figure 154: Time Division Duplex

PA in FDD System
What is expected of a PA in a Frequency Division Duplex System?

Orange represents transmit frequency
Blue represents receive frequency
Power Amplifier Power Amplifier
Antenna
Antenna
Circulator Circulator
Figure 155: Frequency Division Duplex
• PA is continuously on unless in sleep mode

• High junction temperatures for devices
• VSWR constraints not stringent
• Expected reverse isolation high
• Turn on and off times not important
• Performance droop not expected during performance
• Receive band emissions are expected to be low
• Point to point link requires in-between transmit-receive frequency translation

PA in TDD System
What is expected of a PA in a Time Division Duplex System?
Power Amplifier
Power Amplifier
Antenna Antenna
BPF BPF
Switch Switch

Blue represents transmit & receive frequency
Figure 156: Time Division Duplex
• PA operates in pulsed mode

• Low junction temperatures for the devices
• VSWR constraints stringent
• Expected reverse isolation low
• Turn on and off times important
• Performance droop expected at turn on
• Point to point does not require in-between transmit-receive frequency translation

Output Power & Gain of a PA
What decides gain and peak output power of a PA?
Power Amplifier
Power Amplifier
Antenna Antenna
BPF BPF
Switch Switch
Figure 157: Link Budget and Peak PA Power
Transmission Medium Related Factors
In a line of sight transmission, path length, attenuation, fading and noise are easier to characterize compared to non-line of sight transmission and non-
stationary channels.
Receiver Related Factors
Receiver sensitivity depends on

• System Bandwidth
• Minimum Signal-to-Noise Ratio required at the detector
• Noise Figures of the stages between the receiver antenna and the detector
• Gains and losses of stages between the receiver antenna and the detector

PA Transfer Characteristics
What are Saturated Power Amplifiers and Linear Amplifiers?
Figure shows output power Vs input power of a power amplifier.
Linear Region
P_output (dBm)
At low power levels the output power varies linearly with the input power.
Linear Non Saturated
Non-Linear Region
Linear
Supply voltage and current limit the output power for a given output resistance as the input power
increases. The gain starts dropping in the non-linear region.
P_input (dBm) Saturated Region
Output power becomes constant limited by the DC supply and the output resistance in the
saturated region.
“Saturated Amplifiers” operate in “Saturated Region” while “Linear Amplifiers operate in “Linear
Gain (dB)
Region”
P_input (dBm)
Figure 158: Linear, Non-Linear & Saturated

regions of operation of a PA

PAs for different Modulation Schemes
What are the various modulation schemes used in communication systems?
Most of the communication systems are digital as digital data can be compressed, correction codes can be applied and multiple access can be performed in
a number of ways. Various modulation schemes are-
As visible from the figures, FSK and QPSK are constant envelope modulation schemes while QAM 16 and
higher are non-constant envelope schemes if transmitted as it is. In case QAM is broken down to I and Q
signals, the transmission is non constant envelope.
Constant envelope signals are not bandwidth efficient but can be amplified using high efficiency saturated
amplifiers. Non-constant envelope signals are bandwidth efficient but have to be amplified using low efficiency
linear amplifiers.
Figure 159: Frequency Shit Keying
01 00
11 10
Figure 160: Quadrature Phase Shift Keying Figure 161: QAM 16

Power Added Efficiency & Back-off
What do the terms “Power Added Efficiency” and “Back off” mean?
P_output (dBm)
Pout
P. A.E =
Pin + PDC
Linear Non Saturated
Linear
Figures shows that PAE goes up with the input power. PAE reaches its peak as the amplifier
compresses. To operate amplifier at its highest efficiency it must be operated in non-linear or
saturated region. For non-constant envelope signals amplifier has to be operated in linear region
such that the peak power is just in non-linear region. Figure below shows non-constant envelope
P_input (dBm)
signal. For peak efficiency the amplifier is operated backed off in output power by the crest
factor.
Peak Power
PAE (%)
Crest Factor
Average Power
P_input (dBm)
Figure 162: Linear, Non-Linear & Saturated

regions of operation of a PA Figure 163: Non-Constant Envelope Signal

Classes of PA & Comparison
Power Amplifier
Class F
• Odd order peaking

Class A Class E resonators are used at
odd harmonics
• Total conduction Class B • Optimum output
angle is 360° Push-pull Class C Class D power at 50% Duty • Ideal efficiency of 100%
cycle is possible
• Ideal efficiency of
25% is possible • Total conduction • Total conduction • Push-Pull Class F • Ideal efficiency of • DUF of 0.159 is
angle is 360° angle is less than 100% is possible possible
• DUF of 0.125 is 180° • Ideal efficiency of
possible • Ideal efficiency of 100% is possible • DUF of 0.0981 is
78.4% is possible • Ideal efficiency of possible
• Used for linear 89.6% at 120° • DUF of 0.318 is
applications • DUF of 0.125 is conduction possible
possible
• DUF of 0.0981 is at
• Used for linear 120° conduction
applications
Figure 164: Power Amplifier Classes

PA Performance Parameters
Gain
MTBF/MTTF Bandwidth
Noise/Receive
Linearity
Band Noise
Switch-off Efficiency
Isolation
Supply Voltage Power

Cost/Size
Range Amplifier
Number of
components Modulation Scheme
Ruggedness Quiescent Current
Standby Current Harmonic Distortion

Yield
Figure 165: Power Amplifier Performance Parameters
Power Amplifier performance parameters decide amplifier class and circuit topology. Specifications for various performance parameters have to be met
across operating condition extremes like supply voltage and ambient temperature range and across process corners. The specifications have to be met on
volume with a certain yield.

Small Signal & Large Signal
What do the terms “Small Signal” and “Large Signal” mean?
Active devices like transistors or diodes may be biased to some DC Operating Point for optimum performance. As the signal level goes up there is clipping
of the signal at saturation or cut-off regions. This changes the DC operating conditions. At large signal levels a linearized model cannot be used beyond
certain threshold. For BJT and FET devices, threshold input signal voltage is as follows
For BJT
KT
vi  Vt where Vt = is large signal and otherwise is small signal
q
For FET
2 I ds
vi  2VOV where VOV = is large signal and otherwise is small signal
 nCox (W L )
From the equations it is visible that FET can be operated in wider input range as small signal by choosing high bias current and low W/L ratio.

PA Gain and Return Losses
Gain
Gain of Power Amplifier is defined as the ratio of the power at the output ( Pout ) to power at
the input ( Pin ).
If both the input and output matches are conjugate matches for maximum power transfer,
the gain is referred to as Available Gain. Power delivered to the load under conjugate match
to power delivered by the source is referred to as Transducer Gain. Ratio of power delivered
to the load to the power delivered by the source is called Power Gain. Power Gain includes
both input and output mismatch losses. Expressed in decibel (dB)
GaindB = 10 log10 (Pout Pin )
Figure 166: Power Amplifier Reflection Coefficients
Return Losses
Ratio of power reflected back into the source to the power incident at the input of a PA is called Input Return Loss. The definition holds true for small as
well as large signals. PA is not bilateral and not reciprocal. Ratio of power reflected from the PA output to the power incident at the output is referred to as
Output Return Loss. Output return loss is always measured small signal for a PA.
Vin− S S 
in = +
= S11 + 12 21 L For Conjugate Match at the output L = 0 & in = S11
Vin 1 − S 22L
−
Vout S S 
out = +
= S 22 + 12 21 S For Conjugate Match at the input S = 0 & out = S 22
Vout 1 − S11S
RLinput = −20 log10 (1 in ) & RLoutput = −20 log10 (1 out )

Nature of Gain & PA Transfer Characteristics
Small Signal Gain
Commonly used Gain is Power Gain. Expressed in Small Signal Scattering Parameters, Power Gain is given by
GP =
(
S 21 1 − L2
2
) For input and output match to characteristic impedance S = L = in = out = 0
(1 − 2
in )(1 − S  )
22 L Power Gain and Available Gain are the same GP _ dB = 20 log10 (S 21 )
Large Signal Gain

Large Signal Gain can be evaluated in same manner as small signal gain, by replacing small
signal reflection coefficient by large signal reflection coefficients at the input.
As the input power increases, DC Supply Current increases. Output power increases linearly
with input power. Limit on DC Current causes Output power to saturate. The Power Gain drops
and is referred to as Gain Compression.
Figure 167: Power Gain and Output Power Vs Input Power Characteristics of PA

PA Losses
PA Active
Losses Device
Losses Vds Ids
Ids
Passive
Losses
Vds t
Figure 168: Losses in PA Figure 169: Source of loss in active devices
Various Losses in a PA are-
• Device Loss due to voltage across the device and current through the device
• Loss due to finite voltage across the device during saturation (BJT)
• Finite resistance of the channel during saturation (on-time) (FET)
• Loss of energy stored in the reactive components
• Resistive losses in reactive components due to finite Quality Factor
• Conductor Losses in Inter-connects
• Dielectric Losses in the substrate
• Radiation Losses from traces

PA Efficiency
Efficiency of Power Amplifier is the ratio of RF power produced at the output to power input to the Power Amplifier.
In case only the DC Supply Power is accounted for as input power, the efficiency is called the drain or collector efficiency
In case the DC Supply Power as well as the input RF Power is accounted for as input power, the efficiency is called Power Added Efficiency (PAE)
In case net RF Power is considered as output power and DC Supply Power is considered as input power, the efficiency is still called PAE but refers to
conversion efficiency of the PA
Drain/Collector Efficiency
Pout
Effdrain / Collector =
PDC
Power Added Efficiency
Pout
PAE =
Pin + PDC
Conversion Efficiency
Pout − Pin
Effconversion =
PDC

PA Linearity and Harmonic Distortion
Power Amplifier output to small signal input in linear region can be represented by S L x(t ) = 1 x(t −  1 )
Power Amplifier output to small signal input in non-linear region can be represented by
S NL x(t ) = 1 x(t −  1 ) +  2 x(t −  2 ) +  3 x(t −  3 ) +  4 x(t −  4 ) + ...

2 3 4
For Small Signal Input x(t −  1 )  x(t −  2 )  x(t −  3 )  ...

2 3
M
Large Signal Input has fundamental and harmonics x(t ) =  A (t )cos
m =1
m m t + m (t )
For Sense of Completion the non linear output of a PA when large signal input is applied to non linear transfer function of a PA, M tone input has 1 to N
order mix components.
For N-order transfer function, the response to M tone large signal input is given by
N n M
S NL x(t ) = 
1 n!
n
 n  m
e sign (m ). j .(m (t − n )+m (t ))
qm !
n =1 2 q =1 m =1

− m A m (t )
qm
For Modulated Signal with modulation component around fundamental and harmonics, the mixing is even more complicated.

PA Spectral Emission and EVM
What is the impact of PA non-linearity on non-linear input signal?

Even order mixing causes out-band components displaced away from the fundamental and can easily be filtered using Band-Pass Filter at the output
Odd order mixing causes in-band and adjacent band components- Inter-modulation and in-modulation components. For simplicity let us consider two tones
and third order mixing as shown in figure below
-f2 -f1 f1 f2
0 1 0 2 +-(2f2-f1)
1 0 2 0 +-(2f1-f2)
1 0 0 2 +-(2f2-f2)
2 f 2 − f1 f2 f1 2 f1 − f 2
0 1 2 0 +-(2f1-f1)
Figure 171: Cross Modulation (Inter-modulation)
Figure 170: Cross Modulation (Inter-modulation) and Co-

modulation (In-modulation or AM-AM/AM-PM)
Figure 172: AM-AM and AM-PM Non-Linearity

High Efficiency Saturated Amplifiers
Switches have voltage and current in

Voltage & Current in quadrature. This results in zero active power at
Quadrature as in switch the output of the switch and zero switch loss.
Vds Ids
In high efficiency amplifiers device acts as a
switch as shown in the figure. To derive power
at the output, the load network provides voltage
and current in phase across the load.
Ids
Energy stored in reactive load components

(inductors & capacitors) should not dissipate to
ground. This is assured by smooth switching.
Parasitic resistances and leakages to ground

Vds t
have to be minimized for high efficiency.
Figure 173: Negligible device loss due to voltage and current in quadrature in the
device in high efficiency amplifiers
Vo
Io
Vds Load t
Network
Vo
I ds Io
R
Figure 174: Switching Power Amplifier Figure 175: Output (Load) Voltage & Current Waveforms

High Linearity Power Amplifiers
Modulates Cosine Carrier
Gain (dB)
Pout (dBm)
Figure 178: Output Constellation
Phase
Gain and Phase response of PA is expected to be flat
for ideal power amplification. In case this is not so the
Pout (dBm) output is in error.
Figure 177: Power Amplifier Output
Gain & Phase Characteristics There is a permissible %Error Vector that is tolerable
Q (t) and yet the symbol is de-modulated correctly. Larger the
Modulates Sine Carrier
number of states, larger the bandwidth and lower the
I (t) supply voltage, lower is the %EVM that is expected.
Junction Temperature variation can cause time

dependent phase and gain variations in TDD System.
t I and Q phase imbalance can skew the constellation.
Figure 176: QAM 16 Modulated Input to a PA

Introduction to Switching Amplifiers
Tutorial 13: High Efficiency Class E Amplifier Operation & Design
Class E Amplifier Topology
Ideal Class E Topology
Ideal Class E Amplifier Topology consists of –
1) DC Supply Voltage and Radio Frequency Choke act as ideal current source
2) An ideal switch
3) A shunt capacitor across the switch
4) A Series Resonant Circuit load with high quality factor
Figure 179: Ideal Class E Topology (Voltage Mode)
Merits of Class E Topology
1) Output capacitance of the device can be included in the shunt capacitor
2) Inter-winding capacitance of RFC can be included in the shunt capacitor
3) Series resistance of the series resonant circuit can be included with the load resistance
4) Lead inductance of the capacitor can be included in series inductance.

Ideal Class E Amplifier Operation
Figure 180: Ideal Class E Current Waveforms Figure 181: Ideal Class E Voltage Waveforms
Ideal RFC and Supply Voltage constitute an ideal DC current source. If a sinusoidal current flows through the load, DC shifted sinusoidal current wave
shown in the left figure flows through parallel combination of Switch and shunt capacitor. Blue colored portion of sine wave flows through the switch and
green colored portion flows through the shunt capacitor. Switch is on during blue portion of the current sine wave and off during the green portion. The
current through the shunt capacitor integrates causing voltage across the shunt capacitor shown in red in the right figure. A high Q Series resonant load
network filters voltage to the load at switching (fundamental) frequency. The only dissipating element in the circuit is load. Switch on/off instants are chosen
in such a way that at turn on voltage across the capacitor and current through it are zero. This avoids shorting of energy stored in shunt capacitor. Voltage
across the switch and current through it are in quadrature. On-time resistance of the switch is zero. This causes zero dissipation in the switch. Ideal 100%
Drain Efficiency is achieved.

Exact Class E Amplifier Design
Figure shows Class E Amplifier in two states- On-State is on left and Off-State
is on right. During On-State Shunt capacitor is shorted out. The voltage loop at
the output is resonant at frequency lower than the switching frequency.
1.8
A2
1.6 A1
1.4
A2
A1-blue,A2-green
1.2
Figure 182: Circuit in On and Off States
1 1
1 02 = 2f 02 =
01 = 2f 01 = LCC1
LC
C + C1 0.8
L
Q= A1
R
0.6
f  f 
A1 = 01 = 01 A2 = 02 = 02
f  f  0.4
0 2 4 6 8 10 12 14 16 18 20
During Off-State Shunt capacitor is in circuit. The voltage loop at the Q1
output is resonant at frequency higher than the switching frequency. Figure 183: On/Off State Resonant Frequencies Vs Q

Exact Class E Amplifier Design Equations
  2  
   A   
sin  1 −  1

 2Q A 
 A1 
2
  −A1Q(1− D )   1
 1 2   
2 (1 − D )  A cos 2  A
 − h1 e 1
− 1 + 1
2
 A2    A2 2Q1 A2  2Q1 A2 
2
   
 
   
 2  2 
 1 −  A1 
   A1
cos 2 1 − 

 
  2Q A  −A1 (1− D )  
 A sin 

  1 2  
 1  2Q1 A2  
+ h2  − e + =0
Q1 2
 A2  2Q1 A2 2 A2 
  
  
  
2  −A1 (1− D ) 
 A1   
  − (h1 cos 2 − h2 sin  2 )e  Q1 
=0
 A2 
where 1 and 2, h1 and h2 are intermediate variables from
Marian K. Kazimierczuk and Krzysztof Puczko, “Exact Analysis Of Class E Tuned Power Amplifier At Any Q and Switch Duty Cycle,” IEEE
Transactions On Circuits And Systems, vol. CAS-34, No.2, pp. 149-159, February 1987.
Solving the two simultaneous equations for two unknowns using Numerical Methods and desired load network Q, the three circuit unknowns C1, L, and C
can be computed for given load resistance R and Switch-On Duty Cycle D.

NatTel Algorithm for Class E Design
Figure 184: Class E Design using NatTel Circuit Designer

Objective
We will design ideal Class E Amplifiers at various load network quality factors (Q) and switch on duty cycles (D).
Design Specifications
f 0 = 5 GHz
R = 50 
Vdd = 1V
Design Q D Design Q D
1 8 35% 6 4 35%
2 8 45% 7 15 35%
3 8 50% 8 4 50%
4 8 55% 9 15 50%
5 8 65%
10 4 65%
Figure 185: Variation of Duty Cycles
11 15 65%
Figure 186: Variation of Load Network Quality Factor
We have used different Switch On Duty Cycles for same value of Q to see its impact on circuit component values in the left table. In the right table we
have used low, mid and high value Q for low, mid and high value duty cycle. We will use NatTel Circuit Designer for this purpose and list the circuit
components.

Introduction to Class E Designer Form
Input Fields have type and range

validation; Units are specified
“Calculate” button to calculate
components and plot outputs
Warnings are issued here. Use

Load Resistance, Device Utilization,
“Clear Warning” to move ahead
Current Drawn, & Device Stress
Figure 187: Input Parameters Figure 188: Class E Performance Parameters, Warnings Area, Clear Buttons & Calculate Button

Introduction to Class E Designer Form
Figure shows the output voltage and current waveforms from
various Class E designs in time and frequency along with
spectral power distribution. The software allows you to choose
the number of harmonics you would like to view at various
supply voltages
Figure 189: Over-laid Plots for Design Comparison

Class E Amplifier Design
Freq=5 GHz
Design Q D C1 C L V_peak I_peak Idc
R=50 Ohm
1 8 35% 0.156 pf 0.111 pf 12.73 nH 2.788 V 14.41 mA 3.298 mA Vcc=1 V
2 8 45% 0.146 pf 0.097 pf 12.73 nH 3.275 V 24.29 mA 7.738 mA
3 8 50% 0.127 pf 0.093 pf 12.73 nH 3.595 V 30. 37 mA 10.838 mA
4 8 55% 0.105 pf 0.091 pf 12.73 nH 3.987 V 37.10 mA 14.492 mA
5 8 65% 0.057 pf 0.086 pf 12.73 nH 5.115 V 51.90 mA 23.085 mA
6 4 35% 0.149 pf 0.445 pf 6.366 nH 2.825 V 13.09 mA 2.778 mA
7 15 35% 0.159 pf 0.049 pf 23.870 nH 2.771 V 15.18 mA 3.538 mA
8 4 50% 0.135 pf 0.238 pf 6.366 nH 3.631 V 27.51 mA 9.962 mA
9 15 50% 0.123 pf 0.046 pf 23.870 nH 3.579 V 31.64 mA 11.187 mA
10 4 65% 0.069 pf 0.191 pf 6.366 nH 5.152 V 50.34 mA 23.155 mA

11 15 65% 0.051 pf 0.044 pf 23.870 nH 5.098 V 52.38 mA 22.925 mA
Figure 190: Class E Amplifier Designs

Class E Power Amplifier Design & Simulations
Exercise 10:
Class E Power Amplifier Simulations using Harmonic Balance
Ideal Class E Amplifier Circuit in ADS
We will set up the circuit in ADS for simulating an ideal Class E amplifier with following specifications and design.
8 4 50% 0.135 pf 0.238 pf 6.366 nH 3.631 V 27.51 mA 9.962 mA
Figure 191: Class E Amplifier Circuit Components for simulation in ADS
We will put together the ideal Class E Circuit using

ideal switch and lumped component components.
We can perform transient simulations or harmonic

balance simulations to plot the waveforms.
Component Values may need little tuning as formulas

are correct for high value of Q and we are choosing
low Q load network.
Figure 192: Class E Amplifier Circuit Topology (Note that jX is not circuit
component, it is residual reactance at switching frequency)

Class E Circuit & HB Simulations
Setup the Class E Circuit using SPDT Dynamic Switch from “System-Switch & Algorithmic” palette. The design is accurate to within 10% at low Q of the
load network. Refer to the instructor for “Tuning a Class E Amplifier”
Figure 193: Class E Amplifier Circuit and HB Simulation Setup

Class E Simulations
Reason for low
device loss
Low loss smooth

Switching
Low Harmonic content

in the output
Figure 194: Class E Amplifier Circuit Waveforms

Introduction to Two Stage Class AB Amplifier
Tutorial 14: Design Flow for a Class AB Two Stage Power Amplifier for Linear Applications
Design Flow
Two stage Cascaded Class AB Linear Power Amplifier has two gain stages- the Driver stage and the Power Stage. Driver Stage provides most of the Gain
while the power stage provide large power at lower gain. Driver and Power Stages are separately sized, biased, stabilized and tuned for best match, gain
and output power. The two stages are cascaded by combining output match of driver stage and input match of power stage.
The designed Two Stage Power Amplifier is characterized for Gain, Output Power and Linearity. A power Amplifier may be optimized for performance
though load and source pull.
Device Sizing
Driver Stage Design Power Stage Design Power stage is sized to carry certain current for chosen DC Voltage to deliver the
output power. Driver stage should be sized Power Stage Gain times smaller
Size the Driver Stage Size the Power Stage Power Stage. Usually a larger driver is chosen for better linearity.
RF & DC De-coupling
RF De-coupling at input and output of a transistor is done to avoid DC supply
Create RF De-coupling to DC from loading the transistor. A LC-tank circuit, a RF Choke or a resistor can be
Create RF De-coupling to DC
& DC De-coupling to RF used for RF De-coupling. DC De-coupling using series capacitors is done to
& DC De-coupling to RF
avoid DC current from flowing into load or ground.
Biasing, Stability & Stabilization
Transistors are biased to carry certain quiescent current. Driver is biased as deep
Bias the device & perform Bias the device & perform class AB for gain and Power Stage is biased for output power, linearity and
stability analysis stability analysis efficiency as class B. Thus Gain and Phase Flatness is achieved.
Whole of the Smith Chart at all frequencies is assured to be stable termination at
input and output of Driver and Power Stage through feedback techniques.
Stabilize the device & Stabilize the device & Small Signal and Large Signal Tune
perform small signal tune perform small signal tune Transistors are matched to 50 Ω at input and output for small signal and under
compression. LC matches are used for this purpose.
Inter-Stage Design & simplification
Perform Large Signal Tune. Perform Large Signal Tune. Match 50 Ω tuned stages can be cascaded without RF reflection. Output match of Driver
Match the stage for Gain the stage for Peak linear power & input match of Power Stage can be combined and simplified.
Combine O/P Match of Driver & Simplify Inter-

PA for Characterization
I/P Match of Power Stage stage Match
Figure 195: Design Flow for a typical two stage amplifier design

Self Heating
HBT is most commonly used power device due to high power densities it can handle. Silicon and Silicon Germanium HBTs have positive or flat
thermal coefficient of Forward Current Gain. Gallium Arsenide HBTs have negative thermal coefficient of Forward Current Gain. This is visible in
Output Characteristics of a device. It is referred to as self-heating. Self heating is worse for Gallium Arsenide HBTs as compared to Silicon or Silicon
Germanium devices due to poor thermal conductivity of Gallium Arsenide substrate.
Ic
Ic
Vce Vce
Figure 196: Output Characteristics of typical Silicon or Figure 197: Output Characteristics of typical Gallium
Silicon Germanium HBT Arsenide HBT

Thermal Instabilities
Thermal Instabilities manifest in the form of “Emitter Collapse” visible in DC as well as RF Performance of large Silicon, Silicon Germanium and Indium
Phosphide power HBTs.
Hot Finger
Ic
Cold
Finger
Vce Temperature (K)
Figure 198: Output Characteristics of typical Silicon or Silicon Figure 199: Source of “Emitter Collapse” of HBT
Germanium Power HBT

Physically Large Vs Shrunk HBTs
In case the device fingers are closely spaced, thermal coupling between the fingers is more severe leading to higher junction temperature.
Silicon and Silicon Germanium HBTs are grounded using very thin
conductive epoxy that is poor thermal conductor. There are no
substrate vias and there is no back plating. To improve electrical as
well as thermal grounding number of ground pads are to be used.
Adding substrate contacts helps thermal design.
In case a multilayer board is used, a large ground plane under the

device helps dissipate the heat.
Device Layout should be sufficiently spread out to minimize thermal

coupling between device fingers.
Figure 200: Physically spaced Vs shrunk fingers

Ballasting
One way to avoid thermal instability is to insert a resistor in series with Base-Emitter junction, either in base or in emitter, for all the devices. The
resistors are scaled such that for hotter fingers they are higher and for colder fingers they are lower in value. This causes higher Vbe required for
hotter fingers for same collector current as compared to colder fingers.
Merit of emitter ballast is that it is easier to incorporate in layout. The demerits are-
a) It causes lower gain and gain droops across the frequency band
b) It causes increased thermal capacitance via emitter
Merit of base ballast are-

a) It does not affect the gain much. Gain is flat across the frequency band.
b) It does not hurt the heat flow through the emitter
The demerit is that the required gate voltage is higher
Figure 201: Base Ballast (left) and Emitter Ballast (right)

Design Objective
We will design two stage power amplifier tuned to 50 Ohm across 1.92-1.98 GHz band.
Design Specifications
f 0 = 1.92 − 1.98 GHz

R = 50 
Vdd = 4.5 V
S11  −10dB
S 22  −10dB
S 21  30dB
Iq  90mA
Pout @ −1dB  24dBm
ACPR  −33dBc
ACLR  −50dBc
Note
For this design we will use “DemoKit_NonLinear_v1”. Install the design kit provided on the Training CD

Bias De-coupling Circuit
Exercise 11a:
Design of an On-board Bias De-coupling (RF De-coupling) using a tank circuit
Bias Decoupling Design
Figure shows Bias Decoupling design on 4 layer FR4 board using SMT 0402 Components.
Follow the instructor for step by step design. Use the simulated dataset file
“BiasDeCoupPassive_mom.ds” from the same project on training CD to reduce simulation
time.
Port 2
195 mil
Ground
Reference
Port
115 mil
Ground
Reference
Port 1 Port
Figure 203: Bias De-coupling
Figure 202: Bias De-Coupling Circuit Layout Circuit Simulation

Bias Decoupling Response
Plot the S-Parameter Simulation Results. Notice the de-coupling in the required band (1.92 GHz to 1.98 GHz).
Figure 204: Bias De-coupling Circuit Simulation Response

Device Biasing, Stabilization & Tuning
Exercise 11b, 11c, 11d, 12
Device Sizing & DC Characteristics
We will use a “DK-HEMT” device for our design. Once the gate voltage has been fixed, the drain current is fixed. Hence the PA is a voltage gain
stage.
Higher the DC Supply Voltage and lower the output impedance higher the power delivered to the output. Size only decides the output impedance of
the FET. In our case, lets choose a DK_HEMT with 8 fingers each 100 um wide. Setup the DC Simulation as shown in the figure.
On-board
Gate Bias Bias Decoupling
Decoupling
High Frequency
Feedback
High Frequency
SPICE Model of Coupling Cap Feedback
Substrate Via for the FET

Figure 205: DC Simulation Setup to determine device bias point

Power Stage Biasing and Stability
Plot the device DC Characteristics as shown in the figure. Choose the bias current to be 45 mA and determine the gate voltage using a marker. Save
the design as “PwrStgStab.dsn”. Replace DC Simulation Controller by S-Parameter Simulation Controller. Set the variables Vdd=4.5V and Vgg=-0.55
V
Figure 206: DC Characteristics of the power device
Use Source and Load Stability Circle components for viewing

small signal stability of the device
Stability Circle Components from

Simulation-S-Para palette
Figure 207: S-Parameter settings to compute load and source stability circles

Small Signal Stability
Plot the load and source stability circles. Note that after high frequency feedbacks are applied, the device is absolutely stable.
Figure 208: Load and Source Stability of the unmatched device

Power Stage Matching
Save the design as “PwrStgMatchingSS.dsn”. The S-parameters of the unmatched device show that L-series-L-shunt match can be used at the input
and C-series-L-shunt match can be used at the output. Setup the circuit as shown in the figure and enable tune on all the tuning components.
Output Match
Input Match
Figure 209: S-Parameter Setup for Small Signal Tuning of the Power Stage

Power Stage Tuning
Figure 210: Small signal match for the Power Stage

Large Signal Tune of Power Stage
Generate a component of the matched Power Stage. Copy “Stab_vs_freq_pwr.dsn” from “../ADSxxxx /examples/ MW_Ckts/LargeSigAmp_prj/ networks/” to
the networks folder of the project. Copy “Stab_vs_freq_pwr.dds” from “../ADSxxxx /examples/ MW_Ckts/LargeSigAmp_prj” to the root folder of the project.
Make following changes to the schematic.
Small Signal Tuned

Power Stage
Figure 211: HB Setup for Large Signal

Tuning of Power Stage

Large Signal Tuned Power Stage
Hit Tune button and use tuners to tune input and output match at compression point. Adjust the supply to be 5 V and bias voltage to be -0.25 V.
Achieve a compression point better than 24 dB.
Figure 212: Large Signal Tuned Power Stage achieves -1dB Compression Point better than 24 dBm

Driver Stage Design
Save “PwrStgMatchingSS.dsn” to “DriverStgMatchingSS.dsn”. Resize the transistor to be smaller size. We choose number of fingers to be 6 with each
finger 100 um wide. Retune the input and output match as shown in the figure.
Figure 213: Small Signal Tuned Driver Stage

Response of Driver Stage
Figure shows the match of the driver stage. Driver stage draws a quiescent current of 39 mA from 5 V supply.
Figure 214: Small Signal Response of Driver Stage

Inter-stage Design
Exercise 13:
Inter-stage design & two stage amplifier simulations
Inter-stage Design
Copy the output match of the driver stage and input match of the power stage on to a new schematic. Save it as “Interstage.dsn”. Setup the other
components as shown in the figure. Attach non-50 ohm ports as shown in the figure. Perform single point simulation at 1950 MHz. Refer to the
instructor for further details.
Figure 215: Inter-Stage reduction

Inter-Stage Response
Plot S11, S22, S33, S44 on one smith chart and S55 and S66 on other Smith Chart. Note that center of the Smith Chart for S33 and S44 is the port
impedance. S55 and S66 also center in the Smith Chart suggesting that network 3-4 is same as network 5-6.
Both Networks are equivalent
Figure 216: Response of reduced inter-stage match

Two Stage Power Amplifier
Create a component for Power Stage without input match and driver stage without output match. Create a component for inter-stage. Connect them as
shown in the figure and setup Small Signal Simulations.
Figure 217: S-Parameter Setup for Two Stage Amplifier

Two Stage Amplifier Small Signal Response
Plot the small signal response of the two

stage power amplifier.
Replace all the ideal components with

SPICE Models and re-simulate the
response. Note that parallel model of
capacitor can not be used as that will
affect the gate bias of both stages. One
alternative is to use series model or
simply remove all parallel leakage
resistors from capacitor models.
Figure 218: Small Signal Response of the

Two Stage PA

HB Simulation of Two Stage PA
Use the same schematic for two stage PA simulations. Figure shows the HB setup. Adjust input power sweep to be 18 dB lower to capture the
compression point of two stage PA.
Figure 219: HB Setup to simulate two stage PA

Large Signal Response of Two Stage PA
Figure shows -1dB compression point across the band to be better than 24 dBm. Any FET will not be able to deliver higher power from the same
supply voltage and similar quiescent current unless balanced stages are designed.
Figure 220: Large Signal Response of Two Stage PA (Vcc=6 V and Icq=152 mA)

Load Pull Technique
Tutorial 15: Introduction to Load Pull Techniques used to tune & optimize PA performance
What is Source & Load Pull
It is a technique to determine source and load reflection coefficients that should be

presented to a transistor to achieve target specifications. At times a trade-off has
PA to be accomplished among various performance criteria while establishing source
and load match.
Impedances in a region of Smith Chart at regularly spaced points are presented at

load or source. Contours connecting points with constant PA performance
parameter are plotted. Various PA Performance Parameters can be Gain, Pout,
PAE, IM3, ACPR etc. Contours for various performance parameters can be
plotted on same chart and tradeoff impedance can be determined at source and
load. As the two ports are coupled, few iterations have to be performed alternating
between load and source ports.
Figure 221: Symbolic Representation of Source & Load Pull
In labs, the load and source pull is accomplished using manual or automatic tuners. In case of simulations, it is accomplished using equation based linear
termination. The load pull is performed at fundamental frequency. More elaborate setup is required for including harmonics.

Load & Source Pull Setup
Power Meter
Signal Generator Spectrum Analyzer

Power Power
Sensor Sensor
Tuner Tuner
DUT
Figure 222: Manual Load-pull Stand
Figure shows Load & Source Pull Setup. Manual Load Pull Setups are useful only for devices that are pre-tuned to characteristic impedance as calibration is
carried out only at characteristic impedance. Automated load pull setups like Maury and Focus perform calibration at numerous impedance points.
Simulations on the other hand have ideal equation based reflection coefficients hence load pull in simulations yields meaningful data as accurate as the
device model allows.

Important facts about Load & Source Pull
The region of the smith chart that can easily be considered in

practical load pull systems is shown to be within Γ=0.9. The
Γ=0.9
limiting factor is the Q of the tuners. Manual tuners can
approach maximum Γ=0.7
In case of HBT devices the input impedance can really be small.

Thus at times pre-tune may be required for such devices
Load pull performed on partially stable devices may result in

incorrect data.
Load pull is usually performed for constant delivered power.
In practical systems higher harmonic impedances are out of

control unless harmonic tune is used. Short or open at higher
harmonics may yield a more efficient PA compared to arbitrary
impedance
Figure 223: Smith Chart to explain regions of high Q

Load Pull Setup in ADS
Exercise 14:
Performing Load pull on tuned two stage PA to optimize PAE
Load Pull Setup in ADS
We will set up Load Pull for our PA Design to further improve its performance at -1 dB Compression Point.
Copy HB1Tone_LoadPull_ConstPdel.dsn” from “..\ ADSxxxx\ examples\ RF_Board_LoadPull_prj\ networks” to the project’s networks folder.
Copy “HB1Tone_LoadPull_ConstPdel.dds” from “..\ ADSxxxx\ examples\ RF_Board_LoadPull_prj” to the project’s root folder.
Replace the PA by the designed two stage PA as shown in the figure, without deleting wire names. Adjust the drain supply to 6V and gate supply to
-0.15 V and -0.4 V.
Figure 224: Setting up the PA for Load Pull

Variables for HB Simulation
Make the following changes to the variables. Remove Goal 2. Adjust the region of Smith Chart where load pull takes place to the center of the smith chart
Add Net list Include File
Change the loadpull region
Set the goal as

Delivered Power
Add a new variable to sweep input power for

same delivered power using optimization
Change the DC Supply Voltages &

remove optimization on gate voltage
Figure 225: Setting up Variables for Load-Pull
Change the simulation frequency

HB Simulation for Loadpull
Figure 226: Loadpull Results
Hit Simulate. Observe the plots with the instructor. Notice that optimization for PAE is already
achieved through large signal tuning. This makes loadpull an ornamental exercise to
understand linearity and PAE tradeoffs. Observe the effect of reducing Drain Supply Voltage
on PAE and Delivered Power.

Two Tone Characterization of PA
Exercise 15:
Performing Two Tone Simulations on the PA to determine its TOI & IM3 Levels
Two Tone Characterization
Non Linearity of Power amplifier causes side band. In a spectrally efficient communication system all the channels are close. This spectral emission in
adjacent channels is not desirable. Odd order mix components land near the band. The strongest components adjacent to the band due to PA non-
linearity are third order inter-modulation products. Simplest way to have insight into the sideband emissions is “Two Tone Characterization”. Tone
separation and relative phase between the tones can cause sidebands to reinforce or cancel in a “Multi-tone” case. In a statistically determinant
system like CDMA or OFDM there may be an optimum separation between tones and relative phase of tones that gives best correlation to ACPR in
power range. Thus two tone is not an ultimate analysis for linearity of a PA for a given modulation scheme.
Typical Class A PAE
IP3 IP3
Figure 227: Two Tone Simulation of Two Stage PA

Two Tone HB Setup
Figure 228: HB Simulation Setup for Tone Simulation of PA

Third Order Intercept, IP3 and PAE
Move marker m2 to see IP3

Components to vary with
compression
Figure 229: Tone Simulation Results

ACPR Characterization
Exercise 16:
Performing Ptolemy Co-simulations on the PA with WCDMA 3GPP Uplink Input to determine ACPR
Adjacent Channel Power Ratio
We will determine ACPR of the designed PA near compression for Wideband CDMA input. Important note is that devices in the demo kit are not
behaving as real world devices do at compression. This is the reason we are not able to deliver power. Thus we do not expect wonderful results from
this two stage PA.
Copy “WCDMA3G_PA_UE_ACLR.dsn” from “…\ADS2008U1\examples\WCDMA3G\WCDMA3G_PA_Test_prj\networks” with hierarchical copy

enabled.
Copy “WCDMA3G_PA_UE_ACLR.dds” from “….:\ADSxxxx\examples\WCDMA3G\WCDMA3G_PA_Test_prj” into your project root folder. Make the
changes.
Good News! PA passes

Linearity Specifications
for WCDMA 3 GPP PA
Figure 230: Simulated Output Spectrum

Circuit-Ptolemy Co-simulations
After you have copied the necessary files make the following changes and simulate.
Better to place it one level lower in hierarchy

in one of the RF Sub-Circuits
Figure 231: Ptolemy-Envelope Co-simulations Setup to simulate ACPR

Spectral Emission Response of PA
Figure 232: Simulated Output Spectrum from two stage PA

% EVM Characterization
Exercise 17:
Performing Ptolemy Co-simulations on the PA with WCDMA 3GPP Uplink Input to determine % EVM
% EVM Simulations
Copy “WCDMA3G_PA_UE_EVM.dsn” from “…\ADS2008U1\examples\WCDMA3G\WCDMA3G_PA_Test_prj\networks” with hierarchical copy

enabled.
Copy “WCDMA3G_PA_UE_EVM.dds” from “….:\ADSxxxx\examples\WCDMA3G\WCDMA3G_PA_Test_prj” into your project root folder. Make the
changes.
Better to place it one level

lower in hierarchy in one
of the RF Sub-Circuits
Figure 233: Ptolemy-Envelope Co-simulations Setup to simulate %EVM

%EVM Response of PA
%EVM @ 24 dBm
Power Output
Figure 234: %EVM Performance of PA across output power

Q&A Session- Thanks
Anurag Nigam

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Advanced RF Designs using ADS-Part II

© Copyright 2009 Agilent Technologies 2

© Copyright 2009 Agilent Technologies 3

© Copyright 2009 Agilent Technologies 4

Figure below shows typical architecture Spectral

amplification and Noise improvement is Radio

© Copyright 2009 Agilent Technologies 6

© Copyright 2009 Agilent Technologies 7

Transmit Data Packets Receive Data Packets

© Copyright 2009 Agilent Technologies 8

90º In the figure you can easily distinguish

RF Mixer BALUN LNA Transmitter

© Copyright 2009 Agilent Technologies 9

+ Figure shows direct conversion architecture of a transceiver. Its

PLL at high frequency requires high-end CMOS Technology

© Copyright 2009 Agilent Technologies 10

Stability LP =   = −20 log10  

© Copyright 2009 Agilent Technologies 11

e = k .f .T .(S N )det .NFT .Z 0 (V)

© Copyright 2009 Agilent Technologies 12

Figure 12: Complete Transmitter RF Section in ADS

© Copyright 2009 Agilent Technologies 14

Various inputs are ConvGain =6.5 dB,

Creating New Schematic Sources to Use

Use “File> Save Design” to name the

© Copyright 2009 Agilent Technologies 15

© Copyright 2009 Agilent Technologies 16

Add a HB Controller to the Insert a “Var” Component & write equations

Name output node “Vout”

Create an ADS Schematic as shown in

Add IF and LO input sources as

Set the frequency and power for the

© Copyright 2009 Agilent Technologies 17

Figure 14: Output of the mixer

Analysis & Conclusion

© Copyright 2009 Agilent Technologies 18

Figure 15: S-Parameter Simulation of Chebyshev

Figure 16: S-Parameter Response of Band

© Copyright 2009 Agilent Technologies 19

Write the equations

© Copyright 2009 Agilent Technologies 20

Source of Mix Components & their Gains

Pout = g1 ( A1Cos(1t ) + A2Cos(2t ))

IM3 Lower IM3 Upper

IM3 Lower IM3 Upper

836.5 MHz 837.5 MHz Pin (dBm)

© Copyright 2009 Agilent Technologies 21

Copy the data display “TOIandSOI.dds” from the workshop

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P -1dB of Driver 19.4 dB

Add “Amplifier2” from “System-

Figure 20: ADS Schematic to analyze compression characteristics of transmitter

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Save data display “TOIandSOI.dds” as IM3 @ peak

Analysis & Conclusion

Figure 21: Response of the transmitter to

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Save “TransmitterTOIandSOI.dsn” as “TransmitterSpurLevel.dsn”. Replace input power source with

Delete all the equations in “Meas1” except “Pout_S”. Hit Simulate.

Figure 23: Spectral Response of the

Figure 22: ADS Schematic to simulate spurious response of the transmitter

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