Latched Comparator: ADC Converters (Continued)

EE247
Lecture 21
ADC Converters (continued)
– Comparator architecture examples
– Flash ADC sources of error
• Sparkle code
• Meta-stability
– Techniques to reduce flash ADC complexity
• Interpolating
• Folding
– Pipelined ADCs
EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 1
Latched Comparator
fs
Vi+ Do+
Av Latch
Vi- Do-
Preamp
• Clock rate fs
• Resolution
• Overload recovery
• Input capacitance (and linearity!)
• Power dissipation
• Common-mode rejection
• Kickback noise
• …

Comparators Overdrive Recovery
Linear model for a single-pole amplifier:
UÆ amplification after time ta
During reset amplifier settles

exponentially to its zero input Example: Worst case input/output waveforms
condition with τ0=RC
Æ Limit output voltage swing by
1. Passive clamp
Assume Vm Æ maximum input
2. Active restore
normalized to 1/2lsb (=1)
3. Low gain/stage
Comparators Overdrive Recovery

Limiting Output
Active Restore
Clamp
Adds parasitic capacitance After outputs are latchedÆ Activate φR &
equalize output nodes

CMOS Comparator Example
•Flash ADC: 8bits, +-1/2LSB INL @ fs=15MHz (Vref=3.8V, LSB~15mV)

•No offset cancellation
Ref: A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” JSSC June 1985, pp. 775-9
Flash ADC
Comparator with Auto-Zero
Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel
Applications,” JSSC July 1999, pp. 912-20.

Flash ADC
Voffset
VC + −VC − =
(VR e f + −VR e f − ) −VO ffs et
Flash ADC
Voffset
Vo
Vo = AP1 ∗ AP2 [(VIn+ −VIn− ) − (VC + − VC − ) − −VO f fs e t ]
Subs tituting for (VC + −VC − ) fr om pre v ious c yc le:
Vo = AP1 ∗ AP2 ⎡⎣(VIn+ −VIn− ) − (VRe f + −VRe f − )⎤⎦
Note: O ffse t is c a nc e lle d & differ enc e be twe e n

in p ut & re fe re nc e e st a b li sh e d

Auto-Zero Implementation
Ref:I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” JSSC
March 2000, pp. 318-25
Comparator Example
• Used in a pipelined ADC with digital
correction
Æno offset cancellation required
• Note: Differential reference
• M7, M8 operate in triode region
• Preamp gain ~10
•Input buffers suppress kick-back
• φ1 high Æ Cs charged to VR & φ2B is

also high Æ current diverted to latch
•φ2 highÆ Cs connected to S/Hout &

comparator input (VR-S/Hout), current
sent to preamp Æ comparator
operates
Ref: S. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC ,NO.
6, Dec. 1987

Comparator Example
• Application: Pipelined ADC

with low resolution/stage
Vo1
• Variation on Yukawa latch
used without preamp
• Good for low resolution &
low accuracy ADCs
• During resetÆ φ is low

• φ high Æ Comparison ….
Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE
Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995
Comparator Example (continued)

• M1, M2, M11, M12 operate in triode
mode
• M11 & M12 added to control comparator
threshold
μCo x VVo1 Vo2

G1 = × ⎡⎣W1 (VI1 −Vth ) − W1 1 (VR − −Vth )⎤⎦ o1
L
μCo x
G2 = × ⎣⎡W1 (VI 2 −Vth ) − W1 1 (VR + −Vt h )⎦⎤
L
μCox
→ ΔG = × ⎡⎣W1 (VI1 −VI 2 ) − W1 1 (VR − −VR + )⎤⎦
L
G1 G2
• To 1st order, for W1= W2 & W11=W12
Vth latch = W11/W1 x VR
where VR = VR+ - VR-
Æ Eliminates need for resistive divider
Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE
Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995

Bipolar Comparator Example
•Used in 8bit 400Ms/s & 6bit

2Gb/s flash ADC
•Signal amplification during

φ1 high, latch operates
when φ1 low
•Input buffers suppress kick-

back & input current
•Separate ground and

supply buses for front-end
preamp Æ kick-back noise
reduction
Preamp Latched Comparator
Ref: Y. Akazawa, et al., "A 400MSPS 8b flash AD conversion LSI," IEEE International Solid-State Circuits
Conference, vol. XXX, pp. 98 - 99, February 1987
Ref: T. Wakimoto, et al, "Si bipolar 2GS/s 6b flash A/D conversion LSI," IEEE International Solid-State Circuits
Conference, vol. XXXI, pp. 232 - 233, February 1988
Flash Converter Sources of Error

VREF VIN fs
R/2
• Comparator input:
R – Offset
R – Nonlinear input capacitance
.. Digital – Kickback noise (disturbs
Encoder
.. Output reference)
. – Signal dependent sampling
R time
R
• Comparator output:
R/2
– Sparkle codes (… 111101000
…)
– Metastability

Typical Flash Output Encoder
Binary Output (negative)
VDD
b3
b2
b1
b0
0
0 b3 b2 b1 b0
0 OutputÆ 0 1 1 1
1
1 • Thermometer
0 code Æ 1-of-n
1 decoding
0
1 • Final encoding Æ
Thermometer to Binary encoder ROM NOR ROM
Sparkle Codes
VDD
Erroneous 0 b3
(comparator b2
b1
offset?) b0
0
1
Correct Output:
1
1000
0
0 Erroneous
1 Output:
1
0
0000
1

Sparkle Tolerant Encoder
0 0
0 1
1 0
0 0
1 0
Protects against a single sparkle.
Ref: C. Mangelsdorf et al, “A 400-MHz Flash Converter with Error Correction,” JSSC February
1990, pp. 997-1002
Meta-Stability
Different gates interpret
metastable output X differently
0
Correct output: 1000
0
0
Erroneous output: 0000
1
X
1 Solutions:
1 –Latches (high power)
0 –Gray encoding
1
Ref: C. Portmann and T. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash
A/D Converters,” JSSC August 1996, pp. 1132-40

Gray Encoding
Thermometer Code Gray Binary
T1 T2 T3 T4 T5 T6 T7 G3 G2 G1 B3 B2 B1
0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 0 0 1 G1 = T1T3 + T5 T7
1 1 0 0 0 0 0 0 1 1 0 1 0
1 1 1 0 0 0 0 0 1 0 0 1 1
G2 = T2 T6
1 1 1 1 0 0 0 1 1 0 1 0 0 G3 = T4
1 1 1 1 1 0 0 1 1 1 1 0 1
1 1 1 1 1 1 0 1 0 1 1 1 0
1 1 1 1 1 1 1 1 0 0 1 1 1
• Each Ti affects only one Gi

Æ Avoids disagreement of interpretation by multiple gates
• Protects also against sparkles
• Follow Gray encoder by (latch and) binary encoder
Reducing Flash ADC Complexity

E.g. 10-bit “straight” flash
– Input range: 0 … 1V
– LSB = Δ: ~ 1mV
– Comparators: 1023 with offset << LSB
– Input capacitance: 1023 * 100fF = 102pF
– Power: 1023 * 3mW = 3W
Techniques to reduce complexity & power dissipation :

– Interpolation
– Folding
– Folding & Interpolation
– Two-step, pipelining

Interpolation
• Idea
– Interpolation between preamp outputs
• Reduces number of preamps
– Reduced input capacitance
– Reduced area, power dissipation
• Same number of latches
• Important “side-benefit”
– Decreased sensitivity to preamp offset
Æ improved DNL
Preamp Output
Vin
A1
A1
0.5 A2
0.4 A2
Preamp Output
0.3
0.2
0.1
0
-0.1
-0.2 Zero crossings (to be
-0.3 detected by latches) at Vin =
-0.4
-0.5
0 0.5 1 1.5 2 2.5 3 Vref1 = 1 Δ

Vin / Δ
Vref2 = 2 Δ

Simulink Model
Vin
1
Vin
Vi
A2
Preamp2
2*Delta 2
Vref2 Y
A1
Preamp1
1*Delta
Vref1
Differential Preamp Output

Preamp Output
0.6
0.4 A1
-A1
0.2 A2
0 -A 2 Zero crossings at Vin =
-0.2
-0.4
0 0.5 1 1.5 2 2.5 3 Vref1 = 1 Δ
0.6
0.4 A1+A2 Vref12 = 0.5*(1+2) Δ
A1+A2
0.2
0
Vref2 = 2 Δ
-0.2
-0.4
0 0.5 1 1.5 2 2.5 3
Vin / Δ

Interpolation in Flash ADC
Vin
A1 Half as many reference
voltages and preamps
Interpolation factor:x2
A2
Possible to accomplish
higher interpolation factor
Æ Resistive interpolation
Resistive Interpolation
• Resistors produce
additional levels
• With 4 resistors,
the “interpolation
factor” M=8
(ratio of
latches/preamps)
Ref: H. Kimura et al, “A

10-b 300-MHz
Interpolated-Parallel
A/D Converter,”
JSSC April 1993, pp.
438-446

DNL Improvement
• Preamp offset distributed over
M resistively interpolated
voltages:
Æ impact on DNL divided by
M
• Latch offset divided by gain of

preamp
Æ use “large” preamp gain …
Ref: H. Kimura et al, “A

10-b 300-MHz
Interpolated-Parallel
A/D Converter,”
JSSC April 1993, pp.
438-446
Preamp Input Range

Preamp Output
0.6
A1
0.4
-A1
0.2
0
A2
-A2
Linear preamp input ranges
-0.2 must overlap
-0.4
0 0.5 1 1.5 2 2.5 3

i.e. range > Δ
0.6
A1 +A2
0.4
A1+A2
0.2 Sets upper bound on preamp

0
-0.2 gain << VDD / Δ
-0.4
0 0.5 1 1.5 2 2.5 3
Vin / Δ

Interpolated-Parallel ADC
10-bit overall resolution:

Æ7-bit flash (127
comparators and 128
resistors) & x8
interpolation
Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC April 1993, pp.
438-446
Measured Performance
(7+3)
Low input
capacitance
Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC April 1993, pp.
438-446

Folding Converter
MSB
VIN
ADC
Digital
Output
LSB
ADC
Folding Circuit
• Significantly fewer comparators than flash ~2B/2+1

• Fast
• Nonidealities in folder limit resolution to ~10Bits
Folding
• Folder maps input to
smaller range
1.2
• MSB ADC determines

Folder Output
0.8
which fold input is in LSB
ADC
0.4
• LSB ADC determines
position within fold 0
0 0.5 1 1.5 2 2.5 3 3.5 4

Normalized Input
• Logic circuit combines
LSB and MSB results
MSB ADC
Analog Input

Generating Folds
0.5 1
A1-A2
A1
0 0.5
-0.5 0
0.5 0.5
A2
A3
0 0
-0.5 -0.5
A1-A2+A3
1 0.5
A1-A2
0.5 0
0 -0.5
0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4
Vin / Δ Vin / Δ
Folding Circuit
VDD
R1 R2
-Vo+
Vref1 Vref2 Vref3 Vref4

M1 M2 M3 M4 M5 M6 M7 M8
I1 I2 I3 I4
Vin

CMOS Folder Output
0.5
Folder Output
Ideal
Folder
0 Accurate only at
CMOS
Folder zero-crossings
-0.5
0 0.5 1 1.5 2 2.5 3 3.5 4
Lowdown Æ
In fact, most folding
0.1
ADCs do not use the
0.05
folds, but only the
0
zero-crossings!
Error
-0.05
-0.1
0 0.5 1 1.5 2 2.5 3 3.5 4
Vin /Δ
Parallel Folders
Fine Flash
Folder 4 ADC 4
Vref + 3/4 * Δ
Fine Flash
Folder 3 ADC 3
Vref + 2/4 *Δ Logic

Fine Flash
Folder 2 ADC 2
Vref + 1/4 *Δ
Fine Flash
Folder 1 ADC 1
Vref + 0/4 *Δ

Parallel Folder Outputs
0.5
F1
0.4 F2
F3
0.3 F4
• 4 Folders with 4 folds
0.2 each
• 16 Zero crossings
Folder Output
0.1
0 • Æ only 4 LSB bits

-0.1
-0.2 • Better resolution

-0.3 • More folders
-0.4 Æ Large complexity
-0.5
• Interpolation
0 1 2 3 4 5
Vin / Δ
Folding & Interpolation
Folder 4
Vref + 3/4 * Δ
E
Folder 3 N
Fine C
Vref + 2/4 *Δ Flash O
ADC D
Folder 2 E
R
Vref + 1/4 *Δ
Folder 1
Vref + 0/4 *Δ

Folder / Interpolator Output
0.5
F1
0.4 F2
I1
0.3 I2 0.04
I3
0.2 0.02
0.1
0
0
-0.02
-0.1
-0.2 1.5 1.6 1.7 1.8
-0.3
-0.4
-0.5
0 1 2 3 4 5
Vin / Δ
0.5 0.06
F1
0.4 F2 0.04
I1
I2 0.02
0.3 I3
0
0.2
-0.02
0.1
-0.04
0 -0.06
-0.1 1.5 1.6 1.7 1.8 1.9 2 2.1
-0.2
-0.3 Interpolate only
-0.4 between closely
-0.5 spaced folds to avoid
0 1 2 3 4 5
nonlinear distortion
Vin / Δ

A 70-MS/s 110-mW 8-b CMOS Folding
and Interpolating A/D Converter
Ref: B. Nauta and G. Venes, JSSC Dec 1985, pp. 1302-8
A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter

A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter
Pipelined ADCs

Pipelined A/D Converters
• Ideal operation
• Errors and correction
– Redundancy
– Digital calibration
• Implementation
– Practical circuits
– Stage scaling
Block Diagram
Vres1 Vres2
Vin Stage 1 Stage 2 Stage k
B1 Bits B2 Bits Bk Bits
MSB... ...LSB
Align and Combine Data
Digital output
(B1 + B2 + ... + Bk) Bits
• Idea: Cascade several low resolution stages to obtain

high overall resolution
• Each stage performs coarse A/D conversion and
computes its quantization error, or "residue"

Characteristics
• Number of components (stages) grows
linearly with resolution
• Pipelining
– Trading latency for conversion speed
– Latency may be an issue in e.g. control systems
– Throughput limited by speed of one stage → Fast
• Versatile: 8...16bits, 1...200MS/s
• Many analog circuit non-idealities can
be corrected digitally
Concurrent Stage Operation

φ1 acquire convert ...
φ2 convert acquire ...

φ1
CLK
φ2 Align and Combine Data
Digital output
(B1 + B2 + ... + Bk) Bits
• Stages operate on the input signal like a shift register

• New output data every clock cycle, but each stage
introduces at least ½ clock cycle latency

Data Alignment
φ1 acquire convert ...
φ2 convert acquire ...

φ1
CLK
φ2 Dout
+ +
CLK CLK CLK
• Digital shift register aligns sub-conversion

results in time
Latency
[Analog Devices, AD 9226 Data Sheet]

Pipelined ADC Analysis
• Ignore timing and use simple static model
Vres1 Vres2
Dout
+ +
• Let's first look at "two-stage pipeline"

– E.g.: Two cascaded 2-bit ADCs to get 4 bits of
total resolution
Two Stage Example

11 Vin
2-bit ADC 2-bit ADC 10
Dout
Vin 01
00
0 1 2 3
??? 1
[LSB]
0.5
+
0
Dout = Vin+ εq1
εq1
-0.5
-1
0 1 2 3
ADC Input Voltage [LSB]
• Using only one ADC: output contains large quantization error
• "Missing voltage" or "residue" (-εq1)
• Idea: Use second ADC to quantize and add -εq1

Two Stage Example
2-bit ADC 2-bit DAC 2-bit ADC
-εq1
Vin
“Coarse“ + “Fine“
-
-εq1 + εq2
+
Dout= Vin + ε -ε
+
q1 q1 q2
ε
• Use DAC to compute missing voltage

• Add quantized representation of missing voltage
• Why does this help? How about εq2 ?
−εq1
Two Stage Example
11
10
V /22 V Second ADC
ref1 ref2 “Fine“
Vref1 Vin 01
00
00 01 10 11
First ADC
“Coarse“
• Fine ADC is re-used 22 times

• Fine ADC's full scale range needs to span only 1 LSB of coarse
quantizer V V
ε q2 = ref 2
=
ref 1
2 2
2 ⋅ 22
2

Two Stage Pipelined ADC Transfer Function
Dout
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Vin
Vref1
Coarse Fine
Bits Bits
(MSB) (LSB)

Latched Comparator: ADC Converters (Continued)

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Latched Comparator: ADC Converters (Continued)

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EE247

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 1

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 2

UÆ amplification after time ta

During reset amplifier settles

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 3

Comparators Overdrive Recovery

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 4

•Flash ADC: 8bits, +-1/2LSB INL @ fs=15MHz (Vref=3.8V, LSB~15mV)

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 5

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 6

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 7

Vo = AP1 ∗ AP2 [(VIn+ −VIn− ) − (VC + − VC − ) − −VO f fs e t ]

Subs tituting for (VC + −VC − ) fr om pre v ious c yc le:

Vo = AP1 ∗ AP2 ⎡⎣(VIn+ −VIn− ) − (VRe f + −VRe f − )⎤⎦

Note: O ffse t is c a nc e lle d & differ enc e be twe e n

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 8

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 9

• φ1 high Æ Cs charged to VR & φ2B is

•φ2 highÆ Cs connected to S/Hout &

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 10

• Application: Pipelined ADC

• During resetÆ φ is low

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 11

Comparator Example (continued)

μCo x VVo1 Vo2

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 12

•Used in 8bit 400Ms/s & 6bit

•Signal amplification during

•Input buffers suppress kick-

•Separate ground and

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 13

Flash Converter Sources of Error

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 14

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 15

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 16

Protects against a single sparkle.

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 17

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 18

• Each Ti affects only one Gi

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 19

Reducing Flash ADC Complexity

Techniques to reduce complexity & power dissipation :

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 20

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 21

0 0.5 1 1.5 2 2.5 3 Vref1 = 1 Δ

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 22

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 23

Differential Preamp Output

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 24

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 25

Ref: H. Kimura et al, “A

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 26

• Latch offset divided by gain of

Ref: H. Kimura et al, “A

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 27

Preamp Input Range

0 0.5 1 1.5 2 2.5 3

0.2 Sets upper bound on preamp

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 28

10-bit overall resolution:

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 29

EECS 247 Lecture 21: Data Converters © 2005 H.K. Page 30