Experiment #10

Ripple counters

10.1 Objective
To be familiarized with the design and implementation of simple Ripple
(asynchronous) counters.

10.2 Background
Ripple counters, are made by cascading flip-flops, with the input clock
connected to the first flip-flop, and the output of the first flip-flop used as the
clock of the second one and so on. These counters are also called asynchronous
counters as the outputs of the flip-flops change at different times with respect to
the clock. These types of counters are easy to design, but cannot be used at higher
clock speeds.

10.2.1 Binary Ripple Counter

Figure 10.1 : 4-bit binary ripple counter

Figure
10.2:
Timing
diagra
m of a
4-bit
binary
ripple
counter
10.3 Lab Work
Parts list:
1. 74x93 4-bit binary counter.
2. 74x47 decoder/driver.
3. 7-segment display.

Part I : 4-bit binary Asynchronous counter

The 7493 is a 4 stage asynchronous counter containing high speed FF.

Features a master reset ( MR1 & MR2 ) to override the clock
and force all outputs low. The 74LS93 can be used as:

1- A 4-bit ripple counter - the output Q0 must be

externally connected to input CP1. The input count
pulses are applied to input CP0. Outputs are taken at
Q0 to Q3.
2- A 3-bit ripple counter - the input count pulses are applied to input CP1. The
outputs are available at Q1 to Q3.

Install the 74x93 in the board and connect the master reset inputs to switches,
and the outputs to the respective inputs of a 74x47 as in experiment # 9 part I.

a) Derive the functional table of the 74x93, and verify it experimentally.

b) Verify that the 74x93 behaves as a divided by 16 counter (to count 0, 1,
2… 15).
c) Verify that the 74x93 can also behave as a divided by 8 counter (to count
0, 1, 2… 7).
d) Design the 74x93 as a divided by 4 counter (to count 0, 1, 2, 3) without
any SSI logic.
e) Design the 74x93 as a divided by 12 counter (to count 0, 1, 2… 11)
without any SSI logic.
f) Simulate parts c, d, e, f by PROTUES simulator.
 Note: Show schematic diagram & timing diagram for each circuit
connections in each part.

Part II : Asynchronous counter design

Design a ripple counter to count as the following:

1,2,3,4,5,6,1,2,3 … and so on.

a) Draw the logic Diagram of your design.

b) Test your design using PROTEUS.
c) Test your design and verify it experimentally.

11.5 Exercise
Design a ripple counter to count as the following:
6, 7, 8, 9, 10, 11, 12 … and so on.

a) Draw the logic Diagram of your design.

b) Test your design using PROTEUS.
c) Include your work in the report.