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5 4 3 2 1

SYSTEM PAGE REF.


01. Block Diagram
02. System Setting
03. CPU(1)_DMI,PEG,FDI
PT10SG platform Rev1.1
04. CPU(2)_CLK,MISC,JTAG,DDI
05. CPU(3)_DDR3
06. CPU(4)_PROCESSOR POWER
07. CPU(5)_***
08. CPU(6)_GND N14P-GV2
D
09. CPU(7)_RESERVED
10. CPU_PCH_XDP Page 70 BLOCK DIAGRAM D
16. DDR3(1)_SO-DIMM0
17. DDR3(2)_SO-DIMM1 PCIE x8
18. DDR3(3)_CA/DQ Voltage
20. PCH(1)_SATA,IHDA,RTC DDR3 1600MHz
21. PCH(2)_CLK,SMB,PEG,LPC Panel
LVDS eDP to LVDS eDP CPU DDR3L SO-DIMM x 2
22. PCH(3)_FDI,DMI,SYS PWR RTD2132 Haswell
23. PCH(4)_DP,PCI,CRT Page 16~18
24. PCH(5)_PCIE,NVRAM,USB Page 45 Page 45
25. PCH(6)_CPU,GPIO,MISC Page 3~9
26. PCH(7)_POWER,GND
27. PCH(8)_POWER,GND 0 USB Port(left front)
28. PCH(9)_SPI,SMB DDIC Page 52
30. EC_IT8528 HDMI
31. TP / Keyboard
Page 48 1

FDI x 2

DMI x4
32. RST_Reset Circuit
33 LAN-QCA8171/72
USB Port(left back)
Page 52
34. LAN_RJ45
36. AUD(1)_92HD95 1 USB 3.0
37. AUD(2)_HP/MIC JACK CRT USB 2.0(right front)
40. CB(1)_AU6465 CRT 2
44. BUG_Debug Page 52
Page 46
45. LVDS_output 2 USB 3.0
46 CRT CON
48. TV(1)_HDMI 3 USB 2.0(right back)
Debug Conn.
50. THERMAL / FAN Page 52
C 51. SATA HDD/ODD Page 44 C

52. USB JACK


53. MINICARD_WLAN LPC
4
56. LED
57. DSG_Discharge Touchpad and Keyboard ITE IT8528 PCH Touch Panel
60. DC_DC/BAT CONN Lynx Point (Reserved)
65. ME_CONN,Skew Hole Page 31 Page 30 Page 45
70.VGA-PCIE
71.VGA-N14-FRAME BUFFER USB 2.0
72.VGA-RGB,XTAL
SPI ROM 5
73.VGA-LVDS_HDMI Page 28 Page 20~28
Camera
74.VGA-GPIO,STRAP Page 54
75.VGA-Power,GND

SATA
PCIE
Analog Fan
76.VGA-FBA_HYNIX DDR3 [31:0] 8
77.VGA-FBA_HYNIX DDR3 [63:32] Card Reader Power
80_POWER_VCORE Page 50
Page 40
81_POWER_SYSTEM +VCORE
82_POWER_ +1.05VS +VGFX_CORE
83_POWER_DDR & VTT Azalia 4 Page 80
84_POWER_1.5VS AUDIO Jack Codec HDD
86_POWER_*** Page 51
87_POWER_VGA_VCORE ID92HD95 System (5V & 3.3V)
88_POWER_CHARGER Page 37 5 Page 81
89_POWER_**** Page 36
90_POWER_DETECT ODD
B 91_POWER_LOAD SWITCH Page 51 DDR & VCCP B
92_POWER_PROTECT Page 82
93_POWER_SIGNAL MiniCard 3
94_POWER_FLOWCHART
95. POWER_ HISTORY WLAN + BT3.0 9 USB 2.0 VCCSA & VTT
Page 83
Page 53

4 +1.8VS
RJ45 LAN Page 84
Page 35 AR8172/AR8171
Page 33~34 +VGA_VCORE
Page 87
A01 Power SW
A03 TP BATTERY CHARGER
A04 IO_USB
Page 88

https://t.me/schematicslaptop DETECT
Page 90
https://t.me/biosarchive
LOAD SWITCH
A Page 91 A

Power Protect
https://t.me/schematicslaptop Page 92
Discharge Circuit DC & BATT. Conn.
https://t.me/biosarchive Page 57 Page 60
Title : Block Diagram
Reset Circuit Skew Holes BG1\CORE Engineer: Ruby Tsai
Page 32 Page 65 Size Project Name Rev
C PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 1 of 104
5 4 3 2 1
5 4 3 2 1

https://t.me/schematicslaptop
PCH_CPT PCH_CPT
Internal &
External
EC
ITE8528 EC GPIO Use As Signal Name EC Name Use As Signal Name
https://t.me/biosarchive
GPIO GPIO Use As Signal Name
Pull-up/down
Power
GPA0 PWR_WHITE_LED# LAD0 LPC_AD0
GPIO 00 PCB_ID2 EXT PD REV PU +3VS GPA1 BAT_ORG_LED# LAD1 LPC_AD1
GPIO 01 PCB_ID3 EXT PD REV PU +3VS GPA2 AOAC_RST#(test point) LAD2 LPC_AD2
GPIO 02 PCB_ID10 REV PU REV PD +3VS GPA3 DC_IN_LED# LAD3 LPC_AD3
GPIO 03 SATA_ODD_DA# EXT PU +3VS GPA4 FB_CLAMP_TGL_REQ# LCLK CLK_KBCPCI_PCH
GPIO 04 PCB_ID11 REV PU REV PD +3VS GPA5 CHGCB2# LFRAME# LPC_FRAME#
D D
GPIO 05 PCB_ID8 EXT PU REV PD +3VS GPA6 THERM_ALERT#_EC LRESET# BUF_PLT_RST#
GPIO 06 PCB_ID4 EXT PU REV PD +3VS GPA7 PCH_FLASH_DESCRIPTOR SERIRQ INT_SERIRQ
GPIO 07 PCB_ID5 REV PU REV PD +3VS GPB0 NUM_LED# WRST# EC_RST#
GPIO 08 GPIO8 REV PU REV PD +3VSUS_ORG GPB1 CAP_LED# PECI H_PECI_EC
GPIO
GPIO
09
10
OC5#/GPIO9
OC6#/GPIO10
EXT PU
EXT PU
+3VSUS_ORG
+3VSUS_ORG
GPB2
GPB3
THRO_CPU
SMB0_CLK
FSCK
FMISO
SCK
SO
https://t.me/schematicslaptop
GPIO
GPIO
11
12
SMLA_ALERT#
PM_LANPHY_EN
EXT PU
EXT PU
+3VSUS_ORG
+3VSUS_ORG
GPB4
GPB5
SMB0_DAT
A20GATE
FMOSI
FSCE#
SI
SCE#
https://t.me/biosarchive
GPIO 13 EXT_SCI# EXT PU +3VSUS_ORG GPB6 RCIN# KSI0 KSI0
GPIO 14 OC7#/GPIO14 EXT PU +3VSUS_ORG GPB7 PM_RSMRST# KSI1 KSI1
GPIO 15 EXT_SMI# EXT PU +3VSUS+ORG GPC0 RF_ON(Test point) KSI2 KSI2
GPIO 16 GPIO16 EXT PU +3VS GPC1 SMB1_CLK KSI3 KSI3
GPIO 17 DGPU_PWROK EXT PU +3VS GPC2 SMB1_DAT KSI4 KSI4
GPIO 18 CLK_REQ1# EXT PU +3VS GPC3 KSO16 KSI5 KSI5
GPIO 19 BBS_BIT0_R REV PU REV PD +3VS GPC4 AC_IN_OC KSI6 KSI6
GPIO 20 CLK_REQ_WLAN# EXT PU REV PD +3VS GPC5 KSO17 KSI7 KSI7
GPIO 21 SATA_DET0_R_N EXT PU +3VS GPC6 BAT1_IN_OC# KSO0 KSO0
GPIO 22 WLAN_LED EXT PD GPC7 ME_AC_PRESENT KSO1 KSO1
GPIO 23 SNN_LPC_DRQ#1 T2133 GPD0 PM_SUSB# KSO2 KSO2
GPIO
GPIO
24
25
BT_ON/OFF#
CLK_REQ_LAN#
EXT PU REV PD
EXT PU REV PD
+3VSUS+ORG
+3VSUS_ORG
GPD1
GPD2
PM_SUSC#
BUF_PLT_RST#
KSO3
KSO4
KSO3
KSO4 https://t.me/schematicslaptop
GPIO 26 CLK_REQ4# EXT PU +3VSUS_ORG GPD3 EXT_SCI# KSO5 KSO5
GPIO 27 GPIO27 REV PU +VCCDSW GPD4 EXT_SMI# KSO6 KSO6 https://t.me/biosarchive
GPIO 28 WLAN_ON EXT PU +3VSUS_ORG GPD5 PM_PWROK KSO7 KSO7
GPIO 29 SLP_WLAN# T2205 GPD6 FAN0_TACH KSO8 KSO8
C C
GPIO 30 SUS_PWR_ACK_R EXT PU +3VSUS_ORG GPD7 USBP01_EN KSO9 KSO9
GPIO 31 AC_PRESENT_R EXT PU +VCCDSW GPE0 VSUS_ON KSO10 KSO10
GPIO 33 HDA_DOCK_EN# T2001 GPE1 SUSC_EC# KSO11 KSO11
GPIO 34 +15.7V_PWRGD EXT PU +3VS GPE2 SUSB_EC# KSO12 KSO12
GPIO 35 CRT_IN# EXT PU +3VS GPE3 CPU_VRON KSO13 KSO13
GPIO 36 GPIO36 EXT PD GPE4 PWR_SW#_M KSO14 KSO14
GPIO 37 FDI_OVRVLTG EXT PD REV PU +3VS GPE5 USB_OC01#_EC KSO15 KSO15
GPIO 38 PCB_ID0 EXT PD REV PU +3VS GPE6 LID_SW#
GPIO 39 PCB_ID1 REV PU EXT PD +3VS GPE7 USB_OC2#_EC
GPIO 40 OC1#/GPIO40 EXT PU +3VSUS_ORG GPF0 BAT_LEARN
GPIO 41 OC2#/GPIO41 EXT PU +3VSUS_ORG GPF1 ME_SUSPWRDNACK
GPIO 42 OC3#/GPIO42 EXT PU +3VSUS_ORG GPF2 PM_PWRBTN#
GPIO 43 OC4#/GPIO43 EXT PU +3VSUS_ORG GPF3 SUSACK#(Test_point) SM_BUS ADDRESS :
GPIO 44 CLK_TV_REQ# EXT PU +3VSUS_ORG GPF4 TP_CLK
SM-Bus Device SM-Bus Address
GPIO 45 CLK_REQ6# EXT PU +3VSUS_ORG GPF5 TP_DAT
GPIO 46 CLK_REQ7# EXT PU +3VSUS_ORG GPF6 H_PECI_EC
@ SO-DIMM 0 1010000x ( A0h )
GPIO 47 CLKREQ_PEG# EXT PU +3VSUS_ORG GPF7 LCD_BACKOFF#
N/A SO-DIMM 1 1010001x ( A4h )
GPIO 48 PCB_ID6 REV PU REV PD +3VS GPG0 HDMI_HPD_M
/UMA UMA only
GPIO 49 SATA_ODD_PRSNT#_R EXT PU +3VS GPG1 FDIO2(Test point)
/VGA Optimus only
GPIO 50 DGPU_HOLD_RST# EXT PU +3VS GPG2 AOAC_PWREN(Test point)
/DSC discrete only
GPIO 51 BBS_BIT1 REV PU REV PD +3VS GPG6 FDIO3(Test point)
/UMA/VGA UMA,Optimus 都都都
GPIO 52 PCB_ID9 REV PU REV PD +3VS GPH0 PM_CLKRUN#
/VGA/DSC Optimus,Discrete 都都都
GPIO 53 DGPU_PWM_SELECT# REV PU +3VS GPH1 CHGCB0#
/EMI EMI 都都
EMI 預預預預都
GPIO 54 VGA_PWRON EXT PU +3VS GPH2 CHGCB1#
@/EMI
Giga 都都要
GPIO 55 STP_A16OVR REV PD GPH3 SPI_CS#1 PCIE 1 NC USB 0 USB2.0 Port(Reserved)
/Giga
Giga EMI 都都要
B B
GPIO 56 CLK_REQ_PEG_B# EXT PU +3VSUS_ORG GPH4 SPI_CLK PCIE 2 NC USB 1 USB2.0 Port(debug)
/EMIGiga
GPIO 57 GPIO57 REV PU +3VSUS_ORG GPH5 SPI_SO PCIE 3 Minicard WLAN USB 2 USB3.0 Port (1)
/10_100 /10_100 transformer
GPIO 58 SML1_CLK EXT PU +3VSUS_ORG GPH6 SPI_SI
/CRT/UMA/VGA CRT 在UMA,Optimus都都 PCIE 4 LAN USB 3 USB3.0 Port (2)

CRT Discrete only都都


GPIO 59 OC0#/GPIO59 EXT PU +3VSUS_ORG GPI0 AD_IINP PCIE 5 NC USB 4 Touch Panel (reserved)
/CRT/DSC
/LVDS/UMA/VGALVDS 在UMA,Optimus 都都
GPIO 60 DRAMRST_CNTRL_PCH EXT PU +3VSUS_ORG GPI1 SUS_PWRGD PCIE 6 NC USB 5 Camera

LVDS Discrete only 都都


GPIO 61 PM_SUS_STAT# T2203 GPI2 ALL_SYSTEM_PWRGD PCIE 7 NC USB 6 NC
/LVDS/DSC
HDMI 都都
GPIO 62 SUSCLK_C REV PD GPI3 VRM_PWRGD PCIE 8 NC USB 7 NC
/HDMI
/HDMI/UMA/VGAHDMI 在UMA,Optimus 都都
GPIO 63 SLP_S5# T2204 GPI4 ADAPT_AD USB 8 Card Reader
SATA0 NC
HDMI Discrete only都都
GPIO 64 KB_LED_ID T2111 GPI5 EC_SLP_SUS#(Test point) USB 9 WiFi/WiMax
/HDMI/DSC SATA1 NC
Right Up 都都 USB3.0
GPIO 65 CLK_USB48_CR_R GPI6 WLAN_WAKE#(Test point) USB 10 NC
/USB3.0_U SATA2 NC
Right Up 都都 USB2.0
GPIO 66 PCB_ID14 EXT PU REV PD +3VS GPI7 IMON(Test point) USB 11 NC
/USB2.0_U SATA3 NC
Right down 都都 USB3.0
GPIO 67 PCB_ID12 REV PU REV PD +3VS GPJ0 HDIO2(Test point) USB 12 NC
/USB3.0 SATA4 SATA HDD
Right down 都都 USB2.0
GPIO 68 SATA_ODD_PWRGT REV PU +3VS GPJ1 HDIO3(Test point) USB 13 NC
/USB2.0 SATA5 SATA ODD
GPIO 69 LNB_EN EXT PU +3VS GPJ2 OP_SD#
/USBSLP USB sleep charge
GPIO 70 GPIO70 REV PU REV PD +3VS GPJ3 USBSLP_EN USB3 1 USB3.0 Port (1)
/NON-USBSLP USB sleep don't charge
GPIO 71 PCB_ID7 EXT PU REV PD +3VS GPJ4 FB_CLAMP USB3 2 USB3.0 Port (2)
/TP_A TouchPad Type A
GPIO 72 GPIO72 EXT PU +VCCDSW GPJ5 CTL_FAN USB3 3 NC
/TP_B TouchPad Type B
GPIO 73 CLK_REQ0# EXT PU +3VSUS_ORG GPJ6 SW_RTCRST USB3 4 NC
/WOWL wake on WLAN
GPIO 74 SML1_ALERT# EXT PU +3VSUS_ORG GPJ7 BACK_EN USB3 5 NC
/non-WOWL non wake on WLAN
GPIO 75 SML1_DAT EXT PU +3VSUS_ORG USB3 6 NC

A A

Title : System Setting


BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
D PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 2 of 104
5 4 3 2 1
5 4 3 2 1

+VCCIOA_OUT
+VCCIOA_OUT +VCCIOA_OUT 4,6
U0301A Haswell rPGA EDS PEG_COMP R0301 1 1% 2 24.9Ohm

E23
PEG Compensation
D PEG_RCOMP M29 D
D21 PEG_RXN_0 K28
22 DMI_TXN0 DMI_RXN_0 PEG_RXN_1
C21 M31
22 DMI_TXN1 DMI_RXN_1 PEG_RXN_2
B21 L30
22 DMI_TXN2
A21 DMI_RXN_2 PEG_RXN_3 M33
Enable PCIE Lane Reversal
22 DMI_TXN3 DMI_RXN_3 PEG_RXN_4 Need to PD CFG[2]
L32
D20 PEG_RXN_5 M35
22 DMI_TXP0 DMI_RXP_0 PEG_RXN_6 PCIENB_RXN[7:0] 70
C20 L34
22 DMI_TXP1 DMI_RXP_1 PEG_RXN_7
22 DMI_TXP2 B20 E29 PCIENB_RXN7
A20 DMI_RXP_2 PEG_RXN_8 D28
22 DMI_TXP3 PCIENB_RXN6
https://t.me/schematicslaptop

DMI
DMI_RXP_3 PEG_RXN_9 E31 PCIENB_RXN5
D18 PEG_RXN_10 D30 PCIENB_RXN4
22
22
DMI_RXN0
DMI_RXN1
C17 DMI_TXN_0 PEG_RXN_11 E35 PCIENB_RXN3 https://t.me/biosarchive
B17 DMI_TXN_1 PEG_RXN_12 D34 PCIENB_RXN2
22 DMI_RXN2 DMI_TXN_2 PEG_RXN_13
A17 E33 PCIENB_RXN1
22 DMI_RXN3 DMI_TXN_3 PEG_RXN_14 E32 PCIENB_RXN0
D17 PEG_RXN_15 L29
22 DMI_RXP0 DMI_TXP_0 PEG_RXP_0
C18 L28
22 DMI_RXP1 DMI_TXP_1 PEG_RXP_1
22 DMI_RXP2 B18 L31
A18 DMI_TXP_2 PEG_RXP_2 K30
22 DMI_RXP3 DMI_TXP_3 PEG_RXP_3
PEG_RXP_4
L33 https://t.me/schematicslaptop
K32
PEG_RXP_5
https://t.me/biosarchive

PEG
L35
PEG_RXP_6 PCIENB_RXP[7:0] 70
K34
C PEG_RXP_7 C
F29 PCIENB_RXP7
H29 PEG_RXP_8 E28 PCIENB_RXP6
22 FDI_CSYNC

FDI
J29 FDI_CSYNC PEG_RXP_9 F31 PCIENB_RXP5
22 FDI_INT DISP_INT PEG_RXP_10 E30 PCIENB_RXP4
PEG_RXP_11 F35 PCIENB_RXP3
PEG_RXP_12 E34 PCIENB_RXP2
PEG_RXP_13
PEG_RXP_14
F33
D32
PCIENB_RXP1
PCIENB_RXP0
https://t.me/schematicslaptop
PEG_RXP_15
PEG_TXN_0
H35
H34
https://t.me/biosarchive
PEG_TXN_1 J33
PEG_TXN_2 H32
PEG_TXN_3 J31
PEG_TXN_4 G30
PEG_TXN_5 C33
PEG_TXN_6 B32
PEG_TXN_7 B31 PEG_TXN8_C C0309 2 1 0.22UF/10V /VGA/DSC
PEG_TXN_8 PCIEG_TXN7 70
A30 PEG_TXN9_C C0310 2 1 0.22UF/10V /VGA/DSC
PEG_TXN_9 PCIEG_TXN6 70
B29 PEG_TXN10_C C0311 2 1 0.22UF/10V /VGA/DSC
PEG_TXN_10 PCIEG_TXN5 70
A28 PEG_TXN11_C C0312 2 1 0.22UF/10V /VGA/DSC PCIEG_TXN4 70
PEG_TXN_11 B27 PEG_TXN12_C C0313 2 1 0.22UF/10V /VGA/DSC
PEG_TXN_12 PCIEG_TXN3 70
A26 PEG_TXN13_C C0314 2 1 0.22UF/10V /VGA/DSC PCIEG_TXN2 70
PEG_TXN_13 B25 PEG_TXN14_C C0315 2 1 0.22UF/10V /VGA/DSC
PEG_TXN_14 PCIEG_TXN1 70
B A24 PEG_TXN15_C C0316 2 1 0.22UF/10V /VGA/DSC B
PEG_TXN_15 PCIEG_TXN0 70
J35
PEG_TXP_0 G34
PEG_TXP_1 H33
PEG_TXP_2 G32
PEG_TXP_3 H31
PEG_TXP_4 H30
PEG_TXP_5 B33
PEG_TXP_6 A32
PEG_TXP_7 C31 PEG_TXP8_C C0325 2 1 0.22UF/10V /VGA/DSC
PEG_TXP_8 PCIEG_TXP7 70
B30 PEG_TXP9_C C0326 2 1 0.22UF/10V /VGA/DSC
PEG_TXP_9 PCIEG_TXP6 70
C29 PEG_TXP10_C C0327 2 1 0.22UF/10V /VGA/DSC PCIEG_TXP5 70
PEG_TXP_10 B28 PEG_TXP11_C C0328 2 1 0.22UF/10V /VGA/DSC
PEG_TXP_11 PCIEG_TXP4 70
C27 PEG_TXP12_C C0329 2 1 0.22UF/10V /VGA/DSC PCIEG_TXP3 70
PEG_TXP_12 B26 PEG_TXP13_C C0330 2 1 0.22UF/10V /VGA/DSC
PEG_TXP_13 PCIEG_TXP2 70
C25 PEG_TXP14_C C0331 2 1 0.22UF/10V /VGA/DSC
PEG_TXP_14 PCIEG_TXP1 70
B24 PEG_TXP15_C C0332 2 1 0.22UF/10V /VGA/DSC PCIEG_TXP0 70
PEG_TXP_15

SOCKET_947P
If Support PCIE Gen3, change AC Cap to 0.22uF
12V012BSM001

A A

Title : CPU(1)_DMI,PEG,FDI
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
B PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 3 of 104
5 4 3 2 1
5 4 3 2 1

+VCCIO_OUT +VCCIO_OUT 6,32,57

Haswell rPGA EDS


+1.35V_VCCDDQ +1.35V_VCCDDQ 6
U0301B
+3VSUS +3VSUS 22,23,27,28,30,33,37,53,81,92
T0401 1 TP_SKTOCC#_R AP32 MISC AP3 SM_RCOMP_0 R0418 2 1% 1 100Ohm
SKTOCC# SM_RCOMP_0 AR3 SM_RCOMP_1 R0419 2 1% 1 75Ohm
SM_RCOMP_1 +3V +3V 23,44,45,57,91

THERMAL
1 AN32 AP2 SM_RCOMP_2 R0420 2 1 100Ohm

DDR3
T0402 TP_CATERR#_R 1%
AR27 CATERR# SM_RCOMP_2 AN3
25 H_PECI PECI SM_DRAMRST# CPUDRAMRST# 5 +1.05VS +1.05VS 26,27,32,57,80,82
VCCST R0488 1 @ 2 0Ohm AK31
R0404 1 2 62Ohm H_PROCHOT# R0403 1 56Ohm 2 H_PROCHOT#_D AM30 FC1 AR29 XDP_PRDY# 1 T0403
+VCCIO_OUT PROCHOT# PRDY# +VCCIOA_OUT +VCCIOA_OUT 3,6
SP0401 2 1R0402 H_THRMTRIP#_R AM35 AT29 XDP_PREQ# 1 T0404
25,32 H_THRMTRIP# THERMTRIP# PREQ# AM34 1
D Stuff R0408 XDP_TCK T0405 D
R0402 2 1SP0402 H_PM_SYNC_R TCK AN33 XDP_TMS 1 T0406
22 H_PM_SYNC TMS
Intel MOW WW14: stuff AM33 XDP_TRST# 1 T0407

JTAG
10KOhm 2 1 R0408 AT28 TRST# AM31 XDP_TDI 1 T0408
H_CPUPWRGD PD 10Kohm R1.1 PM_SYNC TDI

PWR
R0402 2 1SP0403 H_CPUPWRGD_R AL34 AL33 XDP_TDO 1 T0409
25 H_CPUPWRGD PWRGOOD TDO
VDDPWRGOOD_R AC10 AP33 XDP_DBRESET# 1 T0410
R0460 1 2 0Ohm BUF_CPU_RST# AT26 SM_DRAMPWROK DBR#
25 PCH_PLTRST_CPU PLTRSTIN# 1
AR30 XDP_BPM0 T0411
BPM_N_0 AN31 XDP_BPM1 1 T0412
R0426 1 2 0Ohm CLK_DP_N_R G28 BPM_N_1 AN29 XDP_BPM2 1 T0413
21 CLK_DP_N DPLL_REF_CLKN BPM_N_2

CLOCK
R0425 1 2 0Ohm CLK_DP_P_R H28 AP31 XDP_BPM3 1 T0414
21 CLK_DP_P DPLL_REF_CLKP BPM_N_3
R0431 1 2 0Ohm CLK_DP_SSC_N_R F27 AP30 XDP_BPM4 1 T0415
21 CLK_DP_SSC_N SSC_DPLL_REF_CLKN BPM_N_4
21
21
CLK_DP_SSC_P
CLK_EXP_N
R0430
R0423
1
1
2
2
0Ohm
0Ohm
CLK_DP_SSC_P_R
CLK_EXP_N_R
E27
D26 SSC_DPLL_REF_CLKP
BCLKN
BPM_N_5
BPM_N_6
AN28
AP29
XDP_BPM5
XDP_BPM6
1
1
T0416
T0417 https://t.me/schematicslaptop
R0422 1 2 0Ohm CLK_EXP_P_R E26 AP28 XDP_BPM7 1 T0418
21 CLK_EXP_P BCLKP BPM_N_7
https://t.me/biosarchive
SOCKET_947P
12V012BSM001
+VCCIO_OUT

/DSC SSC CLOCK TERMINATION


CLK_DP_SSC_P_R R0445 1 2 10KOhm Stuff R0445 & R0446 only when SSC clock not used

CLK_DP_SSC_N_R R0446 1 2 10KOhm

/DSC
U0301H Haswell rPGA EDS

T28 M27 +VCCIO_OUT


DDIB_TXBN_0 EDP_AUXN DP0_AUXN 45 +VCCIOA_OUT
U28 N27
DDIB_TXBP_0 EDP_AUXP DP0_AUXP 45
T30 P27 EDP_HPD#
+1.05VS U30 DDIB_TXBN_1 EDP_HPD E24
DDIB_TXBP_1 EDP_RCOMP

2
C U29 R27 DP_COMP R0402 1 1% 2 24.9Ohm C
V29 DDIB_TXBN_2 EDP_DISP_UTIL 10KOhm
VCCST U31 DDIB_TXBP_2 EDP_DISP_UTIL 1 T0421
V31 DDIB_TXBN_3 eDP R0489
XDP_TDO R0414 1 2 51Ohm DDIB_TXBP_3 P35 DP_L0N_APU 45

1
DPC_TXN2 T34 EDP_TXN_0 R35
48 HDMI_TXN2_PCH DDIC_TXCN_0 EDP_TXP_0 DP_L0P_APU 45
DPC_TXP2 U34 N34 EDP_HPD#
48 HDMI_TXP2_PCH DDIC_TXCP_0 EDP_TXN_1
XDP_TCK R0441 1 2 51Ohm DPC_TXN1 U35 P34
48 HDMI_TXN1_PCH V35 DDIC_TXCN_1 EDP_TXP_1 P33
XDP_TRST# R0442 1 2 51Ohm DPC_TXP1 DDI
FDI_TXN0 22
3
48 HDMI_TXP1_PCH DDIC_TXCP_1 FDI_TXN_0 D
DPC_TXN0 U32 R33 FDI_TXP0 22 Ruby 0925 Q0404
48 HDMI_TXN0_PCH DDIC_TXCN_2 FDI_TXP_0
DPC_TXP0 T32 N32 2N7002
48 HDMI_TXP0_PCH DDIC_TXCP_2 FDI_TXN_1 FDI_TXN1 22
DPC_CLKN U33 P32 FDI_TXP1 22
1 EDP_HPD eDP_HPD 45
48 HDMI_CLKN_PCH DDIC_TXCN_3 FDI_TXP_1
DPC_CLKP V33 G
48 HDMI_CLKP_PCH DDIC_TXCP_3 S 2
P29 pull down 100K ohm at P.45
+3VS R29 DDID_TXDN_0
N28 DDID_TXDP_0 0917 Ken
P28 DDID_TXDN_1
XDP_DBRESET# R0424 1 @ 2 1KOhm P31 DDID_TXDP_1
R31 DDID_TXDN_2
N30 DDID_TXDP_2
P30 DDID_TXDN_3
DDID_TXDP_3

SOCKET_947P
DDI Port B: N/A 12V012BSM001
DDI Port C: HDMI
DDI Port D: N/A
DDI signals Mapping, check 497750

Ruby 0925

B B

R0486 1 @ 2 0Ohm
80 VR_HOT#

+1.35V_VCCDDQ
1

H_PROCHOT#
R0449
1.8KOHM

R1.1 Add PWRLIMIT#


https://t.me/schematicslaptop
2

22 PM_DRAM_PWRGD
0.87 Volt
R0451 1 2 0Ohm VDDPWRGOOD_R
D
3 https://t.me/biosarchive
Q0401
1 THRO_CPU
THRO_CPU 30
1

2N7002 G
S 2
R0450
3.3KOhm
Intel MOW WW14:
change R0449, R0450 value https://t.me/schematicslaptop
2

R1.1

https://t.me/biosarchive
A A
Power good for +1.35V_VCCDDQ (delay > 15ns)
Processor may be damaged if VIH exceeds the maximum voltage for extended periods.
SM_DRAMPWROK VIH MAX = 1.0V ; VIH MIN=0.45*VDDQ
0919 Ken

Title : CPU(2)_CLK,MISC,JTAG,DD
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
Custom PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 4 of 104
5 4 3 2 1
5 4 3 2 1

+1.35V +1.35V 6,16,18,57,83

Haswell rPGA EDS U0301C Haswell rPGA EDS U0301D


16 M_A_D[63:0] 17 M_B_D[63:0]
M_A_D0 AR15 AC7 M_B_D0 AR18 AG8
M_A_D1 AT14 SA_DQ_0 RSVD_AC7 U4 M_B_D1 AT18 SB_DQ_0 RSVD1 Y4
AM14 SA_DQ_1 SA_CK_N_0 V4 M_A_DIM0_CLK#0 16 AM17 SB_DQ_1 SB_CKN0 AA4 M_B_DIM0_CLK#0 17
M_A_D2 M_B_D2
D AN14 SA_DQ_2 SA_CK_P_0 AD9 M_A_DIM0_CLK0 16 AM18 SB_DQ_2 SB_CK0 AF10 M_B_DIM0_CLK0 17 D
M_A_D3 M_B_D3
M_A_D4 AT15 SA_DQ_3 SA_CKE_0 U3 M_A_DIM0_CKE0 16 M_B_D4 AR17 SB_DQ_3 SB_CKE_0 Y3 M_B_DIM0_CKE0 17
M_A_D5 AR14 SA_DQ_4 SA_CK_N_1 V3 M_A_DIM0_CLK#1 16 M_B_D5 AT17 SB_DQ_4 SB_CKN1 AA3 M_B_DIM0_CLK#1 17
M_A_D6 AN15 SA_DQ_5 SA_CK_P_1 AC9 M_A_DIM0_CLK1 16 M_B_D6 AN17 SB_DQ_5 SB_CK1 AG10 M_B_DIM0_CLK1 17
M_A_D7 AM15 SA_DQ_6 SA_CKE_1 U2 M_A_DIM0_CKE1 16 M_B_D7 AN18 SB_DQ_6 SB_CKE_1 Y2 M_B_DIM0_CKE1 17
M_A_D8 AM9 SA_DQ_7 SA_CK_N_2 V2 M_B_D8 AT12 SB_DQ_7 SB_CKN2 AA2
M_A_D9 AN9 SA_DQ_8 SA_CK_P_2 AD8 M_B_D9 AR12 SB_DQ_8 SB_CK2 AG9
M_A_D10 AM8 SA_DQ_9 SA_CKE_2 U1 M_B_D10 AN12 SB_DQ_9 SB_CKE_2 Y1
M_A_D11 AN8 SA_DQ_10 SA_CK_N_3 V1 M_B_D11 AM11 SB_DQ_10 SB_CKN3 AA1
M_A_D12 AR9 SA_DQ_11 SA_CK_P_3 AC8 M_B_D12 AT11 SB_DQ_11 SB_CK3 AF9
M_A_D13 AT9 SA_DQ_12 SA_CKE_3 M_B_D13 AR11 SB_DQ_12 SB_CKE_3
M_A_D14 AR8 SA_DQ_13 M7 M_B_D14 AM12 SB_DQ_13 P4
M_A_D15 AT8 SA_DQ_14 SA_CS_N_0 L9 M_A_DIM0_CS#0 16 M_B_D15 AN11 SB_DQ_14 SB_CS_N_0 R2 M_B_DIM0_CS#0 17
AJ9 SA_DQ_15 SA_CS_N_1 M9 M_A_DIM0_CS#1 16 AR5 SB_DQ_15 SB_CS_N_1 P3 M_B_DIM0_CS#1 17
M_A_D16 M_B_D16
M_A_D17 AK9 SA_DQ_16 SA_CS_N_2 M10 M_B_D17 AR6 SB_DQ_16 SB_CS_N_2 P1
M_A_D18 AJ6 SA_DQ_17 SA_CS_N_3 M8 M_B_D18 AM5 SB_DQ_17 SB_CS_N_3
M_A_D19 AK6 SA_DQ_18 SA_ODT_0 L7 M_A_DIM0_ODT0 16 M_B_D19 AM6 SB_DQ_18 R4
M_A_D20 AJ10 SA_DQ_19 SA_ODT_1 L8 M_A_DIM0_ODT1 16 M_B_D20 AT5 SB_DQ_19 SB_ODT_0 R3 M_B_DIM0_ODT0 17
AK10 SA_DQ_20 SA_ODT_2 L10 AT6 SB_DQ_20 SB_ODT_1 R1 M_B_DIM0_ODT1 17
M_A_D21 M_B_D21
M_A_D22 AJ7 SA_DQ_21 SA_ODT_3 V5 M_B_D22 AN5 SB_DQ_21 SB_ODT_2 P2
AK7 SA_DQ_22 SA_BS_0 U5 M_A_BS0 16 AN6 SB_DQ_22 SB_ODT_3 R7
M_A_D23 M_B_D23
M_A_D24 AF4 SA_DQ_23 SA_BS_1 AD1 M_A_BS1 16 M_B_D24 AJ4 SB_DQ_23 SB_BS_0 P8 M_B_BS0 17
M_A_D25 AF5 SA_DQ_24 SA_BS_2 M_A_BS2 16 M_B_D25 AK4 SB_DQ_24 SB_BS_1 AA9 M_B_BS1 17
M_A_D26 AF1 SA_DQ_25 V10 M_B_D26 AJ1 SB_DQ_25 SB_BS_2 M_B_BS2 17
SA_DQ_26 VSS1 R1.10 SB_DQ_26
M_A_D27 AF2 U6 M_B_D27 AJ2 R10 R1.10
AG4 SA_DQ_27 SA_RAS# U7 M_A_RAS# 16 AM1 SB_DQ_27 VSS2 R6
M_A_D28 M_B_D28
M_A_D29 AG5 SA_DQ_28 SA_WE# U8 M_A_WE# 16 M_B_D29 AN1 SB_DQ_28 SB_RAS# P6 M_B_RAS# 17
M_A_D30 AG1 SA_DQ_29 SA_CAS# M_A_CAS# 16 M_B_D30 AK2 SB_DQ_29 SB_WE# P7 M_B_WE# 17
M_A_D31 AG2 SA_DQ_30 V8 M_A_A0 M_A_A[15:0] 16 M_B_D31 AK1 SB_DQ_30 SB_CAS# M_B_CAS# 17
J1 SA_DQ_31 SA_MA_0 AC6 L2 SB_DQ_31 R8 M_B_A[15:0] 17
M_A_D32 M_A_A1 R1.10 M_B_D32 M_B_A0
M_A_D33 J2 SA_DQ_32 SA_MA_1 V9 M_A_A2 M_B_D33 M2 SB_DQ_32 SB_MA_0 Y5 M_B_A1
SA_DQ_33 SA_MA_2 SB_DQ_33 SB_MA_1 R1.10
M_A_D34 J5 U9 M_A_A3 M_B_D34 L4 Y10 M_B_A2
C M_A_D35 H5 SA_DQ_34 SA_MA_3 AC5 M_A_A4 M_B_D35 M4 SB_DQ_34 SB_MA_2 AA5 M_B_A3 C
M_A_D36 H2 SA_DQ_35 SA_MA_4 AC4 M_A_A5 M_B_D36 L1 SB_DQ_35 SB_MA_3 Y7 M_B_A4
M_A_D37 H1 SA_DQ_36 SA_MA_5 AD6 M_A_A6 M_B_D37 M1 SB_DQ_36 SB_MA_4 AA6 M_B_A5
M_A_D38 J4 SA_DQ_37 SA_MA_6 AC3 M_A_A7 M_B_D38 L5 SB_DQ_37 SB_MA_5 Y6 M_B_A6
M_A_D39 H4 SA_DQ_38 SA_MA_7 AD5 M_A_A8 M_B_D39 M5 SB_DQ_38 SB_MA_6 AA7 M_B_A7
M_A_D40 F2 SA_DQ_39 SA_MA_8 AC2 M_A_A9 M_B_D40 G7 SB_DQ_39 SB_MA_7 Y8 M_B_A8
M_A_D41 F1 SA_DQ_40 SA_MA_9 V6 M_A_A10 M_B_D41 J8 SB_DQ_40 SB_MA_8 AA10 M_B_A9
M_A_D42 D2 SA_DQ_41 SA_MA_10 AC1 M_A_A11 M_B_D42 G8 SB_DQ_41 SB_MA_9 R9 M_B_A10
M_A_D43 D3 SA_DQ_42 SA_MA_11 AD4 M_A_A12 M_B_D43 G9 SB_DQ_42 SB_MA_10 Y9 M_B_A11
M_A_D44 D1 SA_DQ_43 SA_MA_12 V7 M_A_A13 M_B_D44 J7 SB_DQ_43 SB_MA_11 AF7 M_B_A12
M_A_D45 F3 SA_DQ_44 SA_MA_13 AD3 M_A_A14 M_B_D45 J9 SB_DQ_44 SB_MA_12 P9 M_B_A13
M_A_D46 C3 SA_DQ_45 SA_MA_14 AD2 M_A_A15 M_B_D46 G10 SB_DQ_45 SB_MA_13 AA8 M_B_A14
M_A_D47 B3 SA_DQ_46 SA_MA_15 M_B_D47 J10 SB_DQ_46 SB_MA_14 AG7 M_B_A15
M_A_D48 B5 SA_DQ_47 M_B_D48 A8 SB_DQ_47 SB_MA_15
M_A_D49 E6 SA_DQ_48 AP15 M_A_DQS#0 M_A_DQS#[7:0] 16 M_B_D49 B8 SB_DQ_48
M_A_D50 A5 SA_DQ_49 SA_DQS_N_0 AP8 M_A_DQS#1 M_B_D50 A9 SB_DQ_49 AP18 M_B_DQS#0 M_B_DQS#[7:0] 17
M_A_D51 D6 SA_DQ_50 SA_DQS_N_1 AJ8 M_A_DQS#2 M_B_D51 B9 SB_DQ_50 SB_DQS_N_0 AP11 M_B_DQS#1
M_A_D52 D5 SA_DQ_51 SA_DQS_N_2 AF3 M_A_DQS#3 M_B_D52 D8 SB_DQ_51 SB_DQS_N_1 AP5 M_B_DQS#2
M_A_D53 E5 SA_DQ_52 SA_DQS_N_3 J3 M_A_DQS#4 M_B_D53 E8 SB_DQ_52 SB_DQS_N_2 AJ3 M_B_DQS#3
M_A_D54 B6 SA_DQ_53 SA_DQS_N_4 E2 M_A_DQS#5 M_B_D54 D9 SB_DQ_53 SB_DQS_N_3 L3 M_B_DQS#4
M_A_D55 A6 SA_DQ_54 SA_DQS_N_5 C5 M_A_DQS#6 M_B_D55 E9 SB_DQ_54 SB_DQS_N_4 H9 M_B_DQS#5
M_A_D56 E12 SA_DQ_55 SA_DQS_N_6 C11 M_A_DQS#7 M_B_D56 E15 SB_DQ_55 SB_DQS_N_5 C8 M_B_DQS#6
D12 SA_DQ_56 SA_DQS_N_7 AP14 M_A_DQS[7:0] 16 D15 SB_DQ_56 SB_DQS_N_6 C14
M_A_D57 M_A_DQS0 M_B_D57 M_B_DQS#7
M_A_D58 B11 SA_DQ_57 SA_DQS_P_0 AP9 M_A_DQS1 M_B_D58 A15 SB_DQ_57 SB_DQS_N_7 AP17 M_B_DQS0 M_B_DQS[7:0] 17
M_A_D59 A11 SA_DQ_58 SA_DQS_P_1 AK8 M_A_DQS2 M_B_D59 B15 SB_DQ_58 SB_DQS_P_0 AP12 M_B_DQS1
M_A_D60 E11 SA_DQ_59 SA_DQS_P_2 AG3 M_A_DQS3 M_B_D60 E14 SB_DQ_59 SB_DQS_P_1 AP6 M_B_DQS2
M_A_D61 D11 SA_DQ_60 SA_DQS_P_3 H3 M_A_DQS4 M_B_D61 D14 SB_DQ_60 SB_DQS_P_2 AK3 M_B_DQS3
M_A_D62 B12 SA_DQ_61 SA_DQS_P_4 E3 M_A_DQS5 M_B_D62 A14 SB_DQ_61 SB_DQS_P_3 M3 M_B_DQS4
M_A_D63 A12 SA_DQ_62 SA_DQS_P_5 C6 M_A_DQS6 M_B_D63 B14 SB_DQ_62 SB_DQS_P_4 H8 M_B_DQS5
DDR_CA_VREF AM3 SA_DQ_63 SA_DQS_P_6 C12 M_A_DQS7 SB_DQ_63 SB_DQS_P_5 C9 M_B_DQS6
18 DIMM_VREF_CA DDR_WR_VREF01 F16 SM_VREF SA_DQS_P_7 SB_DQS_P_6 C15 M_B_DQS7
18 DIMM0_VREF_DQ F13 SA_DIMM_VREFDQ SB_DQS_P_7
DDR_WR_VREF02
B 18 DIMM1_VREF_DQ SB_DIMM_VREFDQ B
SOCKET_947P
12V012BSM001
Remove power reduction circuit SOCKET_947P
0928 Ruby 12V012BSM001

CPU driven VREF path is stuffed by default


CRB 0.7

close to SO-DIMM
0919 Ken
https://t.me/schematicslaptop
https://t.me/biosarchive 16,17 DDR3_DRAMRST#
1 2
CPUDRAMRST# 4
R0508 0Ohm
1

C0502
0.1UF/10V
2

@
A
https://t.me/schematicslaptop A

Remove power reduction circuit


https://t.me/biosarchive 0928 Ruby

Title : CPU(2)_DDR3
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
Custom PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 5 of 104
5 4 3 2 1
5 4 3 2 1

https://t.me/schematicslaptop +1.35V_VCCDDQ
https://t.me/schematicslaptop +1.35V_VCCDDQ 4

https://t.me/biosarchive +1.35V +1.35V 16,18,57,83


https://t.me/biosarchive +VCORE +VCORE 9,57,80

+VCCIO_OUT +VCCIO_OUT 4,32,57

+VCCIO2PCH +VCCIO2PCH 27

+VCCIOA_OUT +VCCIOA_OUT 3,4


D D

+VCORE
U0301E Haswell rPGA EDS
Remove S3 power reduction circuit
AA26
0928 Ruby VCC100 AA28
K27 VCC99 AA34
L27 RSVD23 VCC98 AA30
T27 RSVD22 VCC97 AA32
V27 RSVD21 VCC96 AB26
RSVD20 VCC95 AB29
+1.35V_VCCDDQ VCC94 AB25
VCC93 AB27
JP0601 VCC92 AB28
1009 Ruby remove 1/16 R1.1 VCC91
+1.35V 2 1 AB11 AB30
2 1 AB2 VDDQ13 VCC90 AB31
3MM_OPEN_5MIL AB5 VDDQ12 VCC89 AB33
VDDQ11 VCC88

1
@ @ @ @ @ @ @ @ @ @ @ AB8 AB34
C0631 C0618 C0657 C0629 C0630 C0633 C0628 C0658 C0616 C0632 C0659 AE11 VDDQ10 VCC87 AB32
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V AE2 VDDQ9 VCC86 AC26

2
AE5 VDDQ8 VCC85 AB35
R1.10 VDDQ7 VCC84
vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small AE8 AC28
vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small AH11 VDDQ6 VCC83 AD25
K11 VDDQ14 VCC82 AC30
N11 VDDQ15 VCC81 AD28
VDDQ5 VCC80

1
@ @ @ @ @ @ @ N8 AC32
C0620 C0621 C0625 C0603 C0602 C0626 C0622 C0624 C0627 C0619 T11 VDDQ16 VCC79 AD31
C
T2 VDDQ4 VCC78 AC34 C
10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V

2
T5 VDDQ17 VCC77 AD34
T8 VDDQ3 VCC76 AD26
vx_c0603_small vx_c0603_small vx_c0603_small vx_c0603_small vx_c0603_small W11 VDDQ18 VCC75 AD27
vx_c0603_small vx_c0603_small vx_c0603_small vx_c0603_small vx_c0603_small W2 VDDQ2 VCC74 AD29
+VCORE W5 VDDQ19 VCC73 AD30
W8 VDDQ1 VCC72 AD32
VDDQ20 VCC71 AD33
Decoupling guide from Intel (EE) N26 VCC70 AD35
K26 RSVD19 VCC69 AE26
VDDQ 22uF * 2pcs (stuff) Placement note: +VCCIOA_OUT AL27 VCC103 VCC68 AE32
10uF * 2pcs (stuff) 1. R0602 close to CPU Unstuff R0622 AK27 RSVD18 VCC67 AE28
RSVD24 VCC66
330uF * 1pcs (stuff) 2. R0603 close to
3. R0605 close to
CPU
VR
+VCCIO2PCH
VCC65
AE30
Intel MOW WW09: renamed AG28
4. R0608 close to CPU +VCCIO_OUT VCC64 AG34
5. R0607 close to VR VCCIO2PCH to RSVD R1.1 100 ohm in power circuit VCC63 AE34
Decoupling guide from Intel ( EE) 6. R0611 close to CPU 0921 Ken VCC62 AF25
VCC61 AF26
+VCORE 10uF * 11pcs (stuff) 1 R0620 2VCC_SENSE_R AL35 VCC60 AF27
22uF * 19pcs (stuff) 80 VCCSENSE
0Ohm E17 VCC_SENSE VCC59 AF28
RSVD27 VCC58
470uF * 5pcs (stuff) R0621 1 0Ohm 2 +VCCIO_OUT_R AN35
VCCIO_OUT VCC57
AF29
+VCCIO_OUT +VCCIO_OUT +VCCIO_OUT +VCCIO_OUT R0622 1 0Ohm@ 2 +VCCIO2PCH_R A23 AF30
R0623 1 0Ohm 2 +VCCIOA_OUT_R F22 RSVD25 VCC56 AF31
W32 VCOMP_OUT VCC55 AF32
RSVD30 VCC54
2

1
R1.10 AL16 AF33
RSVD29 VCC53
2

R0607 R0605 R0603 C0660 C0661 T0601 1 J27 AF34


130Ohm R0608 0.01UF/50V 0.01UF/50V AL13 RSVD26 VCC52 AF35
54.9Ohm 75Ohm

2
1% 130Ohm 1% 1% RSVD28 VCC51 AG26
Intel, 0206
1% VCC50 AH26
80 VR_SVID_ALERT#
1

2
R0602 43Ohm H_CPU_SVIDALRT# AM28 VCC49 AH29
1

+VCORE 1 R0624 2 H_CPU_SVIDCLK AM29 VIDALERT# VCC48 AG30


80 VR_SVID_CLK VIDSCLK VCC102
R0625 1 0Ohm 2 0Ohm H_CPU_SVIDDAT AL28 AG32
80 VR_SVID_DATA VIDSOUT VCC101 AH32
AP35 VCC47 AH35
B T0606 1 H27 VSS3 VCC46 AH25 B
AP34 PWR_DEBUG VCC45 AH27
T0602 1 AT35 VSS4 VCC44 AH28
T0603 1 AR35 RSVD_TP4 VCC43 AH30
Power team suggestion RSVD_TP3 VCC42
1

T0605 1 AR32 AH31


C0604 C0605 C0606 C0607 C0608 C0609 C0610 C0611 C0612 C0613 C0614 T0604 1 AL26 RSVD_TP2 VCC41 AH33
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V AT34 RSVD_TP1 VCC40 AH34
2

AL22 VSS5 VCC39 AJ25


vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small AT33 VSS6 VCC38 AJ26
vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small AM21 VSS7 VCC37 AJ27
AM25 VSS8 VCC36 AJ28
AM22 VSS9 VCC35 AJ29
AM20 VSS10 VCC34 AJ30
AM24 VSS11 VCC33 AJ31
AL19 VSS12 VCC32 AJ32
If XDP not implemented, then Route Processor PWR_DEBUG as a test point. VSS13 VCC31
1

This Test point must be clearly labeled AM23 AJ33


C0634 C0635 C0636 C0637 C0638 C0639 C0640 C0641 C0652 C0653 AT32 VSS14 VCC30 AJ34
(shark bay check list 497750) VSS15 VCC29
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V AJ35
2

VCC28 G25
vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small VCC27 H25
vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small VCC26 J25
+VCORE VCC25 K25
VCC24 L25
VCC23 M25
Y25 VCC22 N25
Y26 VCC11 VCC21 P25
VCC10 VCC20
1

Y27 R25
C0645 C0646 C0647 C0648 C0649 C0650 C0651 C0654 C0655 Y28 VCC9 VCC19 T25
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V Y29 VCC8 VCC18
2

Y30 VCC7 U25


vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small Y31 VCC6 VCC17 U26
vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small vx_c0805_h57_small Y32 VCC5 VCC16 V25
Y33 VCC4 VCC15 V26
Y34 VCC3 VCC14
Y35 VCC2 W26
A VCC1 VCC13 W27 A
VCC12
SOCKET_947P
12V012BSM001

Cap of 470UF or more place at power schematic


Title : CPU(4)_PWR
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
Custom PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 6 of 104
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Title : CPU(4)_PWR
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
Custom PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 7 of 104
5 4 3 2 1

https://t.me/schematicslaptop https://t.me/schematicslaptop
https://t.me/biosarchive https://t.me/biosarchive https://t.me/schematicslaptop
https://t.me/biosarchive
5 4 3 2 1

U0301F Haswell rPGA EDS

A10 AK34 U0301G Haswell rPGA EDS


A13 VSS16 VSS314 AK5
A16 VSS127 VSS315 AL1 B34 K10
A19 VSS238 VSS316 AL10 B4 VSS84 VSS174 K2
A22 VSS268 VSS317 AL11 B7 VSS85 VSS175 K29
A25 VSS279 VSS318 AL12 C1 VSS86 VSS176 K3
D A27 VSS290 VSS319 AL14 C10 VSS87 VSS177 K31 D
A29 VSS301 VSS320 AL15 C13 VSS88 VSS178 K33
A3 VSS312 VSS321 AL17 C16 VSS89 VSS179 K35
A31 VSS323 VSS322 AL18 C19 VSS90 VSS180 K4
A33 VSS17 VSS324 AL2 C2 VSS91 VSS181 K5
VSS28 VSS325 VSS92 VSS182
A4
A7 VSS39 VSS326
AL20
AL21
C22
C24 VSS93 VSS184
K7
K8 https://t.me/schematicslaptop
AA11 VSS50 VSS327 AL23 C26 VSS95 VSS185 K9
AA25 VSS61 VSS328 E22 C28 VSS96 VSS186 L11 https://t.me/biosarchive
AA27 VSS72 VSS329 AL3 C30 VSS97 VSS187 L26
AA31 VSS83 VSS330 AL4 C32 VSS98 VSS188 L6
AA29 VSS94 VSS331 AL5 C34 VSS99 VSS189 M11
AB1 VSS105 VSS332 AL6 C4 VSS100 VSS190 M26
AB10 VSS116 VSS333 AL7 C7 VSS101 VSS191 M28
AA33 VSS128 VSS18 AL8 D10 VSS102 VSS192 M30
AA35 VSS139 VSS19 AL9 D13 VSS103 VSS193 M32
AB3 VSS150 VSS20 AM10 D16 VSS104 VSS195 M34
AC25 VSS161 VSS21 AM13 D19 VSS106 VSS196 M6
AC27 VSS172
VSS183
VSS22
VSS23
AM16 D22 VSS107
VSS108
VSS197
VSS198
N1 https://t.me/schematicslaptop
AB4 AM19 D25 N10
AB6 VSS194
VSS205
VSS24
VSS25
E25 D27 VSS109
VSS110
VSS199
VSS200
N2 https://t.me/biosarchive
AB7 AM32 D29 N29
AB9 VSS216 VSS26 AM4 D31 VSS111 VSS201 N3
AC11 VSS227 VSS27 AM7 D33 VSS112 VSS202 N31
C VSS239 VSS29 VSS113 VSS203 C
AD11 AN10 D35 N33
AC29 VSS250 VSS30 AN13 D4 VSS114 VSS204 N35
AC31 VSS260 VSS31 AN16 D7 VSS115 VSS206 N4
AC33 VSS261 VSS32 AN19 E1 VSS117 VSS207 N5
AC35 VSS262 VSS33 AN2 E10 VSS118 VSS208 N6
AD7 VSS263 VSS34 AN21 E13 VSS119 VSS209 N7
AE1 VSS264 VSS35 AN24 E16 VSS120 VSS210 N9
AE10 VSS265 VSS36 AN27 E4 VSS121 VSS211 P11
VSS266 VSS37 VSS122 VSS212
AE25
AE29 VSS267 VSS38
AN30
AN34
E7
F10 VSS123 VSS213
P26
P5
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VSS269 VSS40 VSS124 VSS214
AE3
AE27 VSS270 VSS41
AN4
AN7
F11
F12 VSS125 VSS215
R11
R26
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AE35 VSS271 VSS42 AP1 F14 VSS126 VSS217 R28
AE4 VSS272 VSS43 AP10 F15 VSS129 VSS218 R30
AE6 VSS273 VSS44 AP13 F17 VSS130 VSS219 R32
AE7 VSS274 VSS45 AP16 F18 VSS131 VSS220 R34
AE9 VSS275 VSS46 AP19 F20 VSS132 VSS221 R5
AF11 VSS276 VSS47 AP4 F21 VSS133 VSS222 T1
AF6 VSS277 VSS48 AP7 F23 VSS134 VSS223 T10
AF8 VSS278 VSS49 W25 F24 VSS135 VSS224 T29
AG11 VSS280 VSS51 AR10 F26 VSS136 VSS225 T3
AG25 VSS281 VSS52 AR13 F28 VSS137 VSS226 T31
AE31 VSS282 VSS53 AR16 F30 VSS138 VSS228 T33
AG31 VSS283 VSS54 AR19 F32 VSS140 VSS229 T35
B B
AE33 VSS284 VSS55 AR2 F34 VSS141 VSS230 T4
AG6 VSS285 VSS56 AR22 F4 VSS142 VSS231 T6
AH1 VSS286 VSS57 AR25 F6 VSS143 VSS232 T7
AH10 VSS287 VSS58 AR28 F7 VSS144 VSS233 T9
AH2 VSS288 VSS59 AR31 F8 VSS145 VSS234 U11
AG27 VSS289 VSS60 AR34 F9 VSS146 VSS235 U27 Placement note:
AG29 VSS291 VSS62 AR4 G1 VSS147 VSS236 V11 1. R0801 close to CPU
AH3 VSS292 VSS63 AR7 G11 VSS148 VSS237 V28
AG33 VSS293 VSS64 AT10 G2 VSS149 VSS240 V30
AG35 VSS294 VSS65 AT13 G27 VSS151 VSS241 V32
AH4 VSS295 VSS66 AT16 G29 VSS152 VSS242 V34 VSS_SENSE_R 2 R0801 1
AH5 VSS296 VSS67 AT19 G3 VSS153 VSS243 W1 VSSSENSE 80
0Ohm
AH6 VSS297 VSS68 AT21 G31 VSS154 VSS244 W10
AH7 VSS298 VSS69 AT24 G33 VSS155 VSS245 W3
AH8 VSS299 VSS70 AT27 G35 VSS156 VSS246 W35
AH9 VSS300 VSS71 AT3 G4 VSS157 VSS247 W4
AJ11 VSS302 VSS73 AT30 G5 VSS158 VSS248 W6
VSS303 VSS74 VSS159 VSS249 100 ohm in power circuit
AJ5 AT4 H10 W7
AK11 VSS304 VSS75 AT7 H26 VSS160 VSS251 W9 0921 Ken
AK25 VSS305 VSS76 B10 H6 VSS162 VSS252 Y11
AK26 VSS306 VSS77 B13 H7 VSS163 VSS253 H11
AK28 VSS307 VSS78 B16 J11 VSS164 VSS254 AL24
AK29 VSS308 VSS79 B19 J26 VSS165 VSS255 F19
A AK30 VSS309 VSS80 B2 J28 VSS166 VSS256 T26 A
AK32 VSS310 VSS81 B22 J30 VSS167 VSS257 AK35
E19 VSS311 VSS82 J32 VSS168 VSS_SENSE AK33
VSS313 J34 VSS169 RSVD31
VSS170
J6
K1 VSS171 Title : CPU(6)_GND
VSS173
SOCKET_947P BG1\CORE Engineer: Ruby Tsai
12V012BSM001 Size Project Name Rev
SOCKET_947P
12V012BSM001
B PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 8 of 104
5 4 3 2 1
5 4 3 2 1

CFG strapping information: The CFG signals have a default value of '1'

U0301I Haswell rPGA EDS

CFG[1:0]: Reserved configuration lane.


AT1
D AT2 RSVD_TP17 C23 D
AD10 RSVD_TP16 RSVD_TP11 B23
CFG[2]: PCIE Static Numbering Lane Reversal- CFG[2] is for the 16x RSVD2 RSVD_TP10 D24
A34 RSVD_TP9 D23
- 1: (Default) Normal Operation, Lane # definition matches sockect pin map definition A35 RSVD_TP15 RSVD_TP8
- 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... RSVD_TP14
T0903 1 W29
T0904 1 W28 RSVD_TP18 AT31 CFG_RCOMP 49.9Ohm 1 2 R0910
R0907 2 1 49.9Ohm H_CPU_RSVD30 G26 RSVD_TP19 CFG_RCOMP AR21 CFG16 1 T0922
CFG[4]: eDP enable W33 TESTLO1 CFG_16 AR23 1
CFG17 T0923
AL30 RSVD3 CFG_18 AP21 CFG18 1 T0924
-1 = Disabled AL29 RSVD4 CFG_17 AP23 CFG19 1 T0925
-0 = Enabled F25 RSVD5 CFG_19
+VCORE VCC104
C35 AR33
B35 RSVD_TP13 RSVD6 G6 VCCST_PW RGD R0912 1 @ 2 6.04KOHM
CFG[6:5]: PCI Express Port Bifurcation Straps RSVD_TP12 FC2 PM_PW ROK 22,30,92
AM27
RSVD7

1
-00 = 1 x8, 2 x4 PCI Express* AL25 AM26
RSVD_TP20 RSVD8 F5 R0913
-01 = reserved T0901 1 W30 RSVD9 AM2 2.67KOhm
-10 = 2 x8 PCI Express* T0902 1 W31 RSVD_TP21 RSVD10 K6 @
-11 = 1 x16 PCI Express* R0908 2 1 49.9Ohm H_CPU_RSVD40 W34 RSVD_TP22 RSVD11

2
TESTLO2 E18
T0906 1 CFG0 AT20 RSVD12
T0907 1 CFG1 AR20 CFG_0 U10
CFG[19:7]: Reserved configuration lane. AP20 CFG_1 RSVD13 P10
T0908 1 CFG2
T0909 1 CFG3 AP22 CFG_2 RSVD14
C
CFG_3 1001 Ken C
T0910 1 CFG4 AT22 B1
T0911 1 CFG5 AN22 CFG_4 NC A2
T0912 1 CFG6 AT25 CFG_5 RSVD15 AR1
T0913 1 CFG7 AN23 CFG_6 RSVD_TP7
T0914 1 CFG8 AR24 CFG_7 E21
T0915 1 CFG9 AT23 CFG_8 RSVD_TP6 E20
T0916 1 CFG10 AN20 CFG_9 RSVD_TP5
T0917 1 CFG11 AP24 CFG_10 AP27
T0918 1 CFG12 AP26 CFG_11 RSVD16 AR26
T0919 1 CFG13 AN25 CFG_12 RSVD17
T0920 1 CFG14 AN26 CFG_13 AL31
1% to 5% CFG_14 VSS258
JR 0924 T0921 1 CFG15 AP25 AL32
CFG_15 VSS259

SOCKET_947P
12V012BSM001

1 2 1KOhm
CFG2 R0902
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CFG4 R0903 1 2 1KOhm

B B

CFG5 R0904 1 @ 2 1KOhm

CFG6 R0905 1 @ 2 1KOhm

remove CFG7 pull down resist +VCORE +VCORE 6,57,80


shark bay check list 497750
Ken

CFG9 R0911 1 @ 2 1KOhm

Sighting 495482

R1.10

A
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Title : CPU(7)_RESERVED
BG1/HW RD Center Engineer: Ruby Tsai
Size Project Name Rev
Custom PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 9 of 104
5 4 3 2 1
5 4 3 2 1

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D
https://t.me/biosarchive D

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https://t.me/biosarchive

C C

B B

A A

Title : CPU_PCH_XDP
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
C PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 10 of 104
5 4 3 2 1
5 4 3 2 1

+1.35V +1.35V 6,18,57,83


+1.35V_DDR3 +0.675VS
+1.35V_DDR3 +1.35V_DDR3 17 +1.35V +1.35V_DDR3
Layout Note: Place these caps near SO DIMM 0
+0.675VS +0.675VS 17,57,83

+3VS JP1601
+3VS 4,17,20,21,22,23,25,26,27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92
1 2
1 2

1
+V_VREF_CA_DIMM0 +V_VREF_CA_DIMM0 17,18
C1609 C1610 C1611 C1612 C1613 C1620 C1616 C1617 C1618 C1619
+V_VREF_DQ_DIMM0 3mm_open_5mil_m1m2 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V
+V_VREF_DQ_DIMM0 18

2
D @ @ @ @ @ D
Remove CE1603
0928 Ruby

5 M_A_A[15:0] M_A_D[63:0] 5 +1.35V_DDR3 +1.35V_DDR3


J1601A J1601B
M_A_A0 98 5 M_A_D7 75 76
M_A_A1 97 A0 DQ0 7 M_A_D0 81 VDD1 VDD2 82
M_A_A2 96 A1 DQ1 15 M_A_D5 87 VDD3 VDD4 88
A2 DQ2 0~7 VDD5 VDD6

1
M_A_A3 95 17 M_A_D3 93 94
M_A_A4 92 A3 DQ3 4 M_A_D4 C1605 C1606 99 VDD7 VDD8 100 C1607 C1608
M_A_A5 91 A4 DQ4 6 M_A_D1 0.1UF/16V 0.1UF/16V 105 VDD9 VDD10 106 0.1UF/16V 0.1UF/16V

2
M_A_A6 90 A5 DQ5 16 M_A_D6 111 VDD11 VDD12 112
M_A_A7 86 A6 0 DQ6 18 M_A_D2 117 VDD13 VDD14 118
M_A_A8 89 A7 DQ7 21 M_A_D8 123 VDD15 VDD16 124
M_A_A9 85 A8 DQ8 23 M_A_D10
Layout Note: Place these caps near SO DIMM 0 VDD17 VDD18
M_A_A10 107 A9 DQ9 33 M_A_D12
M_A_A11 84 A10/AP DQ10 35 M_A_D13
8~15 2 3
M_A_A12 83 A11 DQ11 22 M_A_D9 8 VSS1 VSS2 9
M_A_A13 119 A12/BC# DQ12 24 M_A_D11 13 VSS3 VSS4 14
M_A_A14 80 A13 DQ13 34 M_A_D15 19 VSS5 VSS6 20
C M_A_A15 78 A14 1 DQ14 36 M_A_D14 25 VSS7 VSS8 26 C
A15 DQ15 39 M_A_D20 31 VSS9 VSS10 32
DQ16 41 M_A_D21 37 VSS11 VSS12 38
M_A_DIM0_CLK0 102 DQ17 51 M_A_D19 43 VSS13 VSS14 44
5 M_A_DIM0_CLK1 104 CK1 DQ18 53 48 VSS15 VSS16 49
M_A_D23
5 M_A_DIM0_CLK#1 CK1# DQ19 16~23 VSS17 VSS18
1

1% 101 40 M_A_D17 54 55
5 M_A_DIM0_CLK0 CK0 DQ20 VSS19 VSS20
1

C1621 R1603 103 42 M_A_D22 60 61


150Ohm 5 M_A_DIM0_CLK#0 CK0# DQ21 VSS21 VSS22
10PF/50V 50 M_A_D18 65 66
@ @ 121
2 DQ22 52 M_A_D16 71 VSS23 VSS24 72
5 M_A_DIM0_CS#1
2

114 S1# DQ23 57 M_A_D25 127 VSS25 VSS26 128


5 M_A_DIM0_CS#0
2

M_A_DIM0_CLK#0 S0# DQ24 59 M_A_D29 133 VSS27 VSS28 134


M_A_DIM0_CLK1 120 DQ25 67 M_A_D30 138 VSS29 VSS30 139
5 M_A_DIM0_ODT1
116 ODT1 DQ26 69 M_A_D31
24~31 144 VSS31 VSS32 145
5 M_A_DIM0_ODT0 ODT0 DQ27 VSS33 VSS34
1

1% 56 M_A_D28 150 151


DQ28 VSS35 VSS36
1

C1626 R1604 5 M_A_WE# 113 58 M_A_D24 155 156


10PF/50V 150Ohm 110 WE# DQ29 68 M_A_D27 161 VSS37 VSS38 162
@ @
5 M_A_RAS# 115 RAS# 3 DQ30 70 M_A_D26 167 VSS39 VSS40 168
5 M_A_CAS#
2

CAS# DQ31 129 M_A_D33 172 VSS41 VSS42 173


2

M_A_DIM0_CLK#1 79 DQ32 131 M_A_D38 178 VSS43 VSS44 179


5 M_A_BS2 108 BA2 DQ33 141 184 VSS45 VSS46 185
M_A_D39
5 M_A_BS1 BA1 DQ34 VSS47 VSS48
109 143 M_A_D37 189 190
PLACE CLOSE TO SODIMM 5 M_A_BS0 BA0 DQ35 130 M_A_D36
32~39 195 VSS49 VSS50 196
74 DQ36 132 M_A_D32 VSS51 VSS52
5 M_A_DIM0_CKE1 73 CKE1 DQ37 140 207
M_A_D34
5 M_A_DIM0_CKE0 CKE0 4 DQ38 142 M_A_D35 T1601 1 PM_EXTTS#0_DIM_A 198 GND1 208
R1605 1 2 10KOhm 201 DQ39 147 M_A_D45 125 EVENT# GND2
R1606 1 2 10KOhm 197 SA1 DQ40 149 M_A_D40 TEST 205
SMBus Slave Address: A0H Reserve
SA0 DQ41 157 M_A_D47 77 NP_NC1 206
B DQ42 NC1 NP_NC2 B
159 M_A_D46 122
R1.10
M_A_DQS7 188 DQ43 146 M_A_D43
40~47 NC2 203
5 M_A_DQS[7:0] DQS7 DQ44 +V_VREF_CA_DIMM0 VTT1 +0.675VS +3VS
M_A_DQS#7 186 148 M_A_D41 204
M_A_DQS6 171 DQS#7 DQ45 158 M_A_D44 VTT2
5 M_A_DQS#[7:0]
M_A_DQS#6 169 DQS6 5 DQ46 160 M_A_D42 126
M_A_DQS5 154 DQS#6 DQ47 163 M_A_D52 1 VREFCA 199
For RF DQS5 DQ48 VREFDQ VDDSPD
M_A_DQS#5 152 165 M_A_D53
DQS#5 DQ49

1
M_A_DQS4 137 175 M_A_D50 DDR3_DIMM_204P
M_A_DIM0_CKE1 M_A_DQS#4 135 DQS4 DQ50 177 M_A_D48
M_A_DIM0_CKE0 M_A_DQS3 64 DQS#4 DQ51 164 M_A_D49
48~55 C1624
2.2UF/10V
C1623
0.1UF/16V
12V02GISM000 C1615
0.1UF/16V
C1614
2.2UF/10V

2
SMB_CLK_S_CHA M_A_DQS#3 62 DQS3 DQ52 166 M_A_D51 @ @
SMB_DAT_S_CHA M_A_DQS2 47 DQS#3 DQ53 174 M_A_D55
M_A_DQS#2 45 DQS2 6 DQ54 176 M_A_D54
M_A_DQS1 29 DQS#2 DQ55 181 M_A_D61 +V_VREF_DQ_DIMM0
DQS1 DQ56
1

C1627 C1628 C1629 C1630 M_A_DQS#1 27 183 M_A_D60


M_A_DQS0 12 DQS#1 DQ57 191 M_A_D59
10PF/50V
@
10PF/50V
@
10PF/50V
@
10PF/50V
@ M_A_DQS#0 10 DQS0 DQ58 193 M_A_D62
56~63
2

DQS#0 DQ59

1
180 M_A_D58
187 DQ60 182 M_A_D56 C1622 C1625
170 DM7 DQ61 192 M_A_D63 2.2UF/10V 0.1UF/16V
7

2
153 DM6 DQ62 194 M_A_D57 @
DM should connect to GND directly
Design Guide 1.0 P.88 (436735) 136 DM5 DQ63
63 DM4
46 DM3
28 DM2
11 DM1
DM0
A A
SP1601 2 1 R0402 SMB_CLK_S_CHA 202 30
17,28,31,45,53 SMB_CLK_S 200 SCL RESET# DDR3_DRAMRST# 5,17
SP1602 2 1 R0402 SMB_DAT_S_CHA
17,28,31,45,53 SMB_DAT_S SDA
DDR3_DIMM_204P
12V02GISM000
Title : DDR3L(1)_SO-DIMM0
BG1\CORE Engineer: Ruby Tsai
H:8mm Size
Custom
Project Name
PT10SG
Rev
1.1
Date: Tuesday, February 26, 2013 Sheet 16 of 104
5 4 3 2 1

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5 4 3 2 1

+1.35V_DDR3 +0.675VS
+1.35V_DDR3 +1.35V_DDR3 16 Layout Note: Place these caps near SO DIMM 1
+0.675VS +0.675VS 16,57,83

+3VS +3VS 4,16,20,21,22,23,25,26,27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92

1
+V_VREF_CA_DIMM1 C1709 C1710 C1711 C1712 C1713 C1726 C1716 C1717 C1718 C1719
+V_VREF_CA_DIMM1 16,18
10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V

2
+V_VREF_DQ_DIMM1 @ @ @ @ @
+V_VREF_DQ_DIMM1 18

D D

Remove CE1603
0928 Ruby

+1.35V_DDR3 +1.35V_DDR3
5 M_B_A[15:0] M_B_D[63:0] 5
J1701A J1701B
M_B_A0 98 5 M_B_D0 75 76
M_B_A1 97 A0 DQ0 7 M_B_D7 81 VDD1 VDD2 82
A1 DQ1 VDD3 VDD4

1
M_B_A2 96 15 M_B_D3 87 88
M_B_A3 95 A2 DQ2 17 M_B_D2 C1705 C1706 93 VDD5 VDD6 94 C1707 C1708
M_B_A4 92 A3 DQ3 4 M_B_D1
0~7 0.1UF/16V 0.1UF/16V 99 VDD7 VDD8 100 0.1UF/16V 0.1UF/16V

2
M_B_A5 91 A4 DQ4 6 M_B_D5 105 VDD9 VDD10 106
M_B_A6 90 A5 DQ5 16 M_B_D4 111 VDD11 VDD12 112
M_B_A7 86 A6 0 DQ6 18 M_B_D6 117 VDD13 VDD14 118
M_B_A8 89 A7 DQ7 21 M_B_D10 123 VDD15 VDD16 124
85 A8 DQ8 23
Layout Note: Place these caps near SO DIMM 1 VDD17 VDD18
M_B_A9 M_B_D14
M_B_A10 107 A9 DQ9 33 M_B_D12
M_B_A11 84 A10/AP DQ10 35 M_B_D13 2 3
M_B_A12 83 A11 DQ11 22 M_B_D8
8~15 8 VSS1 VSS2 9
M_B_A13 119 A12/BC# DQ12 24 M_B_D9 13 VSS3 VSS4 14
M_B_A14 80 A13 DQ13 34 M_B_D11 19 VSS5 VSS6 20
C M_B_A15 78 A14 1 DQ14 36 M_B_D15 25 VSS7 VSS8 26 C
A15 DQ15 39 M_B_D16 31 VSS9 VSS10 32
DQ16 41 M_B_D17 37 VSS11 VSS12 38
102 DQ17 51 M_B_D18 43 VSS13 VSS14 44
5 M_B_DIM0_CLK1 104 CK1 DQ18 53 48 VSS15 VSS16 49
M_B_DIM0_CLK0 M_B_D23
5 M_B_DIM0_CLK#1
101 CK1# DQ19 40 M_B_D20
16~23 54 VSS17 VSS18 55
5 M_B_DIM0_CLK0 CK0 DQ20 VSS19 VSS20
1

1% 103 42 M_B_D21 60 61
5 M_B_DIM0_CLK#0 CK0# DQ21 VSS21 VSS22
1

C1720 150Ohm 50 M_B_D22 65 66


10PF/50V R1707 121
2 DQ22 52 M_B_D19 71 VSS23 VSS24 72
5 M_B_DIM0_CS#1 S1# DQ23 VSS25 VSS26
@ @ 114 57 M_B_D29 127 128
5 M_B_DIM0_CS#0
2

S0# DQ24 59 M_B_D28 133 VSS27 VSS28 134


2

M_B_DIM0_CLK#0 120 DQ25 67 M_B_D26 138 VSS29 VSS30 139


5 M_B_DIM0_ODT1 ODT1 DQ26 VSS31 VSS32
M_B_DIM0_CLK1 116 69 M_B_D31 144 145
5 M_B_DIM0_ODT0 ODT0 DQ27 56 M_B_D30
24~31 150 VSS33 VSS34 151
DQ28 VSS35 VSS36
1

1% 113 58 M_B_D25 155 156


5 M_B_WE# W E# DQ29 VSS37 VSS38
1

C1721 150Ohm 110 68 M_B_D27 161 162


10PF/50V R1708
5 M_B_RAS# 115 RAS# 3 DQ30 70 M_B_D24 167 VSS39 VSS40 168
5 M_B_CAS# CAS# DQ31 129 172 VSS41 VSS42 173
@ @ M_B_D33
2

79 DQ32 131 M_B_D37 178 VSS43 VSS44 179


5 M_B_BS2
2

M_B_DIM0_CLK#1 108 BA2 DQ33 141 M_B_D34 184 VSS45 VSS46 185
5 M_B_BS1 109 BA1 DQ34 143 M_B_D35
32~39 189 VSS47 VSS48 190
5 M_B_BS0 BA0 DQ35 130 195 VSS49 VSS50 196
M_B_D32
PLACE CLOSE TO SODIMM 74 DQ36 132 M_B_D36 VSS51 VSS52
5 M_B_DIM0_CKE1 73 CKE1 DQ37 140 M_B_D39 207
5 M_B_DIM0_CKE0 CKE0 4 DQ38 142 M_B_D38 T1701 1 PM_EXTTS#0_DIM_B 198 GND1 208
R1705 1 2 10KOhm 201 DQ39 147 M_B_D44 125 EVENT# GND2
+3VS SA1 DQ40 TEST
SMBus Slave Address: A4H R1706 1 2 10KOhm 197 149 M_B_D45 Reserve 205
SA0 DQ41 157 M_B_D43 77 NP_NC1 206
DQ42 159 M_B_D42 122 NC1 NP_NC2
R1.10
M_B_DQS7 188 DQ43 146 M_B_D40
40~47 NC2 203
B 5 M_B_DQS[7:0] DQS7 DQ44 +V_VREF_CA_DIMM1 VTT1 +0.675VS B
M_B_DQS#7 186 148 M_B_D41 204
5 M_B_DQS#[7:0]
M_B_DQS6 171 DQS#7 5 DQ45 158 M_B_D46 VTT2 +3VS
M_B_DQS#6 169 DQS6 DQ46 160 M_B_D47 126
For RF DQS#6 DQ47 VREFCA
M_B_DQS5 154 163 M_B_D53 1 199
M_B_DQS#5 152 DQS5 DQ48 165 M_B_D55 VREFDQ VDDSPD
DQS#5 DQ49

1
M_B_DIM0_CKE1 M_B_DQS4 137 175 M_B_D51 DDR3_DIMM_204P
M_B_DIM0_CKE0 M_B_DQS#4 135 DQS4 DQ50 177 M_B_D49 C1724 C1723 C1715 C1714
SMB_CLK_S_CHB M_B_DQS3 64 DQS#4 DQ51 164 M_B_D52
48~55 2.2UF/10V 0.1UF/16V
12V02GISM001
0.1UF/16V 2.2UF/10V

2
SMB_DAT_S_CHB M_B_DQS#3 62 DQS3 DQ52 166 M_B_D54 @ @
M_B_DQS2 47 DQS#3 DQ53 174 M_B_D50
M_B_DQS#2 45 DQS2 6 DQ54 176 M_B_D48
DQS#2 DQ55
1

C1727 C1728 C1729 C1730 M_B_DQS1 29 181 M_B_D60 +V_VREF_DQ_DIMM1


10PF/50V 10PF/50V 10PF/50V 10PF/50V M_B_DQS#1 27 DQS1 DQ56 183 M_B_D56
@ @ @ @ M_B_DQS0 12 DQS#1 DQ57 191 M_B_D58
56~63
2

M_B_DQS#0 10 DQS0 DQ58 193 M_B_D63


DQS#0 DQ59

1
180 M_B_D62
187 DQ60 182 M_B_D61 C1722 C1725
170 DM7 DQ61 192 M_B_D57 2.2UF/10V 0.1UF/16V
7

2
153 DM6 DQ62 194 M_B_D59 @
136 DM5 DQ63
63 DM4
46 DM3
28 DM2
11 DM1
DM0
SP1701 2 1 R0402 SMB_CLK_S_CHB 202 30
16,28,31,45,53 SMB_CLK_S SCL RESET# DDR3_DRAMRST# 5,16
SP1702 2 1 R0402 SMB_DAT_S_CHB 200
16,28,31,45,53 SMB_DAT_S SDA
DDR3_DIMM_204P
A 12V02GISM001 A

https://t.me/schematicslaptop https://t.me/schematicslaptop
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H:4mm
Title : DDR3(2)_SO-DIMM1
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
Custom PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 17 of 104
5 4 3 2 1
5 4 3 2 1

+1.35V +1.35V 6,16,57,83

+V_VREF_DQ_DIMM0 +V_VREF_DQ_DIMM0 16

DDR3L Vref +V_VREF_CA_DIMM0 +V_VREF_CA_DIMM0 16,17

+V_VREF_DQ_DIMM1 +V_VREF_DQ_DIMM1 17

+V_VREF_CA_DIMM1 +V_VREF_CA_DIMM1 16,17

https://t.me/schematicslaptop
https://t.me/biosarchive
D D

M3: CPU driven VREF path is stuffed be default.


M1: VREF_DQ driven by a Voltage Divider Network during Processor power-off

+V_VREF_DQ_DIMM0

M3
R1821 1 0Ohm 2
5 DIMM0_VREF_DQ
https://t.me/schematicslaptop

1
+V_VREF_DQ_DIMM1

https://t.me/biosarchive @
R1814
0Ohm
0921Ken

2
R1822 1 0Ohm 2
5 DIMM1_VREF_DQ

+1.35V +1.35V

2
C1805 C1804
0.022UF/16V 0.022UF/16V R1810 R1815

2
1KOhm 1KOhm

1
1

1
R1819 R1818
C 24.9Ohm 24.9Ohm C

1
1% 1%
C1802 R1809 C1803 R1816

2
https://t.me/schematicslaptop 0.1UF/16V 1KOhm 0.1UF/16V 1KOhm

2
2

2
https://t.me/biosarchive Intel
DG, 486713
0920 JR

M1

Intel 0203
M3+M1: Default Recommendation

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https://t.me/biosarchive
+V_VREF_CA_DIMM0
M3 0921Ken
+V_VREF_CA_DIMM1
R1823 1 0Ohm 2

B B
R1824 1 0Ohm 2
5 DIMM_VREF_CA

https://t.me/schematicslaptop
https://t.me/biosarchive +1.35V

2
1

R1807
C1806 1KOhm
0.022UF/16V
2

1
1

R1820
24.9Ohm C1801 R1808
1% 0.1UF/16V 1KOhm
2
2

Intel
DG, 486713
0920 JR

M1

A A

Title : DDR3(3)_CA/DQ Voltage


BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
C PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 18 of 104
5 4 3 2 1
5 4 3 2 1

RTC battery
+RTCBAT +3VA +VCC_RTC
D2001
1
3 +VCC_RTC +VCC_RTC 22,27
2 1 +RTC_BAT 2

1
R2001 1KOhm +3VA +3VA 27,30,33,57,60,65,81,88,93
0.8V/0.2mA C2003

1
07V030000001 1UF/6.3V +3VS +3VS 4,16,17,21,22,23,25,26,27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92

2
3 J2001
4 BATT_HOLDER_2P +3VSUS_ORG +3VSUS_ORG 21,22,24,25,26,27
GND
+12VS
2

+12VS 28,48,57,91

GND
12V20GBSM000
M : 1220-001O000
+1.5VS +1.5VS 21,22,24,26,27,53,57,84
https://t.me/schematicslaptop D

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+VCC_RTC RTCRST# RC delay
should be 18ms~25ms C2001 SP2005
2 5% 1 TPM Settings JRST2001 2 1XTAL_32K_X1_C 1 2
R2003 20KOhm Clear ME RTC Shunt GND R0402
Registers 15PF/50V

1
1

1
JRST2001
Keep ME RTC
Registers
Open
(Default) 2
X2001
32.768KHZ R2002 https://t.me/schematicslaptop
1
1

C2004 10MOhm
LPT_PCH_M_EDS
https://t.me/biosarchive
2

SGL_JUMP NC 3 U2001A
1UF/6.3V @ 0920 JR
2

2
BC8
XTAL_32K_X1 B5 SATA_RXN_0 BE8

4
RTCX1 SATA_RXP_0
T2015 2 1 XTAL_32K_X2 B4 AW8
GND GND 1 C2002 15PF/50V RTCX2 SATA_TXN_0 AY8

RTC
T2012 GND SRTC_RST# B9 SATA_TXP_0
R2005 SRTCRST#
1 BC10
2 1 SM_INTRUDER# A8 SATA_RXN_1 BE10
INTRUDER# SATA_RXP_1
T2011 +VCC_RTC R2006 1 2 330KOhm PCH_INTVRMEN G10 AV10
1MOhm 1 INTVRMEN SATA_TXN_1 AW10
2 5% 1 RTC_RST# D9 SATA_TXP_1
RTCRST#

SATA
R2004 20KOhm BB9
SATA_RXN_2 BD9
R2052 33Ohm HDA_BCLK_R B25 SATA_RXP_2
36 ACZ_BCLK_AUD
1

HDA_BCLK AY13
JRST2002 3 R2051 33Ohm HDA_SYNC_R A22 SATA_TXN_2 AW13
1

D 36 ACZ_SYNC_AUD
1

C2005 Q2001 HDA_SYNC SATA_TXP_2


2

SGL_JUMP 2N7002 AL10 BC12


36 SB_SPKR SPKR SATA_RXN_3
1UF/6.3V 1 BE12
C @ SW_RTCRST 30 C
2

G R2053 33Ohm HDA_RST#_R C24 SATA_RXP_3


S 2 36,37 ACZ_RST#_AUD HDA_RST# AR13
2

L22 SATA_TXN_3 AT13

AZALIA
@ 36 ACZ_SDIN0
@ HDA_SDI0 SATA_TXP_3
R2026
GND GND 10KOhm K22
12/3 R1.1 T2022 1 HDA_SDI1 BD13
SATA_RXN4/PERN1 SATA_RXN0 51
SP2006 G22 BB13 SATA_RXP0 51
1

2 1 HDA_SDI2 SATA_RXP4/PERP1
30 PCH_FLASH_DESCRIPTOR SATA HDD
HDA_SDI3 F22 AV15
HDA_SDI3 SATA_TXN4/PETN1 SATA_TXN0 51
Request by CSC NB_R0402_20MIL_SMALL AW15 SATA_TXP0 51
R2054 33Ohm HDA_SDO_R A24 SATA_TXP4/PETP1
for CMOS clear GND
36 ACZ_SDOUT_AUD HDA_SDO BC14
function EC reset CMOS feature B17 SATA_RXN5/PERN2 BE14
SATA_RXN2 51
DOCKEN#/GPIO33 SATA_RXP5/PERP2 SATA_RXP2 51
T2001 1 HDA_DOCK_EN#
C22 AP15 SATA ODD
CMOS Settings JRST2002 30 EXT_SCI# HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 AR15
SATA_TXN2 51
SATA_TXP5/PETP2 SATA_TXP2 51
1 2
Clear CMOS Shunt R2058 10KOhm
+3VSUS_ORG
Open SATA_RCOMP
AY5 SATA_COMP R2007 1 2 7.5KOhm
+1.5VS
Keep CMOS (Default)
AP3 SATA_LED# R2025 1 2 10KOhm
SATALED# +3VS
@
T2023 1 PCH_JTAG_TCK_BUF AB3 AT1 SATA_DET0_R_N 1 T2028
JTAG_TCK SATA0GP/GPIO21
T2024 1 PCH_JTAG_TMS AD1 AU2 Int. PU BBS_BIT0_R R2057 2 1 0Ohm
JTAG_TMS SATA1GP/GPIO19 BBS_BIT0 23
INTVRMEN: Integrated SUS 1.05V VRM Enables T2025 1 PCH_JTAG_TDI AE2 BD4

JTAG
Low: Enable External VRs JTAG_TDI SATA_IREF
High:Enable Internal VRs T2026 1 PCH_JTAG_TDO AD3 BA2
JTAG_TDO TP9 SATA_IREF R2056 2 1 0Ohm +1.5VS
R2055 1 2 0Ohm F8 BB2
GND TP25 TP8
PCH_INTVRMEN R2030 1 2 330KOhm @ 0927 Ruby
C26
TP22
@
R1.10 T2027 1 PM_TEST_RST_N AB6
GND TP20

B B

POINT
02V000000013

R1.0 +3VSUS_ORG
For JTAG to pull high and low.
PCH_JTAG_TMS R2040 1 1% 2 220Ohm /XDP
PCH_JTAG_TDO R2038 1 1% 2 220Ohm /XDP
PCH_JTAG_TDI R2039 1 1% 2 220Ohm /XDP

Strap information: +3VS


R2041 1 1% 2 100Ohm /XDP
R2042 1 1% 2 100Ohm /XDP HDA_SPKR: No reboot strap SB_SPKR R2020 1 @ 2 1KOhm +3VS
R2043 1 1% 2 100Ohm /XDP Low: Disable (Default)
High:Enable
PCH_JTAG_TCK_BUF R2044 1 2 51Ohm /XDP Ruby 0925
SATA_DET0_R_N 1 2
R2027 10KOhm
GND HDA_SDO: HDA_SDO_R R2034 1 @ 2 1KOhm
+3VSUS_ORG
1.Flash descriptor security:
Sampled Low: in effect. R1.10
Sampled High: override

2.HDA_SDO which sample high on the rising edge of PWROK


Will also disable Intel ME.

HDA_DOCK_EN#:
A Reserved A

[0216] : ACZ_SYNC strap is no longer supported on LPT, by Intel FAE Stu.

Title : PCH(1)_SATA,IHDA,RTC,LPC
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
Custom PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 20 of 104
5 4 3 2 1
5 4 3 2 1

+3VS +3VS 4,16,17,20,22,23,25,26,27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92

+1.5VS +1.5VS 20,22,24,26,27,53,57,84

+3VSUS_ORG +3VSUS_ORG 20,22,24,25,26,27

+VCCAXCK_VRM +VCCAXCK_VRM 27
LPT_PCH_M_EDS
U2001C
CLK_BUF_CPYCLK_P 3 4 RN2108B
10KOhm
CLK_BUF_CPYCLK_N 1 2 RN2108A
10KOhm
Y43 AB35 CLK_PCIE_PEG#_R R2124 1 2 0Ohm
CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PCIE_PEG#_PCH 70
Y45 AB36 CLK_PCIE_PEG_R R2127 1 2 0Ohm CLK_PCIE_PEG_PCH 70 100MHz CLK_BUF_EXP_P 3 4 RN2109B
CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P 1 10KOhm 2
CLK_BUF_EXP_N RN2109A
10KOhm
CLK_REQ0# AB1 AF6 CLKREQ_PEG# CLKREQ_PEG# 70 CLK_BUF_DOT96_P 3 4 RN2110B
D PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 10KOhm D
CLK_BUF_DOT96_N 1 2 RN2110A
AA44 Y39 1 10KOhm 2
CLK_BUF_CKSSCD_N RN2111A
CLKOUT_PCIE_N_1 CLKOUT_PEG_B 10KOhm
AA42 CLK_BUF_CKSSCD_P 3 4 RN2111B
CLKOUT_PCIE_P_1 Y38 10KOhm
CLK_REQ1# AF1 CLKOUT_PEG_B_P CLK_BUF_REF14 R2116 1 2 10KOhm
PCIECLKRQ1#/GPIO18 U4 CLK_REQ_PEG_B#
R2122 1 2 0Ohm CLK_PCIE_WLAN#_R AB43 PEGB_CLKRQ#/GPIO56
53 CLK_PCIE_WLAN# CLKOUT_PCIE_N_2 AF39 CLOCK TERMINATION for FCIM
1 2 0Ohm AB45 CLKOUT_DMI CLK_EXP_N 4 Default power-on mode is ICC.
53 CLK_PCIE_WLAN R2123 CLK_PCIE_WLAN_R 100MHz GND
CLKOUT_PCIE_P_2 AF40
CLKOUT_DMI_P CLK_EXP_P 4
CLK_REQ2# AF3
53 CLK_REQ_WLAN# PCIECLKRQ2#/GPIO20/SMI# AJ40
CLKOUT_DP CLK_DP_SSC_N 4 +3VS
33 CLK_PCIE_LAN# R2158 1 2 0Ohm CLK_PCIE_LAN#_R AD43 AJ39 135MHz
1 2 0Ohm AD45 CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_DP_SSC_P 4
33 CLK_PCIE_LAN R2159 CLK_PCIE_LAN_R
CLK_REQ3_LAN# T3 CLKOUT_PCIE_P_3 AF35
33 CLK_REQ_LAN# PCIECLKRQ3#/GPIO25 CLKOUT_DPNS CLK_DP_N 4
AF36 135MHz
AF43 CLKOUT_DPNS_P CLK_DP_P 4
INT_SERIRQ R2129 1 2 10KOhm
AF45 CLKOUT_PCIE_N_4 AY24 CLK_BUF_EXP_N
CLK_REQ4# V3 CLKOUT_PCIE_P_4 CLKIN_DMI AW24 CLK_BUF_EXP_P
PCIECLKRQ4#/GPIO26 CLKIN_DMI_P
AE44 AR24 CLK_BUF_CPYCLK_N 25-MHz is required in:
AE42 CLKOUT_PCIE_N5 CLKIN_GND AT24 CLK_BUF_CPYCLK_P 1. FCIM
CLK_TV_REQ# AA2 CLKOUT_PCIE_P_5 CLKIN_GND_P 2. BTM for PCH Display Clock gereration
PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DOT96_N in Integrated Graphics platforms
AB40 CLKIN_DOT96N G33 CLK_BUF_DOT96_P
AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P SP2111
CLK_REQ6# AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD_N R0402 12PF/50V
PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_CKSSCD_P 1 2 XTAL_25M_OUT_C
1 2
CLKIN_SATA_P GND

1MOhm
AJ44
CLKOUT_PCIE_N_7 F45 CLK_BUF_REF14 C2102

1
AJ42 REFCLK14IN D17 CLK_PCI_FB

1
CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK 25MHZ
CLK_REQ7# Y3 AL44 XTAL_25M_OUT 2X2103 GND PCH CLKREQ Setting: +3VS
PCIECLKRQ7#/GPIO46 XTAL25_OUT AM43 XTAL_25M_IN
T2141 1 CLK_XDP_N AH43 XTAL25_IN 4
CLKOUT_ITPXDP C40 KB_LED_ID 0927 Ken 1 T2111
100MHz

2
T2142 1 CLK_XDP_P AH45 CLKOUTFLEX0/GPIO64 CLK_REQ1# 3 4 RN2107B

R2142
CLKOUT_ITPXDP_P 10KOhm
C F38 CLK_USB48_CR_R 12PF/50V CLK_REQ_WLAN# 1 2 RN2107A C

3
1 D44 CLKOUTFLEX1/GPIO65 1 2 10KOhm
T2127 CLKOUT_PCI0 GND
CLKOUT_33MHZ0 F36 PCB_ID14 +3VSUS_ORG
CLKOUTFLEX2/GPIO66 PCB_ID14 25
CLK_PCI_FB 22Ohm 2 1 R2110 CLKOUT_PCI1 E44 C2101
CLKOUT_33MHZ1 F39 PCB_ID12
CLKOUTFLEX3/GPIO67 PCB_ID12 25
30 CLK_KBCPCI_PCH 22Ohm 2 1 R2111 CLK_KBCPCI_R B42
CLKOUT_33MHZ2 AM45 ICLK_IREF 0Ohm 1 2 R2145 R1.1 12/5 CLK_REQ4# R2134 1 2 10KOhm
ICLK_IREF +1.5VS
44 CLK_DEBUG SP2105 1 2 R0402 CLK_DEBUG_R F41 CLKREQ_PEG# R2136 1 2 10KOhm
CLKOUT_33MHZ3 AD39
T2101 1 CLK_PCI_DBG_R A40 TP19 AD38 CLK_REQ0# R2131 1 2 10KOhm
CLKOUT_33MHZ4 TP18 CLK_TV_REQ# R2132 1 2 10KOhm
AN44 DIFFCLK_BIASREF R2146 1 2 7.5KOhm
+VCCAXCK_VRM
2

DIFFCLK_BIASREF CLK_REQ6# R2128 1 2 10KOhm


CLOCK SIGNAL
C2103 CLK_REQ7# R2149 1 2 10KOhm
10PF/50V
1

@ CLK_REQ_PEG_B# R2133 1 2 10KOhm


POINT 1 2 10KOhm
CLK_REQ_LAN# R2350
02V000000013 CLK_USB48_CR_R R2165 1 2 22Ohm
CLK_USB48_CR 40 0919 Ken
Reserved for Wireless team 1009 Ruby
GND
10PF/50V

1
@ C2104

2
GND 0921 Ken
LPT_PCH_M_EDS
U2001D

CLK_REQ_WLAN# R2138 1 @ 2 10KOhm

N7 SMLA_ALERT# 1 T2151 CLK_REQ_LAN# R2137 1 @ 2 10KOhm


A20 SMBALERT#/GPIO11
30,44 LPC_AD0 LAD_0
SMBus R10
SMBCLK SCL_3A 28
30,44 LPC_AD1 C20
LAD_1 U11 CLKREQ_PEG# R2141 1 @ 2 10KOhm
SMBDATA SDA_3A 28
A18
LPC

B 30,44 LPC_AD2 LAD_2 B


N8 DRAMRST_CNTRL_PCH
C18 SML0ALERT#/GPIO60
30,44 LPC_AD3 LAD_3 U8 SML0_CLK
B21 SML0CLK
30,44 LPC_FRAME# LFRAME# R7 SML0_DAT Default : Clock free run. (PD 10K).
T2132 1 SNN_PCH_DRQ#0 D21 SML0DATA Reserver 10K PU for power saving purpose. GND
LDRQ0# H6 SML1_ALERT#
PCB_ID15 G20 SML1ALERT#/PCHHOT#/GPIO74
R1.1 2/19 25 PCB_ID15 LDRQ1#/GPIO23 K6 SML1_CLK
SML1CLK/GPIO58 SML1_CLK 28
30,44 INT_SERIRQ Serial Interrupt Request AL11
SERIRQ N11 SML1_DAT
SML1DATA/GPIO75 SML1_DAT 28

AF11 CL_CLK 1 T2152 +3VSUS_ORG


AJ11 CL_CLK
28,30 SPI_CLK
SPI

SPI_CLK AF10 CL_DATA 1 T2153


AJ7 C-Link CL_DATA
28 SPI_CS#0 SPI_CS0# AF7 CL_RST# 1 T2154 SMLA_ALERT# R2118 1 2 10KOhm
AL7 CL_RST#
30 SPI_CS#1 SPI_CS1# SCL_3A 1 2 RN2112A
2.2KOhm
AJ10
SPI_CS2# BA45 SDA_3A 3 4 RN2112B
TP1 2.2KOhm
28,30 SPI_SI AH1
SPI_MOSI BC45 DRAMRST_CNTRL_PCH R2130 1 2 1KOhm
AH3 Thermal TP2
28,30 SPI_SO SPI_MISO BE43 SML0_CLK 5 6 RN2112C
AJ4 TP4 2.2KOhm
28,30 SPI_WP_IO2 SPI_IO2 BE44 SML0_DAT 7 8 RN2112D
AJ2 TP3 2.2KOhm
28,30 SPI_HOLD#_IO3 SPI_IO3 AY43 SML1_CLK R2163 2 1 2.2KOhm
TD_IREF
SML1_DAT R2164 2 1 2.2KOhm
1

R2119 SML1_ALERT# R2125 1 2 10KOhm


POINT 8.2KOhm
02V000000013
2

A A

GND

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https://t.me/biosarchive https://t.me/schematicslaptop https://t.me/schematicslaptop Title : PCH(2)_PCIE,CLK,SMB,PEG
https://t.me/biosarchive https://t.me/biosarchive BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
C PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 21 of 104
5 4 3 2 1
5 4 3 2 1

+3VSUS_ORG +3VSUS_ORG 20,21,24,25,26,27

+3VS +3VS 4,16,17,20,21,23,25,26,27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92

+1.5VS +1.5VS 20,21,24,26,27,53,57,84


LPT_PCH_M_EDS
U2001B +VCC_RTC +VCC_RTC 20,27
AW22
3 DMI_RXN0 DMI_RXN_0 +3VSUS +3VSUS 23,27,28,30,33,37,53,81,92
AR20
3 DMI_RXN1 DMI_RXN_1 AJ35 FDI_TXN0 4 +5VSUS
AP17 FDI_RXN_0 +5VSUS 51,52,81,83
3 DMI_RXN2 DMI_RXN_2
3 DMI_RXN3 AV20 AL35 FDI_TXN1 4 +12VSUS
DMI_RXN_3 FDI_RXN_1 +12VSUS 33,51,81,91
AY22 AJ36
3 DMI_RXP0 DMI_RXP_0 FDI_RXP_0 FDI_TXP0 4 +VCCDSW +VCCDSW 25,27
3 DMI_RXP1 AP20
DMI_RXP_1 FDI
AL36
FDI_RXP_1 FDI_TXP1 4
3 DMI_RXP2 AR17
D
AW20 DMI_RXP_2 AV43 D
3 DMI_RXP3 DMI
DMI_RXP_3 TP16

3 DMI_TXN0 BD21 AY45


BE20 DMI_TXN_0 TP5
3 DMI_TXN1 DMI_TXN_1 AV45
BD17 TP15
3 DMI_TXN2 DMI_TXN_2
3 DMI_TXN3 BE18 AW44
DMI_TXN_3 TP10

3 DMI_TXP0 BB21 AL39 FDI_CSYNC_R SP2202 1 2 R0402


FDI_CSYNC 3
BC20 DMI_TXP_0 FDI_CSYNC
3 DMI_TXP1

3 DMI_TXP2
BB17
DMI_TXP_1

DMI_TXP_2
FDI_INT
AL40 FDI_INT_R SP2201 1 2 R0402
FDI_INT 3 https://t.me/schematicslaptop
BC18 AT45 FDI_IREF 0Ohm 1 2 R2243
3 DMI_TXP3

+1.5VS R2242 2 1 0Ohm DMI_IREF BE16


DMI_TXP_3

DMI_IREF
FDI_IREF

TP17
AU42
+1.5VS
https://t.me/biosarchive
AW17 AU44
TP12 TP13
AV17 AR44 FDI_RCOMP R2206 1 2 7.5KOhm
TP7 FDI_RCOMP +1.5VS
R2202 1 2 7.5KOhm DMI_RCOMP AY17
+1.5VS DMI_RCOMP
If SUSWARN #/SUS_ACK # handshake
is not used, these signals are tied on the board SUS_PWR_ACK_R R2208 2 1 0Ohm
R2215 @ 330KOhm GND DSWODVREN - On Die DSW VR Enable
30 SUSACK# SUSACK#_PCH R2203 2 @ 1 0Ohm SUSACK#_R R6 C8 DSWODVREN R2214 330KOhm +VCC_RTC HIGH - Enabled(DEFAULT) ; LOW-Disabled
SUSACK# DSWVRMEN
2 1 10KOhm AM1 System Power L13
+3VS R2205 PCH_DPROK SP2220 1 2 R0402 PM_RSMRST_R
SYS_RESET# Management DPWROK
DG, 486713 SYS_PWROK R2210 2 1 0Ohm SYS_PWROK_R AD7 K3
SYS_PWROK WAKE# PCIE_WAKE# 33,53
CHKLST, 497750
0920 JR R2211 2 1 0Ohm PM_PCH_PWROK_R F10 AN7 PM_CLKRUN#
9,30,92 PM_PWROK PWROK CLKRUN# PM_CLKRUN# 30
R2240 2 1 0Ohm PM_APWROK_R AB7 U7 PM_SUS_STAT# 1 T2203
APWROK SUS_STAT#/GPIO61

4 PM_DRAM_PWRGD H3 Y6 SUSCLK_C 1 T2210


DRAMPWROK SUSCLK/GPIO62
R2212 2 1 0Ohm PM_RSMRST_R J2 Y7 SLP_S5# 1 T2204
30 PM_RSMRST# RSMRST# SLP_S5#/GPIO63
C C
SP2218 1 2 R0402 SUS_PWR_ACK_R J4 C6 SLP_S4#_R SP2206 1 2 R0402
30 ME_SUSPWRDNACK SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PM_SUSC# 30
SP2214 1 2 R0402 K1 H1 SLP_S3#_R SP2207 1 2 R0402
30

30
PM_PWRBTN#

ME_AC_PRESENT SP2219 1 2 R0402 AC_PRESENT_R E6


PWRBTN# SLP_S3#
F3 1
PM_SUSB#
T2207
30
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ACPRESENT/GPIO31 SLP_A#
GPIO72 K7
BATLOW#/GPIO72 SLP_SUS#
F1 SLP_DSW#_R 1 T2209 https://t.me/biosarchive
T2202 1 RI# N4 AY3
RI# PMSYNCH H_PM_SYNC 4
AB10 G5 1 T2206
TP21 SLP_LAN#
T2205 1 SLP_WLAN# D2
SLP_WLAN#/GPIO29

POINT
02V000000013

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+3VSUS https://t.me/biosarchive
B B
U2201
PM_PWROK SP2209 1 2 R0402 1 A 5
VCC

92 DELAY_VR_AND_ALL_SYS SP2210 1 2 R0402 2 B


+VCCDSW
3 4 SYS_PWROK R1.1
GND
Y
Vcc=2~5.5
0921 Ken
PCIE_WAKE# R2226 1 2 10KOhm
ME_AC_PRESENT R2228 1 2 10KOhm
GPIO72 R2224 1 2 10KOhm

R2209 2 @ 1 0Ohm
+3VSUS_ORG

+3VS

0921 Ken RI# 1 2


PM_CLKRUN# 1 2 R2223 10KOhm
R2220 8.2KOhm ME_SUSPWRDNACK 1 2
R2227 10KOhm

PM_PWROK 1 2
R2221 10KOhm

GND

Remove DS3 circuit


A A
0928 Ruby

PLL ON DIE VR ENABLE


SUSCLK_C R2249 1 @ 2 1KOhm GND HIGH - ENABLED (DEFAULT)
LOW - DISABLED

Title : PCH(3)_FDI,DMI,SYS PWR


BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
C PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 22 of 104
5 4 3 2 1
5 4 3 2 1

+3VS +3VS 4,16,17,20,21,22,25,26,27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92

+3V +3V 44,45,57,91

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2
D RN2303B RN2303A D
LPT_PCH_M_EV
U2001E 2.2KOhm 2.2KOhm
JP2301 /UMA/VGA /UMA/VGA
50 ohm 2 1 37.5 ohm CRT_B_J T45 R40
46 CRT_B_PCH VGA_BLUE DDPB_CTRLCLK
JP2302 Ruby 0924

1
50 ohm SHORT_PIN 2 1 37.5 ohm CRT_G_J U44 R39
46 CRT_G_PCH VGA_GREEN DDPB_CTRLDATA
JP2303
50 ohm SHORT_PIN 2 1 37.5 ohm CRT_R_J V45 R35
46 CRT_R_PCH VGA_RED DDPC_CTRLCLK HDMI_DDC_CLK_PCH 48
SHORT_PIN M43 R36
46 DDC_CLK_PCH VGA_DDC_CLK DDPC_CTRLDATA HDMI_DDC_DATA_PCH 48
M45 N40

CRT
46 DDC_DATA_PCH VGA_DDC_DATA DDPD_CTRLCLK
R0402

1
SP2304 1 2CRT_HSYNC_R N42 N38
46 CRT_HSYNC_PCH VGA_HSYNC DDPD_CTRLDATA
R2304 R2305 R2306
SP2305 1 2CRT_VSYNC_R N44 Strap information:
46 CRT_VSYNC_PCH VGA_VSYNC H45
150Ohm 150Ohm 150Ohm R0402
/UMA/VGA /UMA/VGA /UMA/VGA R2303 1 2 DAC_IREF U40 DDPB_AUXN There signals have a weak internal pull down
Close to CPU

2
649OHM DAC_IREF K43
U39 DDPC_AUXN DDPB_CTRLDATA: "0" = Port is not detected; "1"= Port is detected
+3VS GND VGA_IRTN DDPC_CTRLDATA: "0" = Port is not detected; "1"= Port is detected
J42

DISPLAY
DDPD_AUXN DDPD_CTRLDATA: "0" = Port is not detected; "1"= Port is detected
GND
SP2306 1 2 R0402 N36 H43
45 L_BKLT_CTRL EDP_BKLTCTL DDPB_AUXP
R2309 1 @ 2 1KOhm L_BKLT_CTRL

LVDS
eDP_BL_EN K36 K45
R2307 1 @ 2 1KOhm eDP_BL_EN EDP_BKLTEN DDPC_AUXP
EDP_VDD_EN G36 J44
R2308 1 @ 2 1KOhm EDP_VDD_EN +3VS EDP_VDDEN DDPD_AUXP
C C
K40
R2320 1 @ 2 10KOhm DGPU_PWM_SELECT# 5 6 RN2301C INT_PIRQA# H20 DDPB_HPD
10KOhm PIRQA# K38
DDPC_HPD HDMI_HPD_PCH 48
3 4 RN2301B INT_PIRQB# L20
PIRQB# H39
Ruby 0925 10KOhm
DDPD_HPD
R2322 1 2 10KOhm DGPU_HOLD_RST# 1 2 RN2301A INT_PIRQC# K17 +3VS
10KOhm PIRQC#
R2323 1 2 10KOhm DGPU_PWR_EN 7 8 RN2301D INT_PIRQD# M20
10KOhm PIRQD# PCI
G17 PCB_ID10
1/14 R1.1 PIRQE#/GPIO2 PCB_ID10 25
DGPU_HOLD_RST# A12
70 DGPU_HOLD_RST# GPIO50
R2355 1 2 2.2KOhm DDC_CLK_PCH F17 R2330 1 2 10KOhm
PCB_ID9 B13 PIRQF#/GPIO3
25 PCB_ID9 GPIO52 SATA_ODD_DA# 51
R2356 1 2 2.2KOhm DDC_DATA_PCH JR 0924 L15 PCB_ID11 PCB_ID11 25
DGPU_PWR_EN C12 PIRQG#/GPIO4
1/14 R1.1 GPIO54 M15 PCB_ID8
PIRQH#/GPIO5 PCB_ID8 25
BBS_BIT1 Int. PU C10
CRT Disable: (For discrete graphic) GPIO51 AD10 PCI_PME# 1 T2301
T2304 1 strap Pin DGPU_PWM_SELECT# A10
GPIO53
PME#
1. NC: 3. Connected to GND: Y11 PLT_RST#
STP_A16OVRInt. PU AL6 PLTRST#
GPIO55
CRT_R,CRT_G,CRT_B CRT_ITRN
CRT_HSYCN,CRT_VSYNC 4. Connect to +V3.3: POINT
02V000000013
2. 1KΩ+-5% pull-down to GND: VCCADAC
+3V
B DAC_IREF B

STP_A16OVR: U2302 0921Ken


BBS_BIT0,BBS_BIT1 : Boot BIOS Strap 1 5
A16 swap override Strap/ PLT_RST# 2 A VCC
B
Boot BIOS Strap Top-Block swap override jumper 3
GND Y
4
BUF_PLT_RST# 30,32,33,40,53,70
SN74LVC1G08DCKR
BBS_BIT1 BBS_BIT0 Boot BIOS Location Low=Enabled A16 swap override/

1
GND
0 0 LPC Top-Block swap override R2326
1 @ 2 100KOhm
0 1 Reserved (NAND) R2325 0Ohm
High=Default

2
1 0 Reserved
R1.10
1 1 SPI (PCH) 1/14 R1.1
GND

Sampled on rising edge of PWROK.

BBS_BIT0 R2317 1 @ 2 1KOhm STP_A16OVR R2319 1 @ 2 1KOhm


20 BBS_BIT0

A BBS_BIT1 R2318 1 @ 2 1KOhm A


GND

GND +3VS
U2303 @
+3VSUS
5 1 DGPU_PWR_EN
VCC A
R2328 1 @ 2 10KOhm
4 B
2
3
SUSB_EC# 30,57,91,92 Title : PCH(4)_DP,LVDS,CRT
74,91 VGA_PWRON Y GND GND
R2329 1 @ 2 10KOhm Engineer: Ruby Tsai
SN74LVC1G08DCKR BG1\CORE
R1.1
Size Project Name Rev
This signal has a weak internal pull-up. R2357 1 2 0Ohm
Ken
Custom PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 23 of 104
5 4 3 2 1

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5 4 3 2 1

+3VSUS +3VSUS 22,23,27,28,30,33,37,53,81,92

+3VSUS_ORG +3VSUS_ORG 20,21,22,25,26,27

+1.5VS +1.5VS 20,21,22,26,27,53,57,84

LPT_PCH_M_EDS
U2001I

AW31 B37
D PERN1/USB3RN3 USB2N0 USB_PN0 52 D
AY31 D37 USB port(daughter board, 17 only)
PERP1/USB3RP3 USB2P0 A38 USB_PP0 52
USB2N1 USB_PN1 52 1
BE32 C38 USB port (Debug Port, daughter board)
BC32 PETN1/USB3TN3 USB2P1 A36 USB_PP1 52
PETP1/USB3TP3 USB2N2 USB_PN2 52
C36 USB port USB CONN location
USB2P2 USB_PP2 52
AT31 A34 TP
AR31 PERN2/USB3RN4 USB2N3 C34 USB_PN3 52 3
PERP2/USB3RP4 USB2P3 USB_PP3 52 USB port 2
B33 TP
BD33 USB2N4 D33 USB_PN4 45
PETN2/USB3TN4 USB2P4 USB_PP4 45 TP
BB33 F31
PETP2/USB3TP4 USB2N5 USB_PN5 45
G31 Camera
USB2P5 K31 USB_PP5 45
AW33 USB2N6 L31
53 PCIE_RXN_WLAN AY33 PERN_3 USB2P6 G29
53 PCIE_RXP_WLAN PERP_3 USB2N7
WLAN H29
C2403 1 2 0.1UF/16V PCIE_TXN_WLAN_C BE34 USB2P7 A32
53 PCIE_TXN_WLAN PETN_3 USB2N8 USB_PN8 40
C2404 1 2 0.1UF/16V PCIE_TXP_WLAN_C BC34 C32 Card Reader
53 PCIE_TXP_WLAN PETP_3 USB2P8 USB_PP8 40
A30
AT33 USB2N9 C30 USB_PN9 53
33 PCIE_RXN_LAN PERN_4 USB2P9 USB_PP9 53 WIFI/BT module
33 PCIE_RXP_LAN AR33 B29
PERP_4 USB2N10 D29
LAN USB2P10
C2407 1 2 0.1UF/16V PCIE_TXN_LAN_C BE36 A28
33 PCIE_TXN_LAN PETN_4 USB2N11
33 PCIE_TXP_LAN C2408 1 2 0.1UF/16V PCIE_TXP_LAN_C BC36 C28
PETP_4 USB2P11 G26

PCIe
AW36 USB2N12 F26
AV36 PERN_5 USB2P12 F24

USB
PERP_5 USB2N13 G24
BD37 USB2P13
BB37 PETN_5
PETP_5
USB3RN1
AR26
USB3_RX1_N 52
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AY38 AP26
AW38 PERN_6
PERP_6
USB3RP1
USB3TN1
BE24
BD23
USB3_RX1_P
USB3_TX1_N
52
52 https://t.me/biosarchive
BC38 USB3TP1 AW26 USB3_TX1_P 52
PETN_6 USB3RN2 USB3_RX2_N 52
BE38 AV26
PETP_6 USB3RP2 USB3_RX2_P 52
BD25
AT40 USB3TN2 BC24 USB3_TX2_N 52
PERN_7 USB3TP2 USB3_TX2_P 52
C AT39 AW29 C
PERP_7 USB3RN5 AV29
BE40 USB3RP5 BE26
BC40 PETN_7 USB3TN5 BC26
PETP_7 USB3TP5 AR29
AN38 USB3RN6 AP29
AN39 PERN_8 USB3RP6 BD27
PERP_8 USB3TN6 BE28
BD42 USB3TP6
BD41 PETN_8 K24 USB_BIAS# R2416 1 2 22.6Ohm
PETP_8 USBRBIAS# GND +3VSUS_ORG
K26
USBRBIAS
USBCOMP (R2416): TIE TRACES TOGETHER CLOSE
+1.5VS R2402 2 1 0Ohm PCIE_IREF BE30 M33 TO PINS,WITH LENGTH NO
PCIE_IREF TP24 L33 LONGER THAN 450 MILS TO RESISTOR
TP23
BC30 P3 OC0#/GPIO59 7 8 RN2401D
TP11 OC0#/GPIO59 V1 1 10KOhm 2
OC1#/GPIO40 RN2401A
OC1#/GPIO40 10KOhm
U2 OC2#/GPIO41 3 4 RN2401B
OC2#/GPIO41 10KOhm
BB29 P1 OC3#/GPIO42 1 2 RN2402A
TP6 OC3#/GPIO42 7 10KOhm 8
M3 OC4#/GPIO43 RN2402D
OC4#/GPIO43 10KOhm
T1 OC5#/GPIO9 5 6 RN2401C
1 2 7.5KOhm OC5#/GPIO9 3 10KOhm 4
+1.5VS R2401 PCIE_RCOMP BD29 N2 OC6#/GPIO10 RN2402B
PCIE_RCOMP OC6#/GPIO10 10KOhm
M1 OC7#/GPIO14 5 6 RN2402C
OC7#/GPIO14 10KOhm

Place within 500 mils of PCH


POINT
02V000000013

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B B

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A
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Title : PCH(5)_PCI,NVRAM,USB
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
C PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 24 of 104
5 4 3 2 1
5 4 3 2 1

+3VS +3VS 4,16,17,20,21,22,23,26,27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92

+3VSUS_ORG
BIOS Rev. SKU +VCCDSW
+3VSUS_ORG

+VCCDSW 22,27
20,21,22,24,26,27

+3VS +3VS +3VS +3VS +3VS +3VS


ID0 ID1 ID2 PCB Rev.

0 0 0 R1.0
1 0 0 R1.1 PCB_ID3 PCB_ID4 PCB_ID5 PCB_ID6 PCB_ID9 PCB_ID10 PCB_ID11 PCB_ID12 PCB_ID13 PCB_ID14 PCB_ID15

1
0 1 0 R2.0 R2525 R2527 R2553 R2562 R2561 R2560
1 1 0 R2.1 1: Starndard 1: Premium
1:USB3.0*2 1: HDMI 1: Zero_ODD 1: UMA 1: S&M 1: eDP 1. Disable KB_LED 1: USB3.0 1: PS/2+SMBUS TP
0 0 1 TBD 10KOhm 10KOhm
@
10KOhm
@
10KOhm
@
10KOhm
@
10KOhm
/U3_2
1 0 1 TBD 0: Entry 0: Mainstream

2
0:USB3.0*1 0: no HDMI 0: Non Zero ODD 0: PX 0: NoS&M 0: LVDS 0. Enable KB_LED 0: non USB3.0 0: PS/2 TP
0 1 1 TBD PCB_ID0
PCB_ID1
1 1 1 TBD PCB_ID2
PCB_ID3

D
R1.1 2/19 PCB_ID4
PCB_ID5 D

CPU. PWR

1
R2526 R2528 R2554 R2564 R2565 R2563
ID7 ID8 CPU PWR. 10KOhm 10KOhm 10KOhm 10KOhm 10KOhm 10KOhm
@ /U3_1

2
0 0 CPU 17W @

1 0 CPU 35W
0 1 CPU 45W
1 1 TBD GND GND GND GND GND GND
LPT_PCH_M_EDS
U2001F

PCB_ID2 AT8
BMBUSY#/GPIO0
+3VSUS_ORG PCB_ID3 F13 +3VS +3VS +3VS +3VS +3VS +3VS
TACH1/GPIO1
PCB_ID4 A14
EXT_SMI# R2529 2 1 1KOhm TACH2/GPIO6
PCB_ID5 G15 CPU/Misc
TACH3/GPIO7

1
PM_LANPHY_EN R2538 2 1 10KOhm GPIO8 Y1
T2501 GPIO8 R2572 R2570 R2568 R2582 R2581 R2576
0925 Ken
R2538: 1 PM_LANPHY_EN K13
WLAN_ON R2591 2 @ 1 100KOhm Stuff -> non Intel LAN LAN_PHY_PWR_CTRL/GPIO12 AN10 10KOhm 10KOhm 10KOhm 10KOhm 10KOhm 10KOhm
No stuff -> Intel LAN( Pull up on chip side) TP14 A20GATE 30
SP2501 1 2 R0402 GPIO15 AB11 /HDMI @ @ /UMA @
30,44 EXT_SMI#

2
1120 Ken GPIO15 AY1 H_PECI_R 0Ohm 1 @ 2 R2514 43Ohm
2 1 100KOhm AN2 PECI H_PECI 4 1 2 R2515
BT_ON/OFF# R2592 @ GPIO16 0917 Ken PCB_ID6
SATA4GP/GPIO16 H_PECI_EC 30
AT6 PCB_ID7
RCIN# RCIN# 30

1
12/3 R1.1 DGPU_PWROK C14 GPIO PCB_ID8
2 1 10KOhm 87,91,92 DGPU_PWROK TACH0/GPIO17 AV3 PCB_ID8 23
GPIO8 R2531 @ C2501 PCB_ID9
PROCPWRGD H_CPUPWRGD 4 PCB_ID9 23
0927 Ken 0920 Ken BB4 @ 47PF/50V PCB_ID10
56 WLAN_LED

2
SCLOCK/GPIO22 PCB_ID10 23
0928 JR AV1 PM_THRMTRIP# 390Ohm 1 1% 2 R2516 PCB_ID11
0928 JR Y10 THRMTRIP# H_THRMTRIP# 4,32 PCB_ID11 23
GPIO57 R2541 2 1 10KOhm 1KOhm 1 @ 2 R2566
53 BT_ON/OFF# GPIO24 +V1.05VS_PCH_VCC
@ AU4 GND close to EC
DSW R11 PLTRST_PROC# PCH_PLTRST_CPU 4
GPIO27
GPIO27 0920 Ken

1
N10
VSS3 GND
GPIO8 R2590 2 @ 1 10KOhm AD11 R2569 R2571 R2567 R2579 R2574 R2573
53 WLAN_ON GPIO28
12/3 R1.1 GPIO34 1203 Ruby AN6 10KOhm 10KOhm 10KOhm 10KOhm 10KOhm 10KOhm
GPIO34 @ @ @ /PX @

2
0917 Ken AP1 THRMTRIP#
GND 46 CRT_IN# GPIO35/NMI#
Intel is recommended that motherboard designs implement a
GPIO36 AT3
+3VS SATA2GP/GPIO36 pull-up resistor site on the THRMTRIP# signal to the
FDI_OVRVLTG AK1 PCH 1.05V Core VR
C SATA3GP/GPIO37 GND GND GND GND GND GND C
DGPU_PWROK R2539 2 1 10KOhm PCB_ID0 AT7 0917 Ken
SLOAD/GPIO38
12/3 R1.1 PCB_ID1 AM3 A2
1031 Daniel SDATAOUT0/GPIO39 VSS4 A41
GPIO69 R2545 2 1 10KOhm PCB_ID6 AN4 VSS13 A43
SDATAOUT1/GPIO48 VSS14 A44
GPIO34 R2537 2 1 10KOhm AK3 VSS12 B1 +3VS +3VS +3VS
1203 Ruby 51 SATA_ODD_PRSNT#_R SATA5GP/GPIO49 VSS11 B2
GPIO57 U12 VSS10 B44
GPIO16 R2546 2 1 10KOhm GPIO57 VSS21 B45
C16 VSS9 BA1
51 SATA_ODD_PWRGT TACH4/GPIO68 VSS1
SATA_ODD_PRSNT#_R R2520 2 1 10KOhm BC1

1
0925 Ken 12/3 R1.1 GPIO69 1031 Daniel D13 VSS2 BD1
TACH5/GPIO69 VSS8 BD2 R2588 R2584 R2593
GPIO70 G13 VSS6 BD44
TACH6/GPIO70 VSS7 BD45 10KOhm 10KOhm 10KOhm
PCB_ID7 H15 VSS5 BE2 @ /SMBus

2
TACH7/GPIO71 VSS20 BE3
VSS19 D1 PCB_ID12
+VCCDSW VSS18 PCB_ID12 21
BE41 E1
BE5 VSS25 NCTF VSS17 E45 PCB_ID14
VSS24 VSS16 PCB_ID14 21
C45 A4
A5 VSS23 VSS15 PCB_ID15
2 1 10KOhm VSS22 PCB_ID15 21
GPIO27 R2548 @

POINT

1
02V000000013 GND
GND R2587 R2583 R2594
1KOhm
10KOhm 10KOhm /PS2

2
@ @

remove DDR_VOLT_DEL GND GND GND


0920 Ken
IO Flexible: +3VS R1.1 2/19
USB3 Port 3 PCIE Port2 Mode (USB3P3_PCIEP2_MODE)
R2518 1 1% 2 1KOhm FDI_OVRVLTG R2519 1 2 100KOhm GPIO70 R2556 2 @ 1 10KOhm USB3p3_tach6_gp70 pin is a ‘0’, then Root Port 2 is
+3VS GND assigned to USB3 Port 3, else it is assigned to PCI Express.
@
Functional Strap Definitions
Usage: TLS Confidentiality(Intel Crypto Transport Layer Security)
B "0" = Disable USB3 Port 2 PCIE Port1 Mode (USB3P2_PCIEP1_MODE) B
"1" = Enable
GPIO70 R2558 2 @ 1 10KOhm
USB3p2_tach7_gp71 pin is a ‘0’, then Root Port 1is
assigned to USB3 Port 2, else it is assigned to PCI Express.
GPIO36 R2589 1 2 10KOhm
GND
0925 Ken

Functional Strap Definitions GND


Usage: Reserved

Clear password for TODs required


Place ONTO D-part
JRST2501 1 2 GPIO16
1 2
SGL_JUMP

GND

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A
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Title : PCH(6)_CPU,GPIO,MISC
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
D PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 25 of 104
5 4 3 2 1
5 4 3 2 1

+VCCA_DAC_1_2
B2604
1 2 +1.5VS

1
1kOhm/100Mhz
C2612 C2613 C2614 C2621
0.01UF/50V 0.1UF/16V 10UF/6.3V 22UF/6.3V

2
@
LPT_PCH_M_EDS
U2001G GND GND GND GND
2/4 R1.1
LPT_PCH_M_EDS +V3.3S_ADACBG
U2001J P45 70mA
VCCADAC1_5 GND
1.29A 0Ohm
AL34 K39 AA24 P43 1 2
VSS116 VSS96 +V1.05VS_PCH_VCC VCC7 CRT DAC VSS26 +3VS +VTT_PCH_VCCIO
AL38 L2 AA26 @ R2631
VSS115 VSS95 VCC8

1
D D
AL8 L44 AD20 M31 13mA C2623 1 2 10UF/6.3V GND 0Ohm
AM14 VSS114 VSS94 M17 C2601 C2602 C2603 C2604 AD22 VCC9 VCCADACBG3_3 +V1.5S_VCCAPLL_FDI 1 2
VSS113 VSS93 VCC11 +1.5VS
AM24 M22 10UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V AD24 R2632

2
AM26 VSS112 VSS92 N12 AD26 VCC10 BB44 +V1.05S_VCC_EXP R2634 2 1 0Ohm
AM28 VSS111 VSS40 N35 AD28 VCC12 VCCVRM2
VSS91 VSS42 VCC13

1
FDI
AM30 N39 GND GND GND GND AE18 AN34 vx_r1206_h28
AM32 VSS90 VSS41 N6 AE20 VCC1 VCCIO1 C2610 C2615 C2608 C2607 C2611 C2616
AM16 VSS110 VSS43 P22 AE22 VCC17 AN35 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 10UF/6.3V

2
AN36 VSS118 VSS45 P24 AE24 VCC2 VCCIO2 +3VS
AN40 VSS89 VSS44 P26 AE26 VCC16 R30 +3VS_VCC_GIO
AN42 VSS88 VSS48 P28 AG18 VCC15 HVCMOS VCC3_3_R30 R32 0Ohm
AN8 VSS117 VSS47 P30 AG20 VCC14 VCC3_3_R32 GND 0Ohm 1 2
AP13 VSS109 VSS46 P32 AG22 VCC6 Y12 1 T2601 1 2 R2633
VSS108 VSS49 VCC5 DCPSUS1 +3VSUS_ORG

1
AP24 R12 AG24 R2630
VSS87 VSS50 VCC4

1
AP31 R14 Y26 AJ30 C2618
VSS107 VSS53 VCC3 VCCSUS3_3_1 +3VSUS_VCCPSUS

Core
AP43 R16 AJ32 C2622 0.1UF/16V

2
AR2 VSS86 VSS52 R2 VCCSUS3_3_2 0.1UF/16V

2
AK16 VSS85 VSS51 R34 AJ26 1 T2602 +1.5VS
AT10 VSS84 VSS55 R38 C2609 1 2 1UF/6.3V R2606 1 2 5.1Ohm +PCH_VCCDSW U14 USB3 DCPSUS3_1 AJ28 GND
VSS83 VSS54 GND DCPSUSBYP DCPSUS3_2
AT15 R44 AA18 AK20 +V1.05S_VCC_EXP GND 0Ohm
AT17 VSS82 VSS56 R8 U18 VCCASW12 VCCIO3 AK26 +VCCAPLL_USB3 1 2
AT20 VSS37 VSS58 T43 0.67A U20 VCCASW11 VCCVRM3 AK28 R2635
VSS36 VSS57 VCCASW1 VCCVRM4

1
AT26 U10 U22 0Ohm
VSS35 VSS60 +V1.05VM_VCCASW VCCASW2
AT29 U16 U24 BE22 +VCCAPLL_EXP 1 2 C2624 @
VSS38 VSS59 VCCASW3 VCCVRM5 +1.5VS
AT36 U28 V18 PCIe/DMI 1 2 R2637 1UF/6.3V
GND

2
VSS34 VSS61 VCCASW9

1
AT38 U34 V20 AK18 C2619 10UF/6.3V
D42 VSS80 VSS62 U38 C2625 C2626 C2627 V22 VCCASW10 VCCIO4 0Ohm
VSS33 VSS63 VCCASW4 @
AV13 U42 22UF/6.3V 1UF/6.3V 1UF/6.3V V24 AN11 +VCCAPLL_SATA3 1 2 +1.5VS GND

2
AV22 VSS32 VSS65 U6 Y18 VCCASW5 VCCVRM1 R2636
VSS119 VSS64 VCCASW6

1
SATA
AV24 V14 Y20 AK22
AV31 VSS39 VSS66 V16 Y22 VCCASW7 VCCIO9 C2620
AV33 VSS28 VSS67 V26 GND GND GND VCCASW8 AM18 10UF/6.3V

2
BB25 VSS31 VSS68 V43 VCCIO11 AM20 @
AV40 VSS29 VSS71 W2 VCCIO10 AM22
AV6 VSS30 VSS70 W44 VCCMPHY VCCIO5 AP22
AW2 VSS106 VSS69 Y14 VCCIO6 AR22 GND
F43 VSS105 VSS73 Y16 VCCIO7 AT22
AY10 VSS81 VSS72 Y24 VCCIO8
AY15 VSS104 VSS74 Y28
C AY20 VSS103 VSS76 Y34 C
AY26 VSS102 VSS75 Y36 POINT
AY29 VSS101 VSS78 Y40 02V000000013
AY7 VSS100 VSS77 Y8
B11 VSS99 VSS79
B15 VSS98
VSS97

POINT
02V000000013
GND GND

+1.05VS +V1.05VS_PCH_VCC
JP2601 1.29A +V1.05VM_VCCASW +V1.05VM_VCCASW 27
1 2
1 2
+V1.05VS_PCH_VCC +V1.05VS_PCH_VCC 25
2MM_OPEN_5MIL

+V1.05VM_VCCASW +VTT_PCH_VCCIO +VTT_PCH_VCCIO 27


JP2602
0.67A +1.05VS +1.05VS 4,27,32,57,80,82
2 1
2 1
+1.5VS +1.5VS 20,21,22,24,27,53,57,84
2MM_OPEN_5MIL
B +VTT_PCH_VCCIO +3VS +3VS 4,16,17,20,21,22,23,25,27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92 B
JP2603 3.629 +VCCA_DAC_1_2 +VCCA_DAC_1_2
1 2
1 2
+V3.3S_ADACBG +V3.3S_ADACBG
2MM_OPEN_5MIL
+3VSUS_VCCPSUS +3VSUS_VCCPSUS 27

https://t.me/schematicslaptop
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A
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https://t.me/biosarchive

Title : PCH(7)_POWER,GND
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
Custom PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 26 of 104
5 4 3 2 1
5 4 3 2 1

U2001K LPT_PCH_M_EDS

AA16 B19
AA20 VSS136 VSS171 B23
AA22 VSS197 VSS170 B27
AA28 VSS196 VSS169 B31
D AA4 VSS195 VSS168 B35 +VCCDSW +3VSUS_ORG D
AB12 VSS194 VSS167 B39
AB34 VSS193 VSS166 B7
AB38 VSS192 VSS165 BA40 R2704 1 2 0Ohm +3VSUS_VCCPUSB +3VSUS_VCCPSUS
VSS146 VSS164 +3VSUS_ORG LPT_PCH_M_EDS
AB8 BD11 U2001H
VSS128 VSS163

1
AC2 BD15
AC44 VSS145 VSS162 BD19 C2705
AD14 VSS191 VSS161 AY36 0.1UF/16V

2
AD16 VSS190 VSS160 AT43 R24 R20 +VCCDSW R2714 1 2 0Ohm
AD18 VSS189 VSS159 BD31 R26 VCCSUS3_3_9 VCCSUS3_3_6 R22
VSS204 VSS129 VCCSUS3_3_3 VCCSUS3_3_7

1
AD30 BD35 GND R28 +VCCSST 1 2 GND
AD32 VSS203 VSS130 BD39 U26 VCCSUS3_3_4 GPIO/LPC
0.1UF/16V C2716 +3VS C2715
AD40 VSS202 VSS131 BD7 VCCSUS3_3_5 A16 0.1UF/16V

2
AD6 VSS209 VSS132 D25 M24 VCCDSW3_3
VSS208 VSS144 GND VSS27
AD8 AV7 AA14 0Ohm
AE16 VSS188 VSS133 F15 R2726 1 2 0Ohm +1.05VS_VCCAUSB U35 DCPSST +3VS_VCCPCORE R2730 1 2
VSS187 VSS143 +1.05VS VCCUSBPLL
AE28 F20 AE14 GND

USB
VSS186 VSS134 VCC3_3_2

1
AF38 F29 R2727 1 2 0Ohm +3VS_VCCAUBG L24 AF12 +VTT_PCH_VCCIO
VSS185 VSS142 +3VS VCC3_3_1 VCC3_3_3
AF8 F33 C2714 AG14 0Ohm C2701
AG16 VSS184 VSS135 BC16 0.1UF/16V C2741 1 2 0.1UF/16V U30 VCC3_3_4 +V1.05S_VCCAUX 1 2 0.01UF/50V
GND

2
AG2 VSS183 VSS121 D4 V28 VCCIO12 R2716 +3VSUS_ORG
AG26 VSS201 VSS120 G2 1 R2728 2 0Ohm +1.05VS_VCCUSBCORE V30 VCCIO14 U36
VSS200 VSS122 +VTT_PCH_VCCIO VCCIO13 VCCIO15
AG28 G38 GND vx_r0402_small GND Y30 +3VSUS_VCCPAZSUS 1 0Ohm 2 GND
AG44 VSS199 VSS123 G44 1 2 VCCIO16 R2717
VSS198 VSS124

1
AJ16 G8 +VCCAXCK_VRM C2759 0.1UF/16V T2701 1 Y35 Azalia
+VCC_RTC
AJ18 VSS182 VSS125 H10 R2729 DCPSUS2 A26 C2717
AJ20 VSS148 VSS126 H13 1 2 0Ohm AF34 VCCSUSHDA
+1.5VS 0.1UF/16V

2
VSS147 VSS127 VCCVRM7

1
AJ22 H17 0Ohm C2722 C2723 C2760
AJ24 VSS150 VSS139 H22 1 1 2 +1.05VS_VCC_AXCK_DCB AP45 K8 +VCCPRTCSUS
VSS149 VSS140 +1.05VS VCC20 VCCSUS3_3_8
AJ34 H24 C2742 R2705 GND 0.1UF/16V 0.1UF/16V1UF/6.3V

2
VSS181 VSS141

1
AJ38 H26 10UF/6.3V C2744 +1.05VS_VCC_SSCFF Y32 A6
2

AJ6 VSS180 VSS138 H31 C2743 1UF/6.3V VCCCLK1 VCCRTC


AJ8 VSS179 VSS158 H36 @ 10UF/6.3V +3VS_VCC_FLEX0 M29 RTC P14 +VCCRTCEXT GND

2
AK14 VSS178 VSS137 H40 GND VCCCLK3_3_1 DCPRTC1 P16 @
VSS177 VSS157 DCPRTC2

1
AK24 H7 +3VS_VCC_FLEX1 L29 +1.05VS_VCCPCPU 1 2 R2731 +3VS +1.05VS
VSS176 VSS156 VCCCLK3_3_2 +VCCIO2PCH
AK43 K10 0Ohm C2718

1
AK45 VSS175 VSS155 K15 GND +3VS_VCC_FLEX23 L26 AJ12 1 2 R2732
+1.05VS 0.1UF/16V

2
AL12 VSS174 VSS154 K20 M26 VCCCLK3_3_3 V_PROC_IO_1 AJ14 C2719 C2720 C2754 0Ohm
CPU
VSS173 VSS153 VCCCLK3_3_4 V_PROC_IO_2

2
AL2 K29 0.1UF/16V 0.1UF/16V 1UF/6.3V

2
BC22 VSS172 VSS152 K33 +3VS_VCC_ASEPCI U32 GND R2721 R2720
VSS206 VSS151 VCCCLK3_3_5
Unstuff R2731, stuff R2732
BB42 BC28 V32 AD12

ICC
+3VM_VCCPSPI 0Ohm 0Ohm
VSS205 VSS207 VCCCLK3_3_6 SPI VCCSPI @
Intel MOW WW09: renamed
C +VCCCLKF135 AD34 GND C
VCCIO2PCH to RSVD R1.1 R1.10

1
VCCCLK2 P18
+1.05VS_VCC_SSCFF AA30 VCC18 P20 +3VS_VCCPFUSE
POINT VCCCLK3 VCC19
AA32
VCCCLK4

1
02V000000013 L17 +PCH_VCC_1_1_20 R2722 1 0Ohm 2 C2756
Fuse VCCASW13 +V1.05VM_VCCASW
+1.05VS_VCCCLKF100 AD35 1UF/6.3V
GND GND VCCCLK5 R18 +PCH_VCC_1_1_21 R2723 1 0Ohm 2 +V1.05VM_VCCASW

2
+1.05VS_VCCSSCF100 AG30 VCCASW14
AG32 VCCCLK6
VCCCLK7 AW40 +V1.5S_VCCATS R2724 1 2
VCCVRM6 +1.5VS
+1.05VS_VCCCLKF100 AD36 0Ohm GND
VCCCLK8 AK30
+1.05VS_VCCSSCF100 AE30 VCC3_3_5
Thermal
AE32 VCCCLK9 AK32
VCCCLK10 VCC3_3_6

+1.05VS +3VS +3VS POINT


+3VS_VCCPTS R2725 1 2 +3VS
02V000000013 0Ohm

1
0Ohm 0Ohm 0Ohm
1 2 +1.05VS_VCC_SSCFF 1 2 +3VS_VCC_FLEX0 1 2 +3VS_VCC_FLEX1 C2721
R2706 R2707 R2708 0.1UF/16V

2
1

C2745 C2746 C2747 +3VSUS_ORG +3VA


1UF/6.3V 1UF/6.3V 1UF/6.3V
2

GND

+3VS +3VS +1.05VS R2719 1 2 0Ohm


GND GND GND +3VM_VCCPSPI
0Ohm 0Ohm 0Ohm @
1 2 +3VS_VCC_FLEX23 1 2 +3VS_VCC_ASEPCI 1 2 +VCCCLKF135 20mA +VCCPRTCSUS R2718 1 2 0Ohm
R2709 R2710 R2711
1

1
C2748 C2749 C2750 C2755 +3VM_SPI

1
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V C2753
R2617 2 1 0Ohm 1UF/6.3V
2

2
GND
+1.05VS GND +1.05VS GND GND
GND
0Ohm 0Ohm
B 1 2 +1.05VS_VCCCLKF100 1 2 +1.05VS_VCCSSCF100 B
R2712 R2713
1

C2751 C2752
1UF/6.3V 1UF/6.3V
Deep sleep mode: JP2703
Normal mode: JP2704
2

GND GND

+3VSUS_ORG
261mA

0921Ken

+3VSUS
+V1.05VM_VCCASW +V1.05VM_VCCASW 26
@JP2704
2 1
2 1
1MM_OPEN_M1M2 +3VSUS +3VSUS 22,23,28,30,33,37,53,81,92

+3VSUS_ORG +3VSUS_ORG 20,21,22,24,25,26

+1.5VS +1.5VS 20,21,22,24,26,53,57,84

+3VS +3VS 4,16,17,20,21,22,23,25,26,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92

+1.05VS +1.05VS 4,26,32,57,80,82

+VTT_PCH_VCCIO +VTT_PCH_VCCIO 26

+VCCAXCK_VRM +VCCAXCK_VRM 21

+3VSUS_VCCPSUS +3VSUS_VCCPSUS 26

https://t.me/schematicslaptop https://t.me/schematicslaptop +3VA +3VA 20,30,33,57,60,65,81,88,93

+VCC_RTC +VCC_RTC 20,22

A
https://t.me/biosarchive https://t.me/biosarchive +VCCIO2PCH +VCCIO2PCH 6 A

Title : PCH(8)_POWER,GND
BG1\CORE Engineer: Ruby Tsai
Size Project Name Rev
Custom PT10SG 1.1
Date: Tuesday, February 26, 2013 Sheet 27 of 104
5 4 3