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Design for Reliable Data Processing and Storage M Cecilia Metra
Fault Models: Summary
Fault Models:
Stuck-at (SA)
Transistor Stuck-On (SON)
Resistive Bridging (BF)
Delay faults (DF)
Crosstalk (CF)
Transistor Stuck-Open (SOP)
Transient faults (TF)
Fault equivalence & fault collapsing
Fault dominance & fault collapsing
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Design for Reliable Data Processing and Storage M Cecilia Metra
Fault Models
Goal: to reduce the numerous multiplicity of
physical defects to a more limited number.
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Design for Reliable Data Processing and Storage M Cecilia Metra
Convention
We talk about “stuck-at faults, etc” referring to all
physical defects describable by the stuck-at fault
model, etc.
Example:
f k
Courtesy of V. D. Agrawal, Agere (USA)
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Design for Reliable Data Processing and Storage M Cecilia Metra
Multiple Stuck-at Faults
Statistically,
tests for single SAs can detect also a
high number of multiple SAs.
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Design for Reliable Data Processing and Storage M Cecilia Metra
IC Testing
The (traditional) testing methodology for an IC
consists in :
1. apply a proper sequence of test vectors able to:
activate each fault
propagate the fault effects to the IC primary
outputs
2. Compare the produced outputs with those
expected for the fault-free IC.
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Design for Reliable Data Processing and Storage M Cecilia Metra
Testing for SAs: Example (II)
h stuck-at 0
Possible test vector (activation + propagation):
(a, b) = (1, 0)
Erroneous value
Correct value
c j
0(1)
SA0
a d
1 g h 1(0)
z
0 1 i
b e 1
f k
Example test vector h SA0 Courtesy of V. D. Agrawal, Agere (USA)
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Design for Reliable Data Processing and Storage M Cecilia Metra
Fault Equivalence & Fault Collapsing
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Design for Reliable Data Processing and Storage M Cecilia Metra
Equivalence: Example
sa0 sa0
sa1 sa1
sa0 sa1 sa0 sa1 WIRE
sa0 sa1 sa0 sa1
AND OR
sa0 sa1
NOT
sa1 sa0
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Collapse ratio = ----- = 0.625
32 14
Design for Reliable Data Processing and Storage M Cecilia Metra
Fault Dominance &
Fault Collapsing
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Design for Reliable Data Processing and Storage M Cecilia Metra
Dominance: Example
F2 dominates F1
Test per F2 F2 removed
F1
s-a-1 001
F2
s-a-1 110 010
000
101 011
100
s-a-1
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Design for Reliable Data Processing and Storage M Cecilia Metra
Effects due to BFs
In a CMOS IC, when a BF is activated conductive
path between power supply and ground.
Thus:
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Design for Reliable Data Processing and Storage M Cecilia Metra
Testing for SOPs: Example (I)
VDD
A
1 0
Stuck-
open
0 0
B
C
0 1(0)
Circuit OK
Faulty Circuit
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Design for Reliable Data Processing and Storage M Cecilia Metra
Delay Faults
Describes all physical defects whose effect on the IC
behavior is to affect its dynamic characteristics.
Particularly, there are two delay fault models:
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Design for Reliable Data Processing and Storage M Cecilia Metra
Radiations and Alpha Particles
Radiative decay of Uranium and Thorium
impurities present in packages generation of Alpha
particles (= Helium atoms which lost the electrons).
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Design for Reliable Data Processing and Storage M Cecilia Metra
Radiations and Alpha Particles (cnt’d)
Alpha particle (neutron) hitting the Si penetration
in the Si and generation of electron – hole coupes
droop of energy along the path.
The penetration depth is a function of the initial
energy and of the material and circuit characteristics.
Distortion of the depleted region (funneling).
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Design for Reliable Data Processing and Storage M Cecilia Metra
Radiations and Alpha Particles (cnt’d)
If the Alpha particle penetrates in a region
interested by an electric field (e.g., the depleted region
of the a pn junction) generation of e– hole couples:
[Baumann2001] 41
Design for Reliable Data Processing and Storage M Cecilia Metra
Cosmic Rays and Altitude
The sensitivity to cosmic rays increases with the
altitude.
[Ogorman94] 42
Design for Reliable Data Processing and Storage M Cecilia Metra
Fault Probability
It has been verified that the the most likely faults in VLSI
CMOS ICs (for general applications) are:
stuck-at
transistor stuck-on and resistive bridging
delay
stuck-open
Transient faults are the most likely for VLSI CMOS ICs
for space and avionic applications.
Crosstalk and transient faults are very likely for VLSI
CMOS ICs implemented by technologies below 0.1m
(Very Deep Sub-Micron (VDSM) technologies) also for
general applications
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Design for Reliable Data Processing and Storage M Cecilia Metra
Faults Affecting Memory Arrays
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Design for Reliable Data Processing and Storage M Cecilia Metra
Review of Memory Operation
Address
Cells to be read/written
Column Decoder
are selected by
activating their row and
column, by decoding the
address bits
Decoder
Memory
Row
Memory
Cell Array
Cell Array
Once the cells are selected:
Address For read operations
Decoder (R/#W Enable = 1)
Read/Write
Sense Write
Drivers the content of the
Logic
Amp
selected cells is
R/#W read by the sense
Data Registers amplifiers and
Enable
transferred to the
Data out/in data registers 45
Design for Reliable Data Processing and Storage M Cecilia Metra
Review of Memory Operation (cnt’d)
Address
Cells to be read/written
Column Decoder
are selected by
activating their row and
column, by decoding the
address bits
Decoder
Memory
Row
Memory
Cell Array
Cell Array
Once the cells are selected:
Address For write operations
Decoder (R/#W Enable = 0)
Read/Write
Sense Write
Drivers the content of the
Logic
Amp
data registers is
R/#W written into the
Data Registers selected cells by
Enable
the write drivers
Data out/in 46
Design for Reliable Data Processing and Storage M Cecilia Metra
Faults Affecting Memory Arrays [1]
Stuck-At Faults (SAs)
Effect: the logic value of a cell, or a line, is SA0 or 1
[1] A. Van De Goor, “”, IEEE Design and Test of computers, 2003. 47
Design for Reliable Data Processing and Storage M Cecilia Metra
Faults Affecting Memory Arrays [1] (cnt’d)
Data Retention Faults (DRFs)
Effect: the stored logic value in a cell is lost after a certain
period of time during which the cell is not accessed.
[1] A. Van De Goor, “”, IEEE Design and Test of computers, 2003. 48
Design for Reliable Data Processing and Storage M Cecilia Metra