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## Creating Library
-bus_naming_style {[%d]} \
-mw_reference_library { \
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m \
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/milkyway/saed32nm_lvt_1p9m \
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt/milkyway/saed32nm_hvt_1p9m \
/tools/libraries/28nm/SAED32_EDK/lib/sram_lp/milkyway/saed32sram_lp \
/tools/libraries/28nm/SAED32_EDK/lib/pll/milkyway/SAED32_PLL_FR/ \
set_tlu_plus_files -max_tluplus
/tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_1p9m_Cmax.tluplus \
-min_tluplus
/tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_1p9m_Cmin.tluplus \
-tech2itf_map /tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_tf_itf_tluplus.map
link_physical_library
link
read_sdc /home/guepd2211ce18/srkrao/min_soc_24/inputs/minsoc.sdc
source scripts/create_path_groups.tcl
#source scripts/derive_pg_connection.tcl
save_mw_cel
======power_plan
# Verify PG Nets
save_mw_cel
=======place_IO_ports=====
place_fp_pins -block_level
====cut_row_near_macro
foreach_in_collection a $my_macros {
set macro_llx [lindex [get_attribute [get_cells $a] bbox_ll] 0]
cut_rows_near_macro 0.5
====drive_pg_connection