A B C D E

1 1

Compal Confidential
2 2

PIQY0 M/B Schematics Document

Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
nVIDIA N12P-GT

3 2010-11-26 3

REV:0.3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 1 of 63
A B C D E
 A B C D E

Compal confidential ZZZ1 ZZZ2 ZZZ3

File Name : PIQY0 POWER & ALS BOARD

LA6881P X7625738L01
X761G@
X7625738L03
X762G@
CAP SENSOR & Slid bar
BOARD
1 Intel 1
nVIDIA N12P-GT
PCI-E X16 Sandy Bridge
VRAM 64*16
DDR3*8 Socket-rPGA988B
37.5mm*37.5mm DDR3-SO-DIMM X2
BANK 0, 1, 2, 3
HDMI Passive Dual Channel UP TO 8G
CONN level shift
100MHz FDI *8 DMI *4 DDR3-1066(1.5V)
2.7GT/s DDR3-1333(1.5V)
optimus 1.0
CRT Connector 2Channel Speaker

2 2
optimus 1.0 Array Digital MIC
LVDS Intel Audio Codec
AZALIA RealTek
Connector
Cougar Point ALC272/ALC5503
Audio Jacks
PCI Express USB(WiMAX)
Stereo
6*PCI-E BUS
Mini card Slot 1 PCI-E(WLAN) FCBGA 951 14*USB2.0
HeadPhone Output
WLAN/WiMAX Microphone Input
25mm*25mm CMOS Camera
PCI Express 6*SATA serial BlueTooth CONN
Mini card Slot 2 (port0,1
SSD support SATA3) USB PORT 2.0 x2(Left)
LPC BUS
Option3.0 x2
USB3.0 SPI ROM
SATA(SSD) BIOS WLAN/WiMAX
3 RENESAS 3

UPD720200
EC
ENE KB930 USB PORT 2.0 x1(Right)
Card Reader
Jmicro JMB389
Broadcom
BCM57781/57780
SD/MMC/MS/XD
10/100/1G LAN
Int.KBD
ESATA HDD AND USB CONN
WLAN/WiMAX Touch Pad SPI ROM (Right)
RJ45 CONN
SATA3.0 HDD CONN
Thermal Sensor SATA3.0 HDD (SSD)
4 4
EMC1403
SATA ODD CONN
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 2 of 63
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Voltage Rails
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

+5VS
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+3VS
power
plane +1.5VS S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VCCP
+5VALW +1.5V +CPU_CORE
+B +VGA_CORE Board ID / SKU ID Table for AD channel
+3VALW +GFX_CORE Vcc 3.3V +/- 5%
+1.8VS Ra/Rc/Re 100K +/- 5%
State +0.75VS Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.05VS 0 0 0 V 0 V 0 V
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
S0 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
O O O O
7 NC 2.500 V 3.300 V 3.300 V
2 2

S3
O O O X BOARD ID Table BOM Structure Table
S5 S4/AC
BTO Item BOM Structure
O O X X Board ID PCB Revision
UMA
0 0.1
S5 S4/ Battery only
UMA Only UMA_ONLY@
O X X X 1
Optimus OPTI@
2
S5 S4/AC & Battery
VRAM X76@
X X X X 3
don't exist HDMI HDMI@
4
Blue Tooth BT@
5
SMBUS Control Table 6
USB3.0
ESATA
USB30@
ESATA@
7
Thermal USB Charger USB_CHG@
WLAN Sensor
SOURCE VGA BATT KB930 SODIMM WWAN PCH No USB Charger NO_CHG@
Unpop @
SMB_EC_CK1
SMB_EC_DA1
KB930
+3VALW
X V
+3VALW
X X X X X USB Port Table
3 External
Codec ALC272 272@
USB 2.0 USB 1.1 Port Codec ALC5503 5503@
SMB_EC_CK2
X X X X X X V USB Port
3 3

KB930 LAN 57781 57781@

SMB_EC_DA2 +3VALW +3VS 0 USB/Cable (Right Side)
UHCI0 LAN 57780 57780@
SMBCLK
SMBDATA
PCH
+3VALW
X X X V
+3VS
V
+3VS
X X 1
2
USB Port (Right Side COMBO)
USB/B (Left Side)
Ventura Feature VENTURA@
UHCI1 Camera CMOS@
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X EHCI1
3
4
USB/B (Left Side)
UHCI2
SML1CLK
SML1DATA
PCH
+3VALW
V
+3VS
X V
+3VS
X X V
+3VS
X 5
6
Camera
VRAM BOM Config
UHCI3 X761G@: X7625738L01 Samsung 1GB
7
Sub: X7625738L02 Hynix 1GB
8
UHCI4 X762G@: X7625738L03 Samsung 2GB
EC SM Bus1 address EC SM Bus2 address 9 Mini Card(WLAN)
Sub: X7625738L04 Hynix 2GB
10
EHCI2 UHCI5
Device Address Device Address 11 GPU BOM Config
Smart Battery 0001 011X b 12 N12P SKU: OPTI@
Thermal Sensor EMC1403-2 1001_101xb UHCI6
13 Blue Tooth GS SKU: GS@
GT SKU: GT@
4 4
PCH SM Bus address
Device Address

DDR DIMM0 1001 000Xb

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/30 Deciphered Date 2011/08 Title
DDR DIMM2 1001 010Xb
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
EMC
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 3 of 63

A B C D E
 5 4 3 2 1

+3VS_VGA

+1.05VS_VGA

D tNVVDD >0 D
+VGA_CORE

tNV-IFPAB_IOVDD >0
+1.8VS_VGA

tNV-FBVDDQ >0
+1.5VS_VGA

1. The ramp rate for any rail must be more than 40us.
2. +VGA_CORE <= +3VS_VGA +0.5V
3. +1.5VS_VGA <= +3VS_VGA +0.5V
4. Optimus follows power sequencing rules
specified in discrete GPU design guide.

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 4 of 63
5 4 3 2 1
 5 4 3 2 1

D D
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+1.05VS impedance = 43 mohms
PEG_ICOMPO signals should be routed with -

1
max length = 500 mils
R1
24.9_0402_1%
- typical impedance = 14.5 mohms
JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
<16> DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
<16> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 A25 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23>
<16> DMI_CRX_PTX_N3 B24 K33 PCIE_CRX_GTX_N15
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N14
PEG_RX#[1] M35
<16> DMI_CRX_PTX_P0 B28 L34 PCIE_CRX_GTX_N13
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12
<16> DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35 PEG Static Lane Reversal - CFG2 is for the 16x

DMI
A24 J32 PCIE_CRX_GTX_N11
<16> DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4]
<16> DMI_CRX_PTX_P3 B23 H34 PCIE_CRX_GTX_N10
DMI_RX[3] PEG_RX#[5] PCIE_CRX_GTX_N9
PEG_RX#[6] H31 1: Normal Operation; Lane # definition matches
G21 G33 PCIE_CRX_GTX_N8 CFG2
<16> DMI_CTX_PRX_N0
E22
DMI_TX#[0] PEG_RX#[7]
G30 PCIE_CRX_GTX_N7 socket pin map definition
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PCIE_CRX_GTX_N6
<16> DMI_CTX_PRX_N2 F21 DMI_TX#[2] PEG_RX#[9] F35
D21 E34 PCIE_CRX_GTX_N5 0:Lane Reversed
<16>

<16>
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 G22
DMI_TX#[3]

DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3 *
D22 D31 PCIE_CRX_GTX_N2
C <16> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PCIE_CRX_GTX_N1 C

PCI EXPRESS* - GRAPHICS

<16> DMI_CTX_PRX_P2 F20 DMI_TX[2] PEG_RX#[14] B33
C21 C32 PCIE_CRX_GTX_N0
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..15] <23>
J33 PCIE_CRX_GTX_P15
PEG_RX[0] PCIE_CRX_GTX_P14
PEG_RX[1] L35
K34 PCIE_CRX_GTX_P13
PEG_RX[2] PCIE_CRX_GTX_P12
<16> FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PCIE_CRX_GTX_P11
<16> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] PCIE_CRX_GTX_P10
<16> FDI_CTX_PRX_N2 E19 G34
FDI0_TX#[2] PEG_RX[5] PCIE_CRX_GTX_P9
F18 G31

Intel(R) FDI
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] PCIE_CRX_GTX_P8
<16> FDI_CTX_PRX_N4 B21 F33
FDI1_TX#[0] PEG_RX[7] PCIE_CRX_GTX_P7
<16> FDI_CTX_PRX_N5 C20 F30
FDI1_TX#[1] PEG_RX[8] PCIE_CRX_GTX_P6
<16> FDI_CTX_PRX_N6 D18 E35
FDI1_TX#[2] PEG_RX[9] PCIE_CRX_GTX_P5
<16> FDI_CTX_PRX_N7 E17 E33
FDI1_TX#[3] PEG_RX[10] PCIE_CRX_GTX_P4
F32
PEG_RX[11] PCIE_CRX_GTX_P3
D34
PEG_RX[12] PCIE_CRX_GTX_P2
<16> FDI_CTX_PRX_P0 A22 E31
FDI0_TX[0] PEG_RX[13] PCIE_CRX_GTX_P1
<16> FDI_CTX_PRX_P1 G19 C33
FDI0_TX[1] PEG_RX[14] PCIE_CRX_GTX_P0
<16> FDI_CTX_PRX_P2 E20 B32
FDI0_TX[2] PEG_RX[15]
<16> FDI_CTX_PRX_P3 G18 PCIE_CTX_GRX_N[0..15] <23>
FDI0_TX[3] PCIE_CTX_GRX_C_N15 C1 PCIE_CTX_GRX_N15
<16> FDI_CTX_PRX_P4 B20
FDI1_TX[0] PEG_TX#[0]
M29 1 2 0.1U_0402_10V6K
C19 M32 PCIE_CTX_GRX_C_N14 C2 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N14
<16> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PCIE_CTX_GRX_C_N13 C3 1 2 0.1U_0402_10V6K
OPTI@ PCIE_CTX_GRX_N13
<16> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2] PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_N12
F17 L32 C4 1 2 0.1U_0402_10V6K
OPTI@
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_N11
L29 C5 1 2 0.1U_0402_10V6K
OPTI@
FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_C_N10 C6 PCIE_CTX_GRX_N10
<16> FDI_FSYNC0 J18 K31 1 2 0.1U_0402_10V6K
OPTI@
+1.05VS FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] PCIE_CTX_GRX_C_N9 C7 PCIE_CTX_GRX_N9
<16> FDI_FSYNC1 J17 K28 1 2 0.1U_0402_10V6K
OPTI@
FDI1_FSYNC PEG_TX#[6] PCIE_CTX_GRX_C_N8 C8 PCIE_CTX_GRX_N8
PEG_TX#[7]
J30 1 2 0.1U_0402_10V6K
OPTI@
FDI_INT H20 J28 PCIE_CTX_GRX_C_N7 C9 1 2 0.1U_0402_10V6K
OPTI@ PCIE_CTX_GRX_N7
<16> FDI_INT FDI_INT PEG_TX#[8]
H29 PCIE_CTX_GRX_C_N6 C10 1 2 0.1U_0402_10V6K
OPTI@ PCIE_CTX_GRX_N6
PEG_TX#[9]
1

FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 1 2 0.1U_0402_10V6K

OPTI@ PCIE_CTX_GRX_N5
<16> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
R7 FDI_LSYNC1 H17 E29 PCIE_CTX_GRX_C_N4 C12 1 2 0.1U_0402_10V6K
OPTI@ PCIE_CTX_GRX_N4
B <16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] B
24.9_0402_1% F27 PCIE_CTX_GRX_C_N3 C13 1 2 0.1U_0402_10V6K
OPTI@ PCIE_CTX_GRX_N3
PEG_TX#[12] PCIE_CTX_GRX_C_N2 C14 PCIE_CTX_GRX_N2
D28 1 2 0.1U_0402_10V6K
OPTI@
PEG_TX#[13] PCIE_CTX_GRX_C_N1 C15 PCIE_CTX_GRX_N1
F26 1 2 0.1U_0402_10V6K
OPTI@
2

PEG_TX#[14] PCIE_CTX_GRX_C_N0 C16 PCIE_CTX_GRX_N0

E25 1 2 0.1U_0402_10V6K
OPTI@
EDP_COMP PEG_TX#[15]
A18 OPTI@ PCIE_CTX_GRX_P[0..15] <23>
eDP_COMPIO PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_P15
eDP_COMPIO and ICOMPO signals A17
eDP_ICOMPO PEG_TX[0]
M28 C17 1 2 0.1U_0402_10V6K
OPTI@
eDP_HPD B16 M33 PCIE_CTX_GRX_C_P14 C18 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P14
should be tied together, then eDP_HPD PEG_TX[1]
M30 PCIE_CTX_GRX_C_P13 C19 1 2 0.1U_0402_10V6K
OPTI@ PCIE_CTX_GRX_P13
PEG_TX[2]
connected to the VCCIO rail PEG_TX[3]
L31 PCIE_CTX_GRX_C_P12 C20 1 2 0.1U_0402_10V6K
OPTI@ PCIE_CTX_GRX_P12
C15 L28 PCIE_CTX_GRX_C_P11 C21 1 2 0.1U_0402_10V6K
OPTI@ PCIE_CTX_GRX_P11
via a single 24.9ohm resistor. D15
eDP_AUX PEG_TX[4]
K30 PCIE_CTX_GRX_C_P10 C22 1 2 0.1U_0402_10V6K
OPTI@ PCIE_CTX_GRX_P10
eDP_AUX# PEG_TX[5]
eDP

K27 PCIE_CTX_GRX_C_P9 C23 1 2 0.1U_0402_10V6K

OPTI@ PCIE_CTX_GRX_P9
PEG_TX[6] PCIE_CTX_GRX_C_P8 C24 PCIE_CTX_GRX_P8
J29 1 2 0.1U_0402_10V6K
OPTI@
PEG_TX[7] PCIE_CTX_GRX_C_P7 C25 PCIE_CTX_GRX_P7
C17 J27 1 2 0.1U_0402_10V6K
OPTI@
eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_C_P6 C26 PCIE_CTX_GRX_P6
F16
eDP_TX[1] PEG_TX[9]
H28 1 2 0.1U_0402_10V6K
OPTI@
C16 G28 PCIE_CTX_GRX_C_P5 C27 1 2 0.1U_0402_10V6K
OPTI@ PCIE_CTX_GRX_P5
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_C_P4 C28 PCIE_CTX_GRX_P4
G15 E28 1 2 0.1U_0402_10V6K
OPTI@
eDP_TX[3] PEG_TX[11] PCIE_CTX_GRX_C_P3 C29 PCIE_CTX_GRX_P3
F28 1 2 0.1U_0402_10V6K
OPTI@
PEG_TX[12] PCIE_CTX_GRX_C_P2 C30 PCIE_CTX_GRX_P2
C18 D27 1 2 0.1U_0402_10V6K
OPTI@
eDP_TX#[0] PEG_TX[13] PCIE_CTX_GRX_C_P1 C31 PCIE_CTX_GRX_P1
E16 E26 1 2 0.1U_0402_10V6K
OPTI@
eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_C_P0 C32 PCIE_CTX_GRX_P0
D16 D25 1 2 0.1U_0402_10V6K
OPTI@
eDP_TX#[2] PEG_TX[15]
F15 OPTI@
eDP_TX#[3]
OPTI@

Sandy Bridge_rPGA_Rev1p0
ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 5 of 63
5 4 3 2 1
 5 4 3 2 1

JCPU1B
D D
R10 0_0402_5% DG1.0
A28 CLK_CPU_DMI_R 1 2
BCLK CLK_CPU_DMI <15>

MISC

CLOCKS
C26 A27 CLK_CPU_DMII#_R R11 1 2
<18> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
0_0402_5%
AN34
SKTOCC#
DPLL_REF_CLK
A16 R12 2 1 1K_0402_5% DG1.0
A15 R13 2 1 1K_0402_5% +1.05VS
DPLL_REF_CLK#
+1.05VS
closs to EC 250~750mils H_CATERR# AL33 CATERR#
R9 1 R14

THERMAL
62_0402_5% 0_0402_5%
1 2 H_PECI_ISO AN33 R8 H_DRAMRST#
<19,45> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2

DDR3
MISC
R15
56_0402_5%
H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 R16 2 1 140_0402_1%
<45> H_PROCHOT# PROCHOT# SM_RCOMP[0]
A5 SM_RCOMP1 R17 2 1 25.5_0402_1% DDR3 Compensation Signals
R19 SM_RCOMP[1] SM_RCOMP2 R18
SM_RCOMP[2] A4 2 1 200_0402_1%
0_0402_5%
1 2 H_THEMTRIP#_R AN32
<19> H_THRMTRIP# THERMTRIP#

AP29 XDP_PRDY# +1.05VS

PRDY# XDP_PREQ#
PREQ# AP27

R22 AR26 XDP_TCK XDP_TMS R20 2 1 51_0402_5%

C TCK

PWR MANAGEMENT
XDP_TMS XDP_TDI C
0_0402_5% AR27 R21 2 1 51_0402_5% PU/PD for JTAG signals

JTAG & BPM

H_PM_SYNC_R TMS XDP_TRST# XDP_TDO R23
<16> H_PM_SYNC 1 2 AM34 PM_SYNC TRST# AP30 2 1 51_0402_5%

AR28 XDP_TDI XDP_TCK R24 2 1 51_0402_5%

R26 TDI XDP_TDO XDP_TRST# R25
AP26 2 1 51_0402_5%
0_0402_5%1 H_CPUPWRGD_R TDO
<19> H_CPUPWRGD 2 AP33 UNCOREPWRGOOD
2

R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5% +3VS

DBR#
R27 1 2 PM_DRAM_PWRGD_R V8
130_0402_5% SM_DRAMPWROK
10K_0402_5%
AT28 XDP_BPM#0
BPM#[0] XDP_BPM#1
AR29
1

BPM#[1] XDP_BPM#2
AR30
BUF_CPU_RST# BPM#[2] XDP_BPM#3
AR33 AT30
RESET# BPM#[3] XDP_BPM#4
AP32
BPM#[4] XDP_BPM#5
AR31
BPM#[5] XDP_BPM#6
AT31
BPM#[6] XDP_BPM#7
AR32
BPM#[7]

Sandy Bridge_rPGA_Rev1p0
ME@

+3VALW
Buffered reset to CPU
+1.5V_CPU_VDDQ
1
C33 +3VS
B +3VS 0.1U_0402_16V4Z B
1

R1295 2 R30
1 2 U1 200_0402_5% +1.05VS
1
C34
5

10K_0402_5% 0.1U_0402_16V4Z
2

1
P

B PM_SYS_PWRGD_BUF R32 2
4
O 75_0402_5%
<16> PM_DRAM_PWRGD 2
A
G

5
74AHC1G09GW_TSSOP5 R34 U2
3

@ 43_0402_1% 1 3V

P
R33 BUF_CPU_RST# BUFO_CPU_RST# 4 NC
1 2
39_0402_5% Y PLT_RST#
2 PLT_RST# <18>
A

G
1

SN74LVC1G07DCKR_SC70-5
1 2

3
D @ R35 @
SUSP 2 Q1 0_0402_5%
<10,51,57> SUSP
G 2N7002_SOT23
2

S
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 6 of 63
5 4 3 2 1
 5 4 3 2 1

JCPU1C JCPU1D

<12> DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 <12> <13> DDR_B_D[0..63] SB_CLK[0] AE2 M_CLK_DDR2 <13>
SA_CLK#[0] AA6 M_CLK_DDR#0 <12> SB_CLK#[0] AD2 M_CLK_DDR#2 <13>
DDR_A_D0 C5 V9 DDR_B_D0 C9 R9
DDR_A_D1 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> DDR_B_D1 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
D5 SA_DQ[1] A7 SB_DQ[1]
DDR_A_D2 D3 DDR_B_D2 D10
DDR_A_D3 SA_DQ[2] DDR_B_D3 SB_DQ[2]
D2 C8
DDR_A_D4 SA_DQ[3] DDR_B_D4 SB_DQ[3]
D6 AA5 M_CLK_DDR1 <12> A9 AE1 M_CLK_DDR3 <13>
D DDR_A_D5 SA_DQ[4] SA_CLK[1] DDR_B_D5 SB_DQ[4] SB_CLK[1] D
C6 AB5 M_CLK_DDR#1 <12> A8 AD1 M_CLK_DDR#3 <13>
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDR_B_D6 SB_DQ[5] SB_CLK#[1]
C2 V10 DDR_CKE1_DIMMA <12> D9 R10 DDR_CKE3_DIMMB <13>
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_B_D7 SB_DQ[6] SB_CKE[1]
C3 D8
DDR_A_D8 SA_DQ[7] DDR_B_D8 SB_DQ[7]
F10 G4
DDR_A_D9 SA_DQ[8] DDR_B_D9 SB_DQ[8]
F8 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 AB4 F1 AB2
DDR_A_D11 SA_DQ[10] RSVD_TP[1] DDR_B_D11 SB_DQ[10] RSVD_TP[11]
G9 AA4 G1 AA2
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
F9 W9 G5 T9
DDR_A_D13 SA_DQ[12] RSVD_TP[3] DDR_B_D13 SB_DQ[12] RSVD_TP[13]
F7 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 F2
DDR_A_D15 SA_DQ[14] DDR_B_D15 SB_DQ[14]
G7 G2
DDR_A_D16 SA_DQ[15] DDR_B_D16 SB_DQ[15]
K4 SA_DQ[16] RSVD_TP[4] AB3 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
DDR_A_D18 SA_DQ[17] RSVD_TP[5] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
K1 SA_DQ[18] RSVD_TP[6] W10 K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D19 J1 DDR_B_D19 K9
DDR_A_D20 SA_DQ[19] DDR_B_D20 SB_DQ[19]
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
DDR_A_D22 SA_DQ[21] DDR_B_D22 SB_DQ[21]
J2 SA_DQ[22] SA_CS#[0] AK3 DDR_CS0_DIMMA# <12> K8 SB_DQ[22] SB_CS#[0] AD3 DDR_CS2_DIMMB# <13>
DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# <12> DDR_B_D24 SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# <13>
M8 SA_DQ[24] RSVD_TP[7] AG1 M5 SB_DQ[24] RSVD_TP[17] AD6
DDR_A_D25 N10 AH1 DDR_B_D25 N4 AE6
DDR_A_D26 SA_DQ[25] RSVD_TP[8] DDR_B_D26 SB_DQ[25] RSVD_TP[18]
N8 SA_DQ[26] N2 SB_DQ[26]
DDR_A_D27 N7 DDR_B_D27 N1
DDR_A_D28 SA_DQ[27] DDR_B_D28 SB_DQ[27]
M10 SA_DQ[28] M4 SB_DQ[28]
DDR_A_D29 M9 AH3 DDR_B_D29 N5 AE4
SA_DQ[29] SA_ODT[0] M_ODT0 <12> SB_DQ[29] SB_ODT[0] M_ODT2 <13>

DDR SYSTEM MEMORY B

DDR_A_D30 N9 AG3 DDR_B_D30 M2 AD4

DDR SYSTEM MEMORY A

DDR_A_D31 SA_DQ[30] SA_ODT[1] M_ODT1 <12> DDR_B_D31 SB_DQ[30] SB_ODT[1] M_ODT3 <13>
M7 SA_DQ[31] RSVD_TP[9] AG2 M1 SB_DQ[31] RSVD_TP[19] AD5
DDR_A_D32 AG6 AH2 DDR_B_D32 AM5 AE5
DDR_A_D33 SA_DQ[32] RSVD_TP[10] DDR_B_D33 SB_DQ[32] RSVD_TP[20]
AG5 SA_DQ[33] AM6 SB_DQ[33]
DDR_A_D34 AK6 DDR_B_D34 AR3
DDR_A_D35 SA_DQ[34] DDR_B_D35 SB_DQ[34]
AK5 SA_DQ[35] AP3 SB_DQ[35]
DDR_A_D36 AH5 DDR_B_D36 AN3
C DDR_A_D37 SA_DQ[36] DDR_A_DQS#0 DDR_A_DQS#[0..7] <12> DDR_B_D37 SB_DQ[36] DDR_B_DQS#0 DDR_B_DQS#[0..7] <13> C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 SA_DQ[39] SA_DQS#[2] J3 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D40 AJ8 M6 DDR_A_DQS#3 DDR_B_D40 AP5 N3 DDR_B_DQS#3
DDR_A_D41 SA_DQ[40] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AK8 SA_DQ[41] SA_DQS#[4] AL6 AN9 SB_DQ[41] SB_DQS#[4] AN5
DDR_A_D42 AJ9 AM8 DDR_A_DQS#5 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AK9 SA_DQ[43] SA_DQS#[6] AR12 AT6 SB_DQ[43] SB_DQS#[6] AK12
DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 AN8
DDR_A_D46 SA_DQ[45] DDR_B_D46 SB_DQ[45]
AL9 AR6
DDR_A_D47 SA_DQ[46] DDR_B_D47 SB_DQ[46]
AL8 AR5
DDR_A_D48 SA_DQ[47] DDR_B_D48 SB_DQ[47]
AP11 DDR_A_DQS[0..7] <12> AR9 DDR_B_DQS[0..7] <13>
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AN11 D4 AJ11 C7
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 F6 AT8 G3
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AM12 K3 AT9 J6
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM11 N6 AH11 M3
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AL11 AL5 AR8 AN6
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AP12 AM9 AJ12 AP8
DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AN12 AR11 AH12 AK11
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 AM14 AT11 AP14
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D57 SB_DQ[56] SB_DQS[7]
AH14 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 AR14
DDR_A_D59 SA_DQ[58] DDR_B_D59 SB_DQ[58]
AK15 AT14
DDR_A_D60 SA_DQ[59] DDR_B_D60 SB_DQ[59]
AL14 DDR_A_MA[0..15] <12> AT12 DDR_B_MA[0..15] <13>
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AK14 AD10 AN15 AA8
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 W1 AR15 T7
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
AH15 W2 AT15 R7
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
W7 T6
SA_MA[3] DDR_A_MA4 SB_MA[3] DDR_B_MA4
V3 T2
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
V2 T4
SA_MA[5] DDR_A_MA6 SB_MA[5] DDR_B_MA6
W3 T3
SA_MA[6] DDR_A_MA7 SB_MA[6] DDR_B_MA7
<12> DDR_A_BS0 AE10 W6 <13> DDR_B_BS0 AA9 R2
B SA_BS[0] SA_MA[7] DDR_A_MA8 SB_BS[0] SB_MA[7] DDR_B_MA8 B
<12> DDR_A_BS1 AF10 V1 <13> DDR_B_BS1 AA7 T5
SA_BS[1] SA_MA[8] DDR_A_MA9 SB_BS[1] SB_MA[8] DDR_B_MA9
<12> DDR_A_BS2 V6 W5 <13> DDR_B_BS2 R6 R3
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_BS[2] SB_MA[9] DDR_B_MA10
AD8 AB7
SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
V4 R1
SA_MA[11] DDR_A_MA12 SB_MA[11] DDR_B_MA12
W4 T1
SA_MA[12] DDR_A_MA13 SB_MA[12] DDR_B_MA13
<12> DDR_A_CAS# AE8 AF8 <13> DDR_B_CAS# AA10 AB10
SA_CAS# SA_MA[13] DDR_A_MA14 SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_A_RAS# AD9 V5 <13> DDR_B_RAS# AB8 R5
SA_RAS# SA_MA[14] DDR_A_MA15 SB_RAS# SB_MA[14] DDR_B_MA15
<12> DDR_A_WE# AF9 V7 <13> DDR_B_WE# AB9 R4
SA_WE# SA_MA[15] SB_WE# SB_MA[15]

Sandy Bridge_rPGA_Rev1p0 Sandy Bridge_rPGA_Rev1p0

ME@ ME@

+1.5V

@ R36
1

0_0402_5%
1 2 R37
1K_0402_5%

R38
2

1K_0402_5%
S

H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>
2

Q2
R39 BSS138_NL_SOT23-3
G
2

4.99K_0402_1%
1

A R40 A
0_0402_5%
1 2 DRAMRST_CNTRL
<15> DRAMRST_CNTRL_PCH

1
C35
Eiffel used 0.01u Security Classification Compal Secret Data Compal Electronics, Inc.
Module design used 0.047u Issued Date 2010/11/30 Deciphered Date 2011/08 Title
0.047U_0402_16V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/7) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 7 of 63

5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

CFG2

1
R41
1K_0402_1%

2
D D

JCPU1E PEG Static Lane Reversal - CFG2 is for the 16x

RSVD28
L7 1: Normal Operation; Lane # definition matches
RSVD29
AG7 CFG2 socket pin map definition
AK28 CFG[0] RSVD30 AE7
AK29 CFG[1] RSVD31 AK2
CFG2 AL26 W8 0:Lane Reversed
CFG4
AL27
AK26
CFG[2]
CFG[3]
CFG[4]
RSVD32
*
CFG5 AL29 AT26 CFG4
CFG6 CFG[5] RSVD33
AL30 CFG[6] RSVD34 AM33

1
CFG7 AM31 AJ27
CFG[7] RSVD35
AM32 CFG[8]
AM30 @ R42
CFG[9] 1K_0402_1%
AM28 CFG[10]
AM26

2
CFG[11]
AN28 CFG[12]
AN31 CFG[13] RSVD37 T8
AN26 CFG[14] RSVD38 J16
AM27 CFG[15] RSVD39 H16
AK31 CFG[16] RSVD40 G16
AN29 CFG[17]
Display Port Presence Strap

C C
AR35 1 : Disabled; No Physical Display Port
T9
T10
PAD
PAD
AJ31
AH31
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
RSVD41
RSVD42
RSVD43
AT34
AT33
CFG4 * attached to Embedded Display Port
T11 PAD AJ33 AP35
VCC_VAL_SENSE RSVD44
T12 PAD AH33 VSS_VAL_SENSE RSVD45 AR34 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
AJ26
RSVD5

RESERVED
B34 CFG6
RSVD46
B4 A33
RSVD6 RSVD47 CFG5
D1 A34
RSVD7 RSVD48
B35
RSVD49

1
C35
RSVD50
1

@ R43 @ R44
R64 R353 F25 1K_0402_1% 1K_0402_1%
1K_0402_1% 1K_0402_1% RSVD8
F24
RSVD9
F23

2
RSVD10
D24 AJ32
2

RSVD11 RSVD51
G25 AK32
RSVD12 RSVD52
G24
@ @ RSVD13
E23
RSVD14
D23
RSVD15 PAD T13
C30 AH27
RSVD16 VCC_DIE_SENSE
A31
RSVD17
B30
RSVD18
B29
RSVD19 PCIE Port Bifurcation Straps
D30 AN35
RSVD20 RSVD54
B31 AM35
RSVD21 RSVD55
A30 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
C29
RSVD22
RSVD23
CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B

J20
disabled
RSVD24
B18
RSVD25 RSVD56
AT2 01: Reserved - (Device 1 function 1 disabled ; function
A19 AT1 2 enabled)
VCCIO_SEL RSVD57
AR1
RSVD58
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
J15
RSVD27

B1
KEY CFG7

1
@R45
@ R45
1K_0402_1%

Sandy Bridge_rPGA_Rev1p0

2
ME@

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion

A
0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 8 of 63
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER
+CPU_CORE Cap quantity follow HR_PDDG_Rev07
(6/16 change 10uF_0603_6.3V)*5 22uF*7 NO-STUFF
QC=94A +1.05VS
18A
DC=53A AG35
(22uF_0805_6.3V)*13
VCC1 +1.05VS
1 1 1 1 1 AG34 VCC2 VCCIO1 AH13

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AG33 AH10 1 1 1 1 1 1 1 1 1 1
VCC3 VCCIO2

C36

C37

C38

C39

C40

22U_0805_6.3V6M
C41

22U_0805_6.3V6M
C42

22U_0805_6.3V6M
C43

22U_0805_6.3V6M
C44

22U_0805_6.3V6M
C54

22U_0805_6.3V6M
C45

22U_0805_6.3V6M
C46

22U_0805_6.3V6M
C55

22U_0805_6.3V6M
C56

22U_0805_6.3V6M
C47
AG32 AG10
VCC4 VCCIO3
AG31 AC10
D 2 2 2 2 2 VCC5 VCCIO4 D
AG30 Y10
VCC6 VCCIO5 2 2 2 2 2 2 2 2 2 2
AG29 U10
VCC7 VCCIO6
AG28 P10
VCC8 VCCIO7
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10
1 1 1 1 1 1 AF34 J12
10U_0603_6.3V6M VCC12 VCCIO11
C48

10U_0603_6.3V6M
C49

10U_0603_6.3V6M
C50

10U_0603_6.3V6M
C51

10U_0603_6.3V6M
C52

10U_0603_6.3V6M
C53
AF33 J11 1 1 1 1 1 1 1 1 1
VCC13 VCCIO12

22U_0805_6.3V6M
C57

22U_0805_6.3V6M
C58

22U_0805_6.3V6M
C59

22U_0805_6.3V6M
C60

22U_0805_6.3V6M
C61

22U_0805_6.3V6M
C62

22U_0805_6.3V6M
C63

22U_0805_6.3V6M
C64

22U_0805_6.3V6M
C65
AF32 H14
@ VCC14 VCCIO13 @ @ @ @ @ @ @
AF31 H12
2 2 2 2 2 2 VCC15 VCCIO14
AF30 H11
VCC16 VCCIO15 2 2 2 2 2 2 2 2 2
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13

PEG AND DDR

AF27 VCC19 VCCIO18 G12
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
+CPU_CORE (22uF_0805_6.3V)*16 AD34
AD33
VCC22 VCCIO21 F12
F11
VCC23 VCCIO22
AD32 VCC24 VCCIO23 E14

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
AD31 VCC25 VCCIO24 E12 1 1 1 1

C69

C72
AD30 VCC26
AD29 E11 + C922 + + + C918
1 1 1 1 1 VCC27 VCCIO25
22U_0805_6.3V6M
C66

22U_0805_6.3V6M
C67

22U_0805_6.3V6M
C68

22U_0805_6.3V6M
C70

22U_0805_6.3V6M
C71
AD28 D14 330U_2.5V_M 330U_2.5V_M
VCC28 VCCIO26 @ @
AD27 VCC29 VCCIO27 D13
AD26 D12 2 2 2 2
2 2 2 2 2 VCC30 VCCIO28
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
AC30 VCC36 VCCIO34 B14
1 1 1 1 1 AC29 VCC37 VCCIO35 B12
22U_0805_6.3V6M
C74

22U_0805_6.3V6M
C75

22U_0805_6.3V6M
C76

22U_0805_6.3V6M
C77

22U_0805_6.3V6M
C78
C C
AC28 VCC38 VCCIO36 A14
AC27 VCC39 VCCIO37 A13
AC26 VCC40 VCCIO38 A12
2 2 2 2 2
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31
VCC45
AA30
VCC46
1 1 1 1 1 AA29
VCC47
22U_0805_6.3V6M
C79

22U_0805_6.3V6M
C80

22U_0805_6.3V6M
C81

22U_0805_6.3V6M
C82

22U_0805_6.3V6M
C83

AA28
VCC48
AA27
VCC49
AA26
2 2 2 2 2 VCC50 +1.05VS

CORE SUPPLY
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54

1
Y31
VCC55 R46
Y30
VCC56
1 1 1 1 Y29 75_0402_5%
VCC57
22U_0805_6.3V6M
C84

22U_0805_6.3V6M
C85

22U_0805_6.3V6M
C86

22U_0805_6.3V6M
C87

Y28
VCC58
@ @ @ Y27 VR_SVID_CLK series-resistors close to VR

2
VCC59
Y26
2 2 2 2 VCC60
V35
VCC61

SVID
V34 AJ29 H_CPU_SVIDALRT# R47 1 2 43_0402_5%
VCC62 VIDALERT# H_CPU_SVIDCLK VR_SVID_ALRT# <60>
V33 AJ30 R48 1 2 0_0402_5%
VCC63 VIDSCLK H_CPU_SVIDDAT VR_SVID_CLK <60>
V32 AJ28 R49 1 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT <60>
V31
+CPU_CORE VCC65
V30
VCC66 R50
V29
VCC67 2 1 130_0402_5% +1.05VS
V28
VCC68
V27
B VCC69 B
V26
VCC70
330U_X_2VM_R6M

330U_X_2VM_R6M

330U_X_2VM_R6M

330U_X_2VM_R6M

1 1 1 1 U35
VCC71
U34
VCC72
C88

C89

C90

C91

+ + + + U33
VCC73
(330uF)*4 U32
U31
VCC74
2 2 2 2 VCC75
U30
VCC76
U29
U28
VCC77 8/11 update: Add R1309, R1310.
VCC78
U27
U26
VCC79 PDDG1.21#439028
VCC80 +CPU_CORE
DUAL@ DUAL@ DUAL@ DUAL@ R35
VCC81
R34
VCC82
R33
VCC83

1
R32
VCC84 R51
R31
VCC85
R30 100_0402_1%
C88 C90 VCC86
R29
VCC87
SENSE LINES

C89 C91 R28

2
VCC88
R27 AJ35 VCCSENSE_R R52 1 2 0_0402_5%
VCCSENSE <60>
VCC89 VCC_SENSE
R26 AJ34 VSSSENSE_R R53 1 2 0_0402_5%
VSSSENSE <60>
VCC90 VSS_SENSE
P35
VCC91 +1.05VS R1313
P34
VCC92

1
R1309

R1310
470U_D2_2VM_R4.5M 470U_D2_2VM_R4.5M P33
VCC93 1 2
QUAD@ 470U_D2_2VM_R4.5M QUAD@ 470U_D2_2VM_R4.5M P32 B10 10_0402_1% R54 @ @
VCC94 VCCIO_SENSE VCCIO_SENSE <58>

27.4_0402_1%

27.4_0402_1%
QUAD@ QUAD@ P31 A10 VSSIO_SENSE 100_0402_1%
VCC95 VSSIO_SENSE

2
P30
VCC96 R1314
P29

2
VCC97
P28 10_0402_1%
VCC98
P27
VCC99
P26
1
VCC100
A A

Sandy Bridge_rPGA_Rev1p0
ME@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/7) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 9 of 63
5 4 3 2 1
 5 4 3 2 1

+1.5V @ J1 +1.5V_CPU_VDDQ
1 2
11/17 R56 change to 20K +1.5V
PAD-OPEN 4x4m 1

1
1 2 R55 @ C92
<6,51,57> SUSP 0_0402_5% R668 220_0402_5% 0.1U_0402_10V6K
@ 2

12
D

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
+VSB

C95

C96

C915

C916
+3VALW U3 Q3 2 RUN_ON_CPU1.5VS3# 1 1 1 1
8 1 2N7002_SOT23 G
D @ D
7 2 S

3
1
6 3

1
5 +1.5V_CPU_VDDQ 2 2 2 2
R667
100K_0402_5% R56 DMN3030LSS-13_SOP8L-8

4
@ 20K_0402_1%

2
2
R1347
RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3 1 2

1
300K_0402_1% 1

1
D D
1 2 2 Q7 2 Q4 R57 C97
<45> CPU1.5V_S3_GATE
0_0402_5% R58 @ G 2N7002_SOT23 G 2N7002_SOT23 330K_0402_5% 0.1U_0603_25V7M
S @ S @ 2

2
<45,51,56,58,59> SUSP# 1 2
0_0402_5% R59 @

+VGFX_CORE JCPU1G
POWER

SENSE
LINES
AT24 VAXG1 VAXG_SENSE AK35 VCC_AXG_SENSE <60>
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE <60>
1 1 1 1 1 1 1 1 1 1 AT21 VAXG3
22U_0805_6.3V6M
C98

22U_0805_6.3V6M
C99

22U_0805_6.3V6M
C100

22U_0805_6.3V6M
C101

22U_0805_6.3V6M
C102

22U_0805_6.3V6M
C103

22U_0805_6.3V6M
C104

22U_0805_6.3V6M
C105

22U_0805_6.3V6M
C106

22U_0805_6.3V6M
C107
AT20 VAXG4
AT18 +1.5V_CPU_VDDQ
VAXG5 R61
AT17 VAXG6
2 2 2 2 2 2 2 2 2 2 AR24 0_0402_5%
VAXG7

1
AR23 VAXG8
2 1
C R62 C
AR21 VAXG9
AR20 1K_0402_1%
VAXG10

VREF
AR18 VAXG11
AR17

2
VAXG12 +V_SM_VREF_CNT +V_SM_VREF
AP24 VAXG13 SM_VREF AL1 3 1
AP23 VAXG14

1
AP21 1 100K_0402_5% Q5
VAXG15 C114 R666 AP2302GN-HF_SOT23-3 R63
1 1 1 1 1 1 AP20
VAXG16
22U_0805_6.3V6M
C108

22U_0805_6.3V6M
C109

22U_0805_6.3V6M
C110

22U_0805_6.3V6M
C111

22U_0805_6.3V6M
C112

22U_0805_6.3V6M
C113 AP18 0.1U_0402_16V4Z @ 1K_0402_1%
VAXG17 2
AP17
AN24
VAXG18 2 RUN_ON_CPU1.5VS3@
Fixed

2
2 2 2 @ 2 @ 2 @ 2 @ VAXG19
AN23
VAXG20
AN21
VAXG21
AN20
VAXG22

DDR3 -1.5V RAILS

AN18
VAXG23 +1.5V_CPU_VDDQ
AN17
VAXG24

GRAPHICS
AM24 AF7
VAXG25 VDDQ1
AM23 AF4
VAXG26 VDDQ2

330U_D2_2.5VY_R9M
AM21 AF1 1
VAXG27 VDDQ3
330U_D2_2.5VY_R9M

C123
1 1 AM20 AC7 1 1 1 1 1 1
VAXG28 VDDQ4
C115

10U_0603_6.3V6M
C117

10U_0603_6.3V6M
C118

10U_0603_6.3V6M
C119

10U_0603_6.3V6M
C120

10U_0603_6.3V6M
C121

10U_0603_6.3V6M
C122
AM18 AC4 +
+ + C116 VAXG29 VDDQ5
AM17 AC1
330U_2.5V_M VAXG30 VDDQ6
AL24 Y7
VAXG31 VDDQ7 2 2 2 2 2 2 2 @
AL23 Y4
2 @2 VAXG32 VDDQ8
AL21 Y1
VAXG33 VDDQ9
AL20 U7
VAXG34 VDDQ10
AL18 U4
VAXG35 VDDQ11
AL17 U1
VAXG36 VDDQ12
AK24 P7
VAXG37 VDDQ13
AK23
VAXG38 VDDQ14
P4 8/12 330u unstuff default
AK21 P1
VAXG39 VDDQ15
AK20
B VAXG40 B
AK18
VAXG41
AK17
VAXG42
AJ24
VAXG43
AJ23
VAXG44
AJ21
VAXG45
AJ20
VAXG46
AJ18
VAXG47
AJ17
VAXG48 +VCCSA
AH24

SA RAIL
VAXG49
AH23
VAXG50 +VCCSA
AH21 M27
VAXG51 VCCSA1
AH20 M26
VAXG52 VCCSA2 R65 100_0402_1%
AH18 L26
VAXG53 VCCSA3 VCCSA_SENSE
AH17 J26 1 1 1 1 1 2 VCCSA_SENSE <57>
VAXG54 VCCSA4

10U_0805_6.3V6M
C124

10U_0805_6.3V6M
C125

10U_0805_6.3V6M
C126

10U_0805_6.3V6M
C127

330U_D2_2.5VY_R9M
J25 1
VCCSA5

C128
Sandy Bridge_rPGA_Rev1p0 J24 @
ME@ VCCSA6 +
H26
VCCSA7 2 2 2 2
H25
VCCSA8 R66
2
1.8V RAIL

1 2 0_0402_5% VSSSA_SENSE <57>

+1.8VS R67
0_0805_5% 1.5A
1 2 +1.8VS_VCCPLL B6 H23 VCCSA_SENSE
VCCPLL1 VCCSA_SENSE
MISC

A6
VCCPLL2
10U_0805_6.3V6M
C130

1U_0402_6.3V6K
C131

1U_0402_6.3V6K
C132

1 1 1 1 A2 @
VCCPLL3
22U_0805_6.3V6M
C154

22U_0805_6.3V6M
C345

1 R68 1 2 0_0402_5%
C22 H_FC_C22
FC_C22
C24
2 @ 2 @ 2 2 VCCSA_VID1 R69
2
1 2
1K_0402_1%
A A

VCCSA_SEL <57>

6/9 change 330U to 22U X2

Security Classification Compal Secret Data
Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 10 of 63
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I
D D
AT35 AJ22
VSS1 VSS81
AT32 AJ19
VSS2 VSS82
AT29 AJ16 T35 F22
VSS3 VSS83 VSS161 VSS234
AT27 AJ13 T34 F19
VSS4 VSS84 VSS162 VSS235
AT25 AJ10 T33 E30
VSS5 VSS85 VSS163 VSS236
AT22 AJ7 T32 E27
VSS6 VSS86 VSS164 VSS237
AT19 AJ4 T31 E24
VSS7 VSS87 VSS165 VSS238
AT16 AJ3 T30 E21
VSS8 VSS88 VSS166 VSS239
AT13 AJ2 T29 E18
VSS9 VSS89 VSS167 VSS240
AT10 AJ1 T28 E15
VSS10 VSS90 VSS168 VSS241
AT7 AH35 T27 E13
VSS11 VSS91 VSS169 VSS242
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6
AR16 VSS17 VSS97 AH26 P3 VSS175 VSS248 E5
AR13 VSS18 VSS98 AH25 P2 VSS176 VSS249 E4
AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3
AR7 VSS20 VSS100 AH19 N34 VSS178 VSS251 E2
AR4 VSS21 VSS101 AH16 N33 VSS179 VSS252 E1
AR2 VSS22 VSS102 AH7 N32 VSS180 VSS253 D35
AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
AP28 VSS25 VSS105 AG8 N29 VSS183 VSS256 D26
AP25 VSS26 VSS106 AG4 N28 VSS184 VSS257 D20
AP22 VSS27 VSS107 AF6 N27 VSS185 VSS258 D17
AP19 VSS28 VSS108 AF5 N26 VSS186 VSS259 C34
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31
AP13 VSS30 VSS110 AF2 L33 VSS188 VSS261 C28
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27
AP7 VSS32 VSS112 AE34 L27 VSS190 VSS263 C25
C C
AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23
AP1 VSS34 VSS114 AE32 L8 VSS192 VSS265 C10
AN30 VSS35 VSS115 AE31 L6 VSS193 VSS266 C1
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22
AN25 AE29 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE26 L1 B13
VSS40 VSS120 VSS198 VSS271
AN13 AE9 K35 B11
VSS41 VSS121 VSS199 VSS272
AN10 AD7 K32 B9
VSS42 VSS122 VSS200 VSS273
AN7 AC9 K29 B8
VSS43 VSS123 VSS201 VSS274
AN4 AC8 K26 B7
VSS44 VSS124 VSS202 VSS275
AM29 AC6 J34 B5
VSS45 VSS125 VSS203 VSS276
AM25 AC5 J31 B3
VSS46 VSS126 VSS204 VSS277
AM22 AC3 H33 B2
VSS47 VSS127 VSS205 VSS278
AM19 AC2 H30 A35
VSS48 VSS128 VSS206 VSS279
AM16 AB35 H27 A32
VSS49 VSS129 VSS207 VSS280
AM13 AB34 H24 A29
VSS50 VSS130 VSS208 VSS281
AM10 AB33 H21 A26
VSS51 VSS131 VSS209 VSS282
AM7 AB32 H18 A23
VSS52 VSS132 VSS210 VSS283
AM4 AB31 H15 A20
VSS53 VSS133 VSS211 VSS284
AM3 AB30 H13 A3
VSS54 VSS134 VSS212 VSS285
AM2 AB29 H10
VSS55 VSS135 VSS213
AM1 AB28 H9
VSS56 VSS136 VSS214
AL34 AB27 H8
VSS57 VSS137 VSS215
AL31 AB26 H7
VSS58 VSS138 VSS216
AL28 Y9 H6
VSS59 VSS139 VSS217
AL25 Y8 H5
VSS60 VSS140 VSS218
AL22 Y6 H4
VSS61 VSS141 VSS219
AL19 Y5 H3
VSS62 VSS142 VSS220
AL16 Y3 H2
VSS63 VSS143 VSS221
AL13 Y2 H1
B VSS64 VSS144 VSS222 B
AL10 W35 G35
VSS65 VSS145 VSS223
AL7 W34 G32
VSS66 VSS146 VSS224
AL4 W33 G29
VSS67 VSS147 VSS225
AL2 W32 G26
VSS68 VSS148 VSS226
AK33 W31 G23
VSS69 VSS149 VSS227
AK30 W30 G20
VSS70 VSS150 VSS228
AK27 W29 G17
VSS71 VSS151 VSS229
AK25 W28 G11
VSS72 VSS152 VSS230
AK22 W27 F34
VSS73 VSS153 VSS231
AK19 W26 F31
VSS74 VSS154 VSS232
AK16 U9 F29
VSS75 VSS155 VSS233
AK13 U8
VSS76 VSS156
AK10 U6
VSS77 VSS157
AK7 U5
VSS78 VSS158
AK4 U3
VSS79 VSS159
AJ25 U2
VSS80 VSS160

Sandy Bridge_rPGA_Rev1p0 Sandy Bridge_rPGA_Rev1p0

ME@ ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 11 of 63
5 4 3 2 1
 5 4 3 2 1

+VREF_DQ_DIMMA +1.5V +1.5V +1.5V

3A@1.5V
<7> DDR_A_D[0..63]
DDR3 SO-DIMM A

1
<7> DDR_A_DQS[0..7]
R70
JDIMM1 1K_0402_1%
<7> DDR_A_DQS#[0..7] +VREF_DQ_DIMMA
+VREF_DQ_DIMMA 1 2
VREF_DQ VSS1 DDR_A_D4
3 4 <7> DDR_A_MA[0..15]

2
VSS2 DQ4

0.1U_0402_10V6K

2.2U_0603_6.3V6K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C133

C134
1 1 DDR_A_D1 7 8
DQ1 VSS3 DDR_A_DQS#0
9 VSS4 DQS#0 10

1
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 VSS5 VSS6 14
2 2 DDR_A_D2 DDR_A_D6 R71
15 DQ2 DQ6 16
D DDR_A_D3 17 18 DDR_A_D7 1K_0402_1% D
DQ3 DQ7
19 20

2
DDR_A_D8 VSS7 VSS8 DDR_A_D12
21 DQ8 DQ12 22
DDR_A_D9 23 24 DDR_A_D13
DQ9 DQ13
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# <7,13>
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

<7> DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA

C CKE0 CKE1 DDR_CKE1_DIMMA <7> C
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
<7> DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
<7> M_CLK_DDR0 M_CLK_DDR0 101 102 M_CLK_DDR1
CK0 CK1 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 <7>
105 VDD11 VDD12 106
DDR_A_MA10 DDR_A_BS1
<7> DDR_A_BS0 DDR_A_BS0
107
109
A10/AP BA1 108
110 DDR_A_RAS#
DDR_A_BS1 <7> +1.5V Layout Note: (10uF_0603_6.3V)*8
BA0 RAS# DDR_A_RAS# <7>
111 112 Place near DIMM
DDR_A_WE# VDD13 VDD14 DDR_CS0_DIMMA#
<7> DDR_A_WE# 113 WE# S0# 114 DDR_CS0_DIMMA# <7> (0.1uF_402_10V)*4

1
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118 R72
DDR_A_MA13 VDD15 VDD16 M_ODT1 1K_0402_1%
119 A13 ODT1 120 M_ODT1 <7>
<7> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2
123 124

2
VDD17 VDD18 +VREF_CA +1.5V
125 NCTEST VREF_CA 126
127 VSS27 VSS28 128

0.1U_0402_10V6K

2.2U_0603_6.3V6K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
C135

C136

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_A_D33 131 132 DDR_A_D37 1 1
DQ33 DQ37

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
133 VSS29 VSS30 134 1

C137

C138

C139

C140

C141

C142

C143

C144

C145

C146

C147

C148
DDR_A_DQS#4 135 136 DDR_A_DM4 R73 1 1 1 1 1 1 1 1 1 1 1 1
DDR_A_DQS4 DQS#4 DM4 1K_0402_1% + C149
137 DQS4 VSS31 138
B DDR_A_D38 2 2 220U_B2_2.5VM_R35 B
139 140

2
DDR_A_D34 VSS32 DQ38 DDR_A_D39 @ @
141 DQ34 DQ39 142
DDR_A_D35 2 2 2 2 2 2 2 2 2 2 2 2 2
143 DQ35 VSS33 144
145 146 DDR_A_D44
DDR_A_D40 VSS34 DQ44 DDR_A_D45
147 DQ40 DQ45 148
DDR_A_D41 149 150
DQ41 VSS35 DDR_A_DQS#5
151 VSS36 DQS#5 152
DDR_A_DM5 153 154 DDR_A_DQS5
DM5 DQS5
155 VSS37 VSS38 156 VDDQ(1.5V) =
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52 6*0603 10uf (PER CONNECTOR)
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166 Layout Note:
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6 VTT(0.75V) = Place near DIMM
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54 3*0805 10uf 4*0402 1uf
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178 VREF =
DQ51 VSS45 DDR_A_D60 +0.75VS
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61 1*0402 0.1uf 1*0402 2.2uf DDR_A_DM0
DDR_A_D57 DQ56 DQ61 DDR_A_DM1
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7 VDDSPD (3.3V)= DDR_A_DM2
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7 DDR_A_DM3
187 DM7 DQS7 188

C150

1U_0402_6.3V6K
C151

1U_0402_6.3V6K
C152

1U_0402_6.3V6K
C153

1U_0402_6.3V6K
189 190 1*0402 0.1uf 1*0402 2.2uf DDR_A_DM4
DDR_A_D58 VSS49 VSS50 DDR_A_D62 DDR_A_DM5
191 DQ58 DQ62 192 1 1 1 1
DDR_A_D59 193 194 DDR_A_D63 DDR_A_DM6
DQ59 DQ63
1 R81 2 195 VSS51 VSS52 196 DDR_A_DM7
10K_0402_5% 197 198
SA0 EVENT# SMB_DATA_S3 2 2 2 2
+3VS 199 VDDSPD SDA 200 SMB_DATA_S3 <13,15,37>
2.2U_0603_6.3V6K

0.1U_0402_10V6K

201 202 SMB_CLK_S3 Layout Note:

SA1 SCL SMB_CLK_S3 <13,15,37>
C155

C156

A 203 204 A
1 1 VTT1 VTT2 +0.75VS
1

Short to ground
10K_0402_5%
R83

205 206 0.65A@0.75V

G1 G2
2 2 LCN_DAN06-K4526-0100
2

ME@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 12 of 63
5 4 3 2 1
 5 4 3 2 1

+VREF_DQ_DIMMB 3A@1.5V
<7> DDR_B_D[0..63]
+1.5V +1.5V
<7> DDR_B_DQS[0..7]
JDIMM2 +1.5V
<7> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
VREF_DQ VSS1 DDR_B_D4
3 VSS2 DQ4 4 <7> DDR_B_MA[0..15]

1
2.2U_0603_6.3V6K

0.1U_0402_10V6K
DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5

C158
1 1 DDR_B_D1 7 8 R84
DQ1 VSS3 DDR_B_DQS#0 1K_0402_1%
9 VSS4 DQS#0 10
+VREF_DQ_DIMMB

C157
DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
13 14

2
2 2 DDR_B_D2 VSS5 VSS6 DDR_B_D6
15 DQ2 DQ6 16
DDR_B_D3 17 18 DDR_B_D7
D DQ3 DQ7 D
19 VSS7 VSS8 20

1
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 DQ9 DQ13 24
25 26 R85
DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1 1K_0402_1%
27 DQS#1 DM1 28
DDR_B_DQS1 29 30 DDR3_DRAMRST#
DDR3_DRAMRST# <7,12>

2
DQS1 RESET#
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42 For Arranale only +VREF_DQ_DIMMB
43 VSS15 VSS16 44
DDR_B_DQS#2 45 DQS#2 DM2 46 DDR_B_DM2 supply from a external 1.5V voltage divide
DDR_B_DQS2 47 48
DQS2 VSS17 DDR_B_D22
circuit.
49 VSS18 DQ22 50
DDR_B_D18 51 DQ18 DQ23 52 DDR_B_D23 07/17/2009
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 VDD1 VDD2 76
C 77 78 DDR_B_MA15 C
DDR_B_BS2 NC1 A15 DDR_B_MA14
<7> DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
<7> M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3
CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <7>
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7> +1.5V
DDR_B_BS0 DDR_B_RAS#
<7> DDR_B_BS0 109
111
BA0 RAS# 110
112
DDR_B_RAS# <7> Layout Note: (10uF_0603_6.3V)*8
DDR_B_WE# VDD13 VDD14 DDR_CS2_DIMMB# Place near DIMM
<7> DDR_B_WE# 113 WE# S0# 114 DDR_CS2_DIMMB# <7>

1
DDR_B_CAS# M_ODT2
<7> DDR_B_CAS# 115
117
CAS# ODT0 116
118
M_ODT2 <7>
R86 (0.1uF_402_10V)*4
DDR_B_MA13 VDD15 VDD16 M_ODT3 1K_0402_1%
119 A13 ODT1 120 M_ODT3 <7>
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC2
123 124

2
VDD17 VDD18 +VREF_CB
125 NCTEST VREF_CA 126
+1.5V
0.1U_0402_10V6K
127 VSS27 VSS28 128

2.2U_0603_6.3V6K
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36

1
C159

C160
DDR_B_D33 131 132 DDR_B_D37 1 1
DQ33 DQ37

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
133 VSS29 VSS30 134

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
DDR_B_DQS#4 135 136 DDR_B_DM4 R87
DQS#4 DM4

C161

C162

C163

C164

C165

C166

C167

C168

C169

C170

C171

C172
DDR_B_DQS4 137 138 1K_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1
DQS4 VSS31 DDR_B_D38 2 2
139 140

2
B DDR_B_D34 VSS32 DQ38 DDR_B_D39 B
141 DQ34 DQ39 142
DDR_B_D35 143 144 @ @
DQ35 VSS33 DDR_B_D44 2 2 2 2 2 2 2 2 2 2 2 2
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_B_DQS#5
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 DM5 DQS5 154 VDDQ(1.5V) =
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162 6*0603 10uf (PER CONNECTOR)
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166 Layout Note:
167 VSS41 VSS42 168 VTT(0.75V) =
DDR_B_DQS#6 169 DQS#6 DM6 170 DDR_B_DM6 Place near DIMM
DDR_B_DQS6 171 172 3*0805 10uf 4*0402 1uf
DQS6 VSS43 DDR_B_D54
173 VSS44 DQ54 174
DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS45 178
DDR_B_D60 +0.75VS
179 VSS46 DQ60 180 1*0402 0.1uf 1*0402 2.2uf
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61 DDR_B_DM0
183 DQ57 VSS47 184 VDDSPD (3.3V)=
185 186 DDR_B_DQS#7 DDR_B_DM1
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7 DDR_B_DM2
187 DM7 DQS7 188 1*0402 0.1uf 1*0402 2.2uf

C173

1U_0402_6.3V6K
C174

1U_0402_6.3V6K
C175

1U_0402_6.3V6K
C176

1U_0402_6.3V6K
189 190 DDR_B_DM3
DDR_B_D58 VSS49 VSS50 DDR_B_D62 DDR_B_DM4
191 DQ58 DQ62 192 1 1 1 1
DDR_B_D59 193 194 DDR_B_D63 DDR_B_DM5
DQ59 DQ63 DDR_B_DM6
195 VSS51 VSS52 196
1 R95 2 197 SA0 EVENT# 198 DDR_B_DM7
10K_0402_5% SMB_DATA_S3 2 2 2 2
199 VDDSPD SDA 200 SMB_DATA_S3 <12,15,37>
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 <12,15,37>
2.2U_0603_6.3V6K

0.1U_0402_10V6K

R97 10K_0402_5% 203 204 +0.75VS

VTT1 VTT2 0.65A@0.75V
C177

C178

A A
1 1 Layout Note:
205 G1 G2 206
Short to ground
LCN_DAN06-K4926-0100
2 2 ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 13 of 63
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

W=20mils W=20mils 1 2 PCH_RTCX2

R98 10M_0402_5%
+RTCVCC +RTCBATT

R99

32.768KHZ_12.5PF_9H03200413
1K_0402_5%
1 2

4
1 Y1
C179 CLRP1 1 1

OSC

OSC
1U_0603_10V4Z SHORT PADS C180 C181

2
2 <BOM Structure>
15P_0402_50V8J 15P_0402_50V8J
D 2 2 D

NC

NC
2

3
CMOS
+RTCVCC
U4A

SHORT PADS
CLRP2
R101 1 2 1M_0402_5% SM_INTRUDER#
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <37,45>

1
R102 1 2 330K_0402_5% PCH_INTVRMEN A38 LPC_AD1

LPC
PCH_RTCX2 FWH1 / LAD1 LPC_AD2 LPC_AD1 <37,45>
C183 C20 B37 EC and Mini card debug port
RTCX2 FWH2 / LAD2 LPC_AD3 LPC_AD2 <37,45>
R1330 1 2 330K_0402_5% 1U_0603_10V4Z C37 LPC_AD3 <37,45>

2
@ 2 PCH_RTCRST# FWH3 / LAD3
1 2 D20
R103 20K_0402_5% RTCRST# LPC_FRAME#
INTVRMEN FWH4 / LFRAME# D36 LPC_FRAME# <37,45>
：Integrated 1 2 PCH_SRTCRST# G22 SRTCRST#
* LH： Integrated VRM enable R100 20K_0402_5% E36 +3VS
1

RTC
LDRQ0#

1
SHORT PADS
CLRP3
VRM disable SM_INTRUDER# K22 K36 R104 2 1 10K_0402_5%
C182 INTRUDER# LDRQ1# / GPIO23
(INTVRMEN should always be pull high.) 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ
SERIRQ <45>

2
2 INTVRMEN SERIRQ

AM3 SATA_DTX_C_IRX_N0
+3VS SATA0RXN SATA_DTX_C_IRX_N0 <37>
HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 <37>
HDA_BCLK SATA0RXP

SATA 6G
AP7 SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 2 1 C184 SATA_ITX_DRX_N0 SATA_ITX_DRX_N0 <37> SSD
R105 1 @ HDA_SPKR HDA_SYNC SATA0TXN SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 2 SATA_ITX_DRX_P0
2 1K_0402_5% L34 HDA_SYNC SATA0TXP AP5 1 C185 SATA_ITX_DRX_P0 <37>

HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10 SATA_DTX_C_IRX_N1

<42> HDA_SPKR SPKR SATA1RXN SATA_DTX_C_IRX_N1 <41>
LOW= Disable (Default) SATA_DTX_C_IRX_P1
* HDA_RST# K34 HDA_RST#
SATA1RXP
SATA1TXN
AM8
AP11 SATA_ITX_C_DRX_N1 0.01U_0402_16V7K 2 1 C273 SATA_ITX_DRX_N1
SATA_DTX_C_IRX_P1 <41>
SATA_ITX_DRX_N1 <41> HDD
AP10 SATA_ITX_C_DRX_P1 0.01U_0402_16V7K 2 1 C272 SATA_ITX_DRX_P1 SATA_ITX_DRX_P1 <41>
SATA1TXP
C +3VALW HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
<42> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <41>
AD5 SATA_DTX_C_IRX_P2 SATA_DTX_C_IRX_P2 <41>
HDA_SDOUT SATA2RXP SATA_ITX_C_DRX_N2 0.01U_0402_16V7K 2 SATA_ITX_DRX_N2_CONN
R106 2 @ 1 1K_0402_5% G34 HDA_SDIN1 SATA2TXN AH5 1 C186 SATA_ITX_DRX_N2_CONN <41> ODD
AH4 SATA_ITX_C_DRX_P2 0.01U_0402_16V7K 2 1 C187 SATA_ITX_DRX_P2_CONN
SATA2TXP SATA_ITX_DRX_P2_CONN <41>
Low = Disabled (Default)
* C34

IHDA
HDA_SDIN2
High = Enabled [Flash Descriptor Security Overide] SATA3RXN AB8
A34 HDA_SDIN3 SATA3RXP AB10
AF3
R109 SATA3TXN
AF1
ME_FLASH HDA_SDOUT SATA3TXP
<45> ME_FLASH 1 2 A36

SATA
+3VALW 0_0402_5% HDA_SDO SATA_DTX_C_IRX_N4
Y7 SATA_DTX_C_IRX_N4 <48>
SATA4RXN SATA_DTX_C_IRX_P4
SATA4RXP
Y5 ESATA@ SATA_DTX_C_IRX_P4 <48> ESATA
R108 2 <BOM1Structure>
1K_0402_5% HDA_SYNC R107 1 @ 2 1K_0402_1% PCH_GPIO33 C36 AD3 SATA_ITX_C_DRX_N4 0.01U_0402_16V7K 2 1 C188 SATA_ITX_DRX_N4
HDA_DOCK_EN# / GPIO33 SATA4TXN SATA_ITX_DRX_N4 <48>
AD1 SATA_ITX_C_DRX_P4 0.01U_0402_16V7K 2 1 C189 SATA_ITX_DRX_P4 SATA_ITX_DRX_P4 <48>
Kill_SW# SATA4TXP ESATA@
This signal has a weak internal pull-down <46> Kill_SW# N32
HDA_DOCK_RST# / GPIO13
Y3
R110 SATA5RXN
Y1
On Die PLL VR Select is supplied by 51_0402_5% SATA5RXP
AB3
1.5V when smapled high PCH_JTAG_TCK SATA5TXN
* 1.8V when sampled low
2 1 J3
JTAG_TCK SATA5TXP
AB1

PCH_JTAG_TMS H7 Y11 R111

Needs to be pulled High for Huron River platfrom

JTAG
JTAG_TMS SATAICOMPO 37.4_0402_1% +1.05VS_VCC_SATA
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI
R112 PCH_JTAG_TDO H1
33_0402_5% +3VS JTAG_TDO R113 +1.05VS_SATA3
AB12
SATA3RCOMPO
<42> HDA_BITCLK_AUDIO 1 2 HDA_BIT_CLK 49.9_0402_1%
2
G

R114 Q10 AB13 SATA3_COMP 1 2

33_0402_5% BSS138_NL_SOT23-3 SATA3COMPI

<42> HDA_SYNC_AUDIO 1 2 HDA_SYNC_R 3 1 HDA_SYNC

R116 SPI_CLK_PCH RBIAS_SATA3 R115 1 2 750_0402_1%
S

T3 AH1
33_0402_5% SPI_CLK SATA3RBIAS
B B
<42> HDA_RST_AUDIO# 2 HDA_RST#
1 <BOM Structure> SPI_SB_CS0# Y14
SPI_CS0#
R118 1 2 R117 2 1 10K_0402_5% +3VS
33_0402_5% T1
SPI

SPI_CS1#
<42> HDA_SDOUT_AUDIO 2 HDA_SDOUT
1 <BOM Structure> @ R325 P3 HDD_LED#
HDD_LED# <50>
SATALED#

4MB SPI ROM FOR ME

0_0402_5%
SPI_SI V4 V14 PCH_GPIO21 2 R119 1
SPI_MOSI SATA0GP / GPIO21 +3VS
10K_0402_5%

& Non-share ROM.

SPI_SO_R U3 P1 SATA_DET# SPI_CLK_PCH
+3VALW +3VALW +3VALW SPI_MISO SATA1GP / GPIO19 SATA_DET# <37>
6/17 follow module design
COUGARPOINT_FCBGA989 R316 2 1 10K_0402_5% +3VS
1

1
R121 R122 R123 R124
200_0402_5% 200_0402_5% 200_0402_5% 33_0402_5%
+3VS @
2

2
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI
1

R127 1 2 SPI_WP#_0 C190

<BOM
R125Structure> R126 R128 3.3K_0402_5% 22P_0402_50V8J
100_0402_1% 100_0402_1% 100_0402_1% @
R129 1 2 SPI_HOLD#_0 +3VS
3.3K_0402_5%
2

C191
DPDG1.1 1 2
R130
0_0402_5% U5 0.1U_0402_16V4Z
6/30 update R121, R122, R123 SPI_SB_CS0# 1 2 SPI_SB_CS0#_R 1 8 R1336
SPI_SO_R CS# VCC
1 2 SPI_SO_L0 2 7 SPI_HOLD#_0 0_0402_5%
SPI_WP#_0 SO HOLD# SPI_CLK_PCH_0 SPI_CLK_PCH
3 6 1 2
33_0402_5% WP# SCLK SPI_SI_R0 SPI_SI
4 5 1 2
R131 GND SI
A S IC FL 32M W25Q32BVSSIG SOIC 8P 33_0402_5% A
R133

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/8) SATA,HDA,SPI, LPC, XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 14 of 63
5 4 3 2 1
 5 4 3 2 1

10K_0402_5%
U4B Q60A
2 1 +3VALW 2N7002DW-T/R7_SOT363-6
PCIE_PRX_DTX_N1 BG34 R134 6 1 SMB_CLK_S3
<38> PCIE_PRX_DTX_N1 PERN1 SMB_CLK_S3 <12,13,37>
LAN <38> PCIE_PRX_DTX_P1 PCIE_PRX_DTX_P1 BJ34 E12 EC_LID_OUT#
PERP1 SMBALERT# / GPIO11 EC_LID_OUT# <45>
C192 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 2.2K_0402_5% 2.2K_0402_5%
<38> PCIE_PTX_C_DRX_N1
<38> PCIE_PTX_C_DRX_P1
C193
1
1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1
AV32
AU32
PETN1
H14 PCH_SMBCLK 1 R136 2 1 2 R137 DIMM1

2
PETP1 SMBCLK

<37> PCIE_PRX_DTX_N2
PCIE_PRX_DTX_N2 BE34 PERN2 SMBDATA C9 PCH_SMBDATA
+3VALW
1 2 1
+3VS
2 DIMM2

5
PCIE_PRX_DTX_P2 R135 R138
WLAN
<37> PCIE_PRX_DTX_P2
<37> PCIE_PTX_C_DRX_N2
C194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2
BF34
BB32
PERP2
PETN2
2.2K_0402_5% 2.2K_0402_5% MINI CARD
C195 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3

SMBUS
<37> PCIE_PTX_C_DRX_P2 PETP2 DRAMRST_CNTRL_PCH SMB_DATA_S3 <12,13,37>
A12 DRAMRST_CNTRL_PCH <7>
SML0ALERT# / GPIO60 2.2K_0402_5% 2N7002DW-T/R7_SOT363-6
BG36
PERN3 R1292 2
BJ36
PERP3 SML0CLK
C8 1 2 R329 1 +3VALW Q60B
D 1K_0402_5% D
AV34
PETN3 R1291 2
AU34 G12 1
PETP3 SML0DATA 2.2K_0402_5% Q61A
PCIE_PRX_DTX_N4 BF36 2N7002DW-T/R7_SOT363-6
<49> PCIE_PRX_DTX_N4 PERN4
USB30@ PCIE_PRX_DTX_P4 BE36 10K_0402_5% 6 1 EC_SMB_CK2
<49> PCIE_PRX_DTX_P4 PERP4 EC_SMB_CK2 <23,40,45>
USB3.0 C275 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_GPIO74 2 1 +3VALW
<49> PCIE_PTX_C_DRX_N4 PCIE_PTX_DRX_P4 PETN4 SML1ALERT# / PCHHOT# / GPIO74
C274 1 2 0.1U_0402_10V7K BB34 2.2K_0402_5%
<49> PCIE_PTX_C_DRX_P4
USB30@ PETP4
E14 PCH_SML1CLK R140 1 R141 2 VGA

PCI-E*

2
PCIE_PRX_DTX_N5 SML1CLK / GPIO58
<44> PCIE_PRX_DTX_N5
<44> PCIE_PRX_DTX_P5 PCIE_PRX_DTX_P5
BG37
BH37
PERN5
PERP5 SML1DATA / GPIO75
M16 PCH_SML1DATA
+3VALW
1 2
+3VS EC

5
Card Reader C277 2 0.1U_0402_10V7K PCIE_PTX_DRX_N5 R142
<44> PCIE_PTX_C_DRX_N5
<44> PCIE_PTX_C_DRX_P5
C276
1
1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P5
AY36
BB36
PETN5
PETP5
2.2K_0402_5% thermal sensor
3 4 EC_SMB_DA2
EC_SMB_DA2 <23,40,45>
BJ38 PERN6
BG38 2N7002DW-T/R7_SOT363-6

Controller
PERP6
AU36 PETN6 CL_CLK1 M7 Q61B
AV36 +3VALW
PETP6

Link
BG40 PERN7 CL_DATA1 T11

2
BJ40 PERP7
AY40 R143
PETN7
BB40 PETP7 CL_RST1# P10 10K_0402_5%
OPTI@
BE38 R144

1
PERN8 0_0402_5%
BC38 PERP8
AW38 OPTI@ 1 2
PETN8 CLK_REQ_VGA# <23>
AY38 PETP8 10K_0402_5% R145
PEG_A_CLKRQ# / GPIO47 M10 PEG_CLKREQ#_R 1 2
UMA_ONLY@
Desktop Only Y40
Y39
CLKOUT_PCIE0N
CLKOUT_PCIE0P CLK_PCIE_VGA#_R R146 1 OPTI@ 2 0_0402_5% CLK_PCIE_VGA#
CLKOUT_PEG_A_N AB37 CLK_PCIE_VGA# <23>

CLOCKS
C R147 PCH_GPIO73 CLK_PCIE_VGA_R CLK_PCIE_VGA C
+3VALW 2 1 10K_0402_5% J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 R148 1 2 0_0402_5% CLK_PCIE_VGA <23>
OPTI@

R149 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI#

<37> CLK_PCIE_WLAN1# CLK_PCIE_WLAN1_R CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI CLK_CPU_DMI# <6>
R150 1 2 0_0402_5% AB47 AU22
<37> CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN
<37> WLAN_CLKREQ1# R156 1 2 0_0402_5% WLAN_CLKREQ1#_R M1
R158 PCIECLKRQ1# / GPIO18
+3VS 2 1 10K_0402_5% AM12
CLKOUT_DP_N / CLKOUT_BCLK1_N
AM13
R310 CLK_USB30# CLKOUT_DP_P / CLKOUT_BCLK1_P
<49> CLK_PCIE_USB30# 1 USB30@2 0_0402_5% AA48
CLK_USB30 CLKOUT_PCIE2N
USB3.0 <49> CLK_PCIE_USB30
R309 1 2 0_0402_5% AA47
CLKOUT_PCIE2P
USB30@ BF18 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5%
R308 PCH_GPIO20 CLKIN_DMI_N CLK_BUF_CPU_DMI
<49> USB30_CLKREQ# 1 USB30@2 0_0402_5% V10
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
BE18 R157 1 2 10K_0402_5%
+3VS R301 2 1 10K_0402_5%

R153 1 2 0_0402_5% CLK_PCIE_LAN#_R Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5%

<38> CLK_PCIE_LAN# CLK_PCIE_LAN_R CLKOUT_PCIE3N CLKIN_DMI2_N CLKIN_DMI2
LAN <38> CLK_PCIE_LAN
R154 1 2 0_0402_5% Y36
CLKOUT_PCIE3P CLKIN_DMI2_P
BG30 R160 1 2 10K_0402_5%

R151 1 2 0_0402_5% PCH_GPIO25 A8

<38> CLKREQ_LAN# PCIECLKRQ3# / GPIO25 CLK_BUF_DREF_96M#
+3VALW R152 2 1 10K_0402_5% G24 R162 1 2 10K_0402_5%
CLKIN_DOT_96N CLK_BUF_DREF_96M R163 1 10K_0402_5%
E24 2
CLKIN_DOT_96P
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P CLK_BUF_PCIE_SATA# R164 1 10K_0402_5%
AK7 2
R165 PCH_GPIO26 CLKIN_SATA_N / CKSSCD_N CLK_BUF_PCIE_SATA R166 1
+3VALW 2 1 10K_0402_5% L12 AK5 2 10K_0402_5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P

<44> CLK_PCIE_CARD_PCH#
R312 1 2 0_0402_5% CLK_PCIE_CARD_PCH#_R V45
CLKOUT_PCIE5N REFCLK14IN
K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%
<44> CLK_PCIE_CARD_PCH
R311 1 2 0_0402_5% CLK_PCIE_CARD_PCH_R V46
CLKOUT_PCIE5P
Card Reader
R1308 1 2 0_0402_5% PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
<44> CPPE# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18>
@
B R168 XTAL25_IN B
+3VALW 2 1 10K_0402_5%
AB42 V47 XTAL25_IN
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT XTAL25_OUT
AB40 V49 1 2
CLKOUT_PEG_B_P XTAL25_OUT R169 1M_0402_5%
R170 2 1 10K_0402_5% PCH_GPIO56 E6 R171 +1.05VS_VCCDIFFCLKN
+3VALW PEG_B_CLKRQ# / GPIO56 90.9_0402_1% Y2
Y47 XCLK_RCOMP 1 2 2 1
XCLK_RCOMP
V40 1 1
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P 25MHZ_20PF_7A25000012
C196 C197
+3VALW R172 2 1 10K_0402_5% PCH_GPIO45 T13 27P_0402_50V8J 27P_0402_50V8J
PCIECLKRQ6# / GPIO45 2 2
V38 K43
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 R173
FLEX CLOCKS

V37
CLKOUT_PCIE7P CLK_PCI_DB_R
CLKOUTFLEX1 / GPIO65
F47 1 2 22_0402_5% CLK_PCI_DB <37>
R174 2 1 10K_0402_5% PCH_GPIO46 K12 @
+3VALW PCIECLKRQ7# / GPIO46
H47
CLKOUTFLEX2 / GPIO66
AK14
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK13 K49
CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67

COUGARPOINT_FCBGA989

@ R176 @ C199
33_0402_5% 22P_0402_50V8J
CLK_PCI_LPBACK 2 1 1 2
A A

Reserve for EMI please close to PCH

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/8) PCIE, SMBUS, CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 15 of 63
5 4 3 2 1
 5 4 3 2 1

D D

U4C

DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
<5> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <5>
<5> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 FDI_CTX_PRX_N3 <5>
DMI3RXN FDI_RXN3 FDI_CTX_PRX_N4
BC12 FDI_CTX_PRX_N4 <5>
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5
<5> DMI_CTX_PRX_P0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_CTX_PRX_N5 <5>
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
<5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
<5> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 <5>
DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7
<5> DMI_CTX_PRX_P3 BJ20 DMI3RXP
BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 <5>
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1
<5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <5>
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <5>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 <5>
<5> DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P4
AV18 BE12

DMI
FDI
<5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <5>
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6
<5> DMI_CRX_PTX_P0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 <5>
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
MC74VHC1G08DFT2G SC70 5P DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 DMI2TXP
3

DMI_CRX_PTX_P3 AU18
<5> DMI_CRX_PTX_P3 DMI3TXP
VGATE 1 AW16 FDI_INT
G

A SYS_PWROK FDI_INT FDI_INT <5> +RTCVCC

Y 4
PCH_POK 2 +1.05VS_PCH BJ24 AV12 FDI_FSYNC0
B DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5>
P

1
U6 1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
FDI_FSYNC1 <5>
5

R177 49.9_0402_1% DMI_IRCOMP FDI_FSYNC1 R179

1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 330K_0402_5%
C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C
R178 750_0402_1%
+3VS 4mil width and place BB10 FDI_LSYNC1

：：
FDI_LSYNC1 <5>

2
FDI_LSYNC1
DSWODVREN - On Die DSW VR Enable
R180 2 1 100K_0402_1% SYS_PWROK
within 500mil of the PCH * H Enable
L Disable
SUSACK# is only used on platform A18 DSWODVREN 0_0402_5%
DSWVRMEN

1
that support the Deep Sx state. 1 2 PCH_RSMRST#_R

System Power Management

R181 0_0402_5% R183
T72 PAD SUSACK# C12 E22 PCH_DPWROK_R 1 2 PCH_DPWROK <45> 330K_0402_5%
SUSACK# DPWROK R185 @ R1287 @
0_0402_5%

2
8/02 Modify follow Module Design. +3VS 2 1 SYS_RST# K3 B9 WAKE# 1 2 PCIE_WAKE# <37,38,49>
R184 10K_0402_5% SYS_RESET# WAKE#
1 2 10K_0402_5% +3VALW
+3VS R186
R188 1 @ 2 0_0402_5% SYS_PWROK P12 N3 PM_CLKRUN# PAD T73
<60> VGATE SYS_PWROK CLKRUN# / GPIO32
1 R189 2 +3VS

2
R1298 2 1 200_0402_5% PM_DRAM_PWRGD R190 1 2 0_0402_5% 8.2K_0402_5%
<45> PCH_POK
R191 PWROK L22 G8 SUS_STAT#
AEPWROK can be connect to @ PWROK SUS_STAT# / GPIO61
0_0402_5%
PWROK if iAMT disable
R302 1 2 0_0402_5% APWROK L10 N14 SUSCLK
<45> PCH_APWROK SUSCLK <45>
1

+3VALW APWROK SUSCLK / GPIO62

PM_DRAM_PWRGD B13 D10 SLP_S5#

<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 SLP_S5# <45>
R192 2 @ 1 200_0402_5% PM_DRAM_PWRGD
1 2 PCH_RSMRST#_R C21 H4 SLP_S4#
<45> EC_RSMRST# RSMRST# SLP_S4# SLP_S4# <45>
R194 2 1 10K_0402_5% SUSWARN# R193 0_0402_5%

R195 2 1 10K_0402_5% ACIN_R 1 2 SUSWARN#_R K16 F4 SLP_S3#

<45> SUSWARN# SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# SLP_S3# <45>
R196 0_0402_5%
Can be left NC
B R197 PCH_RSMRST#_R PBTN_OUT#_R B
2 1 10K_0402_5% <45> PBTN_OUT# 1 2 E20
PWRBTN# SLP_A#
G10 when IAMT is not
R198 0_0402_5% support on the
D29 ACIN_R PM_SLP_SUS# platfrom
<45,54> ACIN 1 2 RB751V_SOD323 H20 G16 PAD T71
ACPRESENT / GPIO31 SLP_SUS#
1 2
R199 @ 0_0402_5%
1 R200 2 PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
8.2K_0402_5%
10/02 Change to SCS00000Z00 R201 Can be left NC if no use
+3VALW 2 1 RI# A10
RI# SLP_LAN# / GPIO29
K14 integrated LAN.
10K_0402_5%

COUGARPOINT_FCBGA989

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/8) DMI,FDI,PM,
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 16 of 63
5 4 3 2 1
 5 4 3 2 1

D D

U4D
PCH_ENBKL J47 AP43
<34> PCH_ENBKL PCH_ENVDD L_BKLTEN SDVO_TVCLKINN +3VS
<34> PCH_ENVDD M45 AP45
L_VDD_EN SDVO_TVCLKINP

<34> PCH_PWM P45 L_BKLTCTL SDVO_STALLN AM42

SDVO_STALLP AM40

1
EDID_CLK T40
Pull up R for CONN SIDE <34> EDID_CLK EDID_DATA L_DDC_CLK
K47 AP39 R202 R203
<34> EDID_DATA L_DDC_DATA SDVO_INTN
AP40 2.2K_0402_5% 2.2K_0402_5%
R204 1 CTRL_CLK SDVO_INTP
+3VS 2 2.2K_0402_5% T45 L_CTRL_CLK
HDMI@ HDMI@
R205 1 2 2.2K_0402_5% CTRL_DATA P39

2
2.37K_0402_1% L_CTRL_DATA
R206 2 1 LVDS_IBG AF37 P38 HDMICLK HDMICLK <36>
LVD_IBG SDVO_CTRLCLK HDMIDAT
AF36 LVD_VBG SDVO_CTRLDATA M39 HDMIDAT <36>
0_0402_5% LVD_VREF AE48
R207 LVD_VREFH
2 1 AE47 LVD_VREFL DDPB_AUXN AT49
DDPB_AUXP AT47
DDPB_HPD AT40 TMDS_B_HPD# <36>
AK39

LVDS
<34> LVDS_ACLK# LVDSA_CLK#
<34> LVDS_ACLK AK40 LVDSA_CLK DDPB_0N AV42 TMDS_B_DATA2#_PCH HDMI@ C200 1 2 0.1U_0402_10V6K
HDMI_TX2-_CK <36>
DDPB_0P AV40 TMDS_B_DATA2_PCH HDMI@ C201 1 2 0.1U_0402_10V6K
HDMI_TX2+_CK <36>
<34> LVDS_A0# AN48 LVDSA_DATA#0 DDPB_1N AV45 TMDS_B_DATA1#_PCH HDMI@ C202 1 2 0.1U_0402_10V6K
HDMI_TX1-_CK <36>
AM47 AV46 TMDS_B_DATA1_PCH HDMI@ C203 1 2 0.1U_0402_10V6K

Digital Display Interface

C <34> LVDS_A1# LVDSA_DATA#1 DDPB_1P HDMI_TX1+_CK <36> C
<34> LVDS_A2# AK47 LVDSA_DATA#2 DDPB_2N AU48 TMDS_B_DATA0#_PCH HDMI@ C204 1 2 0.1U_0402_10V6K
HDMI_TX0-_CK <36> HDMI
AJ48 LVDSA_DATA#3 DDPB_2P AU47 TMDS_B_DATA0_PCH HDMI@ C205 1 2 0.1U_0402_10V6K
HDMI_TX0+_CK <36>
DDPB_3N AV47 TMDS_B_CLK#_PCH HDMI@ C206 1 2 0.1U_0402_10V6K
HDMI_CLK-_CK <36>
<34> LVDS_A0 AN47 LVDSA_DATA0 DDPB_3P AV49 TMDS_B_CLK_PCH HDMI@ C207 1 2 0.1U_0402_10V6K
HDMI_CLK+_CK <36>
<34> LVDS_A1 AM49 LVDSA_DATA1
<34> LVDS_A2 AK49 LVDSA_DATA2 HDMI@
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
P42
DDPC_CTRLDATA
AF40
LVDSB_CLK#
AF39 AP47
LVDSB_CLK DDPC_AUXN
AP49
DDPC_AUXP
AH45 AT38
LVDSB_DATA#0 DDPC_HPD
AH47
LVDSB_DATA#1
AF49 AY47
LVDSB_DATA#2 DDPC_0N
AF45 AY49
LVDSB_DATA#3 DDPC_0P
AY43
DDPC_1N
AH43 AY45
DAC_BLU LVDSB_DATA0 DDPC_1P
<35> DAC_BLU AH49 BA47
R208 2 LVDSB_DATA1 DDPC_2N
1 150_0402_1% AF47 BA48
LVDSB_DATA2 DDPC_2P
AF43 BB47
DAC_GRN LVDSB_DATA3 DDPC_3N
<35> DAC_GRN BB49
R209 2 DDPC_3P
1 150_0402_1%

DAC_RED N48 M43

<35> DAC_RED CRT_BLUE DDPD_CTRLCLK
R210 2 1 150_0402_1% P49 M36
CRT_GREEN DDPD_CTRLDATA
T49
CRT_RED
AT45

CRT
CRT_DDC_CLK DDPD_AUXN
<35> CRT_DDC_CLK T39 AT43
Pull up R for CONN SIDE CRT_DDC_DATA CRT_DDC_CLK DDPD_AUXP
<35> CRT_DDC_DATA M40 BH41
CRT_DDC_DATA DDPD_HPD
B B
BB43
DDPD_0N
<35> CRT_HSYNC M47 BB45
CRT_HSYNC DDPD_0P
<35> CRT_VSYNC M49 BF44
CRT_VSYNC DDPD_1N
BE44
DDPD_1P
BF42
CRT_IREF DDPD_2N
T43 BE42
DAC_IREF DDPD_2P
T42 BJ42
CRT_IRTN DDPD_3N
BG42
DDPD_3P
1

R211 COUGARPOINT_FCBGA989
1K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS,CRT,DP,HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 17 of 63
5 4 3 2 1
 5 4 3 2 1

+3VS

R297 1 @ 2 8.2K_0402_5% PCH_GPIO53 U4E

NV_CE#0 AY7
NV_CE#1 AV7
RP2 BG26 AU3
PCI_PIRQA# TP1 NV_CE#2
8 1 BJ26 TP2 NV_CE#3 BG4
7 2 PCI_PIRQD# BH25
PCI_PIRQC# TP3
6 3 BJ16 TP4 NV_DQS0 AT10
5 4 PCI_PIRQB# BG16 BC8
TP5 NV_DQS1
AH38
8.2K_0804_8P4R_5% TP6
AH37 AU2
TP7 NV_DQ0 / NV_IO0
AK43 AT4
D TP8 NV_DQ1 / NV_IO1 D
AK45 AT3
RP1 TP9 NV_DQ2 / NV_IO2
C18 AT1
PCH_GPIO4 TP10 NV_DQ3 / NV_IO3
8 1 N30
TP11 NV_DQ4 / NV_IO4
AY3
7 2 PCH_GPIO54 H3 AT5
PCH_GPIO3 TP12 NV_DQ5 / NV_IO5
6 3 AH12 AV3

NVRAM
PCH_GPIO2 TP13 NV_DQ6 / NV_IO6
5 4 AM4
TP14 NV_DQ7 / NV_IO7
AV1
AM5 BB1
8.2K_0804_8P4R_5% TP15 NV_DQ8 / NV_IO8
Y13 BA3
TP16 NV_DQ9 / NV_IO9
K24 BB5
R225 WL_OFF# TP17 NV_DQ10 / NV_IO10
1 2 8.2K_0402_5% L24 BB3
TP18 NV_DQ11 / NV_IO11
AB46 BB7
TP19 NV_DQ12 / NV_IO12
AB45 BE8

RSVD
R212 PCH_GPIO52 TP20 NV_DQ13 / NV_IO13
1 2 8.2K_0402_5% NV_DQ14 / NV_IO14 BD4
NV_DQ15 / NV_IO15 BF6
R213 1 2 8.2K_0402_5% PCH_GPIO5
B21 TP21 NV_ALE AV5
M20 AY1 NV_CLE
TP22 NV_CLE
AY16 TP23
R214 1 2 8.2K_0402_5% PCH_GPIO50 BG46 AV10
TP24 NV_RCOMP
@ AT8
NV_RB#
DMI Termination Voltage
BE28 TP25 NV_RE#_WRB0 AY5
BC30 TP26 NV_RE#_WRB1 BA2 Set to Vcc when HIGH
BE32 TP27
NV_CLE
BJ32 TP28 NV_WE#_CK0 AT12 Set to Vss when LOW
WL_OFF# R215 1 @ 2 1K_0402_5% BC28 BF3
TP29 NV_WE#_CK1
BE30 TP30 USB DEBUG=PORT1 AND PORT9 +1.8VS
BF32 TP31
BG32 C24 USB20_N0
TP32 USBP0N USB20_N0 <48>
A16 swap overide Strap/Top-Block AV26 A24 USB20_P0 RIGHT USB (CABLE) for SW request
TP33 USBP0P USB20_P0 <48>

1
Swap Override jumper BB26 C25 USB20_N1 7/29 update
C TP34 USBP1N USB20_P1 USB20_N1 <48> C
AU28 B25 RIGHT USB (COMBO) R216
TP35 USBP1P USB20_N2 USB20_P1 <48>
Low=A16 swap AY30 TP36 USBP2N C26 USB20_N2 <49> 2.2K_0402_5%
override/Top-Block AU26 A26 USB20_P2 LEFT USB
TP37 USBP2P USB20_N3 USB20_P2 <49>
PCI_GNT3# Swap Override enabled AY26 K28 USB20_N3 <49>

2
TP38 USBP3N USB20_P3 NV_CLE
High=Default * AV28 TP39 USBP3P H28 USB20_P3 <49> LEFT USB 2 1 H_SNB_IVB# <6>
AW30 E28 R217 1K_0402_5%
TP40 USBP4N
USBP4P D28
C28 USB20_N5 CLOSE TO THE BRANCHING POINT
USBP5N USB20_P5 USB20_N5 <34>
USBP5P
A28 USB20_P5 <34> USB Camera
C29
USBP6N
B29
PCI_PIRQA# USBP6P
K40 N28
PCI_PIRQB# PIRQA# USBP7N
K38 M28

PCI
PCI_PIRQC# PIRQB# USBP7P
H38 L30
PCI_PIRQD# PIRQC# USBP8N
G38 K30
OPTI@ PIRQD# USBP8P USB20_N9
G30 USB20_N9 <37>
PCH_GPIO50 USBP9N USB20_P9 +3VALW
R314 1 2 C46 E30 WLAN 8/03 update

USB
<23> DGPU_HOLD_RST# PCH_GPIO52 REQ1# / GPIO50 USBP9P USB20_P9 <37>
0_0402_5% C44 C30
R315 PCH_GPIO54 REQ2# / GPIO52 USBP10N
<23,51,58,59> DGPU_PWR_EN 1 2 E40
REQ3# / GPIO54 USBP10P
A30
0_0402_5% L32 USB_OC0# 1 2
OPTI@ PCH_GPIO51 USBP11N USB_OC2# R1299 1
D47
GNT1# / GPIO51 USBP11P
K32 2 10K_0402_5%
PCH_GPIO53 E42 G32 USB_OC7# R1300 1 2 10K_0402_5%
WL_OFF# GNT2# / GPIO53 USBP12N USB_OC5# R1301 1
<37> WL_OFF# F46 E32 2 10K_0402_5%
GNT3# / GPIO55 USBP12P USB20_N13 R1302 10K_0402_5%
C32 USB20_N13 <47>
USBP13N USB20_P13
GPIO53=This Signal has a weak internal pull-up. PCH_GPIO2 USBP13P
A32 USB20_P13 <47> Bluetooth
G42
NOTE: The internal pull-up is disabled after ODD_DA# PCH_GPIO3 PIRQE# / GPIO2
<41,45> ODD_DA# 1 2
PCH_GPIO4
G40
PIRQF# / GPIO3 USBRBIAS
Within 500 mils
PLTRST# deasserts. 0_0402_5% R715 C42 C33 1 2
PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# R218 22.6_0402_1%
@ D44
PIRQH# / GPIO5 USB_OC1# 1 2
B33 USB_OC4# R1303 1 2 10K_0402_5%
USBRBIAS USB_OC3# R1304 1
<45> PCI_PME# K10 2 10K_0402_5%
B PME# USB_OC6# R1305 1 B
2 10K_0402_5%
PLT_RST# C6 A14 USB_OC0# R1306 10K_0402_5%
<6> PLT_RST# PLTRST# OC0# / GPIO59 USB_OC1# USB_OC0# <48>
K20 USB_OC1# <49>
R219 22_0402_5% OC1# / GPIO40 USB_OC2#
B17
CLK_PCI_LPBACK_R H49 OC2# / GPIO41 USB_OC3#
<15> CLK_PCI_LPBACK 1 2 C16
CLK_PCI_LPC_R CLKOUT_PCI0 OC3# / GPIO42 USB_OC4#
<45> CLK_PCI_LPC 1 2 H43
CLKOUT_PCI1 OC4# / GPIO43
L16
R220 22_0402_5% J48 A16 USB_OC5#
CLKOUT_PCI2 OC5# / GPIO9 USB_OC6#
K42 D14
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
H40 C14
PCH_GPIO51 R221 @ CLKOUT_PCI4 OC7# / GPIO14
1 2 1K_0402_5%

COUGARPOINT_FCBGA989

Boot BIOS Strap bit1 BBS1

Boot BIOS 1 2
R222 0_0402_5%
Bit11 Bit10 Destination
0 1 Reserved
GNT1#/
GPIO51 1 0 Reserved MC74VHC1G08DFT2G SC70 5P

3
@
1 1 SPI (Default) PLT_RST#
* 1

G
A
<23,37,38,44,45,49> BUF_PLT_RST# 4
Y
0 0 LPC B
2

P
1
1 U7

5
1U_0402_6.3V4Z
C208 R223
100K_0402_5%
A @ 2 +3VS A

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 18 of 63
5 4 3 2 1
 5 4 3 2 1

+3VS

R702 R703 R704

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
@

1
PCH_GPIO69
5503@ OPTI@
PCH_GPIO70
D D

7/29 update for ESATA detect PCH_GPIO71 R707 R705 R706

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
6/24 Change to @ follow module design +3VS R233 1 2 10K_0402_5% PCH_GPIO0

UMA_ONLY@
and double check on module design meeting
<48> ESATA_DET# 1 2 U4F
ICC_EN# 0_0402_5% R303
Integrated Clock Chip Enable T7 C40 PCH_GPIO68

1
BMBUSY# / GPIO0 TACH4 / GPIO68
H ; Disable R227 1 2 10K_0402_5% ESATA_DET_R# A42 B41 PCH_GPIO69 272@
L ; Enable TACH1 / GPIO1 TACH5 / GPIO69
* +3VS R228 1 2 10K_0402_5% DEVICE_RST# H36 TACH2 / GPIO6 TACH6 / GPIO70 C41 PCH_GPIO70 +3VS
@
<37,38,44> DEVICE_RST# 6/23 update for MB ID
R235 1 2 1K_0402_5% EC_SMI# <45> EC_SCI# EC_SCI# E38 A40 PCH_GPIO71
TACH3 / GPIO7 TACH7 / GPIO71

2
EC_SMI# C10 R236
<45> EC_SMI# GPIO8
Weak internal pull-high 10K_0402_5%
R229 1 @ 2 10K_0402_5% PCH_GPIO12 C4
+3VALW LAN_PHY_PWR_CTRL / GPIO12

1
R230 1 2 1K_0402_5% SMIB G2 P4
GPIO15 A20GATE GATEA20 <45> +3VS
<49> SMIB @
GPIO28 AU16 PCH_PECI_R 1 @ 2

CPU/MISC
ESATA_DET_RR# PECI H_PECI <6,45> PCH_GPIO68 R224
On-Die PLL Voltage Regulator +3VS R231 1 2 10K_0402_5% U2 SATA4GP / GPIO16
0_0402_5% R237 1 2 10K_0402_5%
This signal has a weak internal pull up 1 2 P5 KB_RST#

：
<23,59> VGA_PGOOD RCIN# KB_RST# <45>
R1239 OPTI@0_0402_5% KB_RST# R226 1 2 10K_0402_5%

：On-Die

GPIO
H voltage regulator enable R232 2 10K_0402_1% VGA_PGOOD_R
* L On-Die PLL Voltage Regulator disable
1
@
D40 TACH0 / GPIO17 PROCPWRGD AY11 H_CPUPWRGD <6>
R238 1 2 10K_0402_5% BT_DISABLE T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
+3VS SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# <6>
R240 1 @ 2 1K_0402_5% PCH_GPIO28 <37> BT_DISABLE
R239 390_0402_5%
ODD_EN E8 T14
+3VALW <41> ODD_EN GPIO24 / MEM_LED INIT3_3V#
PCH_GPIO27 PCH_THRMTRIP#_R <23>
E16 GPIO27
C R241 INIT3_3V C
1 <BOM 2Structure>
10K_0402_5% PCH_GPIO28 P8 GPIO28
<37,47> BT_OFF# NC_1 AH8 This signal has weak internal
1 @ 2 10K_0402_5% BT_OFF# K1 PU, can't pull low
+3VS STP_PCI# / GPIO34
R242 AK11
PCH_GPIO35 NC_2
PCH_GPIO27 (Have internal Pull-High) 8/5 update R243 1 2 10K_0402_5% K4 GPIO35
AH10
*High: VCCVRM VR Enable
Low: VCCVRM VR Disable +3VS R250 1 @ 2 10K_0402_5% PCH_GPIO36 V8
SATA2GP / GPIO36
NC_3
R1307 1 <BOM 2Structure>
10K_0402_5% AK10
R244 PCH_GPIO37 NC_4
+3VS 1 2 10K_0402_5% M5
SATA3GP / GPIO37
@
NC_5
P37 Intel schematic reviwe recommand.
R245 1 @ 2 10K_0402_5% PCH_GPIO27 R246 1 2 10K_0402_5% PCH_GPIO38 N2
SLOAD / GPIO38
R247 1 2 10K_0402_5% PCH_GPIO39 M3
SDATAOUT0 / GPIO39
R248 1 2 10K_0402_5% PCH_GPIO48 V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
R249 1 2 10K_0402_5% PCH_GPIO49 V3 BG48
+3VS SATA5GP / GPIO49 VSS_NCTF_16
7/29 update for ESATA detect PCH_GPIO57 D6 BH3
GPIO57 VSS_NCTF_17
@ +3VALW R251 1 2 10K_0402_5% BH47
VSS_NCTF_18
<48> ESATA_DET# 1 2 ESATA_DET_RR# NO_VENTURA@
0_0402_5% R1294 R1344 1 2 10K_0402_5% A4 BJ4
VENTURA@ VSS_NCTF_1 VSS_NCTF_19
A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
0812 Checklist Rev.1.2
When Unused as GPIO or SATA*GP - Use 8.2K-10K pull-down to ground. A45 BJ45
VSS_NCTF_3 VSS_NCTF_21

NCTF
A46 BJ46
R1311 10K_0402_5% PCH_GPIO37
<BOM 2Structure> VSS_NCTF_4 VSS_NCTF_22
1
A5 BJ5
B VSS_NCTF_5 VSS_NCTF_23 B
A6 BJ6
VSS_NCTF_6 VSS_NCTF_24
B3 C2
VSS_NCTF_7 VSS_NCTF_25
B47 C48
VSS_NCTF_8 VSS_NCTF_26
BD1 D1
VSS_NCTF_9 VSS_NCTF_27
BD49 D49
VSS_NCTF_10 VSS_NCTF_28
BE1 E1
VSS_NCTF_11 VSS_NCTF_29
BE49 E49
VSS_NCTF_12 VSS_NCTF_30
BF1 F1
VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32

COUGARPOINT_FCBGA989

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 19 of 63
5 4 3 2 1
 5 4 3 2 1

PCH Power Rail Table

+1.05VS U4G POWER +3VS S0 Iccmax
L1 Voltage Rail Voltage Current (A)
1300mA MBK1608221YZF_2P
+1.05VS_PCH AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC
AC23 VCCCORE[2] 1 1 1 V_PROC_IO 1.05 0.001

1U_0402_6.3V6K
C210

1U_0402_6.3V6K
C211

1U_0402_6.3V6K
C212

0.01U_0402_16V7K
C213

0.1U_0402_10V7K
C214
CRT
1 1 1 1 AD21 C215
VCCCORE[3]

10U_0603_6.3V6M
C209
AD23 U47 10U_0805_6.3V6M
VCCCORE[4] VSSADAC
V5REF 5 0.001

VCC CORE
AF21
VCCCORE[5] 2 2 2
AF23
D 2 2 2 2 VCCCORE[6] R252 +3VS D
AG21
VCCCORE[7]
AG23
VCCCORE[8]
0.022_0805_1% V5REF_Sus 5 0.001
AG24 AK36 +VCCA_LVDS 1 2
VCCCORE[9] 1mA VCCALVDS
AG26
VCCCORE[10]
AG27
VCCCORE[11] VSSALVDS
AK37 Vcc3_3 3.3 0.266
AG29
VCCCORE[12]
AJ23

LVDS
VCCCORE[13]
AJ26
VCCCORE[14] VCCTX_LVDS[1]
AM37 VccADAC 3.3 0.001
AJ27 +1.8VS
VCCCORE[15] L2
AJ29 AM38
VCCCORE[16] VCCTX_LVDS[2]
AJ31
VCCCORE[17]
0.1UH_MLF1608DR10KT_10%_1608 VccADPLLA 1.05 0.08
+1.05VS_PCH AP36 +VCCTX_LVDS 2 1
60mA VCCTX_LVDS[3] 0.1uH inductor, 200mA
1 1 1

22U_0805_6.3V6M
C218
VCCTX_LVDS[4] AP37 VccADPLLB 1.05 0.08
R254 2 1 0_0603_5% +1.05VS_VCCDPLLEXP AN19 C216 C217
VCCIO[28] 0.01U_0402_16V7K 0.01U_0402_16V7K
2 2 2 VccCore 1.05 1.3
PAD T47 @ +VCCAPLLEXP BJ22 R256 +3VS
VCCAPLLEXP 0_0805_5%
This pin can be left as no connect in V33 +3VS_VCC3_3_6 1 2 VccDMI 1.05 0.042

HVCMOS
VCC3_3[6]
AN16
On-Die VR enabled mode (default). VCCIO[15]
1
AN17 VCCIO[16]
VccIO 1.05 2.925
V34 C219
VCC3_3[7]
0.1U_0402_10V7K
AN21 2 VccASW 1.05 1.01
@PJP2
@ PJP2 VCCIO[17]
2 1 AN26 VCCIO[18]
VccSPI 3.3 0.02
AN27 2925mA AT16 +VCCAFDI_VRM
PAD-OPEN 4x4m VCCIO[19] VCCVRM[3]
+1.05VS_PCH R257 AP21 +VCCP_VCCDMI +1.05VS VccDSW 3.3 0.003
C VCCIO[20] R258 C
0_0805_5%
1 2 +1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO[21] VCCDMI[1]
@ 1 VccpNAND 1.8 0.19

DMI
+1.05VS_PCH
1U_0402_6.3V6K
C222

1U_0402_6.3V6K
C223

1U_0402_6.3V6K
C224

1U_0402_6.3V6K
C225

1 1 1 1 1 AP24 L75 0_0805_5%

VCCIO
VCCIO[22]
10U_0805_6.3V6M
C221

10UH_LBR2012T100M_20% C220
AP26 VCCIO[23] 20mA VCCIO[1] AB36 +1.05VS_VCC_DMI_CCI 1 2 1U_0402_6.3V6K VccRTC 3.3 6 uA
2
2 2 2 2 2 1 1
AT24 C226 C917
VCCIO[24] 1U_0402_6.3V6K 10U_0603_6.3V6M VccSus3_3 3.3 0.119
@
2
@
2
8/6 439028_HR_PPDG_1.0
AN33
VCCIO[25]
VccSusHDA 3.3 / 1.5 0.01
AN34 AG16
+3VS R260 VCCIO[26] VCCPNAND[1] +VCCPNAND R261 +1.8VS
0_0805_5% 0_0805_5% VccVRM 1.8 / 1.5 0.16

NAND / SPI
1 2 +3VS_VCCA3GBG BH29 AG17 1 2
VCC3_3[3] 190mA VCCPNAND[2]
1
C227 VccCLKDMI 1.05 0.02
0.1U_0402_10V7K AJ16 1
VCCPNAND[3] C228
2 +VCCAFDI_VRM AP16 0.1U_0402_10V7K VccSSC 1.05 0.095
+1.05VS_PCH @ R262 VCCVRM[2]
AJ17
VCCPNAND[4] 2
0_0603_5% Place CH53 Near BG6 pin
2 1 +1.05VS_VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
VCCFDIPLL
+1.05VS_PCH R263
1
1 2 +1.05VS_VCCDPLL_FDI AP17 R313 VccALVDS 3.3 0.001
VCCIO[27]
FDI

@C229
@ C229 0_0805_5% V1 +3V_VCCPSPI 1 2 +3VS
1U_0402_6.3V6K 20mA VCCSPI 0_0805_5%
2 AU20 VccTX_LVDS 1.8 0.06
+VCCP_VCCDMI VCCDMI[2] 1
C230
B COUGARPOINT_FCBGA989 1U_0402_6.3V6K B
2

+VCCAFDI_VRM
+1.5VS

R265 2 1 0_0603_5% +VCCAFDI_VRM

Intel HR_PDDG_1.21
1.5S rail. Default is to poppulate to enable VccVRM.

VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 20 of 63
5 4 3 2 1
 5 4 3 2 1

Have internal VRM

+3VS +1.05VS_PCH @ R268
@ R267 VCC3_3 = 266mA detal waiting for newest spec
0_0805_5% 0_0603_5%
1 2 2 1 +VCCACLK VCCDMI = 42mA detal waiting for newest spec
L3
10UH_LBR2012T100M_20%
+3VS_VCC_CLKF33 +3VALW R269
1 2
1 1 0_0603_5% U4J POWER R270 +1.05VS_PCH

10U_0805_10V4Z
C231

1U_0402_6.3V6K
C232
1 2 +VCCPDSW 0_0603_5%
1 AD49 N26 +1.05VS_VCCUSBCORE 2 1
VCCACLK VCCIO[29]
2 2 1
C234 P26
0.1U_0402_10V7K VCCIO[30] C233
T16 3mA
D C235 2 VCCDSW3_3 1U_0402_6.3V6K D
P28
0.1U_0402_10V7K VCCIO[31] 2
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
@ T29
+3VS_VCC_CLKF33 VCCIO[33] R272 +3VALW
T38
+1.05VS_PCH @ R271 @
L4 VCC3_3[5] 0_0603_5%
0_0603_5% 10UH_LBR2012T100M_20% T23 +3V_VCCPUSB 2 1
1 2 +VCCAPLL_CPY 1 2 +VCCAPLL_CPY_PCH BH23
119mA VCCSUS3_3[7]
VCCAPLLDMI2 +3VALW

0.1U_0402_10V7K
C236
T24 1 R273
R274 +VCCDPLL_CPY VCCSUS3_3[8] +5VALW +3VALW
1 +1.05VS_PCH 1 2 0_0603_5% AL29
VCCIO[14]
0_0603_5%
V23 +3V_VCCAUBG 2 1

USB
VCCSUS3_3[9]

C237
10U_0805_6.3V6M
1

2
@ +VCCSUS1 2 C238
AL24 DCPSUS[3] VCCSUS3_3[10] V24
2 0.1U_0402_10V7K R275 D1
1
P24 100_0402_5% CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 R276 +1.05VS_PCH
1U_0402_6.3V6K AA19 0_0603_5%

1
2 VCCASW[1] +1.05VS_VCCAUPLL +PCH_V5REF_SUS
VCCIO[34] T26 2 1
+1.05VS_PCH R277 AA21 1010mA
VCCASW[2] 1
0_0805_5%
1 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C240
VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 2

22U_0805_6.3V6M
C241

22U_0805_6.3V6M
C242

Clock and Miscellaneous

AA26 @
VCCASW[4] +VCCA_USBSUS C243
DCPSUS[4] AN23 1 2 1U_0402_6.3V6K
AA27 VCCASW[5]
2 2 +3V_VCCPSUS
VCCSUS3_3[1] AN24 10/02 Change to SCS00000Z00.
AA29 VCCASW[6]
AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN R278 +3VALW
VCCASW[8] 1mA V5REF

2
C 0_0603_5% C
1 1 1

1U_0402_6.3V6K
C244

1U_0402_6.3V6K
C245

1U_0402_6.3V6K
C246
AC27 2 1 R279 D2
VCCASW[9] +3V_VCCPSUS 100_0402_5% CH751H-40PT_SOD323-2
VCCSUS3_3[2] N20 1

PCI/GPIO/LPC
AC29 C247
2 2 2 VCCASW[10] 1U_0402_6.3V
N22

1
+1.05VS_PCH VCCSUS3_3[3] +PCH_V5REF_RUN
11/25 0ohm deleted. AC31 VCCASW[11] 2 +3VS
L5 P20 R281 1
10UH_LB2012T100MR_20% VCCSUS3_3[4] 0_0805_5%
AD29
+1.05VS_VCCA_A_DPL VCCASW[12] C248
1 2 P22 2 1
VCCSUS3_3[5] 1U_0603_10V6K
AD31 1
VCCASW[13] C249 2
1 2 +1.05VS_VCCA_B_DPL W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
VCCASW[14] VCC3_3[1]
220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

L6
2 +3VS
1U_0402_6.3V6K
C251

1U_0402_6.3V6K
C253
C250

C252

10UH_LB2012T100MR_20% 1 1 W23 W16 R282

VCCASW[15] VCC3_3[8] 0_0603_5%
1 1
+ + W24 T34 +3VS_VCCPPCI 2 1
VCCASW[16] VCC3_3[4]
1
W26 C254
2 2 2 2 VCCASW[17] 0.1U_0402_10V7K
W29 R283 +3VS
VCCASW[18] 0_0603_5% 2
W31 AJ2 +VCC3_3_2 2 1
R284 VCCASW[19] VCC3_3[2] +1.05VS_SATA3 R285 +1.05VS_PCH
1
0_0603_5% W33 0_0805_5%
+VCCDIFFCLK VCCASW[20] C255
+1.05VS_PCH 2 1 AF13 2 1
VCCIO[5] 0.1U_0402_10V7K
2 1
1 +VCCRTCEXT N16
C256 DCPRTC C257
1 AH13
1U_0402_6.3V6K C258 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
R286 2 VCCVRM[4] VCCIO[13]
0_0603_5% +1.05VS_VCCDIFFCLKN 2
B
2 1 +1.05VS_VCCDIFFCLKN AF14 L7 @ @ R287 +1.05VS_PCH B
+1.05VS_PCH VCCIO[6]
1 +1.05VS_VCCA_A_DPL BD47 10UH_LB2012T100MR_20% 0_0805_5%

SATA
VCCADPLLA 80mA +VCCSATAPLL +VCCSATAPLL_R2
AK1 1 2 1
C259 +1.05VS_VCCA_B_DPL VCCAPLLSATA +VCCAFDI_VRM
BF47
1U_0402_6.3V6K VCCADPLLB 80mA
2 1
AF11 +VCCAFDI_VRM @ C260
R288 +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA R289 +1.05VS_PCH 10U_0805_6.3V6M
AF17
VCCIO[7]
0_0603_5% AF33
VCCIO[8]
0_0805_5% Place CH80 Near AK1 pin
2 1 +1.05VS_SSCVCC AF34 55mA AC16 +1.05VS_VCC_SATA 2 1 2
+1.05VS_PCH VCCIO[9] VCCIO[2]
1 +1.05VS_VCCDIFFCLKN AG34
VCCIO[11]
AC17 1
C262 VCCIO[3] C261
1U_0402_6.3V6K +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
2 VCCIO[10] 95mA VCCIO[4]
@ R290 2
0_0603_5% +VCCSST V16 +1.05VS
+1.05VM_VCCSUS DCPSST
+1.05VS_PCH 2 1 1

1 C263 +1.05VM_VCCSUS T17 T21

0.1U_0402_10V7K DCPSUS[1] VCCASW[22]
V19
DCPSUS[2]
MISC

C264 2
@ 1U_0402_6.3V6K +1.05VS R293 V21
2 0_0603_5% VCCASW[23]
CPU

1 2 +V_CPU_IO BJ8
V_PROC_IO 1mA
T19
VCCASW[21]
1 1 1
+RTCVCC +3VALW
4.7U_0603_6.3V6K
C265

0.1U_0402_10V7K
C266

0.1U_0402_10V7K
C267

RTC

A22 P32 +VCCSUSHDA R295 2 1 0_0603_5%

HDA

2 2 2 VCCRTC 10mA VCCSUSHDA

1U_0402_6.3V6K
C268

0.1U_0402_10V7K
C269

0.1U_0402_10V7K
C270

1 1 1 1
COUGARPOINT_FCBGA989 C271
A 0.1U_0402_16V4Z A

2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

2010/11/30 2011/08 Title
Issued Date Deciphered Date PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 21 of 63
5 4 3 2 1
 5 4 3 2 1

U4I

AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 K26
VSS[161] VSS[261]
AY8 K39
VSS[162] VSS[262]
B11 K46
D U4H VSS[163] VSS[263] D
B15 K7
VSS[164] VSS[264]
H5 B19 L18
VSS[0] VSS[165] VSS[265]
B23 L2
VSS[166] VSS[266]
AA17 AK38 B27 L20
VSS[1] VSS[80] VSS[167] VSS[267]
AA2 AK4 B31 L26
VSS[2] VSS[81] VSS[168] VSS[268]
AA3 AK42 B35 L28
VSS[3] VSS[82] VSS[169] VSS[269]
AA33 AK46 B39 L36
VSS[4] VSS[83] VSS[170] VSS[270]
AA34 AK8 B7 L48
VSS[5] VSS[84] VSS[171] VSS[271]
AB11 AL16 F45 M12
VSS[6] VSS[85] VSS[172] VSS[272]
AB14 AL17 BB12 P16
VSS[7] VSS[86] VSS[173] VSS[273]
AB39 AL19 BB16 M18
VSS[8] VSS[87] VSS[174] VSS[274]
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 BB24 VSS[177] VSS[277] M30
AB7 VSS[12] VSS[91] AL26 BB28 VSS[178] VSS[278] M32
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
C C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 AP42 BF22 T47
VSS[37] VSS[116] VSS[203] VSS[303]
AD45 AP46 BF24 T8
VSS[38] VSS[117] VSS[204] VSS[304]
AD46 AP8 BF26 V11
VSS[39] VSS[118] VSS[205] VSS[305]
AD8 AR2 BF28 V17
VSS[40] VSS[119] VSS[206] VSS[306]
AE2 AR48 BD3 V26
VSS[41] VSS[120] VSS[207] VSS[307]
AE3 AT11 BF30 V27
VSS[42] VSS[121] VSS[208] VSS[308]
AF10 AT13 BF38 V29
VSS[43] VSS[122] VSS[209] VSS[309]
AF12 AT18 BF40 V31
VSS[44] VSS[123] VSS[210] VSS[310]
AD14 AT22 BF8 V36
VSS[45] VSS[124] VSS[211] VSS[311]
AD16 AT26 BG17 V39
VSS[46] VSS[125] VSS[212] VSS[312]
AF16 AT28 BG21 V43
VSS[47] VSS[126] VSS[213] VSS[313]
AF19 AT30 BG33 V7
VSS[48] VSS[127] VSS[214] VSS[314]
AF24 AT32 BG44 W17
VSS[49] VSS[128] VSS[215] VSS[315]
AF26 AT34 BG8 W19
VSS[50] VSS[129] VSS[216] VSS[316]
AF27 AT39 BH11 W2
VSS[51] VSS[130] VSS[217] VSS[317]
AF29 AT42 BH15 W27
VSS[52] VSS[131] VSS[218] VSS[318]
AF31 AT46 BH17 W48
VSS[53] VSS[132] VSS[219] VSS[319]
AF38 AT7 BH19 Y12
VSS[54] VSS[133] VSS[220] VSS[320]
AF4 AU24 H10 Y38
VSS[55] VSS[134] VSS[221] VSS[321]
AF42 AU30 BH27 Y4
VSS[56] VSS[135] VSS[222] VSS[322]
AF46 AV16 BH31 Y42
VSS[57] VSS[136] VSS[223] VSS[323]
AF5 AV20 BH33 Y46
VSS[58] VSS[137] VSS[224] VSS[324]
AF7 AV24 BH35 Y8
VSS[59] VSS[138] VSS[225] VSS[325]
AF8 AV30 BH39 BG29
VSS[60] VSS[139] VSS[226] VSS[328]
AG19 AV38 BH43 N24
B VSS[61] VSS[140] VSS[227] VSS[329] B
AG2 AV4 BH7 AJ3
VSS[62] VSS[141] VSS[228] VSS[330]
AG31 AV43 D3 AD47
VSS[63] VSS[142] VSS[229] VSS[331]
AG48 AV8 D12 B43
VSS[64] VSS[143] VSS[230] VSS[333]
AH11 AW14 D16 BE10
VSS[65] VSS[144] VSS[231] VSS[334]
AH3 AW18 D18 BG41
VSS[66] VSS[145] VSS[232] VSS[335]
AH36 AW2 D22 G14
VSS[67] VSS[146] VSS[233] VSS[337]
AH39 AW22 D24 H16
VSS[68] VSS[147] VSS[234] VSS[338]
AH40 AW26 D26 T36
VSS[69] VSS[148] VSS[235] VSS[340]
AH42 AW28 D30 BG22
VSS[70] VSS[149] VSS[236] VSS[342]
AH46 AW32 D32 BG24
VSS[71] VSS[150] VSS[237] VSS[343]
AH7 AW34 D34 C22
VSS[72] VSS[151] VSS[238] VSS[344]
AJ19 AW36 D38 AP13
VSS[73] VSS[152] VSS[239] VSS[345]
AJ21 AW40 D42 M14
VSS[74] VSS[153] VSS[240] VSS[346]
AJ24 AW48 D8 AP3
VSS[75] VSS[154] VSS[241] VSS[347]
AJ33 AV11 E18 AP1
VSS[76] VSS[155] VSS[242] VSS[348]
AJ34 AY12 E26 BE16
VSS[77] VSS[156] VSS[243] VSS[349]
AK12 AY22 G18 BC16
VSS[78] VSS[157] VSS[244] VSS[350]
AK3 AY28 G20 BG28
VSS[79] VSS[158] VSS[245] VSS[351]
G26 BJ28
COUGARPOINT_FCBGA989 VSS[246] VSS[352]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
A A

COUGARPOINT_FCBGA989

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 22 of 63
5 4 3 2 1
 5 4 3 2 1

UV1A 7/12 Update

PCIE_CTX_GRX_N[0..15]
<5> PCIE_CTX_GRX_N[0..15] PCIE_CTX_GRX_P0 AP17 Part 1 of 7 K1
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N0 PEX_RX0 GPIO0 VGA_GPIO1
<5> PCIE_CTX_GRX_P[0..15] AN17 K2
PCIE_CTX_GRX_P1 PEX_RX0_N GPIO1 VGA_BL_PWM +3VS_VGA
AN19 K3
PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N1 PEX_RX1 GPIO2 VGA_ENVDD
<5> PCIE_CRX_GTX_N[0..15] AP19 H3
PCIE_CTX_GRX_P2 PEX_RX1_N GPIO3 VGA_ENBKL
AR19 H2
PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_N2 PEX_RX2 GPIO4 GPU_VID0 PCH_THRMTRIP#_R
<5> PCIE_CRX_GTX_P[0..15] AR20 H1 GPU_VID0 <59> PCH_THRMTRIP#_R <19>
PEX_RX2_N GPIO5

1
PCIE_CTX_GRX_P3 AP20 H4 GPU_VID1
PCIE_CTX_GRX_N3 PEX_RX3 GPIO6 GPU_VID1 <59>
AN20 H5 RV208
PEX_RX3_N GPIO7

3
PCIE_CTX_GRX_P4 AN22 H6 OVERT# 10K_0402_5%
PCIE_CTX_GRX_N4 PEX_RX4 GPIO8 THERM#_VGA OPTI@ QV7B
AP22 J7
PCIE_CTX_GRX_P5 PEX_RX4_N GPIO9 +3VS_VGA
Under GPU(below 150mils) AR22 K4 2N7002DW-T/R7_SOT363-6

2
D OPTI@ PCIE_CTX_GRX_N5 PEX_RX5 GPIO10 D
150mA PCIE_CTX_GRX_P6
AR23
PEX_RX5_N GPIO11
K5
GPIO12
5 OPTI@
BLM18PG330SN1D_0603 AP23 H7

GPIO
PEX_RX6 GPIO12

6
1 2 +PLLVDD PCIE_CTX_GRX_N6 AN23 J4 @ CV252
+1.05VS_VGA

4
PEX_RX6_N GPIO13 TV1

22U_0805_6.3V6M

CV2

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
LV1 PCIE_CTX_GRX_P7 AN25 J6 1 2 QV7A
PEX_RX7 GPIO14

CV3

CV1

CV4

CV5
220ohms (ESR=0.05) Bead 1 1 1 1 1 PCIE_CTX_GRX_N7 AP25 L1 dGPU_HDMI_HPD 2N7002DW-T/R7_SOT363-6
PCIE_CTX_GRX_P8 PEX_RX7_N GPIO15 0.1U_0402_16V4Z OVERT#
AR25 L2 2 OPTI@
PCIE_CTX_GRX_N8 PEX_RX8 GPIO16 @
AR26 L4
PEX_RX8_N GPIO17

5
OPTI@

OPTI@

OPTI@

OPTI@

OPTI@
PCIE_CTX_GRX_P9 AP26 M4 UV14

1
2 2 2 2 2 PCIE_CTX_GRX_N9 PEX_RX9 GPIO18
AN26 L7 2

P
PCIE_CTX_GRX_P10 PEX_RX9_N GPIO19 B VGA_PGOOD <19,59>
AN28 L5 4
PCIE_CTX_GRX_N10 PEX_RX10 GPIO20 Y
AP28 K6 1 VGA_HDMI_HPD <36>
PEX_RX10_N GPIO21 A

G
PCIE_CTX_GRX_P11 AR28 L6
PCIE_CTX_GRX_N11 PEX_RX11 GPIO22
AR29 M6

3
PCIE_CTX_GRX_P12 PEX_RX11_N GPIO23 NC7SZ08P5X_NL_SC70-5
AP29 M7
PCIE_CTX_GRX_N12 PEX_RX12 GPIO24
AN29
PCIE_CTX_GRX_P13 PEX_RX12_N +3VS_VGA
AN31 N1
PCIE_CTX_GRX_N13 PEX_RX13 MIOA_D0_NC
AP31 P4
PCIE_CTX_GRX_P14 PEX_RX13_N MIOA_D1_NC
AR31 P1
PCIE_CTX_GRX_N14 PEX_RX14 MIOA_D2_NC
AR32 P2
PCIE_CTX_GRX_P15 PEX_RX14_N MIOA_D3_NC
AR34 P3
PCIE_CTX_GRX_N15 PEX_RX15 MIOA_D4_NC OVERT#
AP34 T3 1 2
PEX_RX15_N MIOA_D5_NC RV1 OPTI@10K_0402_5%
T2
MIOA_D6_NC GPIO12
T1 1 2
PCIE_CRX_GTX_P0 CV6 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P0 MIOA_D7_NC RV2 OPTI@10K_0402_5%
1 2 AL17 U4
PCIE_CRX_GTX_N0 PCIE_CRX_C_GTX_N0 PEX_TX0 MIOA_D8_NC VGA_EDID_CLK

PCI EXPRESS
CV7 OPTI@ 1 2 0.1U_0402_10V6K AM17 U1 1 2
PCIE_CRX_GTX_P1 CV8 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P1 PEX_TX0_N MIOA_D9_NC RV3 OPTI@2.2K_0402_5%
1 2 AM18 U2
PCIE_CRX_GTX_N1 CV9 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N1 PEX_TX1 MIOA_D10_NC VGA_EDID_DATA
1 2 AM19 U3 1 2
PCIE_CRX_GTX_P2 CV10 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P2 PEX_TX1_N MIOA_D11_NC RV4 OPTI@2.2K_0402_5%
1 2 AL19 R6
PCIE_CRX_GTX_N2 CV11 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N2 PEX_TX2 MIOA_D12_NC
1 2 AK19 T6

DVO
PCIE_CRX_GTX_P3 CV12 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P3 PEX_TX2_N MIOA_D13_NC
1 2 AL20 N6
PCIE_CRX_GTX_N3 CV13 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N3 PEX_TX3 MIOA_D14_NC
1 2 AM20
PCIE_CRX_GTX_P4 CV14 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P4 PEX_TX3_N
1 2 AM21 Y1
C PCIE_CRX_GTX_N4 CV15 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N4 PEX_TX4 MIOB_D0_NC C
1 2 AM22 Y2
PCIE_CRX_GTX_P5 CV16 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P5 PEX_TX4_N MIOB_D1_NC THERM#_VGA
1 2 AL22 Y3 1 2
PCIE_CRX_GTX_N5 CV17 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N5 PEX_TX5 MIOB_D2_NC RV7 OPTI@ 100K_0402_5%
1 2 AK22 AB3
PCIE_CRX_GTX_P6 CV18 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P6 PEX_TX5_N MIOB_D3_NC HDCP_SCL
1 2 AL23 AB2 1 2
PCIE_CRX_GTX_N6 CV19 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N6 PEX_TX6 MIOB_D4_NC RV8 OPTI@2.2K_0402_5%
1 2 AM23 AB1
PCIE_CRX_GTX_P7 CV20 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P7 PEX_TX6_N MIOB_D5_NC HDCP_SDA
1 2 AM24 AC4 1 2
PCIE_CRX_GTX_N7 CV21 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N7 PEX_TX7 MIOB_D6_NC RV9 OPTI@2.2K_0402_5%
1 2 AM25 AC1
PCIE_CRX_GTX_P8 CV22 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P8 PEX_TX7_N MIOB_D7_NC VGA_CRT_DATA
1 2 AL25 AC2 1 2
PCIE_CRX_GTX_N8 CV23 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N8 PEX_TX8 MIOB_D8_NC RV10 OPTI@2.2K_0402_5%
1 2 AK25 AC3
PCIE_CRX_GTX_P9 CV24 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P9 PEX_TX8_N MIOB_D9_NC VGA_CRT_CLK
1 2 AL26 AE3 1 2
PCIE_CRX_GTX_N9 CV25 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N9 PEX_TX9 MIOBD_10_NC RV11 OPTI@2.2K_0402_5%
1 2 AM26 AE2
PCIE_CRX_GTX_P10 CV26 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P10 PEX_TX9_N MIOB_D11_NC I2CB_SCL
1 2 AM27 U6 1 2
PCIE_CRX_GTX_N10 CV27 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N10 PEX_TX10 MIOB_D12_NC RV12 OPTI@2.2K_0402_5%
1 2 AM28 W6
PCIE_CRX_GTX_P11 CV28 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P11 PEX_TX10_N MIOB_D13_NC I2CB_SDA
1 2 AL28 Y6 1 2
PCIE_CRX_GTX_N11 CV29 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N11 PEX_TX11 MIOB_D14_NC RV13 OPTI@2.2K_0402_5%
1 2 AK28
PCIE_CRX_GTX_P12 CV239 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P12 PEX_TX11_N
1 2 AK29 N3
PCIE_CRX_GTX_N12 CV30 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N12 PEX_TX12 MIOA_HSYNC_NC
1 2 AL29 L3
PCIE_CRX_GTX_P13 CV31 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P13 PEX_TX12_N MIOA_VSYNC_NC VGA_ENVDD
1 2 AM29 1 OPTI@ 2
PCIE_CRX_GTX_N13 CV32 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N13 PEX_TX13 RV14 10K_0402_5%
1 2 AM30 W1
+3VS_VGA PCIE_CRX_GTX_P14 CV33 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P14 PEX_TX13_N MIOB_HSYNC_NC VGA_ENBKL
1 2 AM31 W2 1 OPTI@ 2
PCIE_CRX_GTX_N14 CV34 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N14 PEX_TX14 MIOB_VSYNC_NC RV15 10K_0402_5%
1 2 AM32
PEX_TX14_N
5

UV2 PCIE_CRX_GTX_P15 CV35 OPTI@ 1 2 0.1U_0402_10V6K PCIE_CRX_C_GTX_P15 AN32 N2 VGA_BL_PWM 2 @ 1

BUF_PLT_RST# PCIE_CRX_GTX_N15 CV36 OPTI@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N15 PEX_TX15 MIOA_DE_NC RV16 10K_0402_5%
2 1 2 AP32 P5
P

<18,37,38,44,45,49> BUF_PLT_RST# B PEX_TX15_N MIOA_CTL3_NC

4 PLT_RST_VGA# N5
DGPU_HOLD_RST# 1 Y MIOA_VREF_NC VGA_GPIO1
<18> DGPU_HOLD_RST# 1 2
A
G

Y5 RV17 OPTI@ 100K_0402_5%

MIOB_DE_NC
1

OPTI@ CLK_PCIE_VGA AR16 W3

<15> CLK_PCIE_VGA
3

RV18 CLK_PCIE_VGA# PEX_REFCLK MIOB_CTL3_NC

<15> CLK_PCIE_VGA# AR17 AF1
NC7SZ08P5X_NL_SC70-5 CLK_REQ_GPU# PEX_REFCLK_N MIOB_VREF_NC
10K_0402_5% AR13
PEX_CLKREQ_N
N4 1 2
OPTI@ @ PEX_TSTCLK_OUT MIOA_CLKIN_NC RV19 10K_0402_5%
Differential signal, 1 2 AJ17 R4
2

RV20 200_0402_1% PEX_TSTCLK_OUT# PEX_TSTCLK_OUT MIOA_CLKOUT_NC @

AJ18
PEX_TSTCLK_OUT_N
B
Default can be unstuffed. MIOB_CLKIN_NC
AE1 1
RV21
2
10K_0402_5%
B
V4
PLT_RST_VGA# MIOB_CLKOUT_NC @
AM16
PEX_RST_N +3VS_VGA
AG21 T4
PEX_TERMP PEX_TERMP MIOA_CLKOUT_NC_N
1 2 W4
RV22 2.49K_0402_1% MIOB_CLKOUT_NC_N +3VS_VGA
1 2 OPTI@ 60mA U5
MIOACAL_PD_VDDQ_NC

2
RV23 10M_0402_5% +PLLVDD AE9 T5 OPTI@
PLLVDD MIOACAL_PU_GND_NC OPTI@RV24
OPTI@RV24 RV25
OPTI@ 45mA
AF9 AA7 2.2K_0402_5% 2.2K_0402_5%
YV1 SP_PLLVDD MIOBCAL_PD_VDDQ_NC
45mA MIOBCAL_PU_GND_NC
AA6

5
XTALIN1 2XTAL_OUT AD9 OPTI@

1
VID_PLLVDD QV1B

CLK
1 27MHZ_16PF_X5H027000FG1H1 XTALIN B1 VGA_SMB_CK2 4 3
XTAL_OUT XTAL_IN EC_SMB_CK2 <15,40,45>
CV37 OPTI@ CV38 B2 AM15
XTAL_OUT DACA_RED

2
18P_0402_50V8J 18P_0402_50V8J AM14 OPTI@ 2N7002DW-T/R7_SOT363-6
OPTI@ OPTI@ XTALOUT DACA_GREEN QV1A
D1 AL14
2 2 XTAL_OUTBUFF DACA_BLUE
2 1 XTALSSIN D2 VGA_SMB_DA2 1 6 EC_SMB_DA2 <15,40,45>
XTAL_SSIN
1

RV26 OPTI@ 10K_0402_5% AM13

RV27 DACA_HSYNC 2N7002DW-T/R7_SOT363-6
Internal Thermal Sensor DACA_VSYNC
AL13
10K_0402_5% PU AT EC SIDE, +3VS AND 4.7K
VGA_SMB_CK2 E2 AJ12 +DACA_VDD 1 2
OPTI@ I2CS_SCL DACA_VDD
VGA_SMB_DA2 E1 AK12 RV28 10K_0402_5%
2

I2CS_SDA DACA_VREF OPTI@

<18,51,58,59> DGPU_PWR_EN AK13
VGA_EDID_CLK E3 DACA_RSET
I2CC_SCL

DACs
VGA_EDID_DATA E4 AK4
+3VS_VGA I2CC_SDA DACB_RED
AL4
DACB_GREEN
2

I2CB_SCL G3 AJ4
<33> I2CB_SCL I2CB_SCL DACB_BLUE
RV29 I2CB_SDA

I2C
<33> I2CB_SDA G2
10K_0402_5% I2CB_SDA
AM1
DACB_HSYNC
2

OPTI@ VGA_CRT_CLK G1 AM2

RV30 VGA_CRT_DATA G4 I2CA_SCL DACB_VSYNC
2 1

A I2CA_SDA A
10K_0402_5% AG7 +DACB_VDD 1 2
HDCP_SCL DACB_VDD
G

OPTI@ F6 AK6 RV31 10K_0402_5%

QV2 OPTI@ HDCP_SDA I2CH_SCL DACB_VREF OPTI@
G6 AH7
1

CLK_REQ_GPU# I2CH_SDA DACB_RSET

<15> CLK_REQ_VGA# 1 3
D

2N7002_SOT23-3 UV1 UV1 N12P-GV1-A1_BGA_973P

@ RV32
@RV32
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
@ Issued Date 2010/11/30 Deciphered Date 2011/08 Title
N12P-PCIE/DAC/GPIO
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
N12P-GT-A1 N12P-GS-A1 0.3
GT@ GS@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 23 of 63

5 4 3 2 1
 5 4 3 2 1

UV1D

Part 4 of 7
AM11 IFPA_TXC NC_0 A2
AM12 IFPA_TXC_N NC_1 A7
AM8 IFPA_TXD0 NC_2 B7
AL8 IFPA_TXD0_N NC_3 C5
AM10 IFPA_TXD1 NC_4 C7
AM9 IFPA_TXD1_N NC_5 D5
AK10 IFPA_TXD2 NC_6 D6
D
AL10 IFPA_TXD2_N NC_7 D7 D
AK11 IFPA_TXD3 NC_8 E5
AL11 IFPA_TXD3_N NC_9 E7
NC_10 F4
NC_11 G5
AP13 IFPB_TXC NC_12 H32
AN13 IFPB_TXC_N NC_13 J25
AN8 IFPB_TXD4 NC_14 J26
AP8 IFPB_TXD4_N NC_15 P6
AP10 IFPB_TXD5 NC_16 U7
AN10 IFPB_TXD5_N NC_17 V6
AR11 IFPB_TXD6 NC_18 Y4
AR10 IFPB_TXD6_N NC_19 AA4
AN11 IFPB_TXD7 NC_20 AB4
AP11 IFPB_TXD7_N NC_21 AB7
NC_22 AC5

NC
NC_23 AD6
AM7 IFPC_L0 NC_24 AF6
AM6 IFPC_L0_N NC_25 AG6
AL5 IFPC_L1 NC_26 AG20
AM5 IFPC_L1_N NC_27 AJ5
AM3 IFPC_L2 NC_28 AK15
AM4 IFPC_L2_N NC_29 AL7
AP1 IFPC_L3
AR2 IFPC_L3_N

AR8 IFPD_L0
AR7 IFPD_L0_N
AP7 IFPD_L1
C AN7 IFPD_L1_N
C
AN5 IFPD_L2

LVDS/TMDS
AP5 IFPD_L2_N
AR5 IFPD_L3
AR4 IFPD_L3_N

<36> VGA_HDMI_TX2+ VGA_HDMI_TX2+ AH6

VGA_HDMI_TX2- IFPE_L0
<36> VGA_HDMI_TX2- AH5 IFPE_L0_N
<36> VGA_HDMI_TX1+ VGA_HDMI_TX1+ AH4
VGA_HDMI_TX1- IFPE_L1
<36> VGA_HDMI_TX1- AG4 IFPE_L1_N
<36> VGA_HDMI_TX0+ VGA_HDMI_TX0+ AF4
VGA_HDMI_TX0- IFPE_L2
<36> VGA_HDMI_TX0- AF5 IFPE_L2_N
<36> VGA_HDMI_CLK+ VGA_HDMI_CLK+ AE6
VGA_HDMI_CLK- IFPE_L3
<36> VGA_HDMI_CLK- AE5 IFPE_L3_N VDD_SENSE_VGA trace width: 16mils
D35 VDD_SENSE_VGA VDD_SENSE_VGA <59>
VDD_SENSE_0
AL2 IFPF_L0 VDD_SENSE_1 P7
AL3 IFPF_L0_N VDD_SENSE_2 AD20
AJ3 IFPF_L1
AJ2 IFPF_L1_N
AJ1 IFPF_L2
AH1 AD19 GND_SENSE_VGA GND_SENSE_VGA <59>
IFPF_L2_N GND_SENSE_0
AH2 IFPF_L3 GND_SENSE_1 E35
AH3 IFPF_L3_N GND_SENSE_2 R7

+3VS_VGA
AP2 IFPC_AUX_I2CW _SCL
AN3
B
1 2 VGA_HDMI_CLK
HDMI
IFPC_AUX_I2CW _SDA_N TEST B
RV209 4.7K_0402_5%
@ AP4 AP35 TESTMODE
VGA_HDMI_DATA IFPD_AUX_I2CX_SCL TESTMODE
1 2 AN4 IFPD_AUX_I2CX_SDA_N JTAG_TCK AP14 TV2

1
RV210 4.7K_0402_5% AN14
JTAG_TDI TV3
@ AN16
JTAG_TDO TV4 10K_0402_5%
VGA_HDMI_CLK AE4 AR14
<36> VGA_HDMI_CLK IFPE_AUX_I2CY_SCL JTAG_TMS TV5
VGA_HDMI_DATA AD4 AP16 1 2 RV33
<36> VGA_HDMI_DATA IFPE_AUX_I2CY_SDA_N JTAG_TRST_N RV34 OPTI@
10K_0402_5% OPTI@

2
AF3 IFPF_AUX_I2CZ_SCL
AF2 IFPF_AUX_I2CZ_SDA_N SERIAL
ROM_CS_N C3
D3 ROM_SI ROM_SI <32>
+3VS_VGA ROM_SI ROM_SO
ROM_SO C4 ROM_SO <32>
D4 ROM_SCLK ROM_SCLK <32>
ROM_SCLK
2

RV35
10K_0402_5% GENERAL A5 1 2
OPTI@ NC/SPDIF_NC RV36 @ 36K_0402_5%
A4 BUFRST_N
N9 1 2
1

MULTI_STRAP_REF0_GND RV37 OPTI@ 40.2K_0402_1%

AB5 CEC
MULTI_STRAP_REF1_GND M9 1 2
<32> STRAP0 STRAP0 W5 RV38 OPTI@ 40.2K_0402_1%
STRAP1 STRAP0
<32> STRAP1 W7 STRAP1 THERMDP B5
<32> STRAP2 STRAP2 V7 B4
STRAP2 THERMDN
A A

N12P-GV1-A1_BGA_973P
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P-LVDS/HDMI/DP/THM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 24 of 63
5 4 3 2 1
 5 4 3 2 1

UV1E Close to PEX_IOVDD PIN:

+1.5VS_VGA
Near GPU 2000mA +1.05VS_VGA
3.2A Part 5 of 7
AK16, AK17, AK21, AK24, and AK27
J23 AG11
Near GPU
FBVDDQ_0 PEX_IOVDDQ_0

CV51

CV52
10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
J24 FBVDDQ_1 PEX_IOVDDQ_1 AG12

OPTI@ CV42

OPTI@ CV39

OPTI@ CV40

OPTI@ CV41

OPTI@ CV43

OPTI@ CV44

OPTI@ CV45

OPTI@ CV46

OPTI@ CV47

OPTI@ CV48

OPTI@ CV49

OPTI@ CV50
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
J29 AG13

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 FBVDDQ_2 PEX_IOVDDQ_2 1 1 1 1 1 1 2 2 1 1
AA27 FBVDDQ_3 PEX_IOVDDQ_3 AG15
AA29 FBVDDQ_4 PEX_IOVDDQ_4 AG16

OPTI@

OPTI@
AA31 FBVDDQ_5 PEX_IOVDDQ_5 AG17
2 2 2 2 AB27 AG18 2 2 2 2 2 2 1 1 2 2
FBVDDQ_6 PEX_IOVDDQ_6
AB29 FBVDDQ_7 PEX_IOVDDQ_7 AG22
AC27 FBVDDQ_8 PEX_IOVDDQ_8 AG23
D
AD27 FBVDDQ_9 PEX_IOVDDQ_9 AG24 D
+1.05VS_VGA
+1.5VS_VGA
AE27 FBVDDQ_10 PEX_IOVDDQ_10 AG25 Under GPU(below 150mils)
Under GPU(below 150mils)

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
AJ28 FBVDDQ_11 PEX_IOVDDQ_11 AG26

OPTI@ CV53

OPTI@ CV54

OPTI@ CV55

OPTI@ CV56
B18 FBVDDQ_12 PEX_IOVDDQ_12 AJ14 1 1 1 1
E21 FBVDDQ_13 PEX_IOVDDQ_13 AJ15
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
G17 FBVDDQ_14 PEX_IOVDDQ_14 AJ19
OPTI@ CV57

OPTI@ CV58

OPTI@ CV59

OPTI@ CV60

OPTI@ CV61

OPTI@ CV62

OPTI@ CV63

OPTI@ CV64
1 1 1 1 1 1 1 1 G18 FBVDDQ_15 PEX_IOVDDQ_15 AJ21
G22 AJ22 2 2 2 2
FBVDDQ_16 PEX_IOVDDQ_16
G8 FBVDDQ_17 PEX_IOVDDQ_17 AJ24
G9 FBVDDQ_18 PEX_IOVDDQ_18 AJ25
2 2 2 2 2 2 2 2 H29 AJ27
FBVDDQ_19 PEX_IOVDDQ_19

POWER
J14 FBVDDQ_20 PEX_IOVDDQ_20 AK18
J15 FBVDDQ_21 PEX_IOVDDQ_21 AK20
J16 FBVDDQ_22 PEX_IOVDDQ_22 AK23
J17 FBVDDQ_23 PEX_IOVDDQ_23 AK26
+1.05VS_VGA
J20 FBVDDQ_24 PEX_IOVDDQ_24 AL16 Under GPU(below 150mils)
J21 LV2
FBVDDQ_25
J22 FBVDDQ_26 2 1
120ohms @100MHz (ESR=0.18)

0.1U_0402_10V7K
N27

4.7U_0603_6.3V6K
FBVDDQ_27

OPTI@ CV65

OPTI@ CV66

OPTI@ CV67
BLM18PG121SN1D_0603

1U_0402_6.3V6K
P27 FBVDDQ_28 PEX_IOVDD_0 AK16 1 1 1
R27 FBVDDQ_29 PEX_IOVDD_1 AK17
T27 FBVDDQ_30 PEX_IOVDD_2 AK21
U27 FBVDDQ_31 PEX_IOVDD_3 AK24
U29 AK27 2 2 2
FBVDDQ_32 PEX_IOVDD_4
V27 FBVDDQ_33 120mA 7/20 Vendor recommends that
V29
V34
FBVDDQ_34 change to +1.05VS_VGA
FBVDDQ_35 +PEX_PLLVDD
W 27 FBVDDQ_36 PEX_PLLVDD AG14
Y27 FBVDDQ_37 +1.05VS_VGA
C
2 OPTI@1 +IFPAB_PLLVDD AK9 AG19
240mA (120mA each) C

@ IFPAB_PLLVDD PEX_SVDD_3V3
2 RV39 10K_0402_5%

0.1U_0402_10V7K

4.7U_0603_6.3V6K
1 AJ11 IFPAB_RSET PEX_SVDD_3V3_NC F7

OPTI@ CV68

OPTI@ CV288

OPTI@ CV289
RV40 1K_0402_1%

1U_0402_6.3V6K
1 1 1
+3VS_VGA
2 OPTI@1 +IFPAB_IOVDD AG9
120mA(12~16mils)
RV41 10K_0402_5% IFPA_IOVDD
AG10 IFPB_IOVDD VDD33_0 J10
2 2 2

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0603_6.3V6K
VDD33_1 J11

OPTI@ CV70

OPTI@ CV71

OPTI@ CV72

OPTI@ CV73
OPTI@ CV287

1U_0402_6.3V6K
VDD33_2 J12 1 1 1 1 1
2 OPTI@1 +IFPC_PLLVDD AJ9 J13
@ IFPC_PLLVDD VDD33_3
1 2 RV42 10K_0402_5% AK7 IFPC_RSET VDD33_4 J9
RV43 1K_0402_1%
2 OPTI@1 +IFPC_IOVDD AJ8 2 2 2 2 2
RV44 10K_0402_5% IFPC_IOVDD

MIOA_VDDQ_NC_0 P9
2 OPTI@1 +IFPD_PLLVDD AC6 R9
IFPD_PLLVDD MIOA_VDDQ_NC_1

2
1 @ 2 RV45 10K_0402_5% AB6 T9 Under GPU(below 150mils)
RV46 1K_0402_1% IFPD_RSET MIOA_VDDQ_NC_2 RV48
MIOA_VDDQ_NC_3 U9
2 OPTI@1 +IFPD_IOVDD AK8 10K_0402_5%
RV47 10K_0402_5% IFPD_IOVDD OPTI@
AA9

1
OPTI@1 +IFPEF_PLLVDD MIOB_VDDQ_NC_0
2 AJ6 IFPEF_PLLVDD MIOB_VDDQ_NC_1 AB9
1 OPTI@2RV49 10K_0402_5% AL1 W9
RV50 1K_0402_1% IFPEF_RSET MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3 Y9
2 OPTI@1 +IFPE_IOVDD AE7 IFPE_IOVDD

2
RV51 10K_0402_5% AD7 IFPF_IOVDD RV52
10K_0402_5%
OPTI@

1
B B
N12P-GV1-A1_BGA_973P

300ohms @100MHz (ESR=0.25) @

+3VS_VGA
Under GPU(below 150mils) 220mA +3VS to +3VS_VGA
LV9
2 1 +IFPEF_PLLVDD +3VS +3VS_VGA
BLM18PG181SN1D_0603
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
@ CV146

@ CV147

@ CV148

@ CV149

@ CV150

@ QV5
1U_0402_6.3V6K
4.7U_0603_6.3V6K

1 1 1 1 1
AO3413_SOT23
1380mA (60mils) 3via OPTI@ 1380mA (60mils) 3via
2 2 2 2 2

D
3 1

1
G
2
RV205 RV206
1 2 470_0603_5%
<51> DGPU_PWR_EN#
5.1K_0402_5% @

1 2
OPTI@ CV241
OPTI@ 1 @
+1.05VS_VGA D RV207
Under GPU(below 150mils) 570mA

0.1U_0402_10V7K
LV10 2 2 1 DGPU_PWR_EN# <51>
+IFPE_IOVDD G 10K_0402_5%
0.1U_0402_10V7K

0.1U_0402_10V7K

2 1
2
@ CV151

@ CV152

@ CV153

@ CV154

BLM18PG181SN1D_0603 QV6
1U_0402_6.3V6K

1 1 1 1 S

3
220ohms @100MHz (ESR=0.05) 2N7002_SOT23
@

0.1U_0402_10V7K
@

@ CV242
4.7U_0603_6.3V6K

2 2 2 2 1

A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P-POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 25 of 63
5 4 3 2 1
 5 4 3 2 1

UV1F

B3 Part 6 of 7
GND_0
B6 V18
GND_1 GND_97
B9 V20
GND_2 GND_98
30.54A (41.02A Peak) B12
B15
GND_3 GND_99
V22
V24
GND_4 GND_100
B21 V31
+VGA_CORE +VGA_CORE GND_5 GND_101
B24 Y11
UV1G GND_6 GND_102
B27 Y13
GND_7 GND_103
B30 Y15
GND_8 GND_104
AB11 P21 B33 Y17
VDD_0 Part 7 of 7 VDD_56 GND_9 GND_105
AB13 P23 C2 Y19
D VDD_1 VDD_57 GND_10 GND_106 D
AB15 P25 C34 Y21
VDD_2 VDD_58 GND_11 GND_107
AB17
VDD_3 VDD_59
R11 Near GPU E6
GND_12 GND_108
Y23
AB19 R12 E9 Y25
VDD_4 VDD_60 GND_13 GND_109
AB21 R13 E12 AA2
VDD_5 VDD_61 GND_14 GND_110
AB23 R14 E15 AA5
VDD_6 VDD_62 GND_15 GND_111
AB25 R15 E18 AA11
VDD_7 VDD_63 GND_16 GND_112
AC11 R16 E24 AA12
VDD_8 VDD_64 +VGA_CORE GND_17 GND_113
AC12 R17 E27 AA13
VDD_9 VDD_65 GND_18 GND_114
AC13 R18 E30 AA14
VDD_10 VDD_66 GND_19 GND_115
AC14 R19 F2 AA15
VDD_11 VDD_67 GND_20 GND_116
AC15 R20 F31 AA16
VDD_12 VDD_68 GND_21 GND_117

CV79

CV80

CV81
47U_0805_4V6
10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M
AC16 R21 F34 AA17

4.7U_0603_6.3V6K
VDD_13 VDD_69 GND_22 GND_118

OPTI@ CV77

OPTI@ CV78
AC17 R22 2 2 1 1 1 F5 AA18
VDD_14 VDD_70 GND_23 GND_119
AC18 R23 J2 AA19
VDD_15 VDD_71 GND_24 GND_120
AC19 R24 J5 AA20
VDD_16 VDD_72 GND_25 GND_121

OPTI@

OPTI@
AC20 R25 @ J31 AA21
VDD_17 VDD_73 1 1 2 2 2 GND_26 GND_122
AC21 T12 J34 AA22
VDD_18 VDD_74 GND_27 GND_123
AC22 T14 K9 AA23
VDD_19 VDD_75 GND_28 GND_124
AC23 T16 L9 AA24
VDD_20 VDD_76 GND_29 GND_125
POWER
AC24 T18 M2 AA25
VDD_21 VDD_77 GND_30 GND_126
AC25 T20 M5 AA34
VDD_22 VDD_78 GND_31 GND_127
AD12 T22 M11 AB12
VDD_23 VDD_79 GND_32 GND_128
AD14
VDD_24 VDD_80
T24 Under GPU M13
GND_33 GND_129
AB14
AD16 V11 M15 AB16
VDD_25 VDD_81 GND_34 GND_130
AD18 V13 M17 AB18
VDD_26 VDD_82 +VGA_CORE GND_35 GND_131
AD22 V15 M19 AB20
VDD_27 VDD_83 GND_36 GND_132
AD24 V17 M21 AB22
VDD_28 VDD_84 GND_37 GND_133
L11 V19 M23 AB24
VDD_29 VDD_85 GND_38 GND_134
L12 V21 M25 AC9
VDD_30 VDD_86 GND_39 GND_135

4700P_0402_25V7K

4700P_0402_25V7K

4700P_0402_25V7K
1U_0603_10V6K

0.1U_0402_10V7K

0.1U_0402_10V7K
0.047U_0402_25V6K

0.047U_0402_25V6K

0.047U_0402_25V6K

0.022U_0402_25V7K

0.022U_0402_25V7K

0.022U_0402_25V7K
C L13 V23 M31 AD2 C
VDD_31 VDD_87 GND_40 GND_136

OPTI@ CV82

OPTI@ CV83

OPTI@ CV84

OPTI@ CV85

OPTI@ CV86

OPTI@ CV87

OPTI@ CV88

OPTI@ CV89

OPTI@ CV90

OPTI@ CV91

OPTI@ CV92

OPTI@ CV93
L14 V25 1 1 1 1 1 1 1 1 1 M34 AD5
VDD_32 VDD_88 GND_41 GND_137

GND
L15 W11 N11 AD11
VDD_33 VDD_89 GND_42 GND_138
L16 W12 N12 AD13
VDD_34 VDD_90 GND_43 GND_139
L17 W13 N13 AD15
VDD_35 VDD_91 2 2 2 2 2 2 2 2 2 GND_44 GND_140
L18 W14 N14 AD17
VDD_36 VDD_92 GND_45 GND_141
L19 W15 N15 AD21
VDD_37 VDD_93 GND_46 GND_142
L20 W16 N16 AD23
VDD_38 VDD_94 GND_47 GND_143
L21 W17 N17 AD25
VDD_39 VDD_95 GND_48 GND_144
L22 W18 N18 AD31
VDD_40 VDD_96 GND_49 GND_145
L23 W19 N19 AD34
VDD_41 VDD_97 GND_50 GND_146
L24 W20 N20 AE11
VDD_42 VDD_98 GND_51 GND_147
L25 W21 N21 AE12
VDD_43 VDD_99 +VGA_CORE GND_52 GND_148
M12 W22 N22 AE13
VDD_44 VDD_100 GND_53 GND_149
M14 W23 N23 AE14
VDD_45 VDD_101 GND_54 GND_150
M16 W24 N24 AE15
VDD_46 VDD_102 GND_55 GND_151
M18 W25 N25 AE16
VDD_47 VDD_103 GND_56 GND_152
M20 Y12 P12 AE17

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K
VDD_48 VDD_104 GND_57 GND_153
OPTI@ CV94

OPTI@ CV95

OPTI@ CV96

OPTI@ CV97

OPTI@ CV98

OPTI@ CV99

OPTI@ CV100

OPTI@ CV101

CV102

CV103

CV104
0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K
M22 Y14 1 1 1 1 1 1 1 1 P14 AE18

1
VDD_49 VDD_105 GND_58 GND_154
M24 Y16 P16 AE19
VDD_50 VDD_106 GND_59 GND_155
P11 Y18 P18 AE20
VDD_51 VDD_107 GND_60 GND_156

OPTI@

OPTI@

OPTI@
P13 Y20 P20 AE21

2
VDD_52 VDD_108 2 2 2 2 2 2 2 2 GND_61 GND_157
P15 Y22 P22 AE22
VDD_53 VDD_109 GND_62 GND_158
P17 Y24 P24 AE23
VDD_54 VDD_110 GND_63 GND_159
P19 R2 AE24
VDD_55 GND_64 GND_160
R5 AE25
GND_65 GND_161
R31 AG2
GND_66 GND_162
R34 AG5
GND_67 GND_163
T11 AG31
GND_68 GND_164
T13 AG34
B
N12P-GV1-A1_BGA_973P GND_69 GND_165 B
T15 AK2
GND_70 GND_166
T17 AK5
GND_71 GND_167
@ T19 AK14
GND_72 GND_168
T21 AK31
GND_73 GND_169
T23 AK34
GND_74 GND_170
T25 AL6
GND_75 GND_171
U11 AL9
GND_76 GND_172
U12 AL12
GND_77 GND_173
U13 AL15
GND_78 GND_174
U14 AL18
GND_79 GND_175
U15 AL21
GND_80 GND_176
U16 AL24
GND_81 GND_177
U17 AL27
GND_82 GND_178
U18 AL30
GND_83 GND_179
U19 AN2
GND_84 GND_180
U20 AN34
GND_85 GND_181
U21 AP3
GND_86 GND_182
U22 AP6
GND_87 GND_183
U23 AP9
GND_88 GND_184
U24 AP12
GND_89 GND_185
U25 AP15
GND_90 GND_186
V2 AP18
GND_91 GND_187
V5 AP21
GND_92 GND_188
V9 AP24
GND_93 GND_189
V12 AP27
GND_94 GND_190
V14 AP30
GND_95 GND_191
V16 AP33
GND_96 GND_192

A A

N12P-GV1-A1_BGA_973P

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P-VGA CORE, GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 26 of 63
5 4 3 2 1
 5 4 3 2 1

FBA_MA[15..0] <28,29>

FBA_BA[2..0] <28,29>

FBC_MA[15..0] <30,31>
UV1B
FBC_D[0..63] FBC_BA[2..0] <30,31>
UV1C
FBA_CS0#_L <30,31> FBC_D[0..63]
Part 2 of 7 U30
FBA_D[0..63] FBA_D0 FBA_CMD0 FBA_CS0#_L <28> FBC_CS0#_L
Part 3 of 7
<28,29> FBA_D[0..63] FBA_D1
L32
N33
FBA_D0
FBA_D1
FBA_CMD1
FBA_CMD2
V30
U31 FBA_ODT_L
FBA_ODT_L <28>
FBC_D0 B13
FBC_D0
FBC_CMD0
FBC_CMD1
F18
E19
FBC_CS0#_L <30> Mode D - Mirror Mode Mapping
FBA_D2 L33 V32 FBA_CKE_L FBC_D1 D13 D18 FBC_ODT_L
FBA_D3 FBA_D2 FBA_CMD3 FBA_MA14 FBA_CKE_L <28> FBC_D2 FBC_D1 FBC_CMD2 FBC_CKE_L FBC_ODT_L <30>
N34 T35 A13 C17 FBC_CKE_L <30>
D FBA_D4 FBA_D3 FBA_CMD4 FBA_RST# FBC_D3 FBC_D2 FBC_CMD3 FBC_MA14 D
N35
FBA_D4 FBA_CMD5
U33 FBA_RST# <28,29> A14
FBC_D3 FBC_CMD4
F19 DATA Bus
FBA_D5 P35 W32 FBA_MA9 FBC_D4 C16 C19 FBC_RST#
FBA_D6 FBA_D5 FBA_CMD6 FBA_MA7 FBC_D5 FBC_D4 FBC_CMD5 FBC_MA9 FBC_RST# <30,31>
P33
FBA_D6 FBA_CMD7
W33 B16
FBC_D5 FBC_CMD6
B17 Address 0..31 32..63
FBA_D7 P34 W31 FBA_MA2 FBC_D6 A17 E20 FBC_MA7
FBA_D8 FBA_D7 FBA_CMD8 FBA_MA0 FBC_D7 FBC_D6 FBC_CMD7 FBC_MA2
K35
FBA_D8 FBA_CMD9
W34 D16
FBC_D7 FBC_CMD8
B19 FBx_CMD0 CS0#_L
FBA_D9 K33 U34 FBA_MA4 FBC_D8 C13 D20 FBC_MA0
FBA_D10 FBA_D9 FBA_CMD10 FBA_MA1 FBC_D9 FBC_D8 FBC_CMD9 FBC_MA4
K34
FBA_D10 FBA_CMD11
U35 B11
FBC_D9 FBC_CMD10
A19 FBx_CMD1
FBA_D11 H33 U32 FBA_BA0 FBC_D10 C11 D19 FBC_MA1
FBA_D12 FBA_D11 FBA_CMD12 FBA_WE# FBC_D11 FBC_D10 FBC_CMD11 FBC_BA0
G34
FBA_D12 FBA_CMD13
T34 FBA_WE# <28,29> A11
FBC_D11 FBC_CMD12
C20 FBx_CMD2 ODT_L
FBA_D13 G33 T33 FBA_MA15 FBC_D12 C10 F20 FBC_WE#
FBA_D14 FBA_D13 FBA_CMD14 FBA_CAS# FBC_D13 FBC_D12 FBC_CMD13 FBC_MA15 FBC_WE# <30,31>
E34
FBA_D14 FBA_CMD15
W30 FBA_CAS# <28,29> C8
FBC_D13 FBC_CMD14
B20 FBx_CMD3 CKE_L
FBA_D15 E33 AB30 FBA_CS0#_H FBC_D14 B8 G21 FBC_CAS#
FBA_D16 FBA_D15 FBA_CMD16 FBA_CS0#_H <29> FBC_D15 FBC_D14 FBC_CMD15 FBC_CS0#_H FBC_CAS# <30,31>
G31
FBA_D16 FBA_CMD17
AA30 A8
FBC_D15 FBC_CMD16
F22 FBC_CS0#_H <31> FBx_CMD4 A14 A14
FBA_D17 F30 AB31 FBA_ODT_H FBC_D16 E8 F24
FBA_D18 FBA_D17 FBA_CMD18 FBA_CKE_H FBA_ODT_H <29> FBC_D17 FBC_D16 FBC_CMD17 FBC_ODT_H
G30
FBA_D18 FBA_CMD19
AA32 FBA_CKE_H <29> F8
FBC_D17 FBC_CMD18
F23 FBC_ODT_H <31> FBx_CMD5 RST RST
FBA_D19 G32 AB33 FBA_MA13 FBC_D18 F10 C25 FBC_CKE_H
FBA_D20 FBA_D19 FBA_CMD20 FBA_MA8 FBC_D19 FBC_D18 FBC_CMD19 FBC_MA13 FBC_CKE_H <31>
K30
FBA_D20 FBA_CMD21
Y32 F9
FBC_D19 FBC_CMD20
C23 FBx_CMD6 A9 A9
FBA_D21 K32 Y33 FBA_MA6 FBC_D20 F12 F21 FBC_MA8
FBA_D22 FBA_D21 FBA_CMD22 FBA_MA11 FBC_D21 FBC_D20 FBC_CMD21 FBC_MA6
H30
FBA_D22 FBA_CMD23
AB34 D8
FBC_D21 FBC_CMD22
E22 FBx_CMD7 A7 A7
FBA_D23 K31 AB35 FBA_MA5 FBC_D22 D11 D21 FBC_MA11
FBA_D24 FBA_D23 FBA_CMD24 FBA_MA3 FBC_D23 FBC_D22 FBC_CMD23 FBC_MA5
L31
FBA_D24 FBA_CMD25
Y35 E11
FBC_D23 FBC_CMD24
A23 FBx_CMD8 A2 A2
FBA_D25 L30 W35 FBA_BA2 FBC_D24 D12 D22 FBC_MA3
FBA_D26 FBA_D25 FBA_CMD26 FBA_BA1 FBC_D25 FBC_D24 FBC_CMD25 FBC_BA2
M32 Y34 E13 B23 FBx_CMD9 A0 A0

MEMORY INTERFACE
FBA_D27 FBA_D26 FBA_CMD27 FBA_MA12 FBC_D26 FBC_D25 FBC_CMD26 FBC_BA1
N30 Y31 F13 C22

MEMORY INTERFACE C
FBA_D28 FBA_D27 FBA_CMD28 FBA_MA10 FBC_D27 FBC_D26 FBC_CMD27 FBC_MA12
M30
FBA_D28 FBA_CMD29
Y30 F14
FBC_D27 FBC_CMD28
B22 FBx_CMD10 A4 A4
FBA_D29 P31 W29 FBA_RAS# FBC_D28 F15 A22 FBC_MA10
FBA_D30 FBA_D29 FBA_CMD30 FBA_RAS# <28,29> FBC_D29 FBC_D28 FBC_CMD29 FBC_RAS#
R32
FBA_D30 FBA_CMD31
Y29 E16
FBC_D29 FBC_CMD30
A20 FBC_RAS# <30,31> FBx_CMD11 A1 A1
FBA_D31 R30 FBC_D30 F16 G20
FBA_D32 FBA_D31 FBA_DQM0 FBC_D31 FBC_D30 FBC_CMD31
AG30
FBA_D32 FBA_DQM0
P32 F17
FBC_D31 FBx_CMD12 BA0 BA0
FBA_D33 AG32 H34 FBA_DQM1 FBC_D32 D29 A16 FBC_DQM0
FBA_D34 FBA_D33 FBA_DQM1 FBA_DQM2 FBA_DQM[7..0] <28,29> FBC_D33 FBC_D32 FBC_DQM0 FBC_DQM1
AH31
FBA_D34 FBA_DQM2
J30 F27
FBC_D33 FBC_DQM1
D10 FBx_CMD13 WE# WE#
FBA_D35 AF31 P30 FBA_DQM3 FBC_D34 F28 F11 FBC_DQM2
C FBA_D36 FBA_D35 FBA_DQM3 FBA_DQM4 FBC_D35 FBC_D34 FBC_DQM2 FBC_DQM3 FBC_DQM[7..0] <30,31> C
AF30
FBA_D36 FBA_DQM4
AF32 E28
FBC_D35 FBC_DQM3
D15 FBx_CMD14 A15 A15
FBA_D37 AE30 AL32 FBA_DQM5 FBC_D36 D26 D27 FBC_DQM4
FBA_D38 FBA_D37 FBA_DQM5 FBA_DQM6 FBC_D37 FBC_D36 FBC_DQM4 FBC_DQM5
AC32
FBA_D38 FBA_DQM6
AL34 F25
FBC_D37 FBC_DQM5
D34 FBx_CMD15 CAS# CAS#
FBA_D39 AD30 AF35 FBA_DQM7 FBC_D38 D24 A34 FBC_DQM6
FBA_D40 FBA_D39 FBA_DQM7 FBC_D39 FBC_D38 FBC_DQM6 FBC_DQM7
AN33
FBA_D40
E25
FBC_D39 FBC_DQM7
D28 FBx_CMD16 CS0#_H
FBA_D41 AL31 L35 FBA_DQS#0 FBC_D40 E32
FBA_D41 FBA_DQS_RN0 FBC_D40

A
FBA_D42 AM33 G35 FBA_DQS#1 FBC_D41 F32 B14 FBC_DQS#0 FBx_CMD17
FBA_D43 FBA_D42 FBA_DQS_RN1 FBA_DQS#2 FBC_D42 FBC_D41 FBC_DQS_RN0 FBC_DQS#1
AL33 H31 D33 B10
FBA_D44 FBA_D43 FBA_DQS_RN2 FBA_DQS#3 FBC_D43 FBC_D42 FBC_DQS_RN1 FBC_DQS#2
AK30
FBA_D44 FBA_DQS_RN3
N32 FBA_DQS#[7..0] <28,29> E31
FBC_D43 FBC_DQS_RN2
D9 FBx_CMD18 ODT_H
FBA_D45 AK32 AD32 FBA_DQS#4 FBC_D44 C33 E14 FBC_DQS#3
FBA_D46 FBA_D45 FBA_DQS_RN4 FBA_DQS#5 FBC_D45 FBC_D44 FBC_DQS_RN3 FBC_DQS#4 FBC_DQS#[7..0] <30,31>
AJ30
FBA_D46 FBA_DQS_RN5
AJ31 F29
FBC_D45 FBC_DQS_RN4
F26 FBx_CMD19 CKE_H
FBA_D47 AH30 AJ35 FBA_DQS#6 FBC_D46 D30 D31 FBC_DQS#5
FBA_D48 FBA_D47 FBA_DQS_RN6 FBA_DQS#7 FBC_D47 FBC_D46 FBC_DQS_RN5 FBC_DQS#6
AH33
FBA_D48 FBA_DQS_RN7
AC34 E29
FBC_D47 FBC_DQS_RN6
A31 FBx_CMD20 A13 A13
FBA_D49 AH35 FBC_D48 B29 A26 FBC_DQS#7
FBA_D50 FBA_D49 FBA_DQS0 FBC_D49 FBC_D48 FBC_DQS_RN7
AH34
FBA_D50 FBA_DQS_WP0
L34 C31
FBC_D49 FBx_CMD21 A8 A8
FBA_D51 AH32 H35 FBA_DQS1 FBC_D50 C29 C14 FBC_DQS0
FBA_D52 FBA_D51 FBA_DQS_WP1 FBA_DQS2 FBC_D51 FBC_D50 FBC_DQS_WP0 FBC_DQS1
AJ33
FBA_D52 FBA_DQS_WP2
J32 B31
FBC_D51 FBC_DQS_WP1
A10 FBx_CMD22 A6 A6
FBA_D53 AL35 N31 FBA_DQS3 FBC_D52 C32 E10 FBC_DQS2
FBA_D54 FBA_D53 FBA_DQS_WP3 FBA_DQS4 FBC_D53 FBC_D52 FBC_DQS_WP2 FBC_DQS3
AM34
FBA_D54 FBA_DQS_WP4
AE31 B32
FBC_D53 FBC_DQS_WP3
D14 FBx_CMD23 A11 A11
FBA_D55 AM35 AJ32 FBA_DQS5 FBC_D54 B35 E26 FBC_DQS4
FBA_D56 FBA_D55 FBA_DQS_WP5 FBA_DQS6 FBA_DQS[7..0] <28,29> FBC_D55 FBC_D54 FBC_DQS_WP4 FBC_DQS5
AF33
FBA_D56 FBA_DQS_WP6
AJ34 B34
FBC_D55 FBC_DQS_WP5
D32 FBC_DQS[7..0] <30,31> FBx_CMD24 A5 A5
FBA_D57 AE32 AC33 FBA_DQS7 FBC_D56 A29 A32 FBC_DQS6
FBA_D58 FBA_D57 FBA_DQS_WP7 FBC_D57 FBC_D56 FBC_DQS_WP6 FBC_DQS7
AF34
FBA_D58
B28
FBC_D57 FBC_DQS_WP7
B26 FBx_CMD25 A3 A3
FBA_D59 AE35 P29 FBC_D58 A28
FBA_D60 FBA_D59 FBA_WCK0 FBC_D59 FBC_D58
30ohms (ESR=0.01) Bead AE34
FBA_D60 FBA_WCK0_N
R29 C28
FBC_D59 FBC_WCK0
G14 FBx_CMD26 BA2 BA2
FBA_D61 AE33 L29 FBC_D60 C26 G15
+1.05VS_VGA FBA_D62 FBA_D61 FBA_WCK1 FBC_D61 FBC_D60 FBC_WCK0_N
Under GPU(below 150mils) AB32
FBA_D62 FBA_WCK1_N
M29 D25
FBC_D61 FBC_WCK1
G11 FBx_CMD27 BA1 BA1
FBA_D63 AC35 AG29 FBC_D62 B25 G12
FBA_D63 FBA_WCK2 FBC_D63 FBC_D62 FBC_WCK1_N
BLM18PG330SN1D_0603 200mA FBA_WCK2_N
AH29 A25
FBC_D63 FBC_WCK2
G27 FBx_CMD28 A12 A12
1 2 +FB_PLLAVDD_0 AG27 AD29 G28
FB_DLLAVDD_0 FBA_WCK3 FBC_WCK2_N
10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

LV3 AF27
FB_PLLAVDD_0 FBA_WCK3_N
AE29
FBC_WCK3
G24 FBx_CMD29 A10 A10
OPTI@ CV106

OPTI@ CV107

OPTI@ CV108

OPTI@ CV109

OPTI@ CV110

OPTI@ CV111
1U_0402_6.3V6K

OPTI@ 1 1 1 1 1 2 +1.5VS_VGA 1 OPTI@ 2 K27 G25

B +FB_PLLAVDD_1 FBCAL_PD_VDDQ FBC_WCK3_N B
J19
FB_DLLAVDD_1
RV55 40.2_0402_1% FBx_CMD30 RAS# RAS#
J18 T32 FBA_CLK0 1 OPTI@ 2 L27
FB_PLLAVDD_1 FBA_CLK0 FBA_CLK0# FBA_CLK0 <28> FBCAL_PU_GND FBC_CLK0
T31 RV56 40.2_0402_1% E17
2 2 2 2 2 1 FBA_CLK0_N FBA_CLK0# <28> FBC_CLK0 FBC_CLK0# FBC_CLK0 <30>
RV58 OPTI@ J27 1 OPTI@ 2 M27 D17
FB_VREF_NC FBA_CLK1 FBCAL_TERM_GND FBC_CLK0_N FBC_CLK0# <30>
2 60.4_0402_1%
1 T30 AC31 RV57 60.4_0402_1%
FBA_DEBUG0 FBA_CLK1 FBA_CLK1# FBA_CLK1 <29> FBC_CLK1
2 1 T29 AC30 +1.5VS_VGA 60.4_0402_1% 2 OPTI@ 1 RV60 G19 D23
FBA_DEBUG1 FBA_CLK1_N FBA_CLK1# <29> FBC_DEBUG0 FBC_CLK1 FBC_CLK1# FBC_CLK1 <31>
RV59 10K_0402_5% 2 1 G16 E23
FBB_DEBUG1 FBC_CLK1_N FBC_CLK1# <31>
OPTI@ RV61 10K_0402_5%
+1.5VS_VGA @ OPTI@
N12P-GV1-A1_BGA_973P N12P-GV1-A1_BGA_973P @
+1.05VS_VGA

BLM18PG330SN1D_0603 200mA
1 2 +FB_PLLAVDD_1
10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

LV4 FBx_PLLAVDD and

OPTI@ CV112

OPTI@ CV113

OPTI@ CV114

OPTI@ CV115

OPTI@ CV116

OPTI@ CV117
1U_0402_6.3V6K

OPTI@ 1 1 1 1 1 2 FBx_DLLAVDD Combined

2 2 2 2 2 1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P-MEM Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 27 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits FBA_D[0..63] <27,29>

FBA_MA[15..0] <27,29>

FBA_BA[2..0] <27,29>
UV3 UV4
FBA_DQM[7..0] <27,29>
+1.5VS_VGA +FBA_VREF0 M8 E3 FBA_D3 +FBA_VREF0 M8 E3 FBA_D18
VREFCA DQL0 VREFCA DQL0 FBA_DQS[7..0] <27,29>
H1 F7 FBA_D4 H1 F7 FBA_D19
VREFDQ DQL1 FBA_D2 VREFDQ DQL1 FBA_D23
DQL2 F2 DQL2 F2 FBA_DQS#[7..0] <27,29>
1

D FBA_MA0 N3 F8 FBA_D7 FBA_MA0 N3 F8 FBA_D17 Group2 D

RV62 FBA_MA1 A0 DQL3 FBA_D0 FBA_MA1 A0 DQL3 FBA_D21
P7 A1 DQL4 H3 Group0 P7 A1 DQL4 H3
FBA_MA2 FBA_D5 FBA_MA2 FBA_D16
1.1K_0402_1% FBA_MA3
P3
N2
A2
A3
DQL5
DQL6
H8
G2 FBA_D1 FBA_MA3
P3
N2
A2
A3
DQL5
DQL6
H8
G2 FBA_D20 Mode D - Mirror Mode Mapping
OPTI@ FBA_MA4 P8 H7 FBA_D6 FBA_MA4 P8 H7 FBA_D22
2

+FBA_VREF0 FBA_MA5 A4 DQL7 FBA_MA5 A4 DQL7

P2 A5 P2 A5
FBA_MA6 R8 FBA_MA6 R8 DATA Bus
A6 A6
1

OPTI@ CV118

FBA_MA7 FBA_D29 FBA_MA7 FBA_D12

0.01U_0402_25V7K

1 R2 A7 DQU0 D7 R2 A7 DQU0 D7
RV63 FBA_MA8 T8 C3 FBA_D26 FBA_MA8 T8 C3 FBA_D11 Address 0..31 32..63
FBA_MA9 A8 DQU1 FBA_D31 FBA_MA9 A8 DQU1 FBA_D14
R3 A9 DQU2 C8 R3 A9 DQU2 C8
1.1K_0402_1% FBA_MA10 L7 C2 FBA_D28 FBA_MA10 L7 C2 FBA_D8 FBx_CMD0 CS0#_L
OPTI@ 2 FBA_MA11 A10/AP DQU3 FBA_D27 FBA_MA11 A10/AP DQU3 FBA_D13
R7 A7 Group3 R7 A7 Group1
2

FBA_MA12 A11 DQU4 FBA_D25 FBA_MA12 A11 DQU4 FBA_D10

N7 A12 DQU5 A2 N7 A12 DQU5 A2 FBx_CMD1
FBA_MA13 T3 B8 FBA_D30 FBA_MA13 T3 B8 FBA_D15
FBA_MA14 A13 DQU6 FBA_D24 FBA_MA14 A13 DQU6 FBA_D9
T7 A14 DQU7 A3 T7 A14 DQU7 A3 FBx_CMD2 ODT_L
FBA_MA15 M7 FBA_MA15 M7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD3 CKE_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2 FBx_CMD4 A14 A14
FBA_BA1 BA0 VDD FBA_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
FBA_CLK0 FBA_BA2 M3 G7 FBA_BA2 M3 G7 FBx_CMD5 RST RST
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8 FBx_CMD6 A9 A9
2

VDD N1 VDD N1
RV64 FBA_CLK0 J7 N9 FBA_CLK0 J7 N9 FBx_CMD7 A7 A7
<27> FBA_CLK0 CK VDD CK VDD
160_0402_1% FBA_CLK0# K7 R1 FBA_CLK0# K7 R1
<27> FBA_CLK0# CK VDD CK VDD
OPTI@ FBA_CKE_L K9 R9 FBA_CKE_L K9 R9 FBx_CMD8 A2 A2
<27> FBA_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
C C
1

FBx_CMD9 A0 A0
FBA_CLK0# FBA_ODT_L K1 A1 FBA_ODT_L K1 A1
<27> FBA_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_L L2 A8 FBA_CS0#_L L2 A8 FBx_CMD10 A4 A4
<27> FBA_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1
<27,29> FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9 FBA_ODT_L FBx_CMD11 A1 A1
<27,29> FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2
<27,29> FBA_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 FBx_CMD12 BA0 BA0
F1 F1 FBA_CKE_L
FBA_DQS0 VDDQ FBA_DQS2 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 FBx_CMD13 WE# WE#
FBA_DQS3 C7 H9 FBA_DQS1 C7 H9
DQSU VDDQ DQSU VDDQ

2
FBx_CMD14 A15 A15
RV65 RV66
FBA_DQM0 E7 A9 FBA_DQM2 E7 A9 10K_0402_5% 10K_0402_5% FBx_CMD15 CAS# CAS#
FBA_DQM3 DML VSS FBA_DQM1 DML VSS OPTI@ OPTI@
D3 DMU VSS B3 D3 DMU VSS B3
E1 E1 FBx_CMD16 CS0#_H

1
VSS VSS
VSS G8 VSS G8
FBA_DQS#0 G3 J2 FBA_DQS#2 G3 J2 FBx_CMD17
FBA_DQS#3 B7 DQSL VSS FBA_DQS#1 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8
VSS M1 VSS M1 FBx_CMD18 ODT_H
VSS M9 VSS M9
VSS P1 VSS P1 FBx_CMD19 CKE_H
FBA_RST# T2 P9 FBA_RST# T2 P9
<27,29> FBA_RST# RESET VSS RESET VSS
VSS T1 VSS T1 FBx_CMD20 A13 A13
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
FBx_CMD21 A8 A8
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 FBx_CMD22 A6 A6 B
1

RV67 RV68 L1 B9 RV69 L1 B9

10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 FBx_CMD23 A11 A11
OPTI@ OPTI@ L9 D8 OPTI@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 FBx_CMD24 A5 A5
2

2
VSSQ VSSQ
E8 E8
2

VSSQ VSSQ
VSSQ F9 VSSQ F9 FBx_CMD25 A3 A3
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 FBx_CMD26 BA2 BA2
96-BALL 96-BALL FBx_CMD27 BA1 BA1
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 FBx_CMD28 A12 A12
@ @
FBx_CMD29 A10 A10
+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE FBx_CMD30 RAS# RAS#
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
OPTI@ CV119

OPTI@ CV120

OPTI@ CV121

OPTI@ CV122

OPTI@ CV123

@ CV124

OPTI@ CV125

OPTI@ CV126

OPTI@ CV127

OPTI@ CV128

OPTI@ CV129

OPTI@ CV130

OPTI@ CV131

@ CV132

OPTI@ CV133

OPTI@ CV134

OPTI@ CV135

@ CV136

@ CV137

@ CV138

OPTI@ CV139

@ CV140

@ CV141

OPTI@ CV142
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P-VRAM A Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 28 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits

FBA_D[0..63] <27,28>

FBA_MA[15..0] <27,28>
UV5 UV6
+1.5VS_VGA
FBA_BA[2..0] <27,28>
+FBA_VREF1 M8 E3 FBA_D39 +FBA_VREF1 M8 E3 FBA_D58
VREFCA DQL0 FBA_D35 VREFCA DQL0 FBA_D59
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 FBA_DQM[7..0] <27,28>
1
F2 FBA_D37 F2 FBA_D56
RV70 FBA_MA0 DQL2 FBA_D33 FBA_MA0 DQL2 FBA_D63
D N3 A0 DQL3 F8 N3 A0 DQL3 F8 FBA_DQS[7..0] <27,28> D
FBA_MA1 P7 H3 FBA_D38 Group4 FBA_MA1 P7 H3 FBA_D57 Group7
1.1K_0402_1% FBA_MA2 A1 DQL4 FBA_D32 FBA_MA2 A1 DQL4 FBA_D61
P3 A2 DQL5 H8 P3 A2 DQL5 H8 FBA_DQS#[7..0] <27,28>
OPTI@ FBA_MA3 N2 G2 FBA_D36 FBA_MA3 N2 G2 FBA_D60
2

+FBA_VREF1 FBA_MA4 A3 DQL6 FBA_D34 FBA_MA4 A3 DQL6 FBA_D62

P8 A4 DQL7 H7 P8 A4 DQL7 H7
FBA_MA5 FBA_MA5
P2 A5 P2 A5 Mode D - Mirror Mode Mapping
1

OPTI@ CV143 FBA_MA6 FBA_MA6

0.01U_0402_25V7K

1 R8 A6 R8 A6
RV71 FBA_MA7 R2 D7 FBA_D42 FBA_MA7 R2 D7 FBA_D49
FBA_MA8 A7 DQU0 FBA_D45 FBA_MA8 A7 DQU0 FBA_D53
T8 A8 DQU1 C3 T8 A8 DQU1 C3
1.1K_0402_1% FBA_MA9 R3 C8 FBA_D40 FBA_MA9 R3 C8 FBA_D51 DATA Bus
OPTI@ 2 FBA_MA10 A9 DQU2 FBA_D44 FBA_MA10 A9 DQU2 FBA_D55
L7 C2 L7 C2
2

FBA_MA11 A10/AP DQU3 FBA_D41 FBA_MA11 A10/AP DQU3 FBA_D48 Address

R7 A11 DQU4 A7 Group5 R7 A11 DQU4 A7 Group6 0..31 32..63
FBA_MA12 N7 A2 FBA_D47 FBA_MA12 N7 A2 FBA_D54
FBA_MA13 A12 DQU5 FBA_D43 FBA_MA13 A12 DQU5 FBA_D50
T3 A13 DQU6 B8 T3 A13 DQU6 B8 FBx_CMD0 CS0#_L
FBA_MA14 T7 A3 FBA_D46 FBA_MA14 T7 A3 FBA_D52
FBA_MA15 A14 DQU7 FBA_MA15 A14 DQU7
M7 A15/BA3 +1.5VS_VGA
M7 A15/BA3 +1.5VS_VGA
FBx_CMD1
FBx_CMD2 ODT_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 BA0 VDD FBA_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 FBx_CMD3 CKE_L
FBA_CLK1 FBA_BA2 M3 G7 FBA_BA2 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 FBx_CMD4 A14 A14
VDD K8 VDD K8
2

VDD N1 VDD N1 FBx_CMD5 RST RST

RV72 FBA_CLK1 J7 N9 FBA_CLK1 J7 N9
<27> FBA_CLK1 CK VDD CK VDD
160_0402_1% FBA_CLK1# K7 R1 FBA_CLK1# K7 R1 FBx_CMD6 A9 A9
<27> FBA_CLK1# CK VDD CK VDD
OPTI@ FBA_CKE_H K9 R9 FBA_CKE_H K9 R9
<27> FBA_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
C FBx_CMD7 A7 A7 C
1

FBA_CLK1# FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 FBx_CMD8 A2 A2

<27> FBA_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_H L2 A8 FBA_CS0#_H L2 A8
<27> FBA_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD9 A0 A0
<27,28> FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9
<27,28> FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2 FBx_CMD10 A4 A4
<27,28> FBA_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 FBx_CMD11 A1 A1
FBA_DQS4 F3 H2 FBA_DQS7 F3 H2
FBA_DQS5 DQSL VDDQ FBA_DQS6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 FBx_CMD12 BA0 BA0
FBx_CMD13 WE# WE#
FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
FBA_DQM5 DML VSS FBA_DQM6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD14 A15 A15
VSS E1 VSS E1
VSS G8 VSS G8 FBx_CMD15 CAS# CAS#
FBA_DQS#4 G3 J2 FBA_DQS#7 G3 J2
FBA_DQS#5 B7 DQSL VSS FBA_DQS#6 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8 FBx_CMD16 CS0#_H
VSS M1 VSS M1
FBA_CKE_H M9 M9 FBx_CMD17
VSS VSS
VSS P1 VSS P1
FBA_RST# T2 P9 FBA_RST# T2 P9 FBx_CMD18 ODT_H
<27,28> FBA_RST# RESET VSS RESET VSS
FBA_ODT_H T1 T1
VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD19 CKE_H
FBx_CMD20 A13 A13
1

1
B
RV73 RV74 J1 B1 J1 B1 B
10K_0402_5% 10K_0402_5% RV75 NC/ODT1 VSSQ RV76 NC/ODT1 VSSQ
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 FBx_CMD21 A8 A8
OPTI@ OPTI@ 243_0402_1% J9 D1 243_0402_1% J9 D1
OPTI@ NC/CE1 VSSQ OPTI@ NC/CE1 VSSQ
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 FBx_CMD22 A6 A6
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 FBx_CMD23 A11 A11
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 FBx_CMD24 A5 A5
VSSQ G9 VSSQ G9
FBx_CMD25 A3 A3
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD26 BA2 BA2
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
@ @ FBx_CMD27 BA1 BA1
FBx_CMD28 A12 A12
+1.5VS_VGA UV5 SIDE +1.5VS_VGA UV6 SIDE
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
OPTI@ CV144

OPTI@ CV145

OPTI@ CV243

OPTI@ CV244

OPTI@ CV245

OPTI@ CV246

OPTI@ CV247

OPTI@ CV248

OPTI@ CV249

OPTI@ CV250

OPTI@ CV251

OPTI@ CV155

OPTI@ CV156

@ CV157

OPTI@ CV158

OPTI@ CV159

@ CV160

@ CV161

@ CV162

@ CV163

OPTI@ CV164

OPTI@ CV165

@ CV166

@ CV167
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P-VRAM A Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 29 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits FBC_D[0..63]

FBC_MA[15..0]
<27,31>

<27,31>

FBC_BA[2..0] <27,31>

FBC_DQM[7..0] <27,31>
+1.5VS_VGA UV7 UV8
FBC_DQS[7..0] <27,31>
+FBB_VREF0 M8 E3 FBC_D3 +FBB_VREF0 M8 E3 FBC_D22
VREFCA DQL0 VREFCA DQL0 FBC_DQS#[7..0] <27,31>
1
D H1 F7 FBC_D7 H1 F7 FBC_D16 D
RV77 VREFDQ DQL1 FBC_D1 VREFDQ DQL1 FBC_D18
DQL2 F2 DQL2 F2
FBC_MA0 N3 F8 FBC_D4 Group0 FBC_MA0 N3 F8 FBC_D19
1.1K_0402_1% FBC_MA1 A0 DQL3 FBC_D2 FBC_MA1 A0 DQL3 FBC_D23
P7 A1 DQL4 H3 P7 A1 DQL4 H3 Group2 Mode D - Mirror Mode Mapping
OPTI@ FBC_MA2 P3 H8 FBC_D6 FBC_MA2 P3 H8 FBC_D17
2

+FBB_VREF0 FBC_MA3 A2 DQL5 FBC_D0 FBC_MA3 A2 DQL5 FBC_D20

N2 A3 DQL6 G2 N2 A3 DQL6 G2
FBC_MA4 P8 H7 FBC_D5 FBC_MA4 P8 H7 FBC_D21
A4 DQL7 A4 DQL7
1

OPTI@ CV168 FBC_MA5 FBC_MA5 DATA Bus

0.01U_0402_25V7K

1 P2 A5 P2 A5
RV78 FBC_MA6 R8 FBC_MA6 R8
FBC_MA7 A6 FBC_D28 FBC_MA7 A6 FBC_D13 Address
R2 A7 DQU0 D7 R2 A7 DQU0 D7 0..31 32..63
1.1K_0402_1% FBC_MA8 T8 C3 FBC_D24 FBC_MA8 T8 C3 FBC_D10
OPTI@ 2 FBC_MA9 A8 DQU1 FBC_D31 FBC_MA9 A8 DQU1 FBC_D14
R3 C8 R3 C8 FBx_CMD0 CS0#_L
2

FBC_MA10 A9 DQU2 FBC_D25 FBC_MA10 A9 DQU2 FBC_D9

L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
FBC_MA11 R7 A7 FBC_D29 Group3 FBC_MA11 R7 A7 FBC_D12 Group1 FBx_CMD1
FBC_MA12 A11 DQU4 FBC_D27 FBC_MA12 A11 DQU4 FBC_D8
N7 A12 DQU5 A2 N7 A12 DQU5 A2
FBC_MA13 T3 B8 FBC_D30 FBC_MA13 T3 B8 FBC_D15 FBx_CMD2 ODT_L
FBC_MA14 A13 DQU6 FBC_D26 FBC_MA14 A13 DQU6 FBC_D11
T7 A14 DQU7 A3 T7 A14 DQU7 A3
FBC_MA15 M7 FBC_MA15 M7 FBx_CMD3 CKE_L
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD4 A14 A14
FBC_BA0 M2 B2 FBC_BA0 M2 B2
FBC_BA1 BA0 VDD FBC_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 FBx_CMD5 RST RST
FBC_CLK0 FBC_BA2 M3 G7 FBC_BA2 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 FBx_CMD6 A9 A9
VDD K8 VDD K8
2

VDD N1 VDD N1 FBx_CMD7 A7 A7

RV79 FBC_CLK0 J7 N9 FBC_CLK0 J7 N9
<27> FBC_CLK0 CK VDD CK VDD
C 160_0402_1% FBC_CLK0# K7 R1 FBC_CLK0# K7 R1 FBx_CMD8 A2 A2 C
<27> FBC_CLK0# CK VDD CK VDD
OPTI@ FBC_CKE_L K9 R9 FBC_CKE_L K9 R9
<27> FBC_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD9 A0 A0
1

FBC_CLK0# FBC_ODT_L K1 A1 FBC_ODT_L K1 A1 FBx_CMD10 A4 A4

<27> FBC_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBC_CS0#_L L2 A8 FBC_CS0#_L L2 A8
<27> FBC_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBC_RAS# J3 C1 FBC_RAS# J3 C1 FBx_CMD11 A1 A1
<27,31> FBC_RAS# RAS VDDQ RAS VDDQ
FBC_CAS# K3 C9 FBC_CAS# K3 C9
<27,31> FBC_CAS# CAS VDDQ CAS VDDQ
FBC_WE# L3 D2 FBC_WE# L3 D2 FBx_CMD12 BA0 BA0
<27,31> FBC_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 FBx_CMD13 WE# WE#
FBC_DQS0 F3 H2 FBC_DQS2 F3 H2 FBC_ODT_L
FBC_DQS3 DQSL VDDQ FBC_DQS1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 FBx_CMD14 A15 A15
FBC_CKE_L FBx_CMD15 CAS# CAS#
FBC_DQM0 E7 A9 FBC_DQM2 E7 A9
FBC_DQM3 DML VSS FBC_DQM1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD16 CS0#_H
VSS E1 VSS E1

1
G8 G8 RV80 RV81 FBx_CMD17
FBC_DQS#0 G3 VSS FBC_DQS#2 G3 VSS 10K_0402_5% 10K_0402_5%
DQSL VSS J2 DQSL VSS J2
FBC_DQS#3 B7 J8 FBC_DQS#1 B7 J8 OPTI@ OPTI@ FBx_CMD18 ODT_H
DQSU VSS DQSU VSS
VSS M1 VSS M1
M9 M9 FBx_CMD19 CKE_H

2
VSS VSS
VSS P1 VSS P1
FBC_RST# T2 P9 FBC_RST# T2 P9 FBx_CMD20 A13 A13
<27,31> FBC_RST# RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD21 A8 A8
B B
FBx_CMD22 A6 A6
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
1

RV82 RV83 L1 B9 RV84 L1 B9 FBx_CMD23 A11 A11

10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
OPTI@ OPTI@ L9 D8 OPTI@ L9 D8 FBx_CMD24 A5 A5
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
E8 E8 FBx_CMD25 A3 A3
2

VSSQ VSSQ
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 FBx_CMD26 BA2 BA2
VSSQ G9 VSSQ G9
FBx_CMD27 BA1 BA1
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD28 A12 A12
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
@ @ FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
+1.5VS_VGA UV7 SIDE +1.5VS_VGA UV8 SIDE
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
@ CV169

@ CV170

OPTI@ CV171

OPTI@ CV172

OPTI@ CV173

@ CV174

@ CV175

OPTI@ CV176

@ CV177

OPTI@ CV178

@ CV179

@ CV180

OPTI@ CV181

OPTI@ CV182

OPTI@ CV183

OPTI@ CV184

OPTI@ CV185

OPTI@ CV186

OPTI@ CV187

OPTI@ CV188

OPTI@ CV189

OPTI@ CV190

OPTI@ CV191

OPTI@ CV192
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P-VRAM C Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 30 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits FBC_D[0..63] <27,30>

FBC_MA[15..0] <27,30>

FBC_BA[2..0] <27,30>
UV9 UV10

+1.5VS_VGA FBC_DQM[7..0] <27,30>

+FBB_VREF1 M8 E3 FBC_D39 +FBB_VREF1 M8 E3 FBC_D56
VREFCA DQL0 FBC_D33 VREFCA DQL0 FBC_D63
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 FBC_DQS[7..0] <27,30>
D F2 FBC_D38 F2 FBC_D57 D
DQL2 DQL2
1
FBC_MA0 N3 F8 FBC_D32 FBC_MA0 N3 F8 FBC_D60
A0 DQL3 A0 DQL3 FBC_DQS#[7..0] <27,30>
RV85 FBC_MA1 P7 H3 FBC_D36 Group4 FBC_MA1 P7 H3 FBC_D59 Group7
FBC_MA2 A1 DQL4 FBC_D34 FBC_MA2 A1 DQL4 FBC_D61
P3 A2 DQL5 H8 P3 A2 DQL5 H8
1.1K_0402_1% FBC_MA3 N2 G2 FBC_D37 FBC_MA3 N2 G2 FBC_D58
OPTI@ FBC_MA4 A3 DQL6 FBC_D35 FBC_MA4 A3 DQL6 FBC_D62
P8 H7 P8 H7
Mode D - Mirror Mode Mapping
2

+FBB_VREF1 FBC_MA5 A4 DQL7 FBC_MA5 A4 DQL7

P2 A5 P2 A5
FBC_MA6 R8 FBC_MA6 R8
A6 A6
1

OPTI@ CV193 FBC_MA7 FBC_D42 FBC_MA7 FBC_D48 DATA Bus

0.01U_0402_25V7K

1 R2 A7 DQU0 D7 R2 A7 DQU0 D7
RV86 FBC_MA8 T8 C3 FBC_D43 FBC_MA8 T8 C3 FBC_D55
FBC_MA9 A8 DQU1 FBC_D41 FBC_MA9 A8 DQU1 FBC_D49 Address
R3 A9 DQU2 C8 R3 A9 DQU2 C8 0..31 32..63
1.1K_0402_1% FBC_MA10 L7 C2 FBC_D46 FBC_MA10 L7 C2 FBC_D52
OPTI@ 2 FBC_MA11 A10/AP DQU3 FBC_D40 FBC_MA11 A10/AP DQU3 FBC_D51
R7 A7 Group5 R7 A7 Group6 FBx_CMD0 CS0#_L
2

FBC_MA12 A11 DQU4 FBC_D45 FBC_MA12 A11 DQU4 FBC_D54

N7 A12 DQU5 A2 N7 A12 DQU5 A2
FBC_MA13 T3 B8 FBC_D44 FBC_MA13 T3 B8 FBC_D50 FBx_CMD1
FBC_MA14 A13 DQU6 FBC_D47 FBC_MA14 A13 DQU6 FBC_D53
T7 A14 DQU7 A3 T7 A14 DQU7 A3
FBC_MA15 M7 FBC_MA15 M7 FBx_CMD2 ODT_L
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
FBx_CMD3 CKE_L
FBC_BA0 M2 B2 FBC_BA0 M2 B2
FBC_BA1 BA0 VDD FBC_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 FBx_CMD4 A14 A14
FBC_BA2 M3 G7 FBC_BA2 M3 G7
FBC_CLK1 BA2 VDD BA2 VDD
VDD K2 VDD K2 FBx_CMD5 RST RST
VDD K8 VDD K8
VDD N1 VDD N1 FBx_CMD6 A9 A9
2

FBC_CLK1 J7 N9 FBC_CLK1 J7 N9
<27> FBC_CLK1 CK VDD CK VDD
RV87 FBC_CLK1# K7 R1 FBC_CLK1# K7 R1 FBx_CMD7 A7 A7
<27> FBC_CLK1# CK VDD CK VDD
C 160_0402_1% FBC_CKE_H K9 R9 FBC_CKE_H K9 R9 C
<27> FBC_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
OPTI@ FBx_CMD8 A2 A2
1

FBC_ODT_H K1 A1 FBC_ODT_H K1 A1 FBx_CMD9 A0 A0

<27> FBC_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBC_CLK1# FBC_CS0#_H L2 A8 FBC_CS0#_H L2 A8
<27> FBC_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
FBC_RAS# J3 C1 FBC_RAS# J3 C1 FBx_CMD10 A4 A4
<27,30> FBC_RAS# RAS VDDQ RAS VDDQ
FBC_CAS# K3 C9 FBC_CAS# K3 C9
<27,30> FBC_CAS# CAS VDDQ CAS VDDQ
FBC_WE# L3 D2 FBC_WE# L3 D2 FBx_CMD11 A1 A1
<27,30> FBC_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 FBx_CMD12 BA0 BA0
FBC_DQS4 F3 H2 FBC_DQS7 F3 H2
FBC_DQS5 DQSL VDDQ FBC_DQS6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 FBx_CMD13 WE# WE#
FBx_CMD14 A15 A15
FBC_DQM4 E7 A9 FBC_DQM7 E7 A9
FBC_DQM5 DML VSS FBC_DQM6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD15 CAS# CAS#
VSS E1 VSS E1
VSS G8 VSS G8 FBx_CMD16 CS0#_H
FBC_DQS#4 G3 J2 FBC_DQS#7 G3 J2
FBC_DQS#5 B7 DQSL VSS FBC_DQS#6 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8 FBx_CMD17
FBC_ODT_H M1 M1
VSS VSS
VSS M9 VSS M9 FBx_CMD18 ODT_H
VSS P1 VSS P1
FBC_CKE_H FBC_RST# T2 P9 FBC_RST# T2 P9 FBx_CMD19 CKE_H
<27,30> FBC_RST# RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD20 A13 A13
1

RV88 RV89
B
10K_0402_5% 10K_0402_5% FBx_CMD21 A8 A8 B
1

1
OPTI@ OPTI@ J1 B1 J1 B1
RV90 NC/ODT1 VSSQ RV91 NC/ODT1 VSSQ
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 FBx_CMD22 A6 A6
243_0402_1% J9 D1 243_0402_1% J9 D1
2

OPTI@ NC/CE1 VSSQ OPTI@ NC/CE1 VSSQ

L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 FBx_CMD23 A11 A11
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 FBx_CMD24 A5 A5
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 FBx_CMD25 A3 A3
VSSQ G9 VSSQ G9
FBx_CMD26 BA2 BA2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD27 BA1 BA1
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
@ @ FBx_CMD28 A12 A12
FBx_CMD29 A10 A10
+1.5VS_VGA UV9 SIDE +1.5VS_VGA UV10 SIDE FBx_CMD30 RAS# RAS#
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
OPTI@ CV195

@ CV196

OPTI@ CV197

OPTI@ CV198

OPTI@ CV199

OPTI@ CV200

@ CV201

OPTI@ CV202

OPTI@ CV203

@ CV204

OPTI@ CV205

OPTI@ CV206

@ CV207

OPTI@ CV208

@ CV209

@ CV210

OPTI@ CV211

@ CV212

OPTI@ CV213

OPTI@ CV214

OPTI@ CV215

OPTI@ CV216

OPTI@ CV217

OPTI@ CV218
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P-VRAM C Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 31 of 63
5 4 3 2 1
 5 4 3 2 1

Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
+3VS_VGA
ROM_SO +3VS_VGA XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]

2
RV92 RV93 RV94 STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
45.3K_0402_1% 34.8K_0402_1% 15K_0402_1%
OPTI@ @ @ STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
D D

1
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
<24> STRAP0 STRAP0
<24> STRAP1 STRAP1
<24> STRAP2 STRAP2
Pull-up to
RV97 Resistor Values Pull-down to Gnd
+3VS_VGA

2
OPTI@
@ RV95 RV96 RV97 5K 1000 0000
45.3K_0402_1% 34.8K_0402_1% 25.5K_0402_1%
GS@ 10K 1001 0001
1

1
34.8K_0402_1% 15K 1010 0010
GT@
20K 1011 0011
25K 1100 0100
30K 1101 0101

+3VS_VGA
35K 1110 0110
45K 1111 0111
2

2
C C
RV98 RV99 RV100
4.99K_0402_1% 4.99K_0402_1% 15K_0402_1%
@ @ OPTI@
ROM_SO : PD-10K
1

1
ROM_SCLK : PH-15K
<24> ROM_SI ROM_SI ROM_SI : PD20K (Samsung)
ROM_SO
<24> ROM_SO
<24> ROM_SCLK ROM_SCLK Strap 2 : N12P-GS, PD-25K, SUB_VENDOR XCLK_417
N12P-GT, PD35K,
2

Strap 1 : PD-35K 0 No VBIOS ROM 0 277MHz (Default)

2

@ RV101
X76 RV102 RV103
20K_0402_1%
10K_0402_1% 15K_0402_1%
Strap 0 : PH-45K 1 BIOS ROM is present (Default) 1 Reserved
OPTI@ @
1

FB_0_BAR_SIZE USER Straps

DeviceID ROM_SCLK STRAP2
0 256MB (Default) User[3:0]
N12P-GS 0x0DF4 Pull up 15K Pull down 25K
1 Reserved 1000-1100 Customer defined
B B
N12P-GT 0x0DF6 Pull up 15K Pull down 35K
3GIO_PADCFG PEX_PLL_EN_TERM
3GIO_PADCFG[3:0] 0 Disable (Default)

0110 Notebook Default 1 Enable

SLOT_CLK_CFG
0 GPU and MCH don't share a common reference clock
Hynix H5TQ1G63BFR-12C 64Mx16 0010 PD 15K SA000041S30 1 GPU and MCH share a common reference clock (Default)

128Mx16 0110 PD 35K SA00003YO10 SMBUS_ALT_ADDR VGA_DEVICE

0 0x9E (Default) 0 3D Device (Class Code 302h)
Samsung K4W1G1646E-HC12 64Mx16 0011 PD 20K SA000041T10
A 1 0x9C (Multi-GPU usage) 1 VGA Device (Default) A

128Mx16 0111 PD 45K SA000047Q10

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P_MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 32 of 63
5 4 3 2 1
 5 4 3 2 1

TOP side (under inductor)

RV180
<60> CPU_VIN+ 1 2 1 2 10_0402_1%
RV179 0_0402_5%
VENTURA@ 2 VENTURA@ 1
@ CV236 VENTURA@
D
CV235
10/02 Change to SA00004HT00. D
Link to Rsense, PWR side 0.1U_0402_16V4Z UV12
1 0.1U_0402_16V4Z 2 1 8 CPU_A1
VIN+ A1
<60> CPU_VIN- 1 2 10_0402_1% 2 7 CPU_A0 VENTURA@
RV183 VIN- A0 I2C_DATA_R 2 RV184 1 0_0402_5% I2C_DATA
3 6
GND SDA I2C_CLK_R 2 I2C_CLK
VENTURA@ +3VS 4 5 1
VS SCL 0_0402_5%
INA219AIDCNRG4_SOT23-8 RV185 VENTURA@

+3VS VENTURA@

For CPU Ventura

2
RV186 RV187
slave address : 1000010
0_0402_5% @ 0_0402_5% please placemnet near R-sense
@
RV211

1
CPU_A0 1 2 I2C_DATA
0_0402_5% VENTURA@ +3VS
CPU_A1

2
RV190 RV191
VENTURA@ @

1
0_0402_5% 0_0402_5% +3VS_VGA
C RV193 RV194 C
1

1
2.2K_0402_5% 2.2K_0402_5%
VENTURA@ VENTURA@

2
G
I2C_DATA 1 3 I2CB_SDA
I2CB_SDA <23>

S
VENTURA@
QV3
Link to GPU

2
2N7002E-T1-GE3_SOT23-3

G
I2C_CLK 1 3 I2CB_SCL
I2CB_SCL <23>

S
VENTURA@
QV4
2N7002E-T1-GE3_SOT23-3

VENTURA@
<59> GPU_VIN+ 1 2 1 2 10_0402_1%
RV195 RV196
0_0402_5% 1 VENTURA@ 1
CV238 VENTURA@
10/02 Change to SA00004HT00.
CV237
Link to Rsense, PWR side 0.1U_0402_16V4Z UV13
@ 2 0.1U_0402_16V4Z 2 1 8 GPU_A1
VIN+ A1
<59> GPU_VIN- 1 2 10_0402_1% 2 7 GPU_A0
+3VS RV197 VIN- A0 I2C_DATA
B 3 6 B
GND SDA I2C_CLK
VENTURA@ +3VS 4 5
VS SCL
INA219AIDCNRG4_SOT23-8
2

RV198 RV199 VENTURA@

0_0402_5% 0_0402_5%
@ VENTURA@
1

GPU_A1
RV212
GPU_A0 1 2 I2C_DATA
0_0402_5% VENTURA@
Ventura for GPU SIDE
2

RV202 RV203 Slave Address 1000110

0_0402_5% 0_0402_5% Placement near Rsense
1

@ @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N12P_VENTURA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 33 of 63
5 4 3 2 1
 5 4 3 2 1

INVPWM
+LEDVDD B+

1 R813 2 0_0805_5%

470P_0402_50V7K

470P_0402_50V7K
DISPOFF# 1 1
C523
C525 680P_0402_50V7K C524
1 @ 1 @ @ 4.7U_0805_25V6-K
C527 2 2

JLVDS1
2 2 1
1
2
2 G1
31 10/04 place closed to JLVDS1
D
For EMI 3
3 G2
32
D
ECR_EN 4 33
<45> ECR_EN DISPOFF# 4 G3 DMIC_CLK
5 34
R815 INVPWM 5 G4
<45> INVT_PWM 1 2 6
6

1
0_0402_5% @ 7
CE_EN 7 R1341
8
LCD POWER CIRCUIT +3VS
<45> CE_EN
LVDS_ACLK
LVDS_ACLK#
9
10
8
9 33_0402_5%
10 @
11

2
LVDS_A2 11
12
+LCDVDD +5VALW LVDS_A2# 12
13 1
R818 R819 LVDS_A1 13
14
14

22P_0402_50V8J
C926
2.2K_0402_5% 2.2K_0402_5% LVDS_A1# 15
+3VS LVDS_A0 15
W=60mils LVDS_A0#
16 16 2
1 17 17
R816 R817 EDID_DATA 18 @
150_0603_1% 100K_0402_5% EDID_CLK 18
1 19 19
C529 +3VS 20
4.7U_0805_10V4Z 20
1 21 21
@ +3VS +LCDVDD_CONN (60 MIL) 22
2

22
1

3
D R820 220K_0402_5%
S
2 680P_0402_50V7K
G 23 23
2 1 2 2 C528 24
Q67 G 2 24
<42> DMIC_DATA 25 25
2N7002_SOT23 S 1
D AO3413_SOT23-3 26
<42> DMIC_CLK
3

1
26
1

DTC124EK C530 Q68 27

+CMOS_PW USB20_P5 27
W=60mils CMOS <18> USB20_P5 28
OUT

0.1U_0402_16V4Z USB20_N5 28
<18> USB20_N5 29 29
2 +LCDVDD +LCDVDD_CONN 30
L15 30
<17> PCH_ENVDD 2 IN
1 2
GND

ACES_88341-3001
Q69 FBMA-L11-201209-221LMA30T_0805 ME@
1

DTC124EKAT146_SC59-3 1 1 9/21 Rev0.2 update from 40 to 30 pin.

3

C C531 C532 C
R821 @
100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2
2

+3VS

8/4 add ESD request

1
R891 1 2 @
0_0402_5%
+3VS R822
DMIC_DATA USB20_P5 4.7K_0402_5%
D30
@

2
5

U23 DMIC_CLK USB20_N5 BKOFF# 1 2 DISPOFF#

<45> BKOFF#
P

NC

2 4 INVPWM CH751H-40PT_SOD323-2
<17> PCH_PWM A Y

1
@
G

NC7SZ14P5X_NL_SC70-5 10/02 change to SCS00000Z00

@ @ R890
3

10K_0402_5%
D70 D71

2
1 R824 2 PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3

1
2
G

0_0402_5%

3 1 INVPWM 2 R826 1 +3VS

10K_0402_5% @ R825 1 0_0402_5%
S

<17> PCH_ENBKL 2 ENBKL <45>

2N7002_SOT23

2
Q70
@ R827
B 100K_0402_1% B
For GMCH DPST

1
<17> EDID_CLK EDID_CLK
<17> EDID_DATA EDID_DATA

LVDS_A0
<17>
<17>
LVDS_A0
LVDS_A0#
LVDS_A0# CMOS Camera (20 MIL)
LVDS_A1 11/12 Remove 0 ohm
<17> LVDS_A1
LVDS_A1#
<17> LVDS_A1#
R432 +CMOS_PW
LVDS_A2 (20 MIL) 0_0603_5%
<17> LVDS_A2

S
LVDS_A2# 3 1 +CMOS_PW_R 1 2

D
<17> LVDS_A2# +3VS
1 1
LVDS_ACLK CMOS@ CMOS@
<17> LVDS_ACLK
LVDS_ACLK# Q83 C518 C519

G
<17> LVDS_ACLK#

2
+5VALW SI2301BDS-T1-E3_SOT23-3 0.1U_0402_16V4Z 10U_0805_10V4Z
R434100K_0402_5% CMOS@ 2 2
4.7V
1

1
CMOS@ R435 CMOS@
150K_0402_5% C520

OUT
CMOS@ 0.1U_0402_16V4Z
2

<45> CMOS_OFF# 2
IN

GND
A Q84 A
DTC124EKAT146_SC59-3

3
CMOS@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 34 of 63
5 4 3 2 1
 A B C D E

+5VS +5VS +5VS +5VS +5VS

3 3 3 3 3

1 BLUE 1 GREEN 1 RED 1 JVGA_HS 1 JVGA_VS

2 2 2 BAT54S-7-F_SOT23-3 2 2
@ @ @ @ @
D31 D32 D33 D34 D35
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3

1
+5VS
D36
+CRT_VCC
CRT Connector
F1
1

2 1 1 2 +CRT_VCC_CONN
1
RB491D_SC59-3
1.1A_6V_SMD1812P110TF C536

FCM1608CF-121T03 0603 W=40mils 2

0.1U_0402_16V4Z

DAC_RED 1 2 RED 10/02 Change to SCS00003H00.

<17> DAC_RED
L16
FCM1608CF-121T03 0603
DAC_GRN 1 2 GREEN
<17> DAC_GRN
L17
FCM1608CF-121T03 0603 JCRT1
DAC_BLU 1 2 BLUE 6
<17> DAC_BLU
L18 11

1
1 1 1 1 1 1 RED 1
7
R830 R831 R832 C537 C538 C539 C540 C542 C541 CRT_DDC_DAT_CONN 12
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J GREEN 2
2 2 2 2 2 2
8

2
JVGA_HS 13
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J BLUE 3
CLOSE TO CONN 9
JVGA_VS 14 G 16
4 G 17
10
CRT_DDC_CLK_CONN 15
2 5 2
+CRT_VCC 1
R833
C543 TYCO_1775763-1
1 2 ME@
1 100P_0402_50V8J
2
C544 1K_0402_5%
0.1U_0402_16V4Z
2

1OE#
P
2 A 4 CRT_HSYNC_1 1 2 JVGA_HS
<17> CRT_HSYNC Y 0603
FCM1608CF-121T03 L19

G
U24
SN74AHCT1G125DCKR_SC70-5 1

3
@
C545
10P_0402_50V8J
+CRT_VCC 2
R834
1 2
1
C546 1K_0402_5%
0.1U_0402_16V4Z
2
5

1OE#
P
2 A 4 CRT_VSYNC_1 1 2 JVGA_VS
3 <17> CRT_VSYNC Y 0603 3
FCM1608CF-121T03 L20
G

U25 1
SN74AHCT1G125DCKR_SC70-5
3

@ C547
10P_0402_50V8J
2

+3VS +3VS +CRT_VCC

1

1
R835 R836
2.2K_0402_5% 2.2K_0402_5% R837 R838
5

2.2K_0402_5% 2.2K_0402_5%
2

<17> CRT_DDC_DATA CRT_DDC_DATA 4 3 2 CRT_DDC_DAT_CONN

2N7002DW -T/R7_SOT363-6
2

Q73B

<17> CRT_DDC_CLK CRT_DDC_CLK 1 6 CRT_DDC_CLK_CONN

1 1
2N7002DW -T/R7_SOT363-6 @ @
Q73A C548 C549
4
100P_0402_50V8J 68P_0402_50V8K 4
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 35 of 63
A B C D E
 5 4 3 2 1

<17> HDMI_CLK+_CK HDMI_CLK+_CK

<17> HDMI_CLK-_CK HDMI_CLK-_CK
<17> HDMI_TX0+_CK HDMI_TX0+_CK
HDMI_CLK+_CONN 1 @ 2 <17> HDMI_TX0-_CK HDMI_TX0-_CK
R1130 499_0402_1% <17> HDMI_TX1+_CK HDMI_TX1+_CK
HDMI_CLK-_CONN 1 @ 2 <17> HDMI_TX1-_CK HDMI_TX1-_CK
R1132 499_0402_1% <17> HDMI_TX2+_CK HDMI_TX2+_CK
HDMI_TX0+_CONN 1 @ 2 <17> HDMI_TX2-_CK HDMI_TX2-_CK
R1134 499_0402_1%
D HDMI_TX0-_CONN 1 @ 2 <24> VGA_HDMI_CLK+ VGA_HDMI_CLK+ @ CV253 1 2 0.1U_0402_10V6K HDMI_CLK+_CK D
R1135 499_0402_1% <24> VGA_HDMI_CLK- VGA_HDMI_CLK- @ CV254 1 2 0.1U_0402_10V6K HDMI_CLK-_CK
R1130 R1132 HDMI_TX1+_CONN 1 @ 2 <24> VGA_HDMI_TX0+ VGA_HDMI_TX0+ @ CV255 1 2 0.1U_0402_10V6K HDMI_TX0+_CK
R1137 499_0402_1% <24> VGA_HDMI_TX0- VGA_HDMI_TX0- @ CV256 1 2 0.1U_0402_10V6K HDMI_TX0-_CK
HDMI_TX1-_CONN 1 @ 2 <24> VGA_HDMI_TX1+ VGA_HDMI_TX1+ @ CV257 1 2 0.1U_0402_10V6K HDMI_TX1+_CK
R1138 499_0402_1% <24> VGA_HDMI_TX1- VGA_HDMI_TX1- @ CV258 1 2 0.1U_0402_10V6K HDMI_TX1-_CK
HDMI_TX2+_CONN 1 @ 2 <24> VGA_HDMI_TX2+ VGA_HDMI_TX2+ @ CV259 1 2 0.1U_0402_10V6K HDMI_TX2+_CK
R1140 499_0402_1% <24> VGA_HDMI_TX2- VGA_HDMI_TX2- @ CV260 1 2 0.1U_0402_10V6K HDMI_TX2-_CK
680_0402_1% 680_0402_1% HDMI_TX2-_CONN 1 @ 2
HDMI@ HDMI@ R1141 499_0402_1% +3VS
D

1
R1134
R1135 +3VS 2 Q114
G 2N7002_SOT23-3
S

3
1 HDMI@ 2
R1142 100K_0402_5%

2
680_0402_1% HDMI@
HDMI@ 680_0402_1% HDMI@
HDMI@ <17> HDMICLK HDMICLK 1 6 HDMICLK_R

R1137 R1138 2N7002DW -T/R7_SOT363-6

5
Q80A
HDMI@
<17> HDMIDAT HDMIDAT 4 3 HDMIDAT_R

2N7002DW -T/R7_SOT363-6
680_0402_1% 680_0402_1% Q80B
HDMI@ HDMI@
+3VS_VGA
C R1140 C
R1141

2
@

1 6 HDMICLK_R
<24> VGA_HDMI_CLK
680_0402_1% 2N7002DW -T/R7_SOT363-6

5
HDMI@ 680_0402_1% Q115A @
HDMI@
4 3 HDMIDAT_R
<24> VGA_HDMI_DATA
2N7002DW -T/R7_SOT363-6 10/02 Change to SCS00003H00.
Q115B
+5VS

+5VS_HDMI_F

2
HDMI@
D37
RB491D_SC59-3

1 1
+5VS
+3VS R857 @ F2
09/15 Add
0_0805_5%
1.1A_6V_SMD1812P110TF

2
HDMI@

2
DVT, Change to SM070000I00 for EMI request.

2
R859 +5VS_HDMI 1 C561
1M_0402_5% D38 0.1U_0402_16V4Z

2
B HDMI@ BAT54S-7-F_SOT23-3 @ HDMI@ B

1
2
G
L23 Q85

1
HDMI_CLK+_CK HDMI_CLK+_CONN HDMI@ R860 R861 2
1 1 2 2
<17> TMDS_B_HPD# 3 1 HDMI_DET_UMA 2.2K_0402_5% 2.2K_0402_5%
HDMI@ HDMI@

1
HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN 2N7002_SOT23
4 3

2
W CM-2012-900T_4P R864
20K_0402_1%
L24 HDMI@ JHDMI1
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN
8/6 update to 20K :DG1.2 19

1
1 2 HP_DET
18 +5V
17 DDC/CEC_GND
HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN R1143 L67 HDMIDAT_R 16
4 3 HDMICLK_R SDA
15 SCL
W CM-2012-900T_4P 10K_0402_5% BLM18PG181SN1D_0603 14 Reserved
<23> VGA_HDMI_HPD 1 2 2 1 13 CEC
L26 @ @ HDMI_CLK-_CONN 12 20
HDMI_TX1+_CK HDMI_TX1+_CONN CK- G1
1 1 2 2 11 CK_shield G2 21
1
@

HDMI_CLK+_CONN
R1144
100K_0402_5%

10 CK+ G3 22
HDMI_TX0-_CONN 9 23
HDMI_TX1-_CK HDMI_TX1-_CONN D0- G4
4 4 3 3 8 D0_shield
HDMI_TX0+_CONN 7
W CM-2012-900T_4P HDMI_TX1-_CONN D0+
6
2

D1-
5 D1_shield
L27 HDMI_TX1+_CONN 4
HDMI_TX2+_CK HDMI_TX2+_CONN HDMI_TX2-_CONN D1+
1 1 2 2 3 D2-
2 D2_shield
A
HDMI_TX2+_CONN 1 A
HDMI_TX2-_CK HDMI_TX2-_CONN D2+
4 4 3 3
SUYIN_100042GR019M23DZL
W CM-2012-900T_4P
ME@
HDMI_CLK+_CK R865 1 @ 2 0_0402_5% HDMI_CLK+_CONN
HDMI_CLK-_CK R866 1 @ 2 0_0402_5% HDMI_CLK-_CONN
HDMI_TX0+_CK R867 1 @ 2 0_0402_5% HDMI_TX0+_CONN Security Classification Compal Secret Data Compal Electronics,Ltd.
HDMI_TX0-_CK R868 1 @ 2 0_0402_5% HDMI_TX0-_CONN 2010/11/30 2011/08 Title
Issued Date Deciphered Date
HDMI_TX1+_CK R869 @ 0_0402_5% HDMI_TX1+_CONN
HDMI_TX1-_CK R870
1
1 @
2
2 0_0402_5% HDMI_TX1-_CONN HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI_TX2+_CK R871 1 @ 2 0_0402_5% HDMI_TX2+_CONN Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
HDMI_TX2-_CK R872 @ 0_0402_5% HDMI_TX2-_CONN Custom 0.3
1 2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 36 of 63
5 4 3 2 1
 A B C D E

Reserve for SW mini-pcie debug card.

Series resistors closed to KBC side.
LPC_FRAME#_R R873 1 @ 2 0_0402_5% LPC_FRAME#
LPC_FRAME# <14,45>
LPC_AD3_R R874 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 <14,45>
LPC_AD2_R R875 1 @ 2 0_0402_5% LPC_AD2
LPC_AD2 <14,45>
LPC_AD1_R R876 1 @ 2 0_0402_5% LPC_AD1
LPC_AD1 <14,45>
LPC_AD0_R R878 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 <14,45>
PCI_RST#_R R879 1 @ 2 0_0402_5% BUF_PLT_RST#
Mini-Express Card for WLAN/WiMAX(Half) CLK_PCI_DB CLK_PCI_DB <15>

1 Mini-Express Card for SSD(Full) 1

+1.5VS
+3VS_WLAN +1.5VS
+3VS +3VS_WLAN
J3

1
1 1 1
Mini-Express Card(WLAN/WiMAX) 1 2 J4

1
1 2 C563 C564 C565
JUMP_43X79
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

@
JUMP_43X79 2 2 2

2
@
JP1

2
<16,38,49> PCIE_WAKE# PCIE_WAKE# 1 2
@ BT_ACTIVE R877 1 1 2
<47> BT_ACTIVE 2 @ 0_0402_5% 3 4
R1319 1 0_0402_5% BT_DISABLE_R 3 4 +1.5VS_WLAN
<19,47> BT_OFF# 2 5 6
WLAN_CLKREQ1# 5 6 LPC_FRAME#_R
<15> WLAN_CLKREQ1# 7 8
7 8 LPC_AD3_R
9 10
R1320 1 0_0402_5% 9 10 LPC_AD2_R
<19> BT_DISABLE 2 <15> CLK_PCIE_WLAN1# 11 12
11 12 LPC_AD1_R
<15> CLK_PCIE_WLAN1 13 14
13 14 LPC_AD0_R
15 16
PCI_RST#_R 15 16
17 18
CLK_PCI_DB 17 18 R880 1 0_0402_5%
19 20 2 WL_OFF# <18>
19 20 WL_RST#
21 22
21 22 R881 1
<15> PCIE_PRX_DTX_N2 23 24 2 @ 0_0402_5% +3VALW
23 24 R882 1 0_0402_5% +3VS
<15> PCIE_PRX_DTX_P2 25 26 2 +3VS
25 26
27 28
27 28 R883 1
29 30 2 @ 0_0402_5% SMB_CLK_S3 <12,13,15>
29 30 R884 1 +3VS_WLAN
<15> PCIE_PTX_C_DRX_N2 31 32 2 @ 0_0402_5% SMB_DATA_S3 <12,13,15>
31 32
<15> PCIE_PTX_C_DRX_P2 33 34
MC74VHC1G08DFT2G SC70 5P 33 34
3 Q133

S
35 36 USB20_N9 <18> 1
35 36
3

+3VS_WLAN 37 38 +5VS
37 38 USB20_P9 <18>
DEVICE_RST# 1 39 40 AO3414_SOT23-3
G

<19,38,44> DEVICE_RST# A 39 40
4 WL_RST# 41 42 0_0402_5% 2 1 R885 @

G
2
Y 41 42

1
BUF_PLT_RST# 2 43 44 0_0402_5% 2 1 R886 WLAN_LED# WLAN_LED# <47> @
<18,23,38,44,45,49> BUF_PLT_RST# B 43 44
P

@ 100_0402_1% 45 46 R1329
U60 R887 45 46 33K_0402_5%
47 48
5

EC_TX_P80_DATA 1 47 48
<45,46> EC_TX_P80_DATA 2 49 50
EC_RX_P80_CLK 1 49 50
2
<45,46> EC_RX_P80_CLK 2 51 52 2

2
R888 51 52
100_0402_1% 53 54
+3VS GNDGND
2

1
D C921
ACES_51711-0520W-001
1 2 FAST_BOOT# 2
<38,44,45> FAST_BOOT#

2
R1342 0_0402_5% For EC to detect ME@ G
1
0.1U_0402_16V4Z
R889 Q132 S @
debug card insert.

3
100K_0402_5% 2N7002_SOT23-3
@

1
SSD Active:0.22W(0.06A)
+3VS_SSD

+3VS +3VS_SSD 0.1U_0402_16V4Z 10U_0805_10V4Z

J5
1 1 1 1
1 2 @
1 2 C566 C567 C568 C569
Mini-Express Card(SSD) JUMP_43X79 2 2 2 2
@
JP3 0.01U_0402_25V7K 10U_0805_10V4Z
1 2
1 2
3 4
3 4
5 6
5 6
7 8
7 8
9 10
9 10
11 12
11 12
13 14
13 14
15 16
15 16
17 18
17 18
19 20
3
0.01U_0402_16V7K 19 20 3
21 22
SATA_DTX_C_IRX_P0 2 21 22
1 C572 SATA_DTX_IRX_P0 23 24
<14> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_N0 2 23 24
1 C573 SATA_DTX_IRX_N0 25 26
<14> SATA_DTX_C_IRX_N0 25 26
27 28
0.01U_0402_16V7K 27 28
29 30
SATA_ITX_DRX_N0 29 30
<14> SATA_ITX_DRX_N0 31 32
SATA_ITX_DRX_P0 31 32
<14> SATA_ITX_DRX_P0 33 34
33 34
35 36
35 36
37 38
37 38
39 40
+3VS_SSD 39 40
41 42
41 42
43 44
43 44
45 46
100_0402_1% 45 46
47 48
EC_TX_P80_DATA R893 1 47 48
<45,46> EC_TX_P80_DATA 2 @ 49 50
EC_RX_P80_CLK 49 50
<45,46> EC_RX_P80_CLK 1 2 @ 51 52
51 52
R894
100_0402_1% 53 54
GNDGND
DA_DSS 1 2 ACES_51711-0520W-001
DA_DSS R895 0_0402_5%
SATA_DET# 1 2 ME@
<14> SATA_DET# R896 0_0402_5%
For SSD use: @

4 4

Security Classification
2010/11/30
Compal Secret Data
2011/08 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 37 of 63
A B C D E
 5 4 3 2 1

MC74VHC1G08DFT2G SC70 5P

3
DEVICE_RST# 1

G
<19,37,44> DEVICE_RST# A
4 LAN_RST#_R
BUF_PLT_RST# Y U27
<18,23,37,44,45,49> BUF_PLT_RST# 2 B

P
@ +3V_LAN SM010005500 500ma 600ohm@100mhz DCR 0.38 +3V_LAN
U58 L30

5
42 20mil BLM18AG601SN1D_2P
R1323 1 VDDO +LAN_BIASVDDH +LAN_BIASVDDH
2 0_0402_5% BIASVDDH 25 1 2
1
+3VS 57780@ C585
+1.2V_LAN LAN_XTALI_80 R1210 1 2 0_0402_5% LAN_XTALI 0.1U_0402_16V4Z
D
091211 EMI add 1000P XTALVDDH/XTALVDDH/XTALI
12
2 D
15 R1211 1 2 0_0402_5% +LAN_XTALVDDH L28
VDDC 57781@ BLM18AG601SN1D_2P
1 1 1 1 1 1 41
VDDC 20mil

4.7U_0603_6.3V6K
C586

0.1U_0402_16V4Z
C587

0.1U_0402_16V4Z
C588

0.1U_0402_16V4Z
C589

1000P_0402_50V7K
C590

1000P_0402_50V7K
C591
+LAN_XTALVDDH 1 2
SM010005500 500ma 600ohm@100mhz DCR 0.38 1
2 2 2 2 2 2 C592
+1.2V_LAN L29
20mil +LAN_AVDDH 0.1U_0402_16V4Z
30
BLM18AG601SN1D_2P AVDDH 2
36
+LAN_PCIEPLLVDD AVDDH L31
2 1
1 1 20mil BLM18AG601SN1D_2P
+LAN_AVDDH 1 2
C593 C594 27 1 1
4.7U_0603_6.3V6K <BOM Structure>
0.1U_0402_16V4Z AVDDL
33 AVDDL
2 2 +LAN_AVDDL 39 C595 C596
AVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z
BCM57781 37 MDI3-
MDI3- <39>
2 2

+1.2V_LAN L32 TRD3_N MDI3+

20mil +LAN_GPHYPLLVDDL TRD3_P 38 MDI3+ <39>
BLM18AG601SN1D_2P 24
+LAN_GPHYPLLVDDL GPHY_PLLVDDL MDI2-
2 1 35 MDI2- <39>
TRD2_N MDI2+
TRD2_P 34 MDI2+ <39>
1 1
C597 C598 31 MDI1-
TRD1_N MDI1+ MDI1- <39>
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 32
TRD1_P MDI1+ <39>
+LAN_PCIEPLLVDD 18
2 2 PCIE_PLLVDDL MDI0-
21 PCIE_PLLVDDL TRD0_N 29 MDI0- <39>
28 MDI0+
TRD0_P MDI0+ <39>
+1.2V_LAN L33 20mil
BLM18AG601SN1D_2P
2 1 +LAN_AVDDL
C 57780@ C

1 1 R1212 2 1 0_0402_5% ACTIVITY#

C599 C600 45 R1213 2 1 0_0402_5% LAN_SK#
4.7U_0603_6.3V6K 0.1U_0402_16V4Z SO#_LINKLED#/SO#_LINKLED#/TRAFFICLED# 57781@ LAN_SK# <39>

SPD100LED#/SPD100LED#/LINKLED# 48
2 2
<15> PCIE_PRX_DTX_P1 C601 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 46 LAN_SK#
C602 1 PCIE_PRX_C_DTX_N1 SCLK_SPD1000LED#/SCLK_SPD1000LED#/SPD1000LED#
<15> PCIE_PRX_DTX_N1 2 0.1U_0402_16V7K 57781@
17 47 R1214 2 1 0_0402_5% ACTIVITY#
<15> PCIE_PTX_C_DRX_P1 PCIE_TXD_P TRAFFICLED#/TRAFFICLED#/SPD100LED# LAN_SK# ACTIVITY# <39>
16 R1215 2 1 0_0402_5%
<15> PCIE_PTX_C_DRX_N1 PCIE_TXD_N +3V_LAN
22 3 57780@
R901 1 @ PCIE_RXD_P GPIO0/GPIO0/CLK_REQ#
+3V_LAN 2 4.7K_0402_5% 23
R902 1 @ LAN_PME# PCIE_RXD_N
<16,37,49> PCIE_WAKE# 2 0_0402_5% 1
WAKE#/WAKE#/LOW_PWR
R1315 1 @ 2 4.7K_0402_5% Add R1315 for 57781 write protection w/ EEPROM
<45> LAN_WAKE# R903 1 2 0_0402_5% R1216 1 2 0_0402_5% CLKREQ_LAN#
57781@ 6 57780@ +3V_LAN
57781@ PERST#/PERST#/VDDC +3V_LAN
+1.2V_LAN R904 1 2 0_0402_5% 20 R1296 1 57780@ 2 0_0402_5% LAN_WAKE#
LAN_RST#_R PCIE_REFCLK_P PCIE_WAKE#
R1217 1 2 0_0402_5% 19 R1218 1 @ 2 0_0402_5%
57780@ PCIE_REFCLK_N R905 1 57781@ 2 4.7K_0402_5%
SMB_CLK/TEST_1/WAKE#
4 1 @
5 R906 1 57781@ 2 4.7K_0402_5% C603
SMB_DATA/TEST_2/MODE 0.1U_0402_16V4Z
<15> CLK_PCIE_LAN

2
R1219 1 2 0_0402_5% SPROM_DOUT @
<15> CLK_PCIE_LAN# 2

1K_0402_1%
R907

1K_0402_1%
R908
57780@
43 R1220 1 2 0_0402_5% SPROM_CLK
CS#_EECLK/CS#_EECLK/EEDATA 57781@
+3VS
S0 power U28 @

1
44 R1221 1 2 0_0402_5% SPROM_DOUT 8 1
R909 1 SI#_EEDATA/SI#_EEDATA/EECLK VCC A0
2 1K_0402_5% 40
VMAIN_PRSNT
57781@ 7
WP A1
2
LAN_RST#_R R1222 1 2 0_0402_5% 2 R1223 1 2 0_0402_5% SPROM_CLK SPROM_CLK 6 3
57780@ LOW_PWR/LOW_PWR/PERST# 57780@ SPROM_DOUT SCL NC
5 4
+1.2V_LAN SDA GND
+LAN_XTALVDDH R1224 1 57780@ 2 0_0402_5% 40mil L34 AT24C02_SO8

2
1K_0402_1%
R910
B 4.7UH_PG031B-4R7MS_1.1A_20% @ B

1K_0402_1%
R911
LAN_XTALO R1225 2 57781@ 1 200_0402_1% LAN_XTALO_81 14 11 +1.2V_LAN_OUT 1 2
LAN_XTALI R1226 1 LAN_XTALI_81 XTALO/XTALO/XTALVDDH SR_LX
2 0_0402_5% 13
XTALI/XTALI/XTALO SR_VFB
8
57781@ <BOM Structure> 1 1
LAN_XTALO R1227 2 1 200_0402_1% 26

1
LAN_XTALI 57780@ RDAC C604 C605
0.1U_0402_16V4Z 10U_0805_10V4Z
LAN_XTALO 2 2

1 2 LAN_RDAC
R912 1.24K_0402_1% +3V_LAN
Y4 SPROM_CLK SPROM_DOUT
25MHZ_20PF_7A25000012 10 (EECLK) (EEDATA)
SR_VDDP
9
SR_VDD
1 2
1 1 On chip 1 0
1 1 C606 C607
R1228 1 2 0_0402_5% 7 4.7U_0603_6.3V6K 0.1U_0402_16V4Z AT24C02 1 1
C608 C609 <15> CLKREQ_LAN# CLK_REQ#/CLK_REQ#/DC
57781@
33P_0402_50V8J 33P_0402_50V8J 2 2
PAD

2 2
J11 @
2 1 JOPEN
49

+3VALW BCM57781A0KMLG_QFN48_6X6 57781@

+3V_LAN

+5VALW 60mil BCM57781A0KMLG_QFN48_6X6

1 3 Q126
D

U27
AO3414_SOT23-3
1

@ @
G
2

A R1324 A
33K_0402_5%

1 1 BCM57780
2

C583 C584 57780@

4.7U_0603_6.3V6K 0.1U_0402_16V4Z
2 2
2 Security Classification Compal Secret Data Compal Electronics, Inc.
1

D C919
FAST_BOOT# 2 2010/11/30 2011/08 Title
<37,44,45> FAST_BOOT# Issued Date Deciphered Date
G 0.1U_0402_16V4Z
Q127 S 1 @ Broadcom BCM57781
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2N7002_SOT23-3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
@ Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 38 of 63
5 4 3 2 1
 5 4 3 2 1

D
Close to T14 D

T49
C280 2 1 0.01U_0402_16V7K 1 24 MCT3 R320 2 1 75_0603_5%
TCT1 MCT1
MDI3+ 1:1 MDO3+ F3
2 23 LSE-200NX3216TRLF_1206-2
<38> MDI3+ TD1+ MX1+
1 2

MDI3- 3 22 MDO3- @
<38> MDI3- TD1- MX1-
C281 2 1 0.01U_0402_16V7K 4 21 MCT2 R321 2 1 75_0603_5%
TCT2 MCT2
MDI2+ 1:1 MDO2+ F4
5 20 LSE-200NX3216TRLF_1206-2
<38> MDI2+ TD2+ MX2+
1 2

MDI2- MDO2- @
<38> MDI2- 6 TD2- MX2- 19

C282 2 1 0.01U_0402_16V7K 7 18 MCT1 R318 2 1 75_0603_5%

TCT3 MCT3
MDI1+ 1:1 MDO1+ F5
8 17 LSE-200NX3216TRLF_1206-2
<38> MDI1+ TD3+ MX3+
1 2

MDI1- 9 16 MDO1- @
<38> MDI1- TD3- MX3-
C278 2 1 0.01U_0402_16V7K 10 15 MCT0 R319 2 1 75_0603_5%
C TCT4 MCT4 C
MDI0+ 1:1 MDO0+ F6
11 14 LSE-200NX3216TRLF_1206-2
<38> MDI0+ TD4+ MX4+
1 2 1
C129
Place close to TCT pin 1000P_1206_2KV7K
MDI0- MDO0- @ 2
<38> MDI0- 12 TD4- MX4- 13

LG-2446S-1

RJ45 Conn.
JRJ45
<38> LAN_SK# LAN_SK# R317 2 1 300_0402_5% 12
Green LED-
1
+3V_LAN 11
C279 GreenLED+
@68P_0402_50V8K MDO3- 8 16
2 PR4- SHLD2
15
C93 @ MDO3+ SHLD1
7
PR4+
2 1 470P_0402_50V7K
MDO1- 6
PR2-
For EMI.
MDO2- 5
PR3-
MDO2+ 4
B PR3+ B
MDO1+ 3
PR2+
ACTIVITY# MDO0- 2
PR1-
14
LAN_SK# MDO0+ SHLD2
1 13
PR1+ SHLD1
ACTIVITY# R574 2 1 300_0402_5% 10
<38> ACTIVITY# Yellow LED-
3

D68 1 +3V_LAN 9
Yellow LED+
AZC199-02S.R7G C/C SOT23
C610 SUYIN_100073HR012M25KZL
@ 68P_0402_50V8K ME@
2
@
1

ESD request

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 39 of 63
5 4 3 2 1
 5 4 3 2 1

D D

+3VS REMOTE1+
Close to VRAM
Close U20 SMSC thermal sensor 1

1
@ C

1
1
REMOTE1+
+3VS placed near by DDR R920
C621
100P_0402_50V8J
2
B
Q86
MMST3904-7-F_SOT323-3
2 E
10K_0402_5%

3
C622 @ REMOTE1-
2200P_0402_50V7K U29

2
2 REMOTE1-

1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 <15,23,45>
REMOTE1+ EC_SMB_DA2
REMOTE2+ 2
2 DP1 SMDATA 9 EC_SMB_DA2 <15,23,45>
REMOTE2+
near PCH and EC area
1 REMOTE1- 3 8 1
DN1 ALERT#

1
C625 @ C
C623 0.1U_0402_16V4Z REMOTE2+ 4 7 C624 2 Q87
2200P_0402_50V7K 1 DP2 THERM# 100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 REMOTE2- REMOTE2- 2 E
5 6

3
DN2 GND REMOTE2-

EMC1403-2-AIZL-TR_MSOP10
REMOTE1,2+/-:
C Address 1001_101xb Trace width/space:10/10 mil C

8/02 Change PN to SA000046C00, Fintek. Trace length:<8"

B B

FAN1 Conn
+5VS
J13
@ JUMP_43X39
JP4
1 1 2 2 +5VS_FANN 1 1
<45> EC_TACH 2 2
<45> EC_FAN_PW M 3 3
4 4
2 5 G5
6 G6
C626
10U_0805_10V4Z ACES_85205-04001
1 ME@

A A

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title
EMC1403_Thermal sensor/FAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 40 of 63
5 4 3 2 1
 A B C D E F G H

1 1

SATA HDD Conn.

JHDD1

2 2
1 GND
SATA_ITX_DRX_P1 2
<14> SATA_ITX_DRX_P1
<14> SATA_ITX_DRX_N1 SATA_ITX_DRX_N1 3
A+
A-
SATA ODD Conn.
4 GND
SATA_DTX_C_IRX_N1 C627 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 5
<14> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 C628 1 SATA_DTX_IRX_P1 B-
2 0.01U_0402_16V7K 6 B+
<14> SATA_DTX_C_IRX_P1 JODD1
7 GND
1
SATA_ITX_DRX_P2_CONN GND
8 <14> SATA_ITX_DRX_P2_CONN 2
VCC3.3 SATA_ITX_DRX_N2_CONN A+
+3VS 9 <14> SATA_ITX_DRX_N2_CONN 3
VCC3.3 A-
10 4
VCC3.3 SATA_DTX_C_IRX_N2 C629 1 SATA_DTX_IRX_N2 GND
11
GND 2 0.01U_0402_16V7K 5
B-
<14> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 C630 1 SATA_DTX_IRX_P2
12 2 0.01U_0402_16V7K 6
GND <14> SATA_DTX_C_IRX_P2 B+
13 7
@ J12 GND GND
14
+5V_HDD VCC5
+5VS 1 2 15
1 2 VCC5 R921 R710 1 0_0402_5%
16 2 8
VCC5 DP
17 +3VS 1 2 +5V_ODD 9
JUMP_43X79 GND 10K_0402_5% +5V
18 10
Reserved ODD_DA# +5V
19 1 2 11
GND <18,45> ODD_DA# R922 0_0402_5% MD
20 12 15
VCC12 GND GND
21 23 13 14
+5VS +3VS VCC12 GND GND GND
22 24
VCC12 GND
OCTEK_SLS-13PNAB
1 1 1 1 1 1 OCTEK_SAT-22HTAB ME@
@ ME@
C631 C632 C633 C634 C635 C636
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2

3 ODD Power Control 3

@ J6
1 2
1 2

JUMP_43X79 +5V_ODD
+5VS Q88

D
3 1
1

1
AO3413_SOT23-3
C637

G
2
R923 0.1U_0402_16V4Z
10K_0402_5% 2

C638 1

10U_0603_6.3V6M
C639
0.01U_0402_16V7K
1 R1110 2 1 2
100K_0402_5%

1
2

OUT
<19> ODD_EN 2
IN GND

Q89
DTC124EKAT146_SC59-3
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 41 of 63
A B C D E F G H
 5 4 3 2 1

HDA_RST_AUDIO# +5VDDA_CODEC
Adjustable Output
HDA_SYNC_AUDIO
EMI +3VS +3VDD_CODEC

J8 @
2 1 HDA_SDOUT_AUDIO R925
+5VS +5VAMP 1 2

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
JOPEN 1 @ 2 HDA_BITCLK_AUDIO CHB1608U301_0603 1 1 1 1

10U_0805_10V4Z
0.1U_0402_16V4Z
R924 U30 R926 33_0402_5%

C646

C647

C648

C649
1 1
+5VDDA_CODEC 5503@

C644

C645
2 1 1
CHB1608U301_0603 IN
5 1 1 1 1
OUT 2 2 2 2
2
GND 2 2

C650

C651

C652

C653
(FBMA-L10-160808-800LMT)

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
10U_0805_10V4Z

0.1U_0402_16V4Z
@1 @1 3 4 1 1
SHDN BYP 2 2 2 2 COPMAL PN:SM01000DI00
@ @ Place near Pin9
C640

G9191-475T1U_SOT23-5 @ @ @ @ Place near Pin25 Place near Pin38

C642

C643
0.01U_0402_16V7K

4.7U_0805_10V4Z
@ Place near Pin1 +5VDDA_CODEC +3VDD_CODEC +IOVDD_CODEC
2 2 2 2
C641

D
1 2 +3VS D
0_0402_5% R927

1 2 +1.5VS
0_0402_5% @ R928
4.75V LDO

10U_0805_10V4Z
0.1U_0402_16V4Z
1 1
+MIC1_VREFO_L

C654

C655
+3VS 2 2
Adjustable Output

25

38

9
U32
R929 U31

AVDD1

AVDD2

DVDD

DVDD_IO
2

2
2 1 1 +12VDD_CODEC
CHB1608U301_0603 IN D22
5
5503@ OUT D23
2
GND RB751V_SOD323 C_LINE_OUTL C660 LINE_OUTL
14 35 1 2 0.1U_0603_25V7K
10U_0805_10V4Z

0.1U_0402_16V4Z

LINE2-L LOUT1_L LINE_OUTL <43>

1 1 3 4 1 1 RB751V_SOD323 Internal Speaker

1
SHDN BYP C_LINE_OUTR C661 2 0.1U_0603_25V7K LINE_OUTR
C656

15 36 1 LINE_OUTR <43>
LINE2-R LOUT1_R
5503@ 5503@ G9091-120T11U_SOT23-5 Vendor recommend. 2.2K
C658

C659
0.01U_0402_16V7K

4.7U_0805_10V4Z

2
5503@ 16 39 (FBMA-L10-160808-800LMT)
2 2 5503@ 2 2 5503@ R930 R931 MIC2_L LOUT2_L
C657

2.2K_0402_5% 2.2K_0402_5% 17 41 COPMAL PN:SM01000DI00

MIC2_R LOUT2_R
Vendor recommend. 4.7u 23 48 SPDIF 1 2 SPDIF
SPDIF_OUT <43>

1
LINE1_L SPDIFO1 0_0402_5% R932
24 45
LINE1_R SPDIFO2
1.2V LDO for ALC5503 only.
1 2 4.7U_0603_6.3V6K 1 2 C662 MIC_EXTL_C 21 33 HPOUT_L 2 1
<43> EXT_MIC_L MIC1_L HPOUT_L HP_OUTL <43>
1K_0402_5% R933 63.4_0402_1% R934 Headphone
1 2 4.7U_0603_6.3V6K 1 2 C663 MIC_EXTR_C 22 32 HPOUT_R 2 1
<43> EXT_MIC_R MIC1_R HPOUT_R HP_OUTR <43>
1K_0402_5% R935 63.4_0402_1% R936
+3VS Add 64 ohm serial resistor to avoid ESD
external MIC PC_BEEP 12 37
BEEP_IN MONO_OUT
L66
1

HDA_BITCLK_AUDIO 6 46 DMIC_CLK_R 1 2
<14> HDA_BITCLK_AUDIO BITCLK DMIC_CLK1/2 DMIC_CLK <34>
R331
C 4.7K_0402_5% HDA_SDOUT_AUDIO 5 44 FBMA-10-100505-301T_0402 C
<14> HDA_SDOUT_AUDIO SDATA_OUT DMIC_CLK3/4
@
HDA_SDIN0 1 R938 2 SDATA_IN 8 20 (FBMA-10-100505-301T 0402 ) COPMAL PN:SM01000CY00
<14> HDA_SDIN0
2

33_0402_5% SDATA_IN LINE2_VREFO

HDA_RST_AUDIO# 11 18 For EMI request.
<14> HDA_RST_AUDIO# RESET# LINE1_VREFO
HDA_SYNC_AUDIO 10 28
<14> HDA_SYNC_AUDIO SYNC MIC1_VREFO +MIC1_VREFO_L
2
19
C822 DMIC_DATA MIC2_VREFO
<34> DMIC_DATA 2
GPIO0/DMIC_DATA1/2 CPVREF
100P_0402_50V8J 31 1 2
1 CPVREF C664 2.2U_0603_6.3V6K
@ 3
GPIO1/DMIC_DATA3/4 VREF
27
SENSEA VREF
MIC Sense <43> MIC_JD
20K_0402_1%
2 1
R939
13
SENSE A JDREF
40

10U_0805_10V4Z
0.1U_0402_16V4Z
Reserve for EMI. R939 place near pin13 <43> PLUG_IN 2 1 SENSEB 34
SENSE B
JDREF
1 2

1
Capless HP Sense 5.1K_0402_1% R940 CBN

C667

C665
30
EAPD_R CBN R942
1 2 47
R940 place near pin34 <45> EAPD
0_0402_5% R941 EAPD
29 CBP 1 2 20K_0402_1%
CBP C666 2.2U_0603_6.3V6K 2 1
43
NC

2
4 26
DVSS AVSS1
7 42
DVSS AVSS2 C913
+5VDDA_CODEC Place near Pin27 1 2
ALC272-VA2-GR_LQFP48_7X7 0.1U_0402_16V4Z
272@ C914
1 2
0.1U_0402_16V4Z
R943
Pin Assignment Location Function 1 2
0_0402_5%
36

56

35

52
1

U33 R944
LINE-OUT (Pin35/36) Internal Int Speaker 1 2
AVSS1

AVSS2

AVDD1

AVDD2
VDMIC-CLK

VDMIC-DATA

0_0402_5%

Capless HP-OUT (Pin32/33) External Headphone out R945

B
1 2 B
58 0_0402_5%
DMIC_CLK34 DMIC_CLK_R
DMIC_CLK12
60 LINE1 (Pin23/24) External Line in
30 R946
LINE1_R
29 51 1 2
LINE1_L MONO_OUT 0_0402_5%
MCLKO
63 MIC1(Pin21/22) External Mic in
21
LINE2_R HDA_BITCLK_AUDIO
20 8
LINE2_L BCLK HDA_SYNC_AUDIO
SYNC
12 MIC2(Pin16/17) Internal Internal Mic GND GNDA
MIC_EXTR_C 28
MIC_EXTL_C MIC1_R
27 59
MIC1_L SPDIF_OUT2 SPDIF
62
SPDIF_OUT +3VS
23
MIC2_R
PC Beep

1
22
MIC2_L HPOUT_L
43
CBP HPOUT_L HPOUT_R R947
39 42
CBN CBP HPOUT_R 10K_0402_1%
40
CBN

2
SENSEB 44 7 HDA_SDOUT_AUDIO 2 1C668
SENSEA SENSE B SDATA_OUT SDATA_IN
19 10
SENSE A SDATA_IN

1
1U_0603_10V4Z
C_LINE_OUTL 45
C_LINE_OUTR FRONT_L R948
46 5
FRONT_R GPIO1/DMIC-DATA34 DMIC_DATA 10K_0402_1%
4
GPIO0/DMIC-DATA12 +3VDD_CODEC C669 1U_0603_10V4Z
+MIC1_VREFO_L 38

2
VREFO-B
26 1 2PC_BEEP1 2 1 PC_BEEP
VREFO-E R949 20K_0402_5%
25
VREFO-F @
24 49 2 1
VREF VREFO-C VGPIO5/VOL-MUTE/TDO R322 @ 10K_0402_5%
37
VREF VGPIO4/VOL-UP/TCLK
50 2 1 EC Beep

1
47 R323 2 @ 1 10K_0402_5% C670 R950 C
VGPIO3/TDI/VOL-DN

2
34 R324 2 @ 1 10K_0402_5% <45> BEEP# 2 1 1 2 2 Q90
VGPIO2/TMS R326 @ 10K_0402_5% C94 B R951
32 2 1 1 2SC2411KT146_SOT23-3
VGPIO1 R328 @ 10K_0402_5% 560_0402_5% E
55 31 2 1 1 2 20K_0402_5%

3
SURR-R VGPIO0/TRST# R327 10K_0402_5% +12VDD_CODEC C671 1U_0603_10V4Z
53
SURR-L 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z @

1
CPVREF 41 2
JDREF CPVEE
54 64 C672
EAPD_R JDREF DVDD-12
61 33 R952
EAPD DVDD-12
A 16 <14> HDA_SPKR 2 1 1 2 A
DVDD-12
11 +IOVDD_CODEC
DVDD-IO

1
HDA_RST_AUDIO# 1U_0603_10V4Z 560_0402_5%
13 3 +3VDD_CODEC ICH Beep
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

PC_BEEP RESETB DVDD-33 D45 @

14 1 1 1 R953
PCBEEP IN
C673

C674

C675

RB751V_SOD323
10K_0402_5%
9 57

2
DVSS-IO NC 2 2 2
6 48
DVSS NC
18
NC
65 17
THERMAL PAD NC
15
NC
Place near Pin 16,33,64
Security Classification Compal Secret Data Compal Electronics,Ltd.
ALC5503_QFN64_9X9 2010/11/30 2011/08 Title
Issued Date Deciphered Date
5503@
HD Audio Codec_ALC272
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: Monday, November 29, 2010 Sheet 42 of 63
5 4 3 2 1
 5 4 3 2 1

EXT_MIC_L-2

EXT_MIC_R-2

wide 20MIL

2
D69
ZEN ROW PJDLC05C 3P C/A SOT23
JSPK1 L37
SPK_R1- 1 R1280 2 0_0805_5% SPK_R1-_CONN 1 EXT_MIC_L 1 2 EXT_MIC_L-2 @
1 <42> EXT_MIC_L
SPK_R2+ 1 R1281 2 0_0805_5% SPK_R2+_CONN 2

1
SPK_L1- R1282 0_0805_5% SPK_L1-_CONN 2 FBMA-L10-160808-121LMT_2P
1 2 3 3 GND 5
SPK_L2+ R1283 0_0805_5% SPK_L2+_CONN
1 2 4 4 GND 6 1 1 ESD request

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
D D
ACES_87213-0400G C676 @ C677
1 1 1 1
Audio Jack

C678

C679

C680

C681
ME@ 47P_0402_50V8J 10P_0402_50V8J
2 2

2 2 2 2 GNDA GNDA
@ @ @ @ L40 MIC IN
EXT_MIC_R 1 2 EXT_MIC_R-2
<42> EXT_MIC_R
FBMA-L10-160808-121LMT_2P
1 1
SPK_R1-_CONN SPK_L1-_CONN HP_OUTR C682 @ C683 JMIC1
47P_0402_50V8J 10P_0402_50V8J 1
SPK_R2+_CONN SPK_L2+_CONN HP_OUTL 2 2
2
6 GND 7
GNDA GNDA 3 GND 8

2
GND 9
<42> MIC_JD MIC_JD 4 GND 10
@ @ @
1 GNDA 5
D59 D60 D61
PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3 10P_0402_50V8J C684 SUYIN_010168FR006G576ZL
1

1
@ ME@
2
GNDA

220P_0402_50V7K 220P_0402_50V7K
Reserve for ESD request.

2
C C
C685 C686

1
Headphone

1
@ R954 @ R955
1K_0402_5% 1K_0402_5%

2
GNDA

JHP1
1 1
HP_OUTR L41 1 2 PR-OUT 2
<42> HP_OUTR 2
FBMA-L10-160808-121LMT_2P
HP_OUTL L42 1 2 PL-OUT 3
<42> HP_OUTL 3
FBMA-L10-160808-121LMT_2P
4 4

<42> PLUG_IN PLUG_IN 5 5

6 6
DRIVE
+5VS 7 7 IC
SPDIF_OUT 8 9
<42> SPDIF_OUT 8 GND
+3VALW 10
GND

1
1 SINGA_2SJ-A373-H03
+5VAMP C688

2
220P_0402_50V7K C687
ME@

2
B U34 R956 0.1U_0402_16V4Z B
W=40mil 2
10K_0402_5%
16 12 @
VDD NC
6

1
PVDD
15 PVDD AMP_OFF# R957 1
GAIN0 GAIN1
SHUTDOWN 19 2 EC_MUTE# EC_MUTE# <45>
0_0402_5% 0 0 6dB
GAIN0 2 GAIN0 SPK_L1-
0 1 10dB
LOUT- 8
GAIN1 3 GAIN1
1 0 15.6dB
14 SPK_R1-
ROUT- 1 1 21.6dB
4 SPK_L2+
LOUT+
LINE_OUTL C924 1
20mil
<42> LINE_OUTL 2 0.033U_0402_16V7K LIN 5 LIN- ROUT+ 18 SPK_R2+ +5VAMP +5VAMP

LINE_OUTR C925 1 2 0.033U_0402_16V7K RIN 17

<42> LINE_OUTR RIN-
GND 1

2
9 LIN+ GND 11
1

R960 R961 13 @ R962 R963

GND 100K_0402_1% 100K_0402_1%
7 RIN+ GND 20
10K_0402_5%

10K_0402_5%

1 GND 21
@ @

2 1

2 1
C691 10 1 GAIN0 GAIN1
2

BYPASS
0.1U_0603_25V7K
1
2 C695 R965 R966
C692 TPA6017A2PW PR_TSSOP20 4.7U_0805_10V4Z 100K_0402_1% 100K_0402_1%
2 @
0.1U_0603_25V7K
2

1
A A

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title
AMP,Audio speaker CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KIWB1/B2_LA4601P
Date: Monday, November 29, 2010 Sheet 43 of 63
5 4 3 2 1
 5 4 3 2 1

+CRD_POWER

(20mil)
+CRD_POWER
600mA
1 JREAD1 (20mil)
D C696 22 11 D
XD-VCC SD4-VDD
MS9-VCC 18
10U_0805_10V4Z~D MDIO0 30 (20mil)
2 MDIO1 XD10-D0 SD_CLK
29 9 1

0.1U_0402_16V4Z
MC74VHC1G08DFT2G SC70 5P MDIO2 XD11-D1 SD5-CLK MDIO0
Close to CONN. 28 4 1

0.1U_0402_16V4Z
XD12-D2 SD7-DAT0

3
MDIO3 MDIO1

C700
1 27 3

0.1U_0402_16V4Z
DEVICE_RST# MDIO8 XD13-D3 SD8-DAT1 MDIO2

C701
1 26 21

G
<19,37,38> DEVICE_RST# A XD14-D4 SD9-DAT2 2
CARD_RST# MDIO9 MDIO3

C697
Y 4 25 XD15-D5 SD1-DAT3 19
BUF_PLT_RST# MDIO10 MDIO4 2
<18,23,37,38,45,49> BUF_PLT_RST# 2 B 24 XD16-D6 SD2-CMD 16
2

P
@ MDIO11 23 1 SD_CD#
U59 XD17-D7 SD-CD MDIO6
2

5
MDIO4 SD-WP
33 XD07-WE
MDIO6 32 6
MDIO14 XD08-WP SD6-VSS
34 XD06-ALE SD3-VSS 13
XD_CD# 39
+3VS MDIO13 XD01-CD
38 XD02-R/B
MDIO12 37
XD_CLK XD03-RE MS_CLK
1 2 36 XD04-CE MS8-SCLK 17
R1343 0_0402_5% MDIO7 35 10 MDIO0
XD05-CLE MS4-DATA0 MDIO1
MS3-DATA1 8
31 12 MDIO2
XD GND MS5-DATA2 MDIO3
40 XD GND MS7-DATA3 15
U35 14 MS_CD#
MS6-INS MDIO4
MS2-BS 7
CLK_PCIE_CARD_PCH# 3 5 +1.8VS_CARD 108mA 5
<15> CLK_PCIE_CARD_PCH# APCLKN APVDD MS1-VSS
CLK_PCIE_CARD_PCH 4 10 (20mil) 41 20
<15> CLK_PCIE_CARD_PCH APCLKP APV18 SD CD/WP GND MS10-VSS
NC/TAV33 36 42 SD CD/WP GND
<15> PCIE_PTX_C_DRX_N5 9 APRXN
8 19 +3VS_CARD T-SOL_144-1300002600_NR
<15> PCIE_PTX_C_DRX_P5 APRXP DV33
DV33 20 (40mil) 45mA ME@
0.1U_0402_16V7K 2 1 C698 PCIE_PRX_C_DTX_N5 11 44
<15> PCIE_PRX_DTX_N5 APTXN DV33
0.1U_0402_16V7K 2 1 C699 PCIE_PRX_C_DTX_P5 12 18 +1.8VS_CARD
C <15> PCIE_PRX_DTX_P5 APTXP DV18 C
DV18 37 (20mil)
X7R type 1 R968 2 APREXT 7
12K_0402_1% APREXT
(12mil) MDIO0 48 MDIO0
47 MDIO1 @
MDIO1 MDIO2 SD_CLK R1009 @ C703 1
43 SDDV/MDIO4 MDIO2 46 2 1 2
1 39 45 MDIO3
TXIN/NC MDIO3 MDIO4 100_0402_5% 100P_0402_50V8J
MDIO6/4 41
C702 42 MDIO5_R 1 2 R969 SD_CLK @
2.2U_0603_6.3V6K MDIO5 MDIO6 0_0402_5% MS_CLK R1036 @ C765 1
2 JMB389 G/MDIO6
MDIO7
24
40 MDIO7 1 2 R1014 MS_CLK
2 1 2

29 MDIO8 0_0402_5% 100_0402_5% 100P_0402_50V8J

BUF_PLT_RST# MDIO8
2 R970 1 CARD_RST# 1 XRSTN MDIO9 28 MDIO9 1 2 R1029 XD_CLK @
<18,23,37,38,45,49> BUF_PLT_RST# GND 2 27 MDIO10 0_0402_5% XD_CLK R1051 2 @ 1 C821 1 2
100_0402_5% @ XTEST MDIO10 MDIO11
1 MDIO11 26
C704 25 MDIO12 100_0402_5% 100P_0402_50V8J
<15> CPPE# MDIO12
0.1U_0402_16V4Z 13 23 MDIO13 Close to IC
XD_CD# CPPE_N MDIO13 MDIO14
14 CR1_CD2N MDIO14 22
2
Close to connector for EMI request.
NC/SPI_SCK 30
MS_CD# 15 33
SD_CD# CR1_CD1N NC/SPI_CSN
Reserve RC for old IC ESD problem 16 CR1_CD0N NC/SPI_SO 34
JMB389 has internal RC. NC/SPI_SI 35

17 CR1_PCTLN
6 +1.8VS_CARD +1.8VS_CARD +3VS_CARD
APGND
+CRD_POWER NC/GND 31
21 CR1_LEDN NC/GND 32
NC/GND 38

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1

1000P_0402_50V7K

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
JMB389-LGAZ0C_LQFP48_7X7 C709 C710
B B

C705

C706

C707

C708

C711

C712

C713

C714
0.1U_0402_16V4Z 10U_0805_10V4Z
LQFP48 Package 2 2 2 2 2 2 2 2 2 2
@ Close to pin 37 Close to pin 18 @

R973
Close to pin10
+3VS
Close to pin 19,20 Close to pin 36
2 1 Close to pin5->1000P->0.1u->10u
Close to pin 44
0_0603_5%
+3VS_CARD +CRD_POWER

1 3 Q128
D

+5VS
AO3414_SOT23-3 XD_CD# MDIO6 1 R971 2
@ 1K_0402_5%
G
2
1

@
R1325 SD_CD# MDIO13 1 R972 2
33K_0402_5% 1K_0402_5%
1 1
C715 C716
2

0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ 2 @ 2
2
1

D C920
FAST_BOOT# 2
<37,38,45> FAST_BOOT#
G 0.1U_0402_16V4Z
Q129 S 1 @
3

2N7002_SOT23-3
@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Carder JMB389
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 44 of 63
5 4 3 2 1
 +3VALW
10/02 Change to SM010005500. +EC_AVCC +3VALW
1 1 1 1 1 1

2
0.1U_0402_16V4Z
C717

0.1U_0402_16V4Z
C718

0.1U_0402_16V4Z
C719

0.1U_0402_16V4Z
C720

1000P_0402_50V7K
C723

1000P_0402_50V7K
C724
L43 1 2
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603 2 1 R974
@ 10K_0402_5%
C721 2 2 2 2 2 2
0.1U_0402_16V4Z C722

111
125
1000P_0402_50V7K

22
33
96

67

1
9
1 2 1 ECAGND 2 U36 BRDID
L44 FBM-11-160808-601-T_0603

VCC
VCC
VCC
VCC
VCC
VCC

AVCC

2
R977
2 1 @ 10K_0402_5%
TP_LED# LED_KB_PWM <50>
1 21 0_0402_5% R1321
<19> GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP# TP_LED# <47>
<19> KB_RST# 2 23 BEEP# <42>

1
KBRST#/GPIO01 BEEP#/PWM2/GPIO10 LED_KB_PWM_R
<14> SERIRQ 3 26 2 1 PCH_DPWROK <16>
SERIRQ# FANPWM1/GPIO12 ACOFF 0_0402_5% R1333
<14,37> LPC_FRAME# 4 27 ACOFF <52,54>
LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13
<14,37> LPC_AD3 5 @
LPC_AD2 LAD3
<14,37> LPC_AD2 7
LAD2 PWM Output +3VS 6/19 Add BRDID
LPC_AD1 8 63 BATT_TEMP
<14,37> LPC_AD1 LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 SG_SW# BATT_TEMP <53>
LAD0 LPC & MISC
10 64 +3VS
<14,37> LPC_AD0 BATT_OVP/AD1/GPIO39 SG_SW# <46>

1
2 1 2 1 65 ADP_I <53,54>
ADP_I/AD2/GPIO3A
@ C726 22P_0402_50V8J @ R976 10_0402_5%
<18> CLK_PCI_LPC 12
PCICLK AD Input AD3/GPIO3B
66 IMVP_IMON <60>

1
13 75 BRDID R1316
<18,23,37,38,44,49> BUF_PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42
1 2 37 76 10K_0402_5%
+3VALW ECRST# SELIO2#/AD5/GPIO43
R978 47K_0402_5% EC_SCI# 20 11/12 update to +5VALW R975
<19> EC_SCI#

2
SG_SW_LED# SCI#/GPIO0E ESB_INT 10K_0402_5%
2 <47> SG_SW_LED# 38
CLKRUN#/GPIO1D BATT_LRN# @
68 BATT_LRN# <53>

2
C725 DAC_BRIG/DA0/GPIO3C FAST_BOOT# +5VALW EC_FAN_PWM
EN_DFAN1/DA1/GPIO3D 70 FAST_BOOT# <37,38,44>
0.1U_0402_16V4Z DA Output 71 IREF
1 KSI0 IREF/DA2/GPIO3E IREF <54>
55 72 +3VALW
KSI1 KSI0/GPIO30 DA3/GPIO3F CHGVADJ <54>
56 KSI1/GPIO31
KSI2 57 EC_MUTE# R979 1 2 10K_0402_5% +5VS
KSO[0..15] KSI3 KSI2/GPIO32
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# <43>
<46> KSO[0..15] KSI4 59 84 USB_ON# USB_ON# R980 1 2 10K_0402_5% TP_CLK R981 1 2 4.7K_0402_5%
KSI[0..7] KSI5 KSI4/GPIO34 PSDAT1/GPIO4B ESB_INT USB_ON# <48,49>
60 KSI5/GPIO35 PSCLK2/GPIO4C 85 ESB_INT <50>
<46> KSI[0..7] KSI6 61 PS2 Interface 86 TP_DATA R982 1 2 4.7K_0402_5%
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK CMOS_OFF# <34>
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK <46>
+3VALW KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <46>
R983 1 2 47K_0402_5% KSO1 KSO1 40 KSO1/GPIO21
KSO2 41 BATT_TEMP 1 2
KSO2/GPIO22
R984 1 2 47K_0402_5% KSO2 KSO3 42 KSO3/GPIO23 SDICS#/GPXOA00 97 ECR_EN
ECR_EN <34>
C727 100P_0402_50V8J
KSO4 43 98 CE_EN ACIN 1 2
KSO4/GPIO24 SDICLK/GPXOA01 CE_EN <34>
KSO5
KSO5/GPIO25 Int. K/B
+3VALW C728 100P_0402_50V8J
ENE UPDATE 08/10/21 KSO6
44
45 KSO6/GPIO26 Matrix
SDIDO/GPXOA02
SDIDI/GPXID0
99
109 LID_SW# ME_FLASH <14>
LID_SW# <46>
KSO7 46 SPI Device Interface FRD#SPI_SO 2 1
+3VS +3VALW KSO8 KSO7/GPIO27 100K_0402_1%@ R985
R986 47 KSO8/GPIO28
KSO9 48 119 FRD#SPI_SO
KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO <47>
EC_SMB_CK1 KSO10 49 120 FWR#SPI_SI FSEL#SPICS# 2 1
KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK FWR#SPI_SI <47>
R990
2.2K_0402_5% 50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 SPI_CLK <47>
100K_0402_1%@ R987
KSO12 51 128 FSEL#SPICS#
EC_SMB_DA1 KSO13 KSO12/GPIO2C SPICS# FSEL#SPICS# <47>
R988 R989 52
2.2K_0402_5% KSO14 KSO13/GPIO2D
2.2K_0402_5% 2.2K_0402_5% 53 KSO14/GPIO2E
KSO15 54 73 H_PROCHOT_EC
KSO15/GPIO2F CIR_RX/GPIO40 H_PECI_R R991 1
81 74 2 43_0402_1% H_PECI <6,19>
R1285
EC_SMB_CK2 KSO16/GPIO48 CIR_RLC_TX/GPIO41 0_0402_5%
82 89 FSTCHG <54>
EC_SMB_DA2 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 CHARGE_LED0# VR_HOT#
90 CHARGE_LED0# <47> <53,60> VR_HOT# 2 1 H_PROCHOT# <6>
BATT_CHGI_LED#/GPIO52 CAPS_LED#
1 1 91 CAPS_LED# <50>
CAPS_LED#/GPIO53

1
EC_SMB_CK1 PWR_LED# D
@ @
<53> EC_SMB_CK1 77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
92 PWR_LED# <47,50>
C729 C730 EC_SMB_DA1 78 93 CHARGE_LED1# 2
<53> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 CHARGE_LED1# <47>
100P_0402_50V8J 100P_0402_50V8J EC_SMB_CK2 79 SM Bus 95 SYSON 11/15 Add inverter, G Q135
2 2 <15,23,40> EC_SMB_CK2 EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 SYSON <49,51,56>
80 121 S 2N7002_SOT23
<15,23,40> EC_SMB_DA2 VR_ON <60> H_PROCHOT#_EC changed to

3
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 ACIN
127 ACIN <16,54>
AC_IN/GPIO59 H_PROCHOT_EC high active.
R1293
6 100 0_0402_5%
<16> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_LID_OUT# EC_RSMRST# <16> H_PROCHOT_EC
+3VS 14 101 2 1
<16> SLP_S5# EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON EC_LID_OUT# <15>
15 102 @ @
<19> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <50,55>
CPU1.5V_S3_GATE 16 103 ESB_RST# D46 RB751V_SOD323
<10> CPU1.5V_S3_GATE LID_SW#/GPIO0A EC_SWI#/GPXO06 ESB_RST# <50>
1

ESB_CLK 17 104 PCH_POK_EC 1 2 PCH_POK

<50> ESB_CLK SUSP#/GPIO0B ICH_PWROK/GPXO06 PCH_POK <16>
ESB_DAT 18 GPO 105 BKOFF#
<50> ESB_DAT SUSWARN# PBTN_OUT#/GPIO0C BKOFF#/GPXO08 RF_LED# BKOFF# <34>
R992
<16> SUSWARN# 19
EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09
106 RF_LED# <47> 1 2 1 2 +3VS
10K_0402_5% INVT_PWM 25 107 PCH_APWROK <16> R993 0_0402_5% R994 10K_0402_5%
<34> INVT_PWM EC_TACH EC_THERM#/GPIO11 GPXO10
<40> EC_TACH 28 108 SA_PGOOD <57> @
2

EC_TACH ODD_DA# FAN_SPEED1/FANFB1/GPIO14 GPXO11

<18,41> ODD_DA# 29
EC_TX_P80_DATA FANFB2/GPIO15
<37,46> EC_TX_P80_DATA 30
EC_RX_P80_CLK EC_TX/GPIO16
<37,46> EC_RX_P80_CLK 31 110 SLP_S4# <16>
EC_RX/GPIO17 PM_SLP_S4#/GPXID1 +3VALW
<50> ON/OFF# 32 112 ENBKL <34>
EC_FAN_PWM ON_OFF/GPIO18 ENBKL/GPXID2
<40> EC_FAN_PWM 34 114 EAPD <42>
PWR_LED#/GPIO19 GPXID3 NOVO#
<50> NUM_LED# 36
NUMLED#/GPIO1A GPI GPXID4
115 NOVO# <50>

2
116 SUSP#
GPXID5 PBTN_OUT# SUSP# <10,51,56,58,59>
117 R995
GPXID6 PBTN_OUT# <16>
118 10K_0402_5%
EC_RTCX1 122 GPXID7
SUSCLK_R XCLK1
<16> SUSCLK 2 1 123 124

1
0_0402_5% R996 XCLK0 V18R
1
AGND
GND
GND
GND
GND
GND
100K_0402_5%

C731
2

1 4.7U_0805_10V4Z 2 1
R139 C815 KB930QF A0 LQFP 128P 2 0_0402_5% R997 LAN_WAKE# <38>
11
24
35
94
113

69

20P_0402_50V8
2 1
2
ECAGND

0_0402_5%@ R999
1

EC_PME# 1 3

S
PCI_PME# <18>
Q91@
2N7002_SOT23

G
2
+3VS +3VALW
R1317
EC_RTCX1 1 2 ESB_CLK
4.7K_0402_5%
1 R1000 2 SUSCLK_R R1318
20M_0603_5% 1 2 ESB_DAT
@ 4.7K_0402_5%
32.768KHZ_12.5PF_1TJS125DJ4A420P

Y5
1

4
27P_0402_50V8J

27P_0402_50V8J

1 1
OUT
IN

C732 C733
2 2
NC

NC

Security Classification Compal Secret Data Compal Electronics, Inc.

2

@ @ Issued Date 2010/11/30 Deciphered Date 2011/08 Title

@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
6/15 add XTAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
PIQY0 LA6881P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 45 of 63
 5 4 3 2 1

JP5
KSI1 1
INT_KBD Conn. KSI7
KSI6
2
1
2 EC DEBUG PORT
3 3
KSI[0..7] KSO9 4
KSI[0..7] <45> 4
KSI4 5
KSO[0..15] KSI5 5
D KSO[0..15] <45> 6 6 D
KSO0 7
KSI2 7 JP6
8 8
KSI3 9 +3VALW 1
KSO2 C734 1 9 1
2 @ 100P_0402_50V8J KSO1 C735 1 2 @ 100P_0402_50V8J KSO5 10 10 <37,45> EC_TX_P80_DATA
EC_TX_P80_DATA 2 2
KSO1 11 EC_RX_P80_CLK 3
11 <37,45> EC_RX_P80_CLK 3
KSO15 C736 1 2 @ 100P_0402_50V8J KSO7 C737 1 2 @ 100P_0402_50V8J KSI0 12 4
KSO2 12 4
13 13
KSO6 C738 1 2 @ 100P_0402_50V8J KSI2 C739 1 2 @ 100P_0402_50V8J KSO4 14 ACES_85205-0400
KSO7 14
15 15 ME@
KSO8 C740 1 2 @ 100P_0402_50V8J KSO5 C741 1 2 @ 100P_0402_50V8J KSO8 16
KSO6 16
17 17
KSO13 C742 1 2 @ 100P_0402_50V8J KSI3 C743 1 2 @ 100P_0402_50V8J KSO3 18
KSO12 18
19 19
KSO12 C744 1 2 @ 100P_0402_50V8J KSO14 C745 1 2 @ 100P_0402_50V8J KSO13 20
KSO14 20
21 21
KSO11 C746 1 2 @ 100P_0402_50V8J KSI7 C747 1 2 @ 100P_0402_50V8J KSO11 22
KSO10 22
23 23
KSO10 C748 1 2 @ 100P_0402_50V8J KSI6 C749 1 2 @ 100P_0402_50V8J KSO15 24 24
25 G1
KSO3 C750 1 2 @ 100P_0402_50V8J KSI5 C751 1 2 @ 100P_0402_50V8J 26

KSO4 C752 1 2 @ 100P_0402_50V8J KSI4 C753 1 2 @ 100P_0402_50V8J

G2
ACES_85202-24051
Lid Switch
KSI0 C754 1 2 @ 100P_0402_50V8J KSO9 C755 1 2 @ 100P_0402_50V8J ME@
KSO0 C756 1 2 @ 100P_0402_50V8J KSI1 C757 1 2 @ 100P_0402_50V8J
+3VALW 1 2 +VCC_LID R1003 1 2 100K_0402_5%
R1002 0_0402_5%
C C
CONN PIN define need double check

2
5711ACDL-M3T1S SOT-23

VDD
1
OUTPUT 3 LID_SW # <45>
C758
To TP/B Conn. 0.1U_0402_16V4Z 2

GND
2
+5VS J14 C759
@ JUMP_43X39 U37 10P_0402_50V8J

1
1
1 1 2 2
C760

0.1U_0402_16V4Z
JP7
+5VS_TP 1
<45> TP_CLK
TP_CLK
TP_DATA
2
1
2 +3VALW
Kill Switch
<45> TP_DATA 3 3
4 100K_0402_5% LSSM12-P-V-T-R_3P
1
@
C761
1
@
C762
4
2 R1004 1 3 3
Kill
100P_0402_50V8J 100P_0402_50V8J
5
6
GND
2
STATUS
2 2 GND <14> KILL_SW # 2
KILL_SW# 1,2(LOW) OFF
3

JOINT_F1017W R-S-04P
ME@
CONN PIN define need double check @
1 1 2,3(HI) ON
B D58 B
PACDN042Y3R_SOT23-3 SW 1
1

+3VALW SW 3

6
100K_0402_5%

6
2 R1286 1 1 1 1 2 3 4
SG_SW # 2
<45> SG_SW # 2
SG_SW#
3 3

4 4

5 5
SSS-12L-V-T-R_4P
A B
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 46 of 63
5 4 3 2 1
 FOR EC 128KB SPI ROM
(150mil PACKAGE)
P/N : SA00002C100
SPI_CLK_R
+3VALW
20mils

2
1 @

1
C763 R330
0.1U_0402_16V4Z R1005 0_0402_5%
2 10K_0402_5%

1
Changed to BEAD for EMI.

2
U38
<45> FSEL#SPICS#
FSEL#SPICS#
Close to EC. Colse to EC
1 8 1
FRD#SPI_SO R1006 1 SPI_SO CS# VCC HOLD#
<45> FRD#SPI_SO 2 15_0402_5% 2
DO HOLD#
7 R1007 FBMA-10-100505-101T 0402
3 6 SPI_CLK_R 1 2 SPI_CLK C764
WP# CLK SPI_CLK <45>
4 5 10P_0402_50V8J
GND DIO 2
MX25L1005AMC-12G SOP SPI_SI_EC 1 2 15_0402_5% FWR#SPI_SI @
FWR#SPI_SI <45>
R1008

EMI
LED
LED1
<45,50> PWR_LED# 1 2 2 1 +5VALW
300_0402_5% R1010
12-21SYGCS530-E1S155TR8_W
White
Amber LED2
BATT_LOW_LED# 3
<45> CHARGE_LED1#
1 2 1 +5VALW
470_0402_5% R1012
<45> CHARGE_LED0# 2
BATT_CHG_LED# FD1 FD2 FD3 FD4
White
1 1 1 1
12-22-S2ST3D-C30-2C_WHI-ORG

D47
@ LED3
A:H_2P8 *9
<37> WLAN_LED# 1 2 1 2 2 1 +5VS
300_0402_5% R1013
RB751V_SOD323 12-21SYGCS530-E1S155TR8_W H1 H2 H3 H4 H5 H6 H7 H8 H12
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
D57
@ White
BT_LED# 1 2

1
RB751V_SOD323

H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8

<45> RF_LED# 1 2
R1111 0_0402_5%
C:H_3P2 X5
LED4 H10 H11
<45> SG_SW_LED# 1 2 2 1 +5VS HOLEA HOLEA
300_0402_5% R1026
12-21SYGCS530-E1S155TR8_W

1
LED5
D:H_3P8 *3
H13 H14 H15 H_3P2 H_3P2
<45> TP_LED# 1 2 2 1 +5VS
300_0402_5% R1322 HOLEA HOLEA HOLEA H20 H18
12-21SYGCS530-E1S155TR8_W HOLEA HOLEA

1
+5VALW

1
BT MODULE CONN H_3P8 H_3P8 H_3P8
1

H_3P2 H_3P2
BT@ R1022
100K_0402_5% H_6P0N *1
C775
0.1U_0402_16V4Z
F:H_3P8 *3 H_4P5X3P0N
2

1 R1025 2 1 2 H16 H21 H19 H17 H22 H23

100K_0402_5% HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

BT@ BT@
+3VS_BT
OUT

1
2 +3VS Q93 AO3413_SOT23-3 H_6P0N H_4P5X3P0N H_4P5X3P0N
<19,37> BT_OFF# IN Q92 30mils H_3P8
GND

H_3P8 H_3P8
S

DTC124EKAT146_SC59-3 3 1
BT@ 1
BT@ 0.1U_0402_16V4Z H9
3

C776 HOLEA
G
2

BT@
BT_LED# 2
Q94 JP8

1
1

DTC124EKAT146_SC59-3 1
BT@ 1 H_3P2N
2
OUT

USB20_P13 2
<18> USB20_P13 3
USB20_N13 3
<18> USB20_N13 4 4
BTON_LED
IN 2 BT_ACTIVE
5 5 G1 7
<37> BT_ACTIVE 6 8
GND

6 G2
ACES_87213-0600G
ME@
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/EC SPI ROM/BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 47 of 63
 A B C D E

Right USB Conn.(Cable)

+USB_VCCD
W=80mils JUSB1
1 1
R1109 1 @ 0_0402_5% USB20_N0_C

150U_B2_6.3VM_R35M
1 <18> USB20_N0 2 2 2

C911
1 R1108 1 2 0_0402_5% USB20_P0_C 3
+ <18> USB20_P0 3
@ 4
C766 4
5 G5

2
470P_0402_50V7K WCM-2012-900T_4P

PJDLC05_SOT23-3
6 G6
+5VALW +USB_VCCB 2 2 USB20_N0 4 3 USB20_N0_C D49
U39 4 3 @ ACES_85205-04001
1 1
1 8 E-SATA COMBO ME@
C767 0.1U_0402_16V4Z GND OUT USB20_P0 USB20_P0_C
2 IN OUT 7 1 1 2 2
2 1 3 IN OUT 6
USB_ON#_R 4 5 USB_OC0# L64
EN OC# USB_OC0# <18>
APL3510BKI_SO8 1
DVT change to SM070000I00 for EMI request.

1
Low Active C768
@ 1000P_0402_50V7K
<45,49> USB_ON# 2 1
R1289 0_0402_5% 2 +5VALW +USB_VCCD
U56
1 GND OUT 8 RIGHT USB PORT
C909 0.1U_0402_16V4Z 2 7
IN OUT
2 1 3 IN OUT 6
<45,49> USB_ON# USB_ON# 4 5 USB_OC0#
EN OC# USB_OC0# <18>
APL3510BKI_SO8 1
Low Active C910
@ 1000P_0402_50V7K
2

USB20_N1_C
USB20_P1_C +USB_VCCB
2
3
ESATA and USB Conn. 2
2
PJDLC05_SOT23-3

D50 W=80mils
@

220U_6.3V_M
1
1

C769
+ C770 JESAT1
470P_0402_50V7K 1 USB
R1106 VBUS
1 @ 2 0_0402_5% USB20_N1_C 2
2 2 <18> USB20_N1
<18> USB20_P1
R1107 1 2 0_0402_5% USB20_P1_C 3
D-
USB
1

@ D+
4 GND
A+ = RXP
5 GND ESATA
SATA_ITX_DRX_P4 R1015 1 ESATA@2 0_0402_5% SATA_ITX_DRX_P4_R 6
<14> SATA_ITX_DRX_P4
<14> SATA_ITX_DRX_N4
ESATA@
SATA_ITX_DRX_N4 R1016 1
ESATA@
2 0_0402_5% SATA_ITX_DRX_N4_R 7
A+
A-
A- = RXN
8 GND SHIELD 12
SATA_DTX_C_IRX_N4 0.01U_0402_16V7K 2 1 C771 SATA_DTX_IRX_N4 R1017 1 ESATA@2 0_0402_5% SATA_DTX_IRX_N4_R 9 13
<14> SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4 C772 SATA_DTX_IRX_P4 R1018 0_0402_5% SATA_DTX_IRX_P4_R B- SHIELD
<14> SATA_DTX_C_IRX_P4
2 1 1 2 10 B+ SHIELD 14
0.01U_0402_16V7K ESATA@ ESATA@ 11 15
GND SHIELD
7/30 update to port4
USB20_P1
WCM-2012-900T_4P
USB20_P1_C
<19> ESATA_DET#
B- = TXN
4 4 3 3

USB20_N1 USB20_N1_C
B+ = TXP
TAIW_EU131-117CRL-TW
1 1 2 2
L65
ME@
3 DVT change to SM070000I00 for EMI request. 3

+3VS +3VS

0.01U_0402_16V7K
0.1U_0402_16V4Z
1 2

2
R1019
4.7K_0402_5% C773 C774 R1020 R1021
@ @ 4.7K_0402_5% 4.7K_0402_5%
@2 1 @ @

1
U40

1
7/30 update to port4 7 EN VCC 6
VCC 10
SATA_ITX_DRX_P4 1 16
SATA_ITX_DRX_N4 RX_0P VCC
2 RX_0N VCC 20

SATA_DTX_IRX_P4 5 9
SATA_DTX_IRX_N4 TX_1P D0
4 TX_1N D1 8

2
3 15 SATA_ITX_DRX_P4_R
GND TX_0P SATA_ITX_DRX_N4_R R1023 R1024
13 GND TX_0N 14
17 GND 0_0402_5% 0_0402_5%
18 12 SATA_DTX_IRX_N4_R @
GND RX_1N SATA_DTX_IRX_P4_R @
19 11

1
GND RX_1P
21 PAD
4 4
SN75LVCP412RTJR_QFN20_4X4
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB ports/E-SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 48 of 63
A B C D E
 5 4 3 2 1

+3V +1.05VR
DVT, USB3.0 Choke changed to SM070001U00
For EMI request For EMI request
+1.5V to +1.05V Transfer Close to U3.D7 Close to U3.P13 USB30@ USB30@ USB30@ USB30@ USB30@ USB30@ USB30@ L68 USB30@ L69 USB30@
+5VALW +1.5V +5VALW +1.05V

C877

C870

C866

C871

C872

C878

C879

C880

C881

C882

C867

C873

C883

C884

C885
U51 U3TXDP2_L 2 1 U3TXDP2 U3TXDP1_L 2 1 U3TXDP1
+3VA +3VA 2 1 2 1
1U_0603_10V6K

10U_0603_6.3V6M
USB30@
+1.5V
C863

C864
1 1 6 VCNTL
5 3 USB30@ USB30@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 U3TXDN2_L 3 4 U3TXDN2 U3TXDN1_L 3 4 U3TXDN1
VIN VOUT USB30@ USB30@ USB30@ USB30@ USB30@ USB30@ USB30@ USB30@ 3 4 3 4
9 VIN VOUT 4
+5VALW

.1U_0402_16V7K
C865

0.01U_0402_16V7K
C874

8P_0402_50V8D

.1U_0402_16V7K
C875

0.01U_0402_16V7K
C869

8P_0402_50V8D
USB30@ 1 1 1 @ 1 1 1 @ WCM-2012-900T_4P WCM-2012-900T_4P
2 2

C868

C876
SYSON 8 EN 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

10U_0603_6.3V6M
2 1 7 2 1 R1149 2 L70 USB30@ L71 USB30@

GND
POK FB

C886

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

.1U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

.1U_0402_16V7K

0.01U_0402_16V7K

.1U_0402_16V7K

0.01U_0402_16V7K

.1U_0402_16V7K

0.01U_0402_16V7K

.1U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K
USB30@ R1150 5.1K_0402_1% 10K_0402_1% 1 U3RXDP2_L 2 1 U3RXDP2 U3RXDP1_L 2 1 U3RXDP1
2 1 2 1

1
USB30@ 2 2 2 2 2 2
USB30@
Vout=0.8(1+10K/32.4K) APL5930KAI-TRG_SO8 R1151 USB30@

1
D U3RXDN2_L 3 D
1.042 ~ 1.0469 ~ 1.0519V 32.4K_0402_1% USB30@ 4 U3RXDN2 U3RXDN1_L 3 4 U3RXDN1
USB30@ 2 USB30@ 3 4 3 4
Spec: 0.9975 ~ 1.05 ~ 1.1025 WCM-2012-900T_4P WCM-2012-900T_4P

2
L72 L73
7K for customer request, can use other kind U2DN2_L 2 1 U2DN2 U2DN1_L 2 1 U2DN1
2 1 2 1
R1152
of capacitor, like Y5V.
0_0805_5% U2DP2_L 3 4 U2DP2 U2DP1_L 3 4 U2DP1
+3VALW to +3V Transfer +3V
+3V
+1.05V 1 2 +1.05VR +3VA
+3V +3VA
3 4 3 4
USB30@ L74 WCM-2012-900T_4P WCM-2012-900T_4P
+3VALW U52 USB30@ J15 BLM18AG601SN1D_2P For EMI request, L72, L73 change to SM070000I00
@ JUMP_43X39 U43 1 2
3 1 +3V_J 1 1 USB30@ U3TXDP2_L 1 R1153 2U3TXDP2 U3TXDN1_L 1 R1154 2 U3TXDN1
2 2 1

D10

H11
E11
E12

K11
K12

P13
VIN VOUT

F13
F14

L10

L13
L14
SYSON

G3
G4

N4
N5
N6

C4
C5
C6
C7
D5

C8
C9
D8
D9

H3
H4

D7
C887 @ 0_0402_5% @ 0_0402_5%

P3

E3
E4
F3
4 5

L9

L5

L8
<45,51,56> SYSON VIN/CE VOUT U3TXDN2_L 1 R1155
10U_0805_6.3V6M 2U3TXDN2 U3TXDP1_L 1 R1156 2 U3TXDP1
2 USB30@ @ 0_0402_5% @ 0_0402_5%

VDD33
VDD33
VDD33

VDD33
VDD33
VDD33

VDD33
VDD33

VDD33
VDD33

VDD33
VDD33
VDD33
VDD33

VDD10
VDD10
VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

VDD10
VDD10

VDD10
VDD10

VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

U3AVDO33

U2AVDD10
GND 2 U3RXDP2_L 1 R1166 2U3RXDP2 U3RXDN1_L 1 R1167 2 U3RXDN1
RT9701-PB_SOT23-5 @ 0_0402_5% @ 0_0402_5%
U3RXDN2_L 1 R1168 2U3RXDN2 U3RXDP1_L 1 R1157 2 U3RXDP1
B2 USB30@ @ 0_0402_5% @ 0_0402_5%
<15> CLK_PCIE_USB30 PECLKP U2DP2_L
<15> CLK_PCIE_USB30# B1 PECLKN SPEC Max:+3V---200mA;+1.05V---800mA C888.1U_0402_16V7K 1 R1169 2 U2DP2 U2DP1_L 1 R1158 2 U2DP1
USB30@ B6 U3TX_C_DP2 1 2 U3TXDP2_L 0_0402_5% 0_0402_5%
U3TXDP2
<15> PCIE_PRX_DTX_P4
C889 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_P4 D2 PETXP Idle mode:0.489W: U2DN2_L 1 R1159
@ 2 U2DN2 U2DN1_L R1170
1 @ 2 U2DN1
C891 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_N4 D1 A6 U3TX_C_DN2 1 2 U3TXDN2_L 0_0402_5% 0_0402_5%
<15> PCIE_PRX_DTX_N4 USB30@ PETXN +3V---43mA;+1.05V---328mA U3TXDN2
N8 U2DN2_L
U2DM2 @ +USB3_VCCA @ +USB3_VCCA
<15> PCIE_PTX_C_DRX_P4 F2 PERXP D3 mode:0.066W: C890.1U_0402_16V7K For ESD request For ESD request
F1 P8 U2DP2_L USB30@
<15> PCIE_PTX_C_DRX_N4 PERXN +3V---5.4mA;+1.05V---45mA U2DP2 U3RXDP2_L
B8 D66 USB30@ D65 USB30@
U3RXDP2 U3RXDN2 U3RXDN1
1 R- VCC 8 1 R- VCC 8
USB30@ A8 U3RXDN2_L +3V U3RXDP2 2 7 U3RXDP1 2 7
R1171 1 U3RXDN2 U3TXDN2 R+ GND U2DP2 U3TXDN1 R+ GND U2DP1
<18,23,37,38,44,45> BUF_PLT_RST# 2 0_0402_5% 3 6 3 6
C R1161 USB30@ U3TXDP2 T- D- U2DN2 U3TXDP1 T- D- U2DN1 C
H2 PERSTB 4 T+ D+ 5 4 T+ D+ 5
10/02 Change to SC100001K00. PCIE_WAKE#_R K1 G14 OCI2B 1 2 10K_0402_5%
CLKREQ_USB3 PEWAKEB OCI2B
K2 PECREQB Can be attach to EC, either. OCI1B H13 OCI1B 1 2 10K_0402_5% LXES4XBAA6_MSOP8 LXES4XBAA6_MSOP8
7/30 update +3V R1163 1 USB30@2 10K_0402_1% R1162 USB30@
@ R1164 1 2 100_0402_1% J2
+3V R1165 1 AUXDET PWRON2
+3V 2 10K_0402_5% J1 PSEL PPON2 H14 Close to connector
USB30@ SMIB H1 PCI Express/ExpressCard select signal J14 PWRON1
+3V <19> SMIB SMIB PPON1 USB20@ 0_0402_5%
1:others
2

USB30@ USB30@ U2DN1_L 1 R1030 2 USB20_N2

0:Express Card or Mini card U2DP1_L USB20_P2 USB20_N2 <18>
R1187 +3V R1172 1 2 10K_0402_5% P5 C892 .1U_0402_16V7K 1 R1031 2
PONRSTB U3TX_C_DP1 1 USB20_P2 <18>
10K_0402_5% B10 2 U3TXDP1_L USB20@ 0_0402_5%
U3TXDP1
2
G

Q125 USB30@ 1 2 USB20@ 0_0402_5%

SSM3K7002FU_SC70-3 D67 1 2 SPI_CLK_USB M2 A10 U3TX_C_DN1 1 2 U3TXDN1_L U2DN2_L 1 R1034 2 USB20_N3
USB20_N3 <18>
1

SPISCK U3TXDN1
1U_0603_10V6K

3 1 PCIE_WAKE#_R 1SS355TE-17_SOD323-2 SPI_CS_USB# N2 N10 U2DN1_L .1U_0402_16V7K U2DP2_L 1 R1035 2 USB20_P3

SPISCB U2DM1 USB20_P3 <18>
C894

USB30@ USB_SO_SPI_SI N1 C893 USB30@ USB20@ 0_0402_5%

S

1 SPISI
+3V USB_SI_SPI_SO M1 P10 U2DP1_L +5VALW +USB3_VCCA
SPISO U2DP1
USB30@ B12 U3RXDP1_L
U3RXDP1
USB30@ C830 U44 W=60mils
2

<16,37,38> PCIE_WAKE# +3V 2 K13 A12 U3RXDN1_L .1U_0402_16V7K 1 8

R1173 GND U3RXDN1 GND OUT
K14 1 2 2 7
GND IN OUT
10K_0402_5% J13 3 6
GND IN OUT
2
G

Q117 USB30@ P4 R1174 USB_ON# 1 R1068 2 4 5 1 R1069 2 OCI2B

GND <45,48> USB_ON# EN OC#
SSM3K7002FU_SC70-3 1.6K_0402_1% 0_0402_5% USB30@ 0_0402_5%
1

3 1 CLKREQ_USB3 As short as possible P12 1 2 APL3510BKI_SO8 1 R1070 2 OCI1B

<15> USB30_CLKREQ# RREF USB30@ 2A/Active Low USB30@ 0_0402_5%
S

N12
U2AVSS +5VALW
C14
USB30@ GND R1326
N11 1 R1073 2 USB_OC1# <18>
+3V U2PVSS USB20@
1 2
D6 @ 100K_0402_5% 0_0402_5%
+3VALW +3VALW USB3_XT1 N14 U3AVSS
USB3_XT2 M14 XT1 Q130
XT2
2

1
DTC124EKAT146_SC59-3
B @ B
1

OUT
2
10K_0402_5%
R1177

C895 R1175 @ R1176

@R1176 PWRON1 1 R1071 2
.1U_0402_16V7K 10K_0402_5% 47K_0402_5% P6 @ 0_0402_5%
USB30@ USB30@ USB30@ CSEL PWRON2 1 R1072 2 2
1

2 @ 0_0402_5% IN

GND
U53 USB30@ P14
1

SPI_CS_USB# GND
8
VCC CS#
1 A1
GND GND
P11 09/15 Reserve inverter.
2

7 2 USB_SI_SPI_SO A2 P9

3
HOLD# SO GND GND +USB3_VCCA
0_0402_5%
R1178

0_0402_5%
R1179

SPI_CLK_USB 6 3 A3 P7
USB_SO_SPI_SI 5 SCK WP# GND GND
4 A4 P2
SI GND @ GND GND +USB3_VCCA
A5 P1 1 2
AT25F512AN-10SU-2.7_SO8~D GND GND JUSB2 C825 470P_0402_50V7K
A7 N13
1

GND GND
A9 N9 1
GND GND VBUS JUSB3
A11 N7
GND GND

470P_0402_50V7K
220U_6.3V_M

C816
A13 N3 1 U2DN1 2 1
USB30@ GND GND D- VBUS
USB3_XT1 A14 M13 1
GND GND

C814
USB3_XT2 B3 M12 + U2DP1 3 U2DN2 2
+3V GND GND D+ D-
B4 M11
GND GND U2DP2
B5 M10 4 3
GND GND GND D+
1

2 2
B7 M9
R1180 GND GND U3RXDN1
B9 M8 5 4
100_0402_5% USB30@ GND GND SSRX- GND
B11 M7
GND GND U3RXDP1 U3RXDN2
B13 M6 6 5
GND GND SSRX+ SSRX-
B14 M5
2

GND GND U3RXDP2

Y6 Place as close as C1
GND GND
M4 7
GND-DRAIN
6
SSRX+
1 2 C2 M3 10
possibile to C3
GND GND
L12 U3TXDN1 8
GND1
11 7
GND GND SSTX- GND2 GND-DRAIN
24MHZ_12PF_X5H024000DC1H U3.N14 and U3.M14 C10
GND GND
L11
GND3
12
GND1
10
1 USB30@ 1 C11 L7 U3TXDP1 9 13 U3TXDN2 8 11
C897 C898 GND GND SSTX+ GND4 SSTX- GND2
L6 12
12P_0402_50V8J 15P_0402_50V8J GND SUYIN_020052GR009M2026L U3TXDP2 GND3
9 13
USB30@ USB30@ ME@ SSTX+ GND4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

A 2 2 SUYIN_020052GR009M2026L A
ME@
P/N: SA000033W10 (S IC UPD720200F1-DAK-A FBGA 176P USB3.0)
C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

Pin compare table for support USB remote wakeup or not UPD720200F1-XXX-A_FBGA176
MP version
USB30@

AUXDET(Pin J2) CSEL(Pin P6) CLK

Security Classification Compal Secret Data
Support USB pull high Tied to GND Must use 24MHz crystal: mount Issued Date 2010/11/30 Deciphered Date 2011/08 Title
remote wakeup 10k to VDD33 Y1,R19,C40,C41
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 PD720200
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Not support USB Tied to GND pull high Can use either 48MHz or 24MHz When DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.3
remote wakeup to VDD33 use 48MHz clock: mount R22,R25 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 30, 2010 Sheet 49 of 63
5 4 3 2 1
ON/OFF switchSW 2
1 3
Power Button Power Bottom Board Conn. 10pin Silder Bar Board Mdule Conn. 6pin
2 4
SMT1-05_4P
@

6
5
+3VALW
DVT, R1117 change to SM01000CY00 +5VS
TOP Side J7
for EMI request.

2
1 2 JP9
+5VS 1
SHORT PADS R1115 +5VALW R1114 1 1
2 0_0402_5% ESB_INT_R 2
Bottom Side @ 100K_0402_5% JP13
<45> ESB_INT
3
2
D53 3
1 R1117 1 2 0_0402_5% ESB_CLK_R 4
<45> ESB_CLK

1
ON/OFF# 1 R1116 1 4
3 ON/OFF# <45> 2 2 <45> ESB_DAT 2 0_0402_5% ESB_DAT_R 5 5
ON/OFFBTN# 1 3 +3VS 6
51_ON# 3 ESB_RST# 6
2 51_ON# <52> <45> CAPS_LED# 4 4 <45> ESB_RST# 7 7
<45> NUM_LED# 5 5 8 8
DAN202UT106_SC70-3 <14> HDD_LED# 6 2 2 9
NOVO_BTN# 6 @ GND
7 7 10 GND
10/02 Change to SC600000B00. ON/OFFBTN# 8 C858

33P_0402_50V8J
8 33P_0402_50V8J ACES_85201-08051
D <45,47> PW R_LED# 9 9

1
1 1

C859
1 1 10 ME@
EC_ON 10
<45,55> EC_ON 2 11 11 G13 13
G C927 C928 12 14
Q95 100P_0402_50V8J 100P_0402_50V8J 12 G14
S

3
2

2N7002_SOT23-3 2 2 ACES_87151-1207G
R1112
10K_0402_5% ME@
NOVO_BTN# ON/OFFBTN#
1

9/30 remove EC_SMB_CK2, EC_SMB_DA2

2
D54
+3VALW PJSOT24C 3P C/A SOT-23
@
2

1
R1118
100K_0402_5%

D56
1

NOVO# 2
<45> NOVO#
1 NOVO_BTN#
51_ON# 3
<52> 51_ON# EMI REQUEST 1ST = SCA00000E00
DAN202UT106_SC70-3 2ST = SCA00000R00
10/02 Change to SC600000B00.

KB Lighting CONN.4pin
JP12
+VCC_KB_LED 1 +5VS
1
2

0.1U_0402_10V6K
2

C904
2 3 3 GND 5
4 6 +VCC_KB_LED
4 GND Q120

1
@ ACES_87213-0400G
1

D
ME@ 3 1
R1229
10K_0402_5% AO3413_SOT23-3
KBL@

C905
KBL@ KBL@

G
1 2

10U_0805_10V4Z
2

2
1 R1232 2 C906
100K_0402_5% 0.1U_0402_16V4Z
2 1

KBL@
KBL@ 1 KBL@

C907
0.01U_0402_16V7K
2

1
OUT
<45> LED_KB_PW M 2 IN

GND
Q122
DTC124EKAT146_SC59-3

3
KBL@

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2010/11/30 Deciphered Date 2011/08 Title
other IO connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 50 of 63
 A B C D E

7/26 change SI4800 to SI2301

+5VALW TO +5VS +3VALW TO +3VS +1.5V to +1.5VS
+1.5V +1.5VS

+5VALW

S
+5VS +3VALW +3VS

D
3 1
U46 U47 1 1 1

1
8 1 8 1 Q124
C856 C857 C835

G
1 7 2 1 1 1 7 2 1 1

2
1

1
6 3 6 3 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R1119
C836 C837 C838 C839 C840 C841 2 2 2 470_0603_5%
5 5
10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R1113 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R1084 SI2301BDS-T1-E3_SOT23-3 @

2
1 2 2 2 2 2 2 1
DMN3030LSS-13_SOP8L-8 470_0603_5% DMN3030LSS-13_SOP8L-8 470_0603_5%

4
@ @

1 2

1 2

1
+VSB +VSB +3VALW D
D D
2 SUSP
2 SUSP 2 SUSP G

1
G G S Q98

3
S Q96 S Q97 2N7002_SOT23

3
R1085 2N7002_SOT23 R1086 2N7002_SOT23 100K_0402_5% @
20K_0402_5% @ 47K_0402_5% @ R1087

2
5VS_GATE2 R1088 15VS_GATE_R 2 R1090 1 1.5VS_GATE

2
1 1 Q101 0_0402_5% 1 1
1

1
D 10K_0402_5% D R1089 D
SUSP 2 Q99 C842 SUSP 2 Q100 0_0402_5% C843 SUSP# 2 C844 C845
G 2N7002_SOT23 0.1U_0603_25V7K G 2N7002_SOT23 0.1U_0603_25V7K G 0.1U_0603_25V7K
S 2 S @ 2 2N7002_SOT23S 2 2
3

3
0.1U_0603_25V7K

+RTCVCC +5VALW
+1.8VS +1.5V +1.05VS_VGA +0.75VS +1.05VS +5VALW

1
1

1
@
R1096 R1097 @
R1091 R1092 R1093 R1094 R1095 100K_0402_5% 100K_0402_5% R1098
2 470_0603_5% 470_0603_5% 470_0603_5% 22_0603_5% 470_0603_5% 100K_0402_5% 2

2
@ @ @ @ SUSP
<6,10,57> SUSP
1 2

1 2

1 2

1 2

1 2

2
SYSON#
D D D D D Q107 Q108

1
2 SUSP 2 SYSON# 2 SUSP 2 SUSP 2 SUSP DTC124EKAT146_SC59-3 DTC124EKAT146_SC59-3
G G G G G @

OUT

OUT
S Q102 S Q103 S Q104 S Q105 S Q106
3

3
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
@ @ @ @ 2 SYSON 2
<10,45,56,58,59> SUSP# IN <45,49,56> SYSON IN

GND

GND
3

3
For Intel S3 Power Reduction.

+1.5V to +1.5VS_VGA Transfer

J9
+1.5V 2 1 +1.5VS_VGA
2 1
+5VALW @ JUMP_43X118
+1.5V +1.5VS_VGA
1

300mil(7.2A)
R1103 1 1
3 3
100K_0402_5% C849 C850
OPTI@ 10U_0805_6.3V6M 10U_0805_6.3V6M
2

OPTI@ OPTI@
DGPU_PWR_EN# 2 2
DGPU_PWR_EN# <25>
R1104 OPTI@
1

0_0402_5% D U49
Q113
300mil(7.2A)
<18,23,58,59> DGPU_PWR_EN 2 1 2 8 1
G 2N7002_SOT23 7 2
OPTI@ S OPTI@ 6 3
3

2
5 1 1
1

1 C853 C854 R1101

C852 10U_0805_10V4Z 0.1U_0402_16V4Z 470_0603_5%

4
R1105 10U_0805_10V4Z DMN3030LSS-13_SOP8L-8 OPTI@ OPTI@ OPTI@
100K_0402_5% OPTI@ 2 2

1
OPTI@ 2
2

+VSB

OPTI@
1 2

1
R1102 510K_0402_1% D
1 Q111 2 DGPU_PWR_EN#
C855 2N7002_SOT23 G
0.1U_0603_25V7K OPTI@ S

3
OPTI@

1
D 2
DGPU_PWR_EN# 2 Q112
4 G 2N7002_SOT23 4
S OPTI@

3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/11/30 Deciphered Date 2011/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 51 of 63
A B C D E
 5 4 3 2 1

VIN
DC030006J00 Precharge detector
PF101 PL101 15.97V/14.84V FOR
JDCIN1
APDIN 1
12A_65V_451012MRL
2 APDIN1
SMB3025500YA_2P
1 2
ADAPTOR
4 4

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
3
3

1
D D
2
2 PreCHG
1 PQ102

2
1

PC101

PC102

PC103

PC104
PR102 TP0610K-T1-E3_SOT23-3
1K_1206_5%
4602-Q04C-09R 4P P2.5
1 2 2 1 3 1
@ VIN
PR103 PD102
1K_1206_5% LL4148_LL34-2
1 2

100K_0402_1%
1

1
100K_0402_1%
PR104

PR105

PR106
1K_1206_5%

2
1 2

PR107

2
1K_1206_5%
1 2
VIN

100K_0402_1%
2

PR108
PD101
LL4148_LL34-2 PQ103

1
DDTC115EUA-7-F_SOT323-3

2
PD103 51_ON-1 PD104
LL4148_LL34-2 2

1
2 1 <45,54> ACOFF 1 2
BATT+

1
3 PQ104
PR101 PR109 <21,34,38,45,47,48,49,50,51,55,56,57,58> +5VALW DDTC115EUA-7-F_SOT323-3
68_1206_5% 68_1206_5% RB715F_SOT323-3
PQ101 VS 2

3
C TP0610K-T1-E3_SOT23-3 C
2

2
N1 3 1
0.22U_0603_25V7K

3
1

PR110 PC106
PC105

100K_0402_5% 0.1U_0603_25V7K
B+
2

PR111
2

22K_0402_5% PR112
1 2 51_ON-2 2.2M_0402_5%
<50> 51_ON#
2 1

VL
VS

499K_0402_1%
1
0.01U_0402_25V7K

PR113
1

1
PC107
PR114
100K_0402_1%

2
@

2
PU101A

8
PD105 LM393DG_SO8
2 3 @ PRG+

P
<53,55> MAINPWON PRG-1 1 +
1
O

205K_0402_1%

499K_0402_1%

0.01U_0402_25V7K
3 2 PRG-
-

1
+RTCBATT <54> ACON
- +

1
1000P_0402_50V7K

PR115

PR116

PC110
JRTC1 PR117 PR118 @ RB715F_SOT323-3

4
1

1
560_0603_5% 560_0603_5%

PC109
2 1 +RTCBATT 1 2 CHGRTC-11 2 PC108
+CHGRTC

2
B 0.1U_0603_25V7K B

PRG++ 2

2
ML1220T13RE
45@
PQ105
1 2 PR119 2N7002W-T/R7_SOT323-3 PR120
+3VLP

1
34K_0402_1% D 47K_0402_5%
6251VREF 2 1 2 2 1
PD106 G PACIN <54>

1
RB751V-40_SOD323-2 S

3
PQ106

2
DTC115EUA_SC70-3
PR121
66.5K_0402_1% 2 +5VALW

3
ACIN BATT ONLY
Precharge detector Precharge detector
Min. typ. Max. Min. typ. Max.
L-->H 14.991V 15.381V 15.782V L-->H 7.196V 7.349V 7.505V
A A
H-->L 13.860V 14.247V 14.621V H-->L 6.138V 6.214V 6.056V

Security Classification Compal Secret Data Compal Electronics, Inc.

2010/01/25 2010/12/31 Title
Issued Date Deciphered Date PWR DCIN / Vin Detector /Pre-charge
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom PIQY0/Y1 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 52 of 63
5 4 3 2 1
 5 4 3 2 1

PH201 under CPU botten side :

VMB2 VMB
CPU thermal protection at 95 degree C
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P Recovery at 56 degree C
1 1 2 1 2 BATT+
1
2
D 2 EC_SMCA D
3
3 EC_SMDA
4
4 TS
5
5

1
6
6

1
7 PC201 PC202
7 ADP_I <45,54>

100_0402_1%

100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K +3VALW

2
GND
9
GND
VL

PR201

PR202
TYCO_1775789-1
2

2
@

5.23K_0402_1%
1

2
PR222
PC203 PR204
0.1U_0603_25V7K 20K_0402_1% PR205

2
VL @ 100K_0402_1%

2
100K_0402_1%
PU201

1
1
1 8 G718_TMSN1
EC_SMB_CK1 <45> VCC TMSNS1

PR206

2
<45,60> VR_HOT# 2 7 G718_RHYST1
GND RHYST1 PR207
EC_SMB_DA1 <45> G718_TMSN2
3 6 9.53K_0402_1%

2
OT1 TMSNS2

1
D
1 2 +3VALW 2 G718_OT2 4 5

1
OT2 RHYST2

78.7K_0402_1%
PR208 G

G718_RHYST2
2

1
6.49K_0402_1% PQ201 S G718TM1U_SOT23-8

PR209
2N7002KW_SOT323-3 PR223 PH201
@ 0_0402_5% 100K_0402_1%_TSM0B104F4251RZ
1
PR210
2 BATT_TEMP <45> A/D

2
10K_0402_5%
C MAINPWON <52,55> C

2
PR224
10K_0402_1%

1
VS

+3VALW +3VS
0.01U_0402_25V7K
1

PC204

VMB2
PR211 PR212
2

100K_0402_1% 10K_0402_1%
PR213 PR214
2

649K_0402_1% 5.1M_0402_5%
1

1 2 BATT_OUT <54>
PQ203
PR215 TP0610K-T1-E3_SOT23-3
8

10K_0402_1% PQ202
1

BATDE-4 1 D 2N7002KW_SOT323-3
2 BATDE-3 5
P

+ BATDE-1
7 2 B+ 3 1 +VSBP
PR216 O G
6
-
G
2

BATDE-2

100K_0402_1%
B B

0.22U_0603_25V7K
232K_0402_1% PU101B S
3

1
LM393DG_SO8
4

1
PR217

PC205
PQ205 PC206
1

D 2N7002KW_SOT323-3 0.1U_0603_25V7K
1

2
<45> BATT_LRN# 2

2
2 1 G PR219
6251VREF VL
S 22K_0402_1%
3

PR218 1 2
10K_0402_1%
2

PR220
100K_0402_1%

PR221
1

1
1K_0402_5% D PJ201
1 2 2 PQ204 @ JUMP_43X39
<55> SPOK
G 2N7002W-T/R7_SOT323-3 1 1
1U_0402_6.3V6K
+VSBP 2 2 +VSB
S

3
1

PC207
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom PIQY0/Y1 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 53 of 63
5 4 3 2 1
 5 4 3 2 1

P3
B+
P2
65W:0.020 = SD00000S100
90W:0.015 = SD00000DL00
PQ301 PQ302 120W:0.01 = SD00000K810
SI4459ADY-T1-GE3_SO8 SI4459ADY-T1-GE3_SO8
PR302
VIN 8
7
1
2
1
2
8
7 0.01_1206_1% CHG_B+
6 3 3 6 PJ301

5600P_0402_50V7K
5 5 1 4 2 1 PQ303
2 1 SI4459ADY-T1-GE3_SO8

2
@ JUMP_43X118

PC324
2 3 1 8
VIN

4
2 7
3 6

2200P_0402_50V7K
0.1U_0603_25V7K
5

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
D D

2
47K_0402_5%

PQ304
1

2
PC302
@PR303

200K_0402_1%
0.1U_0603_25V7K

PC306

4
1
PR301

PC303

PC304

PC305
DTA144EUA_SC70-3 47K_0402_1% CSIN DISCHG_G

PC301

PR304
CSIP

1
@ PR305

1
PQ305B 47K_0402_1%
VIN PreCHG
2

2
2 @ 2N7002KDW -2N_SOT363-6 1 2

2
VIN

2ACOFF-1
191K_0402_1%

2
1

1
2 5 BATT_OUT <53> PR307 PR308

1DISCHG_G-1
PR306
191K_0402_1% 10K_0402_1%
1

2
@ PD302

4
1SS355_SOD323-2 PR309

1
BATT_ON 2 P2-1 PQ305A PD301 200K_0402_1%

2
PQ306 @ 2N7002KDW -2N_SOT363-6 6251_VDD RB751V-40_SOD323-2 ACSETIN PQ307
DTC115EUA_SC70-3

1 1

1
1
DTC115EUA_SC70-3 PR311

1
0_0402_5% PR312 PD303
3

FSTCHG
2 1 PR310 14.3K_0402_1% PC307 1SS355_SOD323-2

2.2U_0603_6.3V6K
1 <45> FSTCHG 10_1206_5% 1000P_0402_25V8J 2 1 2

2
6

2
PC308

2
1

PR313
150K_0402_1%

2200P_0402_50V7K
2

2
PR314

PQ308A PU301 PC309 PQ310

100K_0402_5%
10K_0402_1%

1
PC310
2 2N7002KDW -2N_SOT363-6 0.1U_0603_25V7K
12

1
D D

@ PR316
6251_DCIN 2N7002W -T/R7_SOT323-3

0.1U_0603_25V7K
1 VDD DCIN 24 2 1

1
2 PACIN

100K_0402_1%
2 BATT_OUT <53>
1

1
PC311
G G

1
PR315
ACSETIN

BATT_ON
S 2 23 ACPRN <55> S
3

3
PQ309 ACSET ACPRN PR317

2N7002W-T/R7_SOT323-3

2
P2-2

2N7002KW _SOT323-3 20_0402_5%

5
6
7
8
C 6251_EN 6251_CSON CSON C
3 EN CSON 22 1 2

1
D

PQ311
PC312

AO4466L_SO8
3

@ PQ312
0.047U_0402_16V7K ACPRN 2
PR319 CELLS 4 21 6251_CSOP 1 2 CSOP G

2
47K_0402_1% PQ308B CELLS CSOP PR318 S

3
PACIN 1 2 5 2N7002KDW -2N_SOT363-6 PC313 6800P_0402_25V7K 20_0402_5% 4
<52> PACIN
1 2 6251_ICOMP 5 20 6251_CSIN 2 1
ICOMP CSIN

2
PC314 PR320
4

PC315 PR321 10K_0402_1% 0.1U_0402_16V7K 20_0402_5%

<52> ACON 1 26251_VCOMP-1
1 2 6251_VCOMP 6 19 6251_CSIP 1 2 PL301 PR324

3
2
1
VCOMP CSIP
1

PQ313 PR322 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1%

DTC115EUA_SC70-3 0.01U_0402_25V7K 2_0402_5% BATT+
1 26251_ICM 7 ICM PHASE 18 LX_CHG 1 2 CHG
1 4
PR323

5
6
7
8
<45,52> ACOFF 1 2ACOFF-1 2 <45,53> ADP_I 100_0402_1% 2 3

1
PQ314
DH_CHG

AO4466L_SO8

4.7_1206_5%
8 VREF UGATE 17

PR326
PR325 PR328 1 2 6251VREF PR329 PC317
1

10K_0402_1% 154K_0402_1% PC316 0_0603_5% 0.1U_0603_25V7K

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
6251_CHLIM BST_CHG 1 BST_CHGA 2

16251_SN
PR327 2 1 0.1U_0402_16V7K 9 16 2 1
3

<45> IREF CHLIM BOOT

1
0_0402_5% PR330 4

1
PC318

PC319

PC323
51K_0402_1% PD304
0.01U_0402_25V7K

2 6251_ACLIM 6251_VDDP RB751V-40TE17_SOD323-2

2N7002KW_SOT323-3

1 10 15
2

ACLIM VDDP
1

6251VREF

2
1
PC320

PQ315 PR331

680P_0603_50V7K
1 2 6251_VDD

3
2
1
1

PC321
100K_0402_1% 6251_VADJ
11 14 DL_CHG

2
VADJ LGATE

1
2 PR333 PR332
<53> BATT_OUT
2

G 1K_0402_1% 4.7_0402_5%
2

S 12 13 PC322
3

2
GND PGND 4.7U_0805_6.3V6K
2

ISL6251AHAZ-T_QSOP24
B PR334 B
Connect to EC A/D Pin. 15.4K_0402_1%
1 2
<45> CHGVADJ
1

PR335
31.6K_0402_1%
CHGVADJ=(Vcell-4)/0.10627 3cell : GND
6251_VDD 6251_VDD
Vcell CHGVADJ 65W Adapter 4cell : VDD
2

4V 0V Vaclim=2.39*(1.96K/(1.96K+16.9K))=0.2484V 6251_VDD

2
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) PR338 PR336 PR337
4.2V 1.882V
where Vaclim=0.2484V, Iinput=2.76A 10K_0402_1% @ 100K_0402_1%@ 100K_0402_1%
1

4.35V 3.2935V 1 2 ACIN <16,45>

PR340

1
PR339 10K_0402_1% CELLS
90W Adapter 47K_0402_1%

3
CC=0.25A~3A PACIN
2

1 2

Vaclim=2.39*(2.87K/(2.87K+16.9K))=0.347V
IREF=1.016*Icharge PR341
Iinput=(1/0.015)((0.05*Vaclim)/2.39+0.05)
1

0_0402_5% 2 5 2 1
IREF=0.254V~3.048V where Vaclim=0.347V, Iinput=3.82A PR342

2
PR343 @ 0_0402_5%

4
<55> ACPRN
VCHLIM need over 95mV 2 BATT_SEL_EC
14.3K_0402_1%
2

PQ316
120W Adapter PQ317A PQ317B
DTC115EUA_SC70-3 @ 2N7002KDW -2N_SOT363-6 @ 2N7002KDW -2N_SOT363-6
3

A Vaclim=2.39*(1K/(1K+50K))=0.047V A
Iinput=(1/0.01)((0.05*Vaclim)/2.39+0.05)
where Vaclim=0.047V, Iinput=5.1A

65W : PR330=16.9K, PR333=1.96K

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
90W : PR330=16.9K, PR333=2.87K
120W : PR330=50K, PR333=1K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS PIQY0/Y1 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 54 of 63

5 4 3 2 1
 5 4 3 2 1

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205 PJ402
+3VALW P 2 2 1 1 +3VALW
@ JUMP_43X118

1U_0603_10V6K
D D

1
PJ403

PC402
+5VALW P 2 1 +5VALW

2
2 1
@ JUMP_43X118

PR401 PR402
13K_0402_1% 30K_0402_1%
1 2 FB_3V FB_5V 1 2

PR403 PR404
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
1 2 1 2
PJ401 Typ: 175mA
B+ 2 1 +3VLP
2 1

ENTRIP2

ENTRIP1
@ JUMP_43X118 PR405 PR406
2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0603_25V7K

0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

110K_0402_1% 154K_0402_1%
680P_0402_50V7K

@
PC401

PC403

PC410
1 2 1 2

4.7U_0805_10V6K
1

1
PC404

PC405

PC406

PC407

PC408

PC409
2

8
7
6
5

5
6
7
8
PU401 PQ402
2

2
AO4466L_SO8

PC411

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
1
C PQ401 C
25 P PAD
AO4466L_SO8

2
4 4
7 VO2 VO1 24
SPOK <53>
8 23 PR408 PC413
PR407 VREG3 PGOOD 0_0603_5% 0.1U_0603_25V7K
1
2
3

3
2
1
12BST_3V-1
1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2BST_5V-1
1 2
0_0603_5%
PL402 PC412 UG_3V 10
VFB=2.0V 21 UG_5V PL401
4.7UH_PCMC063T-4R7MN_5.5A_20% 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_PCMC063T-4R7MN_5.5A_20%
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1

8
7
6
5

1
LG_3V LG_5V
4.7_1206_5%

4.7_1206_5%
12 LGATE2 LGATE1 19

5
6
7
8
PQ403

PR411
SKIPSEL
AO4712_SO8 PR410 @
PR409

VREG5
0_0402_5%

GND

VIN
MAINPW ON 2 RT8205EGQW _W QFN24_4X4

NC
EN
1 1 1
2

2
4
PC414 + 4 PC415 +

13

14

15

16

17

18
1

1
220U_6.3VM_R15 PR412 220U_6.3VM_R15
680P_0603_50V7K

OS-CON 499K_0402_1% AO4712_SO8 OS-CON

PC416

680P_0603_50V7K
2 PQ404 2

PC417
1 2
2

1
2
3

2
B+

3
2
1
1
100K_0402_1%

1U_0603_10V6K
VL

1
PC418

1
PR413

PC419
Typ: 175mA

4.7U_0805_10V6K
B B

2
ENTRIP1 ENTRIP2
2

2
RT8205_B+
6

1
PQ405B
PQ405A 2N7002KDW -2N_SOT363-6

0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2VREF_8205 +3.3VALWP OCP(min)=5.81A

2
PC420
+5VALWP OCP(min)=8.44A
<52,53> MAINPWON
1

PR414
0_0402_5%
2 1

PR415
100K_0402_1%
2 1
VL
1
2N7002W-T/R7_SOT323-3

PR416
D
1

200K_0402_1%
> ACPRN
PQ407

2 1 2 1 2 2 PQ406
G VS DTC115EUA_SC70-3
S PR417
40.2K_0402_1%

2.2U_0603_10V7K
3

A A
1

100K_0402_1%
1

1
PR418

PC421

3
2

<45,50> EC_ON
2

2
PQ408
DTC115EUA_SC70-3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

3VALWP/5VALWP
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PIQY0/Y1 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 55 of 63
5 4 3 2 1
 A B C D

1 1

PJ501
1.5_51117_B+ 2 1
2 1 B+

5
6
7
8
PR502 @ JUMP_43X118

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC502

PC503
267K_0402_1% @ PC504
1 2 PQ501 680P_0402_50V7K
AO4406AL_SO8

2
4
PR501 PR504 PC505
0_0402_5% 0_0603_5% 0.1U_0603_25V7K
1 2 1.5V_EN BST_1.5V 1 2BST_1.5V-1 1 2
<45,49,51> SYSON

3
2
1
2
47K_0402_5%

PL501
PR503

0.82UH_PCMC063T-R82MN_13A_20%

15

14
+1.5VP
1

1
PU501 1 2
PC501 @

EN/DEM

NC

BOOT
.1U_0402_16V7K
1

1.5V_TON 2 13 DH_1.5V
TON UGATE

1
@

330U_B2_2VM_R15M
330U_X_2VM_R6M
3 12 LX_1.5V PR505 1 1
VOUT PHASE

5
6
7
8
4.7_1206_5%
+ +

PC506

@ PC517
1.5V_V5FILT 4 VFB=0.75V 11 1.5V_TRIP 1 2 +5VALW
VDD CS PR507 PQ502

11.5V_SNB 2
2
1.5V_FB 5 10 9.76K_0402_1% AO4726L_SO8 2

FB VDDP 2 2
6 9 DL_1.5V 4
PGOOD LGATE

PGND
PR506

680P_0603_50V7K
GND

1
100_0603_5%

PC508
1 2 @ PC509 PC507
+5VALW 47P_0402_50V8J RT8209BGQW _W QFN14_3P5X3P5 4.7U_0805_10V6K

3
2
1
1 2

2
1

PC510
4.7U_0603_6.3V6K
2

PR508
+1.5VP OCP(min)=15.6A
1 2
1.8VSP max current=4A
10K_0402_1%
1

PR509
10K_0402_1%
PJ503
2

2 2 1 1

@ JUMP_43X118

PJ502 +1.5V
+1.5VP 2 1
2 1
@ JUMP_43X118
3 3

4.5x4.5 2H

PU502 PL502 PJ505

4

PJ504 1UH_PCMB042T-1R0MS_4.5A_20% +1.8VSP 2 1 +1.8VS

1.8V_VIN 10 LX_1.8V 2 1
+5VALW 2 1 2 1 2
PG

2 1 PVIN LX +1.8VSP @ JUMP_43X118

@ JUMP_43X118

68P_0402_50V8J
9 PVIN LX 3
1

1
4.7_1206_5%
1

1
PC512
PC511 8 SVIN
PR510

22U_0805_6.3VAM PR511
6 FB_1.8V 30K_0402_1%
2

2
1.8V_EN FB

22U_0805_6.3VAM

22U_0805_6.3VAM
5
2

2
11.8V_SNB

EN

1
FB=0.6Volt
NC

NC
TP

PC514

PC515
<10,45,51,58,59> SUSP#
680P_0603_50V7K
11

2
1 2
PC513

PR512 0_0402_5%
0.1U_0402_10V7K
2

PC516

SY8033BDBC_DFN10_3X3
2
1

PR513
1M_0402_5%
@
2
1

4
PR514 4

14.7K_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1.5VP/+1.8VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PIQY0/Y1 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 56 of 63
A B C D
 5 4 3 2 1

Ventura_B+
@ PJ601
51117_VCCSAP_B+ 2 1
2 1
JUMP_43X118

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PC602

PC603
1

1
5
6
7
8
PQ601

2
AO4466L_SO8
PR602
280K_0402_1%
1 2
PR601 4
D D
0_0402_5%
<58> VCCPPWRGOOD 1 2 VCCSAP_EN

1
PR603 PC604 +VCCSAP OCP(min)=6.28A

1
@ PR604 0_0603_5% 0.1U_0603_25V7K

3
2
1
47K_0402_5% PC601 BST_VCCSAP
1 2 BST_VCCSAP-1 1 2
@ 0.1U_0402_16V7K

2
PL601

15

14
2

1
PU601 2.2UH_PCMC063T-2R2MN_8A_20%
1 2

NC

BOOT
EN/DEM
+VCCSAP
VCCSAP_TON 2 13 UG_VCCSAP
TON UGATE

1
1
PR606 3 12 LX_VCCSAP
VOUT PHASE

5
6
7
8
100_0603_1% PR605 + PC605
+5VALW 1 2 VCCSAP_V5FILT 4 11 VCCSAP_TRIP 1 2 +5VALW 4.7_1206_5% 220U_6.3V_M
VDD CS PR610 PQ602
OS-CON

1VCCSAP_SNB2
VCCSAP_FB 5 10 13K_0402_1% AO4712_SO8 2
FB VDDP
1

2
PJ602
+3VS 6 9 LG_VCCSAP 4 PR607 +VCCSAP 2 1 +VCCSA
PGOOD LGATE 2 1

PGND
PC608 0_0402_5% PR608

GND
2

VCCSAP_PGOOD
4.7U_0603_6.3V6K 1 2 VSSSA_SENSE <10> @ JUMP_43X118

1
0_0402_5%

1
PR609 RT8209BGQW_WQFN14_3P5X3P5 PC607

3
2
1
10K_0402_5% 4.7U_0805_10V6K PC606

2
470P_0603_50V8J

2
0_0402_5%
1

PR611
2 1
SA_PGOOD <45>
PR612
PR613
2K_0402_1%
1 2 VCCSAP_FB-1 1 2 VCCSA_SENSE <10>
VFB=0.75V
10_0402_5%

C C
+3VS
1

PR615
1

PR614 15K_0402_1%
30K_0402_1% PR616
10K_0402_5%
2

PQ603 PR617
2
1

D 2N7002W-T/R7_SOT323-3 10K_0402_5% PMBT2222A_SOT23-3

2 VCCSASEL-3 2 1 VCCSASEL-2
G PQ604 PR619
1

S 0_0402_5%
3

2VCCSASEL-1
2 1
PC609 PR618 @ VCCSA_SEL <10>

1
@ 4700P_0402_25V7K 100K_0402_5%
2

PR620
2

@ 10K_0402_5%

VID[0] VID[1] VCCSA Vout Require on 2011/ 2012 Required

0 0 0.9 V Yes/Yes
0 1 0.8 V Yes/Yes
1 1 0.75V No/Yes
1 1 0.65V No/Yes
B B

Note:Use VCCSA_SEL to switch High & Low Level for VID[1]

(ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.
+1.5V
PJ603

+0.75VSP 1 2 +0.75VS
1 2

1
@ JUMP_43X79
PJ604

1
JUMP_43X79
@

2
2
PU602
LDO_0.75_VIN 1
VIN VCNTL
6 +3VALW
2 5
GND NC

1
1
PC610 3 7 PC611
4.7U_0805_6.3V6K PR621 VREF NC 1U_0603_10V6K

2
1K_0402_1% 4 8
VOUT NC
9

2
TP
LDO_0.75_VREF G2992F1U_SO8

0.1U_0402_16V7K
1

1
+0.75VSP

PC612
PR623

2
1K_0402_1%

10U_0603_6.3V6M

10U_0603_6.3V6M
1

1
PR622

PC614

PC615
2
1
24.9K_0402_1% D

<6,10,51> SUSP 1 2LDO_0.75_EN 2

2
A G A
1

3 S PQ605
PC613 2N7002W-T/R7_SOT323-3
1U_0402_6.3V6K
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +VCCSAP/+0.75VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C PIQY0/Y1 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 57 of 63
5 4 3 2 1
 5 4 3 2 1

+1.05VS_VCCPP OCP(min)=20.75A

PL702
HCB2012KF-121T50_0805 Ventura_B+ B+
1.05VS_B+ 1 2

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5
6
7
8
PR702

1
267K_0402_1% @ PC704

PC702

PC703
D 1 D

68U_25V_M_R0.36
1 2 PQ701 680P_0402_50V7K
AO4406AL_SO8 +

PC705
2

2
4
PR701 PR703 PC706 2
0_0402_5% 0_0603_5% 0.1U_0603_25V7K
1 2 1.05VS_VCCP_EN BST_1.05VS_VCCP 1 2BST_1.05VS_VCCP-11 2
<10,45,51,56,59> SUSP#

3
2
1
1
PL701

15

14
1
PC701 PU701 1UH_FDUE1040D-1R0M-P3_21.3A_20%
@ .1U_0402_16V7K 2 1 +1.05VS_VCCPP

EN/DEM

NC

BOOT
2
1.05VS_VCCP_TON 2 13 DH_1.05VS_VCCP
TON UGATE

1
PR706 3 12 LX_1.05VS_VCCP PR704
VOUT PHASE

5
6
7
8
100_0603_5% 4.7_1206_5%
1 2 1.05VS_VCCP_V5FILT 4 11 1.05VS_VCCP_TRIP 1 2 +5VALW 1
+5VALW VDD CS PR707 PQ702

330U_X_2VM_R6M
11.05VS_VCCP_SNB2
1.05VS_VCCP_FB 5 VFB=0.75V 10 13.7K_0402_1% AO4726L_SO8 +
FB VDDP

PC707
1

2
6 9 DL_1.05VS_VCCP 4
PGOOD LGATE 2

PGND
PC711

GND
4.7U_0603_6.3V6K PR705
2

1
0_0603_5%
RT8209BGQW _W QFN14_3P5X3P5 PC709

680P_0603_50V7K
7

3
2
1

1
@ PC710 4.7U_0805_10V6K

2
47P_0402_50V8J

PC708
1 2
C C

2
PR708 PR711
4.02K_0402_1% 10_0402_5%
1 2 1.05VS_VCCP_FB1 2 1 VCCIO_SENSE <9>
1

PR710
10K_0402_1%
PR709 1 2 VCCPPW RGOOD <57>
+3VS
10K_0402_1%
2

PR712
10K_0402_1%
@
PJ702
1

2 2 1 1

@ JUMP_43X118
PJ703
+1.05VS_VCCPP 2 2 1 1 +1.05VS
+1.5V @ JUMP_43X118

1
+5VALW +5VALW
B PJ704 B

1
JUMP_43X79 PJ705
2 1
1U_0402_6.3V6K

2 @ +1.05VS_VGAP 2 1 +1.05VS_VGA
1

@ JUMP_43X118
PC712

PR713
@ 0_0402_5% VGAPCIE_VIN
2

PD702
@ RB751V-40_SOD323-2
2

1 2 PC713
4.7U_0805_6.3V6K
6

PU702
2

PR714 5
VCNTL

0_0402_5% VGAPCIE_POK 7 VIN

DGPU_PW R_EN POK
1 2 VOUT 4 +1.05VS_VGAP
<18,23,51,59> DGPU_PW R_EN
PR715 3

22U_0805_6.3V6M
0.01U_0402_25V7K
VOUT
1

1
@ 12.7K_0402_1% PC714

PC715
SUSP# 1 2 VGAPCIE_EN 8 2
EN FB
1

<10,45,51,56,59> SUSP# PR716

@ 47K_0402_5%
0.1U_0603_25V7K

GND

2
1

1.15K_0402_1%
@ PC716

PR717

VIN 9
1 2
2

APL5912-KAC-TRL_SO8
2

PD701 VGAPCIE_FB
2

@ RB751V-40_SOD323-2
1

PR718
A
3.57K_0402_1% A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +1.05VS_VCCPP/1.05VS_VGA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PIQY0/Y1 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 58 of 63
5 4 3 2 1
 5 4 3 2 1

GS: PR840,PR845,PR847,PR853
GPIO6 GPIO5 GT/GT1:PR843,PR844.PR846,PR854
N12P-GS GPU_VID1 GPU_VID0 VGA_CORE 2 1 PQ807
PR801 10K_0402_1% PR845
0_0402_5% D

1
0 0 1.0V 2 1 2N7002KW _SOT323-3
DGPU_PW R_EN <18,23,51,58>
2 1 2
0 1 0.975V @ PR802 G PR848 GPU_VID1 <23>

10K_0402_5%
0.1U_0402_16V7K

2
0_0402_5% S 0_0402_5%
1 1 0.825V

3
2
+3VS

PC801
1 2 SUSP# <10,45,51,56,58>
PR852

PR839
D 10K_0402_5% D

1
1 2 1 2 +3VS_VGA

1
2
+3VS_VGA PR854
GPIO6 GPIO5 +3VS_VGA 0_0402_5% PL801 PR841

2
N12P-GT/GT1 GPU_VID1 GPU_VID0 VGA_CORE PR842 +3VS +3VS_VGA 1 2 1 2
GPU_VID0 <23>
HCB4532KF-800T90_1812 0.004_2512_1%
10K_0402_5% PR847 PR851 VGA_B+ 2 VGA_B+1

0_0402_5%
1 4 1 B+
0 0 1.075V 0_0402_5% 0_0402_5%

PR804

PR840 10K_0402_5%
1
1 2 3 2

2
0 1 0.925V PR846

PR805 10K_0402_5%

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

2
<19,23> VGA_PGOOD 0_0402_5%

PR843 10K_0402_5%
1 1 0.825V

5
+3VS_VGA

PC802

PC803

PC804
0_0402_5%
1 2 PQ806

2
+3VS PR844 PQ801

PR810 10K_0402_1%

1
0_0402_5% D

1
2N7002KW _SOT323-3

PR807

1
2
2
G <33> GPU_VIN-
<33> GPU_VIN+

1
S 4

3
2

2
6264_VID2

10K_0402_5%

10K_0402_5%

6264_VRON
6264_PSI
VCC_PRM1 6264_VID1

6264_VID5

6264_VID4

6264_VID3
1
6264_VID0

PR811

PR809
R809
1
PR853
2
PC805 TPCA8030-H_SOP-ADV8-5
7X7 4H_DCR=1.48mohm

3
2
1
@
@P 0_0402_5% 0.22U_0603_10V7K

1
BST1_VGA1 2BST1_VGA-1 2 PL802

150K_0402_1%
1

36.5K_0402_1%
@1000P_0402_50V7K

0.047U_0603_16V7K
+VGA_CORE

2
PR808 0.42UH_FDUE0640-R42M_20.2A_20%~D
2

2 2.2_0603_1%

40

39

38

37

36

35

34

33

32

31
2 1
1000P_0402_50V7K

6264_SET
2

PC806

PC807

PR813

PR814
2

10K_0402_1%
6.81K_0603_1%

8.87K_0402_1%

PSI_L

VID5

VID4

VID3

VID2

VID1

VID0

BOOT1
PGOOD

VR_ON
1

1
PC808

PR815

5
PR812

1_0402_5%
1

2
@ UG1_VGA PQ802

4.7_1206_5%
1 30 1

330U_D2_2V_Y
1

SET UGATE1

2
PR818

PR819
C C

3.65K_0805_1%
6264_RBIAS 2 PHASE1_VGA +

PR816

PC809
RBIAS PHASE1 29
PC810

PR817
6264_OFS 0.22U_0603_16V7K

1VGA_SNB1
3 28 4

1
OFS PGND1 PR820 2
1 2

1
6264_SOFT 4 27 LG1_VGA 0_0402_5%
SOFT LGATE1
2 1

680P_0603_50V7K
+5VS
PR821 PC812 6264_OCSET 5 26 PVCC_VGA TPCA8028-H_SOP-ADVANCE8-5

3
2
1
97.6K_0402_1% 470P_0402_50V7K OCSET PVCC VSUM1 VGA_ISEN1 VCC_PRM1

PC813
2 1
6264_VW LG2_VGA PC811

10K_0402_1%
1 2 1 2 6 VW LGATE2 25

2
PC814 PU801 4.7U_0603_6.3V6K

2
220P_0402_50V8J 6264_COMP 7 ISL6264CRZ-T_QFN40_6X6 24
COMP PGND2

PR849
1 2
6264_FB 8 23 PHASE2_VGA
FB PHASE2

1
6264_VDIFF 9 22 UG2_VGA
PR823 VDIFF UGATE2 VGA_ISEN2
1K_0402_1% 6264_VSEN 10 21 BST2_VGA
VSEN DROOP BOOT2
2 1

ISEN2

ISEN1
VSUM
PR824 PC815 41
1000P_0402_50V7K

GND

VDD
RTN

GND PAD DFB

2

VIN
255_0402_1% 1000P_0402_50V7K
VO
2

1
1 2 1 2 PC817 VGA_B+
PR822
@ PC816

330P_0603_50V8
1

11

6264_DROOP 12

13

14

15

16

17

18

19

20
2.2_0603_1%
1

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
6264_VDD
<24> VDD_SENSE_VGA
6264_DFB

2
2 1 6264_VIN

5
6264_RTN VGA_ISEN1

PC820

PC821

PC822
PR825 PC819 PQ803

BST2_VGA-1

1
0_0402_5% 180P_0402_50V8J
1000P_0402_50V7K
2

B VGA_ISEN2 B
1 2
+VGA_CORE PR827 PR828
PC823

2 1
1K_0402_1% 1.5K_0402_1% 4
1

PR826 2 1 1 2 +5VS
10_0402_5%

2
PR829
7X7 4H_DCR=1.48mohm

0.22U_0603_10V7K
0_0402_5% TPCA8030-H_SOP-ADV8-5

PC818

3
2
1
2 1 B+
B value=4300K

1
2

PL803
10_0603_5%

<24> GND_SENSE_VGA
+VGA_CORE
2

VCC_PRM1 0.42UH_FDUE0640-R42M_20.2A_20%~D
10_0603_5%
2

PR831

2 1
PR830
PR832
10K_0603_5%_TSM1A103J4302RE
2

10_0402_5%
11K_0402_1%

10K_0402_1%
1
PH801
1

5
PR833

1_0402_5%
0.1U_0402_25V6

0.1U_0402_25V6
0.22U_0402_6.3V6K

2
PQ804

4.7_1206_5%
1 1

330U_D2_2V_Y

330U_D2_2V_Y
2

2
PR836

PR837
3.65K_0805_1%
1

+ +
PC824

PC825

PC826

PR834

PC827

PC828
1U_0402_6.3V6K

PC831

PR835
2.61K_0402_1%

0.01U_0603_50V7K
1

0.22U_0603_16V7K
PC830

1VGA_SNB2
4

1
2

2 2
1 2

1
PR838

PC829

2
1

TPCA8028-H_SOP-ADVANCE8-5 VGA_ISEN2 VCC_PRM1

680P_0603_50V7K
1

3
2
1
VSUM1

PC832

10K_0402_1%
2
VSUM1

PR850
A A

1
VGA_ISEN1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/12/12 Title
2006/12/12 Deciphered Date
Power-VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PIQY0/Y1 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 59 of 63

5 4 3 2 1
 5 4 3 2 1

Alert# PU resister need close CPU, @ PC901 470P_0402_50V7K CPU_B+ 1 2 Ventura_B+

10U_0805_25V6K

10U_0805_25V6K
so the PU resister in HW schematic. 2 1 NTCG PL901
HCB4532KF-800T90_1812
but DAT and CLK need close PWM-IC,

5
Ventura_B+ B+

TPCA8030-H_SOP-ADV8-5
PR901 PQ901

1
so the PU resister in POWER schematic.

PC902

PC903
3.83K_0402_1% PH901 PR968
2 1 2 1 0.004_2512_1%
B value=4700K Ventura_B+ 4 1

2
1000P_0402_50V7K
8.06K_0402_1%

68U_25V_M_R0.36
470KB_0402_5%_ERTJ0EV474J 1
UGATEG
3 2 4 Choke PN:SH00000JX00

1
+

PC904
1 2
DCR=1.33~1.396m ohm

1
PR902
PR903

PC905
27.4K_0402_1%
2 PL902

3
2
1
+VGFX_CORE 0.36UH_PCMB103T-R36MS1R335_23A_20% +VGFX_CORE

2
PR904 PHASEG 4 1
2 1 <33> CPU_VIN-
<33> CPU_VIN+ PC907 1

5
330P_0402_50V7K

10K_0402_1%
SI7170DP-T1-GE3_POWERPAK8-5

SI7170DP-T1-GE3_POWERPAK8-5
D PC906 10_0402_1% BOOTG 2 PR905 1 2 1 PQ902 3 2 D

330U_X_2VM_R6M
+5VS

4.7_1206_5%
PQ903
1 2 2.2_0603_5% +
1

PC910
PC908 PC912 0.22U_0603_10V7K
VCC_AXG_SENSE <10>

1 2PR910
PR906 @ 39P_0402_50V7K PR909 330P_0402_50V7K 330P_0402_50V7K PR908
2

PC909

PR907
499K_0402_1% 2 1 2 1 2 1 PC911 1_0402_5%
VSS_AXG_SENSE <10>

680P_0603_50V7K
1U_0603_10V6K
422_0402_1% 2 1 LGATEG 4 4

2
PC913 PH902
2

2
PC914
150P_0402_50V8J 1000P_0402_50V7K PR913 10K_0402_1%_ERTJ0EG103FA

PC915
2 1 2 1 2 1 2 1 PR916 1 PR914 21 2

1
0_0603_5%

0.22U_0603_10V7K
PR911 PR912 10_0402_1% 2 1 7.5K_0402_1%

3
2
1

3
2
1

2
PR915
475K_0402_1% 2.55K_0402_1% 2.2_0603_5%

BOOT3
PC916 1 PR917 2 .1U_0402_16V7K

ISNG
GFXVR_IMON

ISPG
1

2
PR919 11K_0402_1% PC918
+1.05VS_VCCPP
18.2K_0402_1%

0.047U_0603_16V7K
@ 16.5K_0402_1% 1 2 1 2

2
1

@.1U_0402_16V7K
PC919

PC917 0.033U_0402_16V7K

1
UGATEG

PHASEG
PU902 @ 100_0402_1%

LGATEG
BOOTG

470P_0402_50V7K
PR918

PC920

PC921 @ PR921

NTCG
5 1
2

1
2 VCC BOOT
2 PR920 1

1
130_0402_1%

54.9_0402_1%
1 2 1 2

750_0402_1%
@ 43_0402_1%

PC922
6 8 UGATE3 CPU_B+
<10> VSS_AXG_SENSE FCCM UGATE

1
10U_0805_25V6K

10U_0805_25V6K
PR922

PR923
0.033U_0402_16V7K

ISPG
1

1
PR924
2 7 PHASE3 PQ904
For shortage changed +3VS PWM PHASE
Parallel and tune length

1
+5VS

PC923

PC924
TPCA8030-H_SOP-ADV8-5
LGATE3

49

48

47

46

45

44

43

42

41

40

39

38

37
3 4
2

2
GND LGATE

@
2
1.91K_0402_1%
PR925 ISL6208CRZ-T_QFN8 2 PR926 1ISNG

GND

COMPG

FBG

VSENG

RTNG

ISPG

ISNG

NTCG

PROG2

BOOTG

UGG

PHG

LGG

2
<9> VR_SVID_DAT

1
0_0402_5% 4 @ 0_0402_5%
BOOT2
<9> VR_SVID_ALRT# 1
VWG BOOT2
36 Choke PN:SH00000JX00
DCR=1.33~1.396m ohm

2
PR927
2 35 UGATE2
<9> VR_SVID_CLK 2 IMONG UG2 PL903

3
2
1
PR928 3 34 PHASE2 0.36UH_PCMB103T-R36MS1R335_23A_20%
PGOODG PH2
+3VS 1 2 1 PR929 2 +5VS 4 1 +CPU_CORE

SI7170DP-T1-GE3_POWERPAK8-5

SI7170DP-T1-GE3_POWERPAK8-5
SVID_SDA 4 33
SDA VSSP2

5
1.91K_0402_1% GFX_CORE_PWRGD @ 0_0402_5% ISEN32 PR930 1 3 2 2 PR931 1ISEN1

1
4.7_1206_5%
SVID_ALERT# 5 32 LGATE2 PQ905 PQ906 10K_0402_1% 10K_0402_1%
C ALERT# LG2 C

PR934
PR932
SVID_SCLK 6 31 1 2
<9> VSSSENSE VGATE <16> SCLK VDDP

680P_0603_50V7K
1 PR933 2 7 30 PWM3 0_0402_5% 4 4 PR937

1 2
<45> VR_ON VR_ON PWM3 VSUM+ 2 PR935 1 2 1ISEN2
0.047U_0603_16V7K

PC925
0_0402_5% 8 PU901 29 LGATE1 3.65K_0402_1% 10K_0402_1%
IMVP_IMON PGOOD LG1
19.1K_0402_1%

PC926

ISL95831CRZ-T_TQFN48_6X6
1

2.2U_0603_10V6K
PC927
PR936 9 28

3
2
1

3
2
1

2
IMON VSSP1
1

PR938

1
QC:19.1K
PR936

10 27 PHASE1 VSUM- 2 1
VR_HOT# PH1 1_0402_5%
2

DC:19.6K 11 26 UGATE1
2

2
ISEN3/ FB2

For shortage changed NTC UG1 @

12 25 BOOT1

PROG1
ISUMN

ISUMP
VW BOOT1
COMP

ISEN2

ISEN1

VSEN

VDD
RTN
<45,53> VR_HOT#

VIN
@ PC928 CPU_B+
FB
1

10U_0805_25V6K

10U_0805_25V6K
PR939 2 470P_0402_50V7K
1

5
1 2 PQ907
13

14

15

16

17

18

19

20

21

22

23

24
499_0402_1% PR940 PH903
2

1
TPCA8030-H_SOP-ADV8-5

PC930

PC931
+1.05VS_VCCPP @ 1 2 1 2

3.83K_0402_1% 470KB_0402_5%_ERTJ0EV474J
B value=4700K

2
UGATE2
PC929 PR943
4 Choke PN:SH00000JX00
2 1
DCR=1.33~1.396m ohm

1
47P_0402_50V8J PR941 27.4K_0402_1%
PR942 0 ohm =>98A (Vboot=0v)
PR943
1000P_0402_50V7K
8.06K_0402_1%

change from 43P to 47P 1 2 590_0402_1% 590 ohm=>91A (Vboot=0v) PL904

CPU_B+

3
2
1
1

0.36UH_PCMB103T-R36MS1R335_23A_20%
for shortage problem

4.7_1206_5%
PR944

PC932

PHASE2 4 1 +CPU_CORE

2
2010-03-15 PC933 0_0603_5%
QC: PC935
2

SI7170DP-T1-GE3_POWERPAK8-5
@ 22P_0402_50V8J PR946 2.2_0603_5% PQ908 3 2

1
DC: PC933
0.22U_0603_25V7K

SI7170DP-T1-GE3_POWERPAK8-5
2 1 +5VS PR945
2

PC936

PR947
2 1 BOOT2 2 1 2 1
1U_0603_10V6K

1_0603_5%
ISEN2

ISEN1

PQ909
PC934 10K_0402_1% PR949
ISEN3

B B

680P_0603_50V7K
PC937

0.22U_0402_6.3V6K PC935 0.22U_0603_10V7K PR948 10K_0402_1%

1 2
2 1 LGATE2 4 4 ISEN2 2 1 2 1 ISEN1
2

PC940
PC941
47P_0402_50V8J PC938
PR950
PR951 PC939 VSUM- 2 1 VSUM+ 3.65K_0402_1% PR953

2
1 2 2 1 2 1 2 1 0.22U_0402_6.3V6K PR952 1_0402_5%

3
2
1

3
2
1
1
2.61K_0402_1%
499_0402_1% PC942 VSUM+ 2 1 2 1 VSUM-
0.033U_0402_16V7K

0.033U_0402_16V7K

PR954

@ 499K_0402_1% 470P_0402_50V7K 2 1
0.22U_0603_10V7K

PC943 PR955 PR956 0.22U_0402_6.3V6K

2 1 2 1 2 1 B value=4250K PR969
PC955

PC945

PC944

3.74K_0402_1% @ 10K_0402_1%
1 2
1

1
11K_0402_1%

150P_0402_50V8J 220K_0402_1% CPU_B+ 2 1 ISEN3

10U_0805_25V6K

10U_0805_25V6K
PR958

PR957

5
+CPU_CORE 2 1 PH904 PQ910
2

@ 10_0402_1% 10K_0402_5%_ERTJ0ER103J

1
330P_0402_50V7K

PC948

PC949
TPCA8030-H_SOP-ADV8-5
PC947
2
1

PR959
PR956 2 1
2
PC946

330P_0402_50V7K 2 1 VSUM-

2
<9> VCCSENSE
QC:3.724K 1.54K_0402_1% UGATE1 4 Choke PN:SH00000JX00
2

.1U_0402_16V7K

PR960
<9> VSSSENSE
DC:2.15K
2 1
DCR=1.33~1.396m ohm
PC952

PC950 2 1 2 1
PR961 1000P_0402_50V7K
2

2 1 @ PC951 @ 100_0402_1% PL905

3
2
1
@ 10_0402_1% 330P_0402_50V7K 0.36UH_PCMB103T-R36MS1R335_23A_20%

SI7170DP-T1-GE3_POWERPAK8-5

SI7170DP-T1-GE3_POWERPAK8-5
PHASE1
PR959 4 1 +CPU_CORE

4.7_1206_5%
5

5
QC:1.54K=120A 2.2_0603_5%
0.22U_0603_10V7K 10K_0402_1% 3 2 PR965

1
PQ911

PR963
PR962 PC953 PR964 10K_0402_1%
DC:887=70A

PQ912
BOOT1 2 1 2 1 ISEN1 2 1 2 1 ISEN2
*Iccmax in Turbo Mode for SV (35W) is 53A

680P_0603_50V7K
LGATE1 4 4 3.65K_0402_1% PR967

1 2
+CPU_CORE +VGFX_COREP PR966 1_0402_5%

PC954
VSUM+ 2 1 2 1 VSUM-
A A
Icc-max=53A Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A
3
2
1

3
2
1

2
Rdson=3.6~4.5m ohm Rdson=3.6~4.5m ohm PR970
DCR=1.1m ohm DCR=1.1m ohm 10K_0402_1%
HW output cap: HW output cap: 2 1 ISEN3
@
(1)10U_0805_4V *10 (1)22U_0805_6.3V *12
(2)22U_0805_6.3V *15 (2)470U_D2_2V *2(ESR=4.5m ohm)
(3)470U_D2_2V *4(ESR=4.5m ohm) Security Classification Compal Secret Data Compal Electronics, Inc.
2010/01/25 2010/12/31 Title
Issued Date Deciphered Date PWR +CPU_CORE/+VGFX_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
*OCP setting value=71.5A *OCP setting value=37A Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom PIQY0/Y1 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 60 of 63
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase

1
D D

7
C C

10

11
B B

12

13

14

15

16

17
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2009/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PIQY0/Y1 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 29, 2010 Sheet 61 of 63
5 4 3 2 1
 5 4 3 2 1

PIQY0 HW PIR List

NO DATE PAGE MODIFICATION LIST PURPOSE
EVT TO DVT
1 P18 Reserve R297 Reserve pull down for PCH GPIO53.
2 P18 Exchange SATA port0 & port1 For fast boot function.
D 3 P50 Change KB light control circuit Change KB light control from PWM to on/off. D

Delete U55,C908,R1233,R1235,R1236,1238,R1230,R1231,Q121
4 P36 Add F2 (poly-fuse) For HDMI port diode protection.
5 P19 Stuff R303, unstuff R340 Change ESATA_DET# to GPIO1.
6 P49 Stuff R1068, reserve R1326, Q130 Reserve USB3.0 power swicth control inverter circuit.
7 P48 Add R1327 For CHG_ON# pull down.
8 P45 Stuff R996,R139,C815, unstuff R1000,C732,C733,Y5 Change EC CLK from crystal to SUSCLK.
9 P37 Add U60, Q132, C921, R1329, Q133, R1328 Add WLAN power switch circuit
10 P34 Modify JLVDS1 Modify connector from 40pin to 30pin.
11 P09 Add C922 Add C922 to place at CPU sdie.
12 P21 Add R1330 Add for INTVREN control
13 P41 Modify C639 Modify type from 0805 to 0603
14 P45 Modify TP_LED#, PCH_DPWROK and LED_KB_PWM link Change LED_KB_PWM to U36. pin26 GPIO12.
15 P18 Delete EN_CARD_PW#, EN_WOL# Add FAST_BOOT# to replace EN_CARD_PW# and EN_WOL#
16 P48 Remove USB charger function
17 P42 Change C660, C661 from 3300p to 0.1u For 100Hz High Pass filter
18 P43 Replace R958, R959 to C924, C925 0.033u For 100Hz High Pass filter
C C

19 P14 Add one more SPI-ROM circuit For dual BIOS function
20 P50 Remove EC_SMB_CK2, EC_SMB_DA2 link to JP13 Remove light sensor function
21 P14 Add Q134, R1345, R1346 Add for Fast boot SPI ROM selection by EC.
22 P34 Add R1341, C926 Added for EMI request
23 P37, P44 Add R1342,R1343 Added for WLAN and CARD reader Reset signal.
24 P19 Add R1344 Added for VENTURA detection.
DVT TO PVT
1 P10 Add R1347, Change R56 to 20K, Modify S3 1.5V reduction sequence.
2 P45 Add Q135 Modify PROCHOT control circuit.
Modify R980 link to +5VALW Change USB_ON PU power rail

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2009/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (HW)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6882P
Date: Monday, November 29, 2010 Sheet 62 of 63
5 4 3 2 1
 5 4 3 2 1

D D

PCH_PWR_EN# 2
U14,+3VALW_PCH

V
AC A1
MODE VIN QH4,+5VALW_PCH

V V
A2 A3 B5

VV
PU2 A5 2

V
PU3

V
B+ +3VALW_PCH
+3VALW B7 2 3
BATT V +5VALW_PCH
BATT
MODE
B1
B2
B+ B4 V
V

V
EC 4 SYS_PWROK
13
PQ2 PCH_RSMRST# PM_DRAM_PWRGD

V
V V PCH
B3 A5 B7 5 14
PBTN_OUT# H_CPUPWRGD
CPU

V V
V
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 15
C C
PM_SLP_S5#
A4 B6 PM_SLP_A# 6
PM_SLP_SUS#

V
V
ON/OFF V
SYSON 7 SYSON# +1.5V

V
PU5
DGPU_PWR_EN 8a (DIS) VGA_ON
+3VSDGPU

V
8
Q6 11
SUSP#,SUSP U49

V
VGATE
+5VS

V
+1.5VSDGPU
U40

V
U20

V
+3VS +1.8VSDGPU VGA
U37
B B

V
U13

V
+1.5VS +1.0VSDGPU
PU28

V
PU8

V
+0.75V +VGA_CORE
VCCPPWRGOOD
PU998
V

V
PU9 PU7
+1.05VS_VCCP +VCCSA 8b (DIS)
VGA_PWROK

U47
CK505
VR_ON 9 PU1000
V
10
V

+CPU_CORE

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/11/30 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PIQY0 LA6881P
Date: Monday, November 29, 2010 Sheet 63 of 63
5 4 3 2 1
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