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VLSI Design Finishing School

Course Curriculum
for
Industrial Training
(One Semester/Six Months)
in
VLSI Design – Front End
(RTL Coding & Synthesis)

_____________________
DesignKOP Labs
Knowledge, Operations and Practices

C-53, Lower Ground Floor, Sector – 2, Noida – 201301


Tel: 0120-4276796, 0120-4203797; Tel/Fax: 0120-4274237;
Mob: +91-9311667797; Email: info@designkop.org
Web: http://www.designkop.org
Module Topics

Module – 1 Operating System – Linux

Module – 2 Shell Scripting & Perl/TCL-Tk

Module – 3 Advanced Digital Design

Module – 4 VerilogHDL

Module – 5 Synthesis – FPGA Design Flow

Module – 6 Static Timing Analysis

Module – 7 SystemVerilog Basics

Module – 8 Project Work

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DesignKOP Team
1. Manu Lauria:
o Qualification: M.Tech. in Computer Science &
Engineering from IIT Delhi (1989-90) and B.Tech. in
Electrical Engineering from IIT Delhi (1980-1985)
o Experience: More than 22 years in the Industry with 18
years in the Semiconductor industry at Cadence Design
Systems and 4 years at ONGC. Rich experience in EDA
software tools development - responsible for many
products from concept to reality. Was part of the core
leadership team of Cadence’s Noida Center for 13 years.
Has managed or been part of teams that developed
products in the areas of Synthesis, Simulation, Custom
IC Design, Rule checking, Model Development & Web
based component/design management.

2. Sandeep Gupta:
o Qualification: M.Tech. in Computer Applications from
IIT Delhi and M.Sc. Mathematics from IIT Delhi
o Experience: More than Eighteen years in
Semiconductor industry with Thirteen years in Cadence
Design Systems. Have worked in the R&D of HDL
Simulation tools and Virtuoso platform.

3. Devender Khari:
o Qualification: M.E. Computer Science from BITS,
Pilani and B.Tech in Computer Engineering from
Shivaji University.
o Experience: More than 11 years of experience in
software and EDA industry with 8 years in Cadence
Design Systems. Have worked in the R&D of OrCAD
suite of tools, Allegro Design Editor and Virtuoso
Composer.

4. Neeraj Kr Shukla:
o Qualification: M.Tech & B.Tech in Electronics
Engineering.

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Experience: Eight Years in Academics and Academic –
Industry Interface: Worked as Lecturer in Birla Institute of
Technology & Science (BITS), Pilani, and as an Assistant
Professor in Mody Institute of Technology & Science
(MITS), Laxmangarh

5. Ashish Gulati:
o Qualifications: M.Sc. Computer Science from Pune
University and B.Sc. Computer Science from Lucknow
University, Lucknow
o Experience: More than 9 years of experience in Design
& EDA industry with around 5 years in Cadence Design
Systems and 4 years in Texas Instruments. Have
worked in the R&D of Cadence Encounter platform and
TI Code Composer Studio and Simulators for DSPs
and OMAP.
o Skills: EDA Tool Development, Instruction Set
Simulators, Object Oriented Programming, TCL/Tk,
etc
o Software Development Tools: Visual Studio, GNU
Tool chain, ClearCase, Rational tools like Purify,
Purecov

6. Vaibhav Sharma:
o Qualification: M.Tech(Digital Signal Processing) from
Netaji Subhash Institute of Technology, Delhi
University & B.E in Electronics and
Telecommunication from North Maharashtra University,
Jalgaon..
o Experience: More then Six Years in Telecom Industry
with HP (Hewlett Packard) and with semiconductor
Industry Transwitch India Pvt. Ltd. Rich Experience in
DSP tools and DSP based algorithms development and
DSP processors from TI and Analog Devices.
o Have worked in R&D of HP OV (open view) products
OVC/SA and ISACN and NNM and OVO’s
o Have been involved in R&D of DSP based products in
Telecom codecs and PLC(Power Line
communication) modem.

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7. Rahul Kumar Yadav:
o Qualification: B.Tech. in Electronics &
Communication Engineering from MDU, Rohtak.
o Professional Skills: PG Certificate in VLSI Design
o Design Skills: VHDL, VerilogHDL, ModelSim,
Leonardo Spectrum, Xlinix Design manager,
Precision RTL Synthesis, OrCAD Capture & PSpice,
TSpice, TimingDesigner, Shell & Perl Programming

8. Jyotsna Singhal:
o Qualifications: B.Tech. Computer Science from Delhi
Institute of Technology (DIT), Delhi and Certified
Scrum Master (CSM)
o Experience: More than 15 years of experience in EDA
industry and software industry with around 6 years in
Cadence Design Systems and 9 years in Riverrun
Software managing cross-functional and cross-
geography product releases.
o Skills: Java/J2EE Technologies, Network
Management Applications, Windows based client
server solutions. Have a thorough insight of software
development processes and life cycle, Object Oriented
Analysis and Design concepts and various Design
Patterns. Latest industry processes like: Agile
Methodologies (especially SCRUM), RUP, and ISO –
9001 and industry standard tools/practices. Handling
team dynamics, providing motivation and guidance to
the team.

9. Rachna Raj:
o Qualification: M.Tech. in VLSI, Banasthali Vidyapeeth
o Skills: VerilogHDL, VHDL, SystemVerilog
o EDA Tools: Cadence NC-Sim platform, ModelSim6.3,
Xilinx Design Manager

10. Kavita Sharma:


o Qualification: M.Tech. in VLSI, Banasthali Vidyapeeth
o Skills: VerilogHDL, VHDL, SystemVerilog

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o EDA Tools: Cadence NC-Sim platform, ModelSim6.3,
Xilinx Design Manager

11. Mamta Rana:


o Qualification: M.Sc. Physics with specialization in
Electronics, Jiwaji University. PG Certificate in VLSI
Design, IIMT
o Experience: Started my career at DesignKOP Labs in
2008
o Skills: VerilogHDL, VHDL, SystemVerilog
o EDA Tools: ModelSim6.3, Questa AVM6.3, Leonardo
Spectrum, Xilinx Design Manager and Precision RTL
Synthesis

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Program Details
Program Name : Industrial Training in VLSI Design–Front End
Batch Commences on: July 15th, 2009
Total Seats : 30
Duration : One Semester/ Six Months
(5 days/week, Mon - Fri, 4 hours/day)
Fees : Rs. 30,000/- per student
(Rs 1000/- for seat confirmation
Rs 15000/- at the time of joining
Rs 14000/- within 15 days of joining)

Tools
State-of-the art industry version tools from Cadence Design
Systems and Mentor Graphics Corporations
• Schematic Entry Tools
• RTL Design & Simulation Tools
• SPICE Simulation Tools

Soft Skills Training


1. Resume Writing
2. Interview Facing Skills
3. Presentation Preparation & Delivery
4. Leadership Skills – Team Work
5. English Speaking
6. Aptitude preparation
7. Company screening test preparation
8. Time Management

Benefits for the students

1. Helps student in understanding the practical and industrial


applications of academic curriculum in Chip-Design Industry
2. Build their knowledge to develop innovative projects during their
final year of engineering

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3. Enhances the Skill-Set in your resume as per the requirements
of Semiconductor Industry
4. Helping build knowledge and expertise for the aspirants of
higher studies abroad to face the stiff competition from students
of other countries
5. Build confidence through hands on exposure to various EDA
Tools & Technologies

Facilities
1. Latest configuration PCs with TFT Screens
2. Linux Operating system
3. High Speed unlimited Internet
4. LAN connecting all the PCs for easy distribution of tutorials etc.
5. LCD Projector & White screen
6. Library
7. Pantry
8. Xerox
9. Fax

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How to Apply

1. Download the application form from our website


http://www.designkop.org/AdmissionForm.pdf

2. Complete the printed copy of the downloaded form. Tick the


appropriate box to choose the program

3. Reserve your seat by sending the filled up form alongside a DD


of Rs 1,000/- in favor of "DESIGNKOP LABS" payable at Noida
towards the admission fee

4. First installment of Rs 15,000/- needs to be deposited on the


start/joining date by cash or cheque/draft in favor of
"DESIGNKOP LABS" payable at Noida.

5. Second installment of Rs 14,000/- needs to be deposited within


15 days of joining by cash or cheque/draft as mentioned above.

6. Admission on first-come-first-serve basis.

7. Limited number of Scholarships available based on a


scholarship test to be conducted during first month of training.

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Detailed Course Contents
Module-1 Operating System - Linux
1. Introduction to Linux OS
2. Managing Files and Directories
3. Creating Files Using the vi Editor
4. Managing Documents
5. Securing Files in Linux
6. Automating Tasks using Shell Scripts
7. Using Conditional Execution in Shell Scripts
8. Managing Repetitive Tasks Using Shell Scripts

Module-2 Shell Scripting, Perl/TCL-Tk


1. Introduction
2. Scalar Data
3. Lists and Arrays
4. Subroutines
5. Input and Output
6. Hashes
7. In the World of Regular Expressions
8. Matching with Regular Expressions
9. Processing Text with Regular Expressions
10. Project in TCL-Tk

Module-3 Advanced Digital Design


1. Design Concepts
2. Introduction to Logic
3. Optimized Implementation of Logic Functions
4. Number Representation and Arithmetic Circuits
5. Combinational-Circuits Building Blocks
6. Flip-Flops, Registers, Counters, and Simple Processor
7. Synchronous Sequential Circuits
8. Asynchronous Sequential Circuits
9. Digital System Design
10. Testing of Logic Circuits
11. Computer Aided Design Tools

Module – 4 Verilog HDL


1. Overview of Digital Design with VerilogHDL
2. Hierarchical Modeling Concepts
3. Basic Concepts
4. Modules and Ports
5. Gate-Level Modeling

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6. Dataflow Modeling
7. Behavioral Modeling
8. Tasks and Functions
9. Useful Modeling Techniques
10. Timing and Delays
11. Switch-Level Modeling
12. User Defined Primitives
13. Programming Language Interface
14. Advanced Verification Techniques

Module – 5 Synthesis – FPGA Design Flow


1. Logic Synthesis
2. Impact of Logic Synthesis
3. VerilogHDL Synthesis
4. Synthesis Design Flow
5. Modeling tips for Logic Synthesis
6. Design Entry Phase
7. Design implementation
8. Timing verification
9. Xilinx Device Programming

Module – 6 Static Timing Analysis


1. Timing Classification of digital systems
2. Synchronous Design
a. Synchronous timing basics – Setup & Hold Time
b. Timing Slacks
c. Sources of skew & jitter
d. Clock distribution techniques
3. Self Timed Circuit Design
a. Self-Timed Logic
b. Completion – Signal Generation
c. Self – Timed Signaling
4. Synthesized Design Database
a. Routing Operation on the design
b. Routing Operation on the synthesized design
c. Comparison of the Delays a & b
5. Advanced Timing Analysis
a. Synchronizers and Arbiters
b. Clock Synthesis and Synchronization
6. Timing Designer Labs

Module – 7 SystemVerilog Basics


1. Verification Guidelines
2. Data Types
3. Procedural Statements and Routines

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4. Basic OOP
5. Connecting the Testbench and Design

Module – 8 Project Work – Evaluation and


Presentation
1. Project Study
2. Design & Implementation using Cadence EDA tools
3. Presentation
4. Document submission
5. Evaluation of Project

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