Академический Документы
Профессиональный Документы
Культура Документы
Course Curriculum
for
Industrial Training
(One Semester/Six Months)
in
VLSI Design – Front End
(RTL Coding & Synthesis)
_____________________
DesignKOP Labs
Knowledge, Operations and Practices
Module – 4 VerilogHDL
Page 2 of 12
DesignKOP Team
1. Manu Lauria:
o Qualification: M.Tech. in Computer Science &
Engineering from IIT Delhi (1989-90) and B.Tech. in
Electrical Engineering from IIT Delhi (1980-1985)
o Experience: More than 22 years in the Industry with 18
years in the Semiconductor industry at Cadence Design
Systems and 4 years at ONGC. Rich experience in EDA
software tools development - responsible for many
products from concept to reality. Was part of the core
leadership team of Cadence’s Noida Center for 13 years.
Has managed or been part of teams that developed
products in the areas of Synthesis, Simulation, Custom
IC Design, Rule checking, Model Development & Web
based component/design management.
2. Sandeep Gupta:
o Qualification: M.Tech. in Computer Applications from
IIT Delhi and M.Sc. Mathematics from IIT Delhi
o Experience: More than Eighteen years in
Semiconductor industry with Thirteen years in Cadence
Design Systems. Have worked in the R&D of HDL
Simulation tools and Virtuoso platform.
3. Devender Khari:
o Qualification: M.E. Computer Science from BITS,
Pilani and B.Tech in Computer Engineering from
Shivaji University.
o Experience: More than 11 years of experience in
software and EDA industry with 8 years in Cadence
Design Systems. Have worked in the R&D of OrCAD
suite of tools, Allegro Design Editor and Virtuoso
Composer.
4. Neeraj Kr Shukla:
o Qualification: M.Tech & B.Tech in Electronics
Engineering.
Page 3 of 12
Experience: Eight Years in Academics and Academic –
Industry Interface: Worked as Lecturer in Birla Institute of
Technology & Science (BITS), Pilani, and as an Assistant
Professor in Mody Institute of Technology & Science
(MITS), Laxmangarh
5. Ashish Gulati:
o Qualifications: M.Sc. Computer Science from Pune
University and B.Sc. Computer Science from Lucknow
University, Lucknow
o Experience: More than 9 years of experience in Design
& EDA industry with around 5 years in Cadence Design
Systems and 4 years in Texas Instruments. Have
worked in the R&D of Cadence Encounter platform and
TI Code Composer Studio and Simulators for DSPs
and OMAP.
o Skills: EDA Tool Development, Instruction Set
Simulators, Object Oriented Programming, TCL/Tk,
etc
o Software Development Tools: Visual Studio, GNU
Tool chain, ClearCase, Rational tools like Purify,
Purecov
6. Vaibhav Sharma:
o Qualification: M.Tech(Digital Signal Processing) from
Netaji Subhash Institute of Technology, Delhi
University & B.E in Electronics and
Telecommunication from North Maharashtra University,
Jalgaon..
o Experience: More then Six Years in Telecom Industry
with HP (Hewlett Packard) and with semiconductor
Industry Transwitch India Pvt. Ltd. Rich Experience in
DSP tools and DSP based algorithms development and
DSP processors from TI and Analog Devices.
o Have worked in R&D of HP OV (open view) products
OVC/SA and ISACN and NNM and OVO’s
o Have been involved in R&D of DSP based products in
Telecom codecs and PLC(Power Line
communication) modem.
Page 4 of 12
7. Rahul Kumar Yadav:
o Qualification: B.Tech. in Electronics &
Communication Engineering from MDU, Rohtak.
o Professional Skills: PG Certificate in VLSI Design
o Design Skills: VHDL, VerilogHDL, ModelSim,
Leonardo Spectrum, Xlinix Design manager,
Precision RTL Synthesis, OrCAD Capture & PSpice,
TSpice, TimingDesigner, Shell & Perl Programming
8. Jyotsna Singhal:
o Qualifications: B.Tech. Computer Science from Delhi
Institute of Technology (DIT), Delhi and Certified
Scrum Master (CSM)
o Experience: More than 15 years of experience in EDA
industry and software industry with around 6 years in
Cadence Design Systems and 9 years in Riverrun
Software managing cross-functional and cross-
geography product releases.
o Skills: Java/J2EE Technologies, Network
Management Applications, Windows based client
server solutions. Have a thorough insight of software
development processes and life cycle, Object Oriented
Analysis and Design concepts and various Design
Patterns. Latest industry processes like: Agile
Methodologies (especially SCRUM), RUP, and ISO –
9001 and industry standard tools/practices. Handling
team dynamics, providing motivation and guidance to
the team.
9. Rachna Raj:
o Qualification: M.Tech. in VLSI, Banasthali Vidyapeeth
o Skills: VerilogHDL, VHDL, SystemVerilog
o EDA Tools: Cadence NC-Sim platform, ModelSim6.3,
Xilinx Design Manager
Page 5 of 12
o EDA Tools: Cadence NC-Sim platform, ModelSim6.3,
Xilinx Design Manager
Page 6 of 12
Program Details
Program Name : Industrial Training in VLSI Design–Front End
Batch Commences on: July 15th, 2009
Total Seats : 30
Duration : One Semester/ Six Months
(5 days/week, Mon - Fri, 4 hours/day)
Fees : Rs. 30,000/- per student
(Rs 1000/- for seat confirmation
Rs 15000/- at the time of joining
Rs 14000/- within 15 days of joining)
Tools
State-of-the art industry version tools from Cadence Design
Systems and Mentor Graphics Corporations
• Schematic Entry Tools
• RTL Design & Simulation Tools
• SPICE Simulation Tools
Page 7 of 12
3. Enhances the Skill-Set in your resume as per the requirements
of Semiconductor Industry
4. Helping build knowledge and expertise for the aspirants of
higher studies abroad to face the stiff competition from students
of other countries
5. Build confidence through hands on exposure to various EDA
Tools & Technologies
Facilities
1. Latest configuration PCs with TFT Screens
2. Linux Operating system
3. High Speed unlimited Internet
4. LAN connecting all the PCs for easy distribution of tutorials etc.
5. LCD Projector & White screen
6. Library
7. Pantry
8. Xerox
9. Fax
Page 8 of 12
How to Apply
Page 9 of 12
Detailed Course Contents
Module-1 Operating System - Linux
1. Introduction to Linux OS
2. Managing Files and Directories
3. Creating Files Using the vi Editor
4. Managing Documents
5. Securing Files in Linux
6. Automating Tasks using Shell Scripts
7. Using Conditional Execution in Shell Scripts
8. Managing Repetitive Tasks Using Shell Scripts
Page 10 of 12
6. Dataflow Modeling
7. Behavioral Modeling
8. Tasks and Functions
9. Useful Modeling Techniques
10. Timing and Delays
11. Switch-Level Modeling
12. User Defined Primitives
13. Programming Language Interface
14. Advanced Verification Techniques
Page 11 of 12
4. Basic OOP
5. Connecting the Testbench and Design
Page 12 of 12